2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
77 MLX5_CMD_OP_INIT_HCA
= 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
79 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
80 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
81 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
84 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
85 MLX5_CMD_OP_SET_ISSI
= 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
87 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
91 MLX5_CMD_OP_CREATE_EQ
= 0x301,
92 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
93 MLX5_CMD_OP_QUERY_EQ
= 0x303,
94 MLX5_CMD_OP_GEN_EQE
= 0x304,
95 MLX5_CMD_OP_CREATE_CQ
= 0x400,
96 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
97 MLX5_CMD_OP_QUERY_CQ
= 0x402,
98 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
99 MLX5_CMD_OP_CREATE_QP
= 0x500,
100 MLX5_CMD_OP_DESTROY_QP
= 0x501,
101 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
106 MLX5_CMD_OP_2ERR_QP
= 0x507,
107 MLX5_CMD_OP_2RST_QP
= 0x50a,
108 MLX5_CMD_OP_QUERY_QP
= 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
111 MLX5_CMD_OP_CREATE_PSV
= 0x600,
112 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
113 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
115 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
116 MLX5_CMD_OP_ARM_RQ
= 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
121 MLX5_CMD_OP_CREATE_DCT
= 0x710,
122 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
123 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
124 MLX5_CMD_OP_QUERY_DCT
= 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
142 MLX5_CMD_OP_ALLOC_PD
= 0x800,
143 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
144 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
147 MLX5_CMD_OP_ACCESS_REG
= 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG
= 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
151 MLX5_CMD_OP_MAD_IFC
= 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
154 MLX5_CMD_OP_NOP
= 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL
= 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL
= 0x831,
171 MLX5_CMD_OP_CREATE_TIR
= 0x900,
172 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
173 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
174 MLX5_CMD_OP_QUERY_TIR
= 0x903,
175 MLX5_CMD_OP_CREATE_SQ
= 0x904,
176 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
177 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
178 MLX5_CMD_OP_QUERY_SQ
= 0x907,
179 MLX5_CMD_OP_CREATE_RQ
= 0x908,
180 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
181 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
182 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
183 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
186 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
187 MLX5_CMD_OP_CREATE_TIS
= 0x912,
188 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
189 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
190 MLX5_CMD_OP_QUERY_TIS
= 0x915,
191 MLX5_CMD_OP_CREATE_RQT
= 0x916,
192 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
193 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
194 MLX5_CMD_OP_QUERY_RQT
= 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
205 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c
208 struct mlx5_ifc_flow_table_fields_supported_bits
{
211 u8 outer_ether_type
[0x1];
212 u8 reserved_at_3
[0x1];
213 u8 outer_first_prio
[0x1];
214 u8 outer_first_cfi
[0x1];
215 u8 outer_first_vid
[0x1];
216 u8 reserved_at_7
[0x1];
217 u8 outer_second_prio
[0x1];
218 u8 outer_second_cfi
[0x1];
219 u8 outer_second_vid
[0x1];
220 u8 reserved_at_b
[0x1];
224 u8 outer_ip_protocol
[0x1];
225 u8 outer_ip_ecn
[0x1];
226 u8 outer_ip_dscp
[0x1];
227 u8 outer_udp_sport
[0x1];
228 u8 outer_udp_dport
[0x1];
229 u8 outer_tcp_sport
[0x1];
230 u8 outer_tcp_dport
[0x1];
231 u8 outer_tcp_flags
[0x1];
232 u8 outer_gre_protocol
[0x1];
233 u8 outer_gre_key
[0x1];
234 u8 outer_vxlan_vni
[0x1];
235 u8 reserved_at_1a
[0x5];
236 u8 source_eswitch_port
[0x1];
240 u8 inner_ether_type
[0x1];
241 u8 reserved_at_23
[0x1];
242 u8 inner_first_prio
[0x1];
243 u8 inner_first_cfi
[0x1];
244 u8 inner_first_vid
[0x1];
245 u8 reserved_at_27
[0x1];
246 u8 inner_second_prio
[0x1];
247 u8 inner_second_cfi
[0x1];
248 u8 inner_second_vid
[0x1];
249 u8 reserved_at_2b
[0x1];
253 u8 inner_ip_protocol
[0x1];
254 u8 inner_ip_ecn
[0x1];
255 u8 inner_ip_dscp
[0x1];
256 u8 inner_udp_sport
[0x1];
257 u8 inner_udp_dport
[0x1];
258 u8 inner_tcp_sport
[0x1];
259 u8 inner_tcp_dport
[0x1];
260 u8 inner_tcp_flags
[0x1];
261 u8 reserved_at_37
[0x9];
263 u8 reserved_at_40
[0x40];
266 struct mlx5_ifc_flow_table_prop_layout_bits
{
268 u8 reserved_at_1
[0x2];
269 u8 flow_modify_en
[0x1];
271 u8 identified_miss_table_mode
[0x1];
272 u8 flow_table_modify
[0x1];
273 u8 reserved_at_7
[0x19];
275 u8 reserved_at_20
[0x2];
276 u8 log_max_ft_size
[0x6];
277 u8 reserved_at_28
[0x10];
278 u8 max_ft_level
[0x8];
280 u8 reserved_at_40
[0x20];
282 u8 reserved_at_60
[0x18];
283 u8 log_max_ft_num
[0x8];
285 u8 reserved_at_80
[0x18];
286 u8 log_max_destination
[0x8];
288 u8 reserved_at_a0
[0x18];
289 u8 log_max_flow
[0x8];
291 u8 reserved_at_c0
[0x40];
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
295 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
298 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
303 u8 reserved_at_4
[0x1];
305 u8 reserved_at_6
[0x1a];
308 struct mlx5_ifc_ipv4_layout_bits
{
309 u8 reserved_at_0
[0x60];
314 struct mlx5_ifc_ipv6_layout_bits
{
318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits
{
319 struct mlx5_ifc_ipv6_layout_bits ipv6_layout
;
320 struct mlx5_ifc_ipv4_layout_bits ipv4_layout
;
321 u8 reserved_at_0
[0x80];
324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
341 u8 reserved_at_91
[0x1];
343 u8 reserved_at_93
[0x4];
349 u8 reserved_at_c0
[0x20];
354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
356 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
359 struct mlx5_ifc_fte_match_set_misc_bits
{
360 u8 reserved_at_0
[0x20];
362 u8 reserved_at_20
[0x10];
363 u8 source_port
[0x10];
365 u8 outer_second_prio
[0x3];
366 u8 outer_second_cfi
[0x1];
367 u8 outer_second_vid
[0xc];
368 u8 inner_second_prio
[0x3];
369 u8 inner_second_cfi
[0x1];
370 u8 inner_second_vid
[0xc];
372 u8 outer_second_vlan_tag
[0x1];
373 u8 inner_second_vlan_tag
[0x1];
374 u8 reserved_at_62
[0xe];
375 u8 gre_protocol
[0x10];
381 u8 reserved_at_b8
[0x8];
383 u8 reserved_at_c0
[0x20];
385 u8 reserved_at_e0
[0xc];
386 u8 outer_ipv6_flow_label
[0x14];
388 u8 reserved_at_100
[0xc];
389 u8 inner_ipv6_flow_label
[0x14];
391 u8 reserved_at_120
[0xe0];
394 struct mlx5_ifc_cmd_pas_bits
{
398 u8 reserved_at_34
[0xc];
401 struct mlx5_ifc_uint64_bits
{
408 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
409 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
410 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
411 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
412 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
413 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
414 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
415 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
416 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
417 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
420 struct mlx5_ifc_ads_bits
{
423 u8 reserved_at_2
[0xe];
426 u8 reserved_at_20
[0x8];
432 u8 reserved_at_45
[0x3];
433 u8 src_addr_index
[0x8];
434 u8 reserved_at_50
[0x4];
438 u8 reserved_at_60
[0x4];
442 u8 rgid_rip
[16][0x8];
444 u8 reserved_at_100
[0x4];
447 u8 reserved_at_106
[0x1];
462 struct mlx5_ifc_flow_table_nic_cap_bits
{
463 u8 nic_rx_multi_path_tirs
[0x1];
464 u8 reserved_at_1
[0x1ff];
466 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
468 u8 reserved_at_400
[0x200];
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
472 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
474 u8 reserved_at_a00
[0x200];
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
478 u8 reserved_at_e00
[0x7200];
481 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
482 u8 reserved_at_0
[0x200];
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
486 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
490 u8 reserved_at_800
[0x7800];
493 struct mlx5_ifc_e_switch_cap_bits
{
494 u8 vport_svlan_strip
[0x1];
495 u8 vport_cvlan_strip
[0x1];
496 u8 vport_svlan_insert
[0x1];
497 u8 vport_cvlan_insert_if_not_exist
[0x1];
498 u8 vport_cvlan_insert_overwrite
[0x1];
499 u8 reserved_at_5
[0x1b];
501 u8 reserved_at_20
[0x7e0];
504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
508 u8 lro_psh_flag
[0x1];
509 u8 lro_time_stamp
[0x1];
510 u8 reserved_at_5
[0x3];
511 u8 self_lb_en_modifiable
[0x1];
512 u8 reserved_at_9
[0x2];
514 u8 reserved_at_10
[0x4];
515 u8 rss_ind_tbl_cap
[0x4];
516 u8 reserved_at_18
[0x3];
517 u8 tunnel_lso_const_out_ip_id
[0x1];
518 u8 reserved_at_1c
[0x2];
519 u8 tunnel_statless_gre
[0x1];
520 u8 tunnel_stateless_vxlan
[0x1];
522 u8 reserved_at_20
[0x20];
524 u8 reserved_at_40
[0x10];
525 u8 lro_min_mss_size
[0x10];
527 u8 reserved_at_60
[0x120];
529 u8 lro_timer_supported_periods
[4][0x20];
531 u8 reserved_at_200
[0x600];
534 struct mlx5_ifc_roce_cap_bits
{
536 u8 reserved_at_1
[0x1f];
538 u8 reserved_at_20
[0x60];
540 u8 reserved_at_80
[0xc];
542 u8 reserved_at_90
[0x8];
543 u8 roce_version
[0x8];
545 u8 reserved_at_a0
[0x10];
546 u8 r_roce_dest_udp_port
[0x10];
548 u8 r_roce_max_src_udp_port
[0x10];
549 u8 r_roce_min_src_udp_port
[0x10];
551 u8 reserved_at_e0
[0x10];
552 u8 roce_address_table_size
[0x10];
554 u8 reserved_at_100
[0x700];
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
578 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
581 struct mlx5_ifc_atomic_caps_bits
{
582 u8 reserved_at_0
[0x40];
584 u8 atomic_req_8B_endianess_mode
[0x2];
585 u8 reserved_at_42
[0x4];
586 u8 supported_atomic_req_8B_endianess_mode_1
[0x1];
588 u8 reserved_at_47
[0x19];
590 u8 reserved_at_60
[0x20];
592 u8 reserved_at_80
[0x10];
593 u8 atomic_operations
[0x10];
595 u8 reserved_at_a0
[0x10];
596 u8 atomic_size_qp
[0x10];
598 u8 reserved_at_c0
[0x10];
599 u8 atomic_size_dc
[0x10];
601 u8 reserved_at_e0
[0x720];
604 struct mlx5_ifc_odp_cap_bits
{
605 u8 reserved_at_0
[0x40];
608 u8 reserved_at_41
[0x1f];
610 u8 reserved_at_60
[0x20];
612 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
614 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
616 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
618 u8 reserved_at_e0
[0x720];
621 struct mlx5_ifc_calc_op
{
622 u8 reserved_at_0
[0x10];
623 u8 reserved_at_10
[0x9];
624 u8 op_swap_endianness
[0x1];
633 struct mlx5_ifc_vector_calc_cap_bits
{
635 u8 reserved_at_1
[0x1f];
636 u8 reserved_at_20
[0x8];
637 u8 max_vec_count
[0x8];
638 u8 reserved_at_30
[0xd];
639 u8 max_chunk_size
[0x3];
640 struct mlx5_ifc_calc_op calc0
;
641 struct mlx5_ifc_calc_op calc1
;
642 struct mlx5_ifc_calc_op calc2
;
643 struct mlx5_ifc_calc_op calc3
;
645 u8 reserved_at_e0
[0x720];
649 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
650 MLX5_WQ_TYPE_CYCLIC
= 0x1,
651 MLX5_WQ_TYPE_STRQ
= 0x2,
655 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
656 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
660 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
661 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
662 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
663 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
664 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
668 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
669 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
670 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
671 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
672 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
673 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
677 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
678 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
682 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
683 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
684 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
688 MLX5_CAP_PORT_TYPE_IB
= 0x0,
689 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
692 struct mlx5_ifc_cmd_hca_cap_bits
{
693 u8 reserved_at_0
[0x80];
695 u8 log_max_srq_sz
[0x8];
696 u8 log_max_qp_sz
[0x8];
697 u8 reserved_at_90
[0xb];
700 u8 reserved_at_a0
[0xb];
702 u8 reserved_at_b0
[0x10];
704 u8 reserved_at_c0
[0x8];
705 u8 log_max_cq_sz
[0x8];
706 u8 reserved_at_d0
[0xb];
709 u8 log_max_eq_sz
[0x8];
710 u8 reserved_at_e8
[0x2];
711 u8 log_max_mkey
[0x6];
712 u8 reserved_at_f0
[0xc];
715 u8 max_indirection
[0x8];
716 u8 reserved_at_108
[0x1];
717 u8 log_max_mrw_sz
[0x7];
718 u8 reserved_at_110
[0x2];
719 u8 log_max_bsf_list_size
[0x6];
720 u8 reserved_at_118
[0x2];
721 u8 log_max_klm_list_size
[0x6];
723 u8 reserved_at_120
[0xa];
724 u8 log_max_ra_req_dc
[0x6];
725 u8 reserved_at_130
[0xa];
726 u8 log_max_ra_res_dc
[0x6];
728 u8 reserved_at_140
[0xa];
729 u8 log_max_ra_req_qp
[0x6];
730 u8 reserved_at_150
[0xa];
731 u8 log_max_ra_res_qp
[0x6];
734 u8 cc_query_allowed
[0x1];
735 u8 cc_modify_allowed
[0x1];
736 u8 reserved_at_163
[0xd];
737 u8 gid_table_size
[0x10];
739 u8 out_of_seq_cnt
[0x1];
740 u8 vport_counters
[0x1];
741 u8 reserved_at_182
[0x4];
743 u8 pkey_table_size
[0x10];
745 u8 vport_group_manager
[0x1];
746 u8 vhca_group_manager
[0x1];
749 u8 reserved_at_1a4
[0x1];
751 u8 nic_flow_table
[0x1];
752 u8 eswitch_flow_table
[0x1];
754 u8 reserved_at_1a8
[0x2];
755 u8 local_ca_ack_delay
[0x5];
756 u8 reserved_at_1af
[0x6];
760 u8 reserved_at_1bf
[0x3];
762 u8 reserved_at_1c7
[0x4];
764 u8 reserved_at_1cf
[0x6];
767 u8 reserved_at_1d7
[0x1];
776 u8 stat_rate_support
[0x10];
777 u8 reserved_at_1ef
[0xc];
780 u8 compact_address_vector
[0x1];
781 u8 reserved_at_200
[0x3];
782 u8 ipoib_basic_offloads
[0x1];
783 u8 reserved_at_204
[0xa];
784 u8 drain_sigerr
[0x1];
785 u8 cmdif_checksum
[0x2];
787 u8 reserved_at_212
[0x1];
788 u8 wq_signature
[0x1];
789 u8 sctr_data_cqe
[0x1];
790 u8 reserved_at_215
[0x1];
795 u8 reserved_at_21a
[0x1];
796 u8 eth_net_offloads
[0x1];
799 u8 reserved_at_21e
[0x1];
803 u8 cq_moderation
[0x1];
804 u8 reserved_at_222
[0x3];
808 u8 reserved_at_228
[0x1];
809 u8 scqe_break_moderation
[0x1];
810 u8 reserved_at_22a
[0x1];
812 u8 reserved_at_22c
[0x1];
815 u8 reserved_at_22f
[0x1];
817 u8 reserved_at_231
[0x4];
820 u8 set_deth_sqpn
[0x1];
821 u8 reserved_at_239
[0x3];
827 u8 reserved_at_23f
[0xa];
829 u8 reserved_at_24f
[0x8];
833 u8 reserved_at_260
[0x1];
834 u8 pad_tx_eth_packet
[0x1];
835 u8 reserved_at_262
[0x8];
836 u8 log_bf_reg_size
[0x5];
837 u8 reserved_at_26f
[0x10];
839 u8 reserved_at_27f
[0x10];
840 u8 max_wqe_sz_sq
[0x10];
842 u8 reserved_at_29f
[0x10];
843 u8 max_wqe_sz_rq
[0x10];
845 u8 reserved_at_2bf
[0x10];
846 u8 max_wqe_sz_sq_dc
[0x10];
848 u8 reserved_at_2df
[0x7];
851 u8 reserved_at_2ff
[0x18];
854 u8 reserved_at_31f
[0x3];
855 u8 log_max_transport_domain
[0x5];
856 u8 reserved_at_327
[0x3];
858 u8 reserved_at_32f
[0xb];
859 u8 log_max_xrcd
[0x5];
861 u8 reserved_at_33f
[0x20];
863 u8 reserved_at_35f
[0x3];
865 u8 reserved_at_367
[0x3];
867 u8 reserved_at_36f
[0x3];
869 u8 reserved_at_377
[0x3];
872 u8 basic_cyclic_rcv_wqe
[0x1];
873 u8 reserved_at_380
[0x2];
875 u8 reserved_at_387
[0x3];
877 u8 reserved_at_38f
[0x3];
878 u8 log_max_rqt_size
[0x5];
879 u8 reserved_at_397
[0x3];
880 u8 log_max_tis_per_sq
[0x5];
882 u8 reserved_at_39f
[0x3];
883 u8 log_max_stride_sz_rq
[0x5];
884 u8 reserved_at_3a7
[0x3];
885 u8 log_min_stride_sz_rq
[0x5];
886 u8 reserved_at_3af
[0x3];
887 u8 log_max_stride_sz_sq
[0x5];
888 u8 reserved_at_3b7
[0x3];
889 u8 log_min_stride_sz_sq
[0x5];
891 u8 reserved_at_3bf
[0x1b];
892 u8 log_max_wq_sz
[0x5];
894 u8 nic_vport_change_event
[0x1];
895 u8 reserved_at_3e0
[0xa];
896 u8 log_max_vlan_list
[0x5];
897 u8 reserved_at_3ef
[0x3];
898 u8 log_max_current_mc_list
[0x5];
899 u8 reserved_at_3f7
[0x3];
900 u8 log_max_current_uc_list
[0x5];
902 u8 reserved_at_3ff
[0x80];
904 u8 reserved_at_47f
[0x3];
905 u8 log_max_l2_table
[0x5];
906 u8 reserved_at_487
[0x8];
907 u8 log_uar_page_sz
[0x10];
909 u8 reserved_at_49f
[0x20];
910 u8 device_frequency_mhz
[0x20];
911 u8 device_frequency_khz
[0x20];
912 u8 reserved_at_4ff
[0x5f];
915 u8 cqe_zip_timeout
[0x10];
916 u8 cqe_zip_max_num
[0x10];
918 u8 reserved_at_57f
[0x220];
921 enum mlx5_flow_destination_type
{
922 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
923 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
924 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
927 struct mlx5_ifc_dest_format_struct_bits
{
928 u8 destination_type
[0x8];
929 u8 destination_id
[0x18];
931 u8 reserved_at_20
[0x20];
934 struct mlx5_ifc_fte_match_param_bits
{
935 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
937 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
939 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
941 u8 reserved_at_600
[0xa00];
945 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
946 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
947 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
948 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
949 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
952 struct mlx5_ifc_rx_hash_field_select_bits
{
953 u8 l3_prot_type
[0x1];
954 u8 l4_prot_type
[0x1];
955 u8 selected_fields
[0x1e];
959 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
960 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
964 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
965 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
968 struct mlx5_ifc_wq_bits
{
970 u8 wq_signature
[0x1];
971 u8 end_padding_mode
[0x2];
973 u8 reserved_at_8
[0x18];
975 u8 hds_skip_first_sge
[0x1];
976 u8 log2_hds_buf_size
[0x3];
977 u8 reserved_at_24
[0x7];
981 u8 reserved_at_40
[0x8];
984 u8 reserved_at_60
[0x8];
993 u8 reserved_at_100
[0xc];
994 u8 log_wq_stride
[0x4];
995 u8 reserved_at_110
[0x3];
996 u8 log_wq_pg_sz
[0x5];
997 u8 reserved_at_118
[0x3];
1000 u8 reserved_at_120
[0x4e0];
1002 struct mlx5_ifc_cmd_pas_bits pas
[0];
1005 struct mlx5_ifc_rq_num_bits
{
1006 u8 reserved_at_0
[0x8];
1010 struct mlx5_ifc_mac_address_layout_bits
{
1011 u8 reserved_at_0
[0x10];
1012 u8 mac_addr_47_32
[0x10];
1014 u8 mac_addr_31_0
[0x20];
1017 struct mlx5_ifc_vlan_layout_bits
{
1018 u8 reserved_at_0
[0x14];
1021 u8 reserved_at_20
[0x20];
1024 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
1025 u8 reserved_at_0
[0xa0];
1027 u8 min_time_between_cnps
[0x20];
1029 u8 reserved_at_c0
[0x12];
1031 u8 reserved_at_d8
[0x5];
1032 u8 cnp_802p_prio
[0x3];
1034 u8 reserved_at_e0
[0x720];
1037 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
1038 u8 reserved_at_0
[0x60];
1040 u8 reserved_at_60
[0x4];
1041 u8 clamp_tgt_rate
[0x1];
1042 u8 reserved_at_65
[0x3];
1043 u8 clamp_tgt_rate_after_time_inc
[0x1];
1044 u8 reserved_at_69
[0x17];
1046 u8 reserved_at_80
[0x20];
1048 u8 rpg_time_reset
[0x20];
1050 u8 rpg_byte_reset
[0x20];
1052 u8 rpg_threshold
[0x20];
1054 u8 rpg_max_rate
[0x20];
1056 u8 rpg_ai_rate
[0x20];
1058 u8 rpg_hai_rate
[0x20];
1062 u8 rpg_min_dec_fac
[0x20];
1064 u8 rpg_min_rate
[0x20];
1066 u8 reserved_at_1c0
[0xe0];
1068 u8 rate_to_set_on_first_cnp
[0x20];
1072 u8 dce_tcp_rtt
[0x20];
1074 u8 rate_reduce_monitor_period
[0x20];
1076 u8 reserved_at_320
[0x20];
1078 u8 initial_alpha_value
[0x20];
1080 u8 reserved_at_360
[0x4a0];
1083 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1084 u8 reserved_at_0
[0x80];
1086 u8 rppp_max_rps
[0x20];
1088 u8 rpg_time_reset
[0x20];
1090 u8 rpg_byte_reset
[0x20];
1092 u8 rpg_threshold
[0x20];
1094 u8 rpg_max_rate
[0x20];
1096 u8 rpg_ai_rate
[0x20];
1098 u8 rpg_hai_rate
[0x20];
1102 u8 rpg_min_dec_fac
[0x20];
1104 u8 rpg_min_rate
[0x20];
1106 u8 reserved_at_1c0
[0x640];
1110 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1111 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1112 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1115 struct mlx5_ifc_resize_field_select_bits
{
1116 u8 resize_field_select
[0x20];
1120 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1121 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1122 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1123 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1126 struct mlx5_ifc_modify_field_select_bits
{
1127 u8 modify_field_select
[0x20];
1130 struct mlx5_ifc_field_select_r_roce_np_bits
{
1131 u8 field_select_r_roce_np
[0x20];
1134 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1135 u8 field_select_r_roce_rp
[0x20];
1139 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1140 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1141 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1142 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1143 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1144 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1145 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1146 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1147 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1148 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1151 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1152 u8 field_select_8021qaurp
[0x20];
1155 struct mlx5_ifc_phys_layer_cntrs_bits
{
1156 u8 time_since_last_clear_high
[0x20];
1158 u8 time_since_last_clear_low
[0x20];
1160 u8 symbol_errors_high
[0x20];
1162 u8 symbol_errors_low
[0x20];
1164 u8 sync_headers_errors_high
[0x20];
1166 u8 sync_headers_errors_low
[0x20];
1168 u8 edpl_bip_errors_lane0_high
[0x20];
1170 u8 edpl_bip_errors_lane0_low
[0x20];
1172 u8 edpl_bip_errors_lane1_high
[0x20];
1174 u8 edpl_bip_errors_lane1_low
[0x20];
1176 u8 edpl_bip_errors_lane2_high
[0x20];
1178 u8 edpl_bip_errors_lane2_low
[0x20];
1180 u8 edpl_bip_errors_lane3_high
[0x20];
1182 u8 edpl_bip_errors_lane3_low
[0x20];
1184 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1186 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1188 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1190 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1192 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1194 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1196 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1198 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1200 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1202 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1204 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1206 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1208 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1210 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1212 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1214 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1216 u8 rs_fec_corrected_blocks_high
[0x20];
1218 u8 rs_fec_corrected_blocks_low
[0x20];
1220 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1222 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1224 u8 rs_fec_no_errors_blocks_high
[0x20];
1226 u8 rs_fec_no_errors_blocks_low
[0x20];
1228 u8 rs_fec_single_error_blocks_high
[0x20];
1230 u8 rs_fec_single_error_blocks_low
[0x20];
1232 u8 rs_fec_corrected_symbols_total_high
[0x20];
1234 u8 rs_fec_corrected_symbols_total_low
[0x20];
1236 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1238 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1240 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1242 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1244 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1246 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1248 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1250 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1252 u8 link_down_events
[0x20];
1254 u8 successful_recovery_events
[0x20];
1256 u8 reserved_at_640
[0x180];
1259 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits
{
1260 u8 symbol_error_counter
[0x10];
1262 u8 link_error_recovery_counter
[0x8];
1264 u8 link_downed_counter
[0x8];
1266 u8 port_rcv_errors
[0x10];
1268 u8 port_rcv_remote_physical_errors
[0x10];
1270 u8 port_rcv_switch_relay_errors
[0x10];
1272 u8 port_xmit_discards
[0x10];
1274 u8 port_xmit_constraint_errors
[0x8];
1276 u8 port_rcv_constraint_errors
[0x8];
1278 u8 reserved_at_70
[0x8];
1280 u8 link_overrun_errors
[0x8];
1282 u8 reserved_at_80
[0x10];
1284 u8 vl_15_dropped
[0x10];
1286 u8 reserved_at_a0
[0xa0];
1289 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits
{
1290 u8 transmit_queue_high
[0x20];
1292 u8 transmit_queue_low
[0x20];
1294 u8 reserved_at_40
[0x780];
1297 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1298 u8 rx_octets_high
[0x20];
1300 u8 rx_octets_low
[0x20];
1302 u8 reserved_at_40
[0xc0];
1304 u8 rx_frames_high
[0x20];
1306 u8 rx_frames_low
[0x20];
1308 u8 tx_octets_high
[0x20];
1310 u8 tx_octets_low
[0x20];
1312 u8 reserved_at_180
[0xc0];
1314 u8 tx_frames_high
[0x20];
1316 u8 tx_frames_low
[0x20];
1318 u8 rx_pause_high
[0x20];
1320 u8 rx_pause_low
[0x20];
1322 u8 rx_pause_duration_high
[0x20];
1324 u8 rx_pause_duration_low
[0x20];
1326 u8 tx_pause_high
[0x20];
1328 u8 tx_pause_low
[0x20];
1330 u8 tx_pause_duration_high
[0x20];
1332 u8 tx_pause_duration_low
[0x20];
1334 u8 rx_pause_transition_high
[0x20];
1336 u8 rx_pause_transition_low
[0x20];
1338 u8 reserved_at_3c0
[0x400];
1341 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
1342 u8 port_transmit_wait_high
[0x20];
1344 u8 port_transmit_wait_low
[0x20];
1346 u8 reserved_at_40
[0x780];
1349 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
1350 u8 dot3stats_alignment_errors_high
[0x20];
1352 u8 dot3stats_alignment_errors_low
[0x20];
1354 u8 dot3stats_fcs_errors_high
[0x20];
1356 u8 dot3stats_fcs_errors_low
[0x20];
1358 u8 dot3stats_single_collision_frames_high
[0x20];
1360 u8 dot3stats_single_collision_frames_low
[0x20];
1362 u8 dot3stats_multiple_collision_frames_high
[0x20];
1364 u8 dot3stats_multiple_collision_frames_low
[0x20];
1366 u8 dot3stats_sqe_test_errors_high
[0x20];
1368 u8 dot3stats_sqe_test_errors_low
[0x20];
1370 u8 dot3stats_deferred_transmissions_high
[0x20];
1372 u8 dot3stats_deferred_transmissions_low
[0x20];
1374 u8 dot3stats_late_collisions_high
[0x20];
1376 u8 dot3stats_late_collisions_low
[0x20];
1378 u8 dot3stats_excessive_collisions_high
[0x20];
1380 u8 dot3stats_excessive_collisions_low
[0x20];
1382 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
1384 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
1386 u8 dot3stats_carrier_sense_errors_high
[0x20];
1388 u8 dot3stats_carrier_sense_errors_low
[0x20];
1390 u8 dot3stats_frame_too_longs_high
[0x20];
1392 u8 dot3stats_frame_too_longs_low
[0x20];
1394 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
1396 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
1398 u8 dot3stats_symbol_errors_high
[0x20];
1400 u8 dot3stats_symbol_errors_low
[0x20];
1402 u8 dot3control_in_unknown_opcodes_high
[0x20];
1404 u8 dot3control_in_unknown_opcodes_low
[0x20];
1406 u8 dot3in_pause_frames_high
[0x20];
1408 u8 dot3in_pause_frames_low
[0x20];
1410 u8 dot3out_pause_frames_high
[0x20];
1412 u8 dot3out_pause_frames_low
[0x20];
1414 u8 reserved_at_400
[0x3c0];
1417 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
1418 u8 ether_stats_drop_events_high
[0x20];
1420 u8 ether_stats_drop_events_low
[0x20];
1422 u8 ether_stats_octets_high
[0x20];
1424 u8 ether_stats_octets_low
[0x20];
1426 u8 ether_stats_pkts_high
[0x20];
1428 u8 ether_stats_pkts_low
[0x20];
1430 u8 ether_stats_broadcast_pkts_high
[0x20];
1432 u8 ether_stats_broadcast_pkts_low
[0x20];
1434 u8 ether_stats_multicast_pkts_high
[0x20];
1436 u8 ether_stats_multicast_pkts_low
[0x20];
1438 u8 ether_stats_crc_align_errors_high
[0x20];
1440 u8 ether_stats_crc_align_errors_low
[0x20];
1442 u8 ether_stats_undersize_pkts_high
[0x20];
1444 u8 ether_stats_undersize_pkts_low
[0x20];
1446 u8 ether_stats_oversize_pkts_high
[0x20];
1448 u8 ether_stats_oversize_pkts_low
[0x20];
1450 u8 ether_stats_fragments_high
[0x20];
1452 u8 ether_stats_fragments_low
[0x20];
1454 u8 ether_stats_jabbers_high
[0x20];
1456 u8 ether_stats_jabbers_low
[0x20];
1458 u8 ether_stats_collisions_high
[0x20];
1460 u8 ether_stats_collisions_low
[0x20];
1462 u8 ether_stats_pkts64octets_high
[0x20];
1464 u8 ether_stats_pkts64octets_low
[0x20];
1466 u8 ether_stats_pkts65to127octets_high
[0x20];
1468 u8 ether_stats_pkts65to127octets_low
[0x20];
1470 u8 ether_stats_pkts128to255octets_high
[0x20];
1472 u8 ether_stats_pkts128to255octets_low
[0x20];
1474 u8 ether_stats_pkts256to511octets_high
[0x20];
1476 u8 ether_stats_pkts256to511octets_low
[0x20];
1478 u8 ether_stats_pkts512to1023octets_high
[0x20];
1480 u8 ether_stats_pkts512to1023octets_low
[0x20];
1482 u8 ether_stats_pkts1024to1518octets_high
[0x20];
1484 u8 ether_stats_pkts1024to1518octets_low
[0x20];
1486 u8 ether_stats_pkts1519to2047octets_high
[0x20];
1488 u8 ether_stats_pkts1519to2047octets_low
[0x20];
1490 u8 ether_stats_pkts2048to4095octets_high
[0x20];
1492 u8 ether_stats_pkts2048to4095octets_low
[0x20];
1494 u8 ether_stats_pkts4096to8191octets_high
[0x20];
1496 u8 ether_stats_pkts4096to8191octets_low
[0x20];
1498 u8 ether_stats_pkts8192to10239octets_high
[0x20];
1500 u8 ether_stats_pkts8192to10239octets_low
[0x20];
1502 u8 reserved_at_540
[0x280];
1505 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
1506 u8 if_in_octets_high
[0x20];
1508 u8 if_in_octets_low
[0x20];
1510 u8 if_in_ucast_pkts_high
[0x20];
1512 u8 if_in_ucast_pkts_low
[0x20];
1514 u8 if_in_discards_high
[0x20];
1516 u8 if_in_discards_low
[0x20];
1518 u8 if_in_errors_high
[0x20];
1520 u8 if_in_errors_low
[0x20];
1522 u8 if_in_unknown_protos_high
[0x20];
1524 u8 if_in_unknown_protos_low
[0x20];
1526 u8 if_out_octets_high
[0x20];
1528 u8 if_out_octets_low
[0x20];
1530 u8 if_out_ucast_pkts_high
[0x20];
1532 u8 if_out_ucast_pkts_low
[0x20];
1534 u8 if_out_discards_high
[0x20];
1536 u8 if_out_discards_low
[0x20];
1538 u8 if_out_errors_high
[0x20];
1540 u8 if_out_errors_low
[0x20];
1542 u8 if_in_multicast_pkts_high
[0x20];
1544 u8 if_in_multicast_pkts_low
[0x20];
1546 u8 if_in_broadcast_pkts_high
[0x20];
1548 u8 if_in_broadcast_pkts_low
[0x20];
1550 u8 if_out_multicast_pkts_high
[0x20];
1552 u8 if_out_multicast_pkts_low
[0x20];
1554 u8 if_out_broadcast_pkts_high
[0x20];
1556 u8 if_out_broadcast_pkts_low
[0x20];
1558 u8 reserved_at_340
[0x480];
1561 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
1562 u8 a_frames_transmitted_ok_high
[0x20];
1564 u8 a_frames_transmitted_ok_low
[0x20];
1566 u8 a_frames_received_ok_high
[0x20];
1568 u8 a_frames_received_ok_low
[0x20];
1570 u8 a_frame_check_sequence_errors_high
[0x20];
1572 u8 a_frame_check_sequence_errors_low
[0x20];
1574 u8 a_alignment_errors_high
[0x20];
1576 u8 a_alignment_errors_low
[0x20];
1578 u8 a_octets_transmitted_ok_high
[0x20];
1580 u8 a_octets_transmitted_ok_low
[0x20];
1582 u8 a_octets_received_ok_high
[0x20];
1584 u8 a_octets_received_ok_low
[0x20];
1586 u8 a_multicast_frames_xmitted_ok_high
[0x20];
1588 u8 a_multicast_frames_xmitted_ok_low
[0x20];
1590 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
1592 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
1594 u8 a_multicast_frames_received_ok_high
[0x20];
1596 u8 a_multicast_frames_received_ok_low
[0x20];
1598 u8 a_broadcast_frames_received_ok_high
[0x20];
1600 u8 a_broadcast_frames_received_ok_low
[0x20];
1602 u8 a_in_range_length_errors_high
[0x20];
1604 u8 a_in_range_length_errors_low
[0x20];
1606 u8 a_out_of_range_length_field_high
[0x20];
1608 u8 a_out_of_range_length_field_low
[0x20];
1610 u8 a_frame_too_long_errors_high
[0x20];
1612 u8 a_frame_too_long_errors_low
[0x20];
1614 u8 a_symbol_error_during_carrier_high
[0x20];
1616 u8 a_symbol_error_during_carrier_low
[0x20];
1618 u8 a_mac_control_frames_transmitted_high
[0x20];
1620 u8 a_mac_control_frames_transmitted_low
[0x20];
1622 u8 a_mac_control_frames_received_high
[0x20];
1624 u8 a_mac_control_frames_received_low
[0x20];
1626 u8 a_unsupported_opcodes_received_high
[0x20];
1628 u8 a_unsupported_opcodes_received_low
[0x20];
1630 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
1632 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
1634 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
1636 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
1638 u8 reserved_at_4c0
[0x300];
1641 struct mlx5_ifc_cmd_inter_comp_event_bits
{
1642 u8 command_completion_vector
[0x20];
1644 u8 reserved_at_20
[0xc0];
1647 struct mlx5_ifc_stall_vl_event_bits
{
1648 u8 reserved_at_0
[0x18];
1650 u8 reserved_at_19
[0x3];
1653 u8 reserved_at_20
[0xa0];
1656 struct mlx5_ifc_db_bf_congestion_event_bits
{
1657 u8 event_subtype
[0x8];
1658 u8 reserved_at_8
[0x8];
1659 u8 congestion_level
[0x8];
1660 u8 reserved_at_18
[0x8];
1662 u8 reserved_at_20
[0xa0];
1665 struct mlx5_ifc_gpio_event_bits
{
1666 u8 reserved_at_0
[0x60];
1668 u8 gpio_event_hi
[0x20];
1670 u8 gpio_event_lo
[0x20];
1672 u8 reserved_at_a0
[0x40];
1675 struct mlx5_ifc_port_state_change_event_bits
{
1676 u8 reserved_at_0
[0x40];
1679 u8 reserved_at_44
[0x1c];
1681 u8 reserved_at_60
[0x80];
1684 struct mlx5_ifc_dropped_packet_logged_bits
{
1685 u8 reserved_at_0
[0xe0];
1689 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
1690 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
1693 struct mlx5_ifc_cq_error_bits
{
1694 u8 reserved_at_0
[0x8];
1697 u8 reserved_at_20
[0x20];
1699 u8 reserved_at_40
[0x18];
1702 u8 reserved_at_60
[0x80];
1705 struct mlx5_ifc_rdma_page_fault_event_bits
{
1706 u8 bytes_committed
[0x20];
1710 u8 reserved_at_40
[0x10];
1711 u8 packet_len
[0x10];
1713 u8 rdma_op_len
[0x20];
1717 u8 reserved_at_c0
[0x5];
1724 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
1725 u8 bytes_committed
[0x20];
1727 u8 reserved_at_20
[0x10];
1730 u8 reserved_at_40
[0x10];
1733 u8 reserved_at_60
[0x60];
1735 u8 reserved_at_c0
[0x5];
1742 struct mlx5_ifc_qp_events_bits
{
1743 u8 reserved_at_0
[0xa0];
1746 u8 reserved_at_a8
[0x18];
1748 u8 reserved_at_c0
[0x8];
1749 u8 qpn_rqn_sqn
[0x18];
1752 struct mlx5_ifc_dct_events_bits
{
1753 u8 reserved_at_0
[0xc0];
1755 u8 reserved_at_c0
[0x8];
1756 u8 dct_number
[0x18];
1759 struct mlx5_ifc_comp_event_bits
{
1760 u8 reserved_at_0
[0xc0];
1762 u8 reserved_at_c0
[0x8];
1767 MLX5_QPC_STATE_RST
= 0x0,
1768 MLX5_QPC_STATE_INIT
= 0x1,
1769 MLX5_QPC_STATE_RTR
= 0x2,
1770 MLX5_QPC_STATE_RTS
= 0x3,
1771 MLX5_QPC_STATE_SQER
= 0x4,
1772 MLX5_QPC_STATE_ERR
= 0x6,
1773 MLX5_QPC_STATE_SQD
= 0x7,
1774 MLX5_QPC_STATE_SUSPENDED
= 0x9,
1778 MLX5_QPC_ST_RC
= 0x0,
1779 MLX5_QPC_ST_UC
= 0x1,
1780 MLX5_QPC_ST_UD
= 0x2,
1781 MLX5_QPC_ST_XRC
= 0x3,
1782 MLX5_QPC_ST_DCI
= 0x5,
1783 MLX5_QPC_ST_QP0
= 0x7,
1784 MLX5_QPC_ST_QP1
= 0x8,
1785 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
1786 MLX5_QPC_ST_REG_UMR
= 0xc,
1790 MLX5_QPC_PM_STATE_ARMED
= 0x0,
1791 MLX5_QPC_PM_STATE_REARM
= 0x1,
1792 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
1793 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
1797 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
1798 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
1802 MLX5_QPC_MTU_256_BYTES
= 0x1,
1803 MLX5_QPC_MTU_512_BYTES
= 0x2,
1804 MLX5_QPC_MTU_1K_BYTES
= 0x3,
1805 MLX5_QPC_MTU_2K_BYTES
= 0x4,
1806 MLX5_QPC_MTU_4K_BYTES
= 0x5,
1807 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
1811 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
1812 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
1813 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
1814 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
1815 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
1816 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
1817 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
1818 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
1822 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
1823 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
1824 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
1828 MLX5_QPC_CS_RES_DISABLE
= 0x0,
1829 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
1830 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
1833 struct mlx5_ifc_qpc_bits
{
1835 u8 reserved_at_4
[0x4];
1837 u8 reserved_at_10
[0x3];
1839 u8 reserved_at_15
[0x7];
1840 u8 end_padding_mode
[0x2];
1841 u8 reserved_at_1e
[0x2];
1843 u8 wq_signature
[0x1];
1844 u8 block_lb_mc
[0x1];
1845 u8 atomic_like_write_en
[0x1];
1846 u8 latency_sensitive
[0x1];
1847 u8 reserved_at_24
[0x1];
1848 u8 drain_sigerr
[0x1];
1849 u8 reserved_at_26
[0x2];
1853 u8 log_msg_max
[0x5];
1854 u8 reserved_at_48
[0x1];
1855 u8 log_rq_size
[0x4];
1856 u8 log_rq_stride
[0x3];
1858 u8 log_sq_size
[0x4];
1859 u8 reserved_at_55
[0x6];
1861 u8 ulp_stateless_offload_mode
[0x4];
1863 u8 counter_set_id
[0x8];
1866 u8 reserved_at_80
[0x8];
1867 u8 user_index
[0x18];
1869 u8 reserved_at_a0
[0x3];
1870 u8 log_page_size
[0x5];
1871 u8 remote_qpn
[0x18];
1873 struct mlx5_ifc_ads_bits primary_address_path
;
1875 struct mlx5_ifc_ads_bits secondary_address_path
;
1877 u8 log_ack_req_freq
[0x4];
1878 u8 reserved_at_384
[0x4];
1879 u8 log_sra_max
[0x3];
1880 u8 reserved_at_38b
[0x2];
1881 u8 retry_count
[0x3];
1883 u8 reserved_at_393
[0x1];
1885 u8 cur_rnr_retry
[0x3];
1886 u8 cur_retry_count
[0x3];
1887 u8 reserved_at_39b
[0x5];
1889 u8 reserved_at_3a0
[0x20];
1891 u8 reserved_at_3c0
[0x8];
1892 u8 next_send_psn
[0x18];
1894 u8 reserved_at_3e0
[0x8];
1897 u8 reserved_at_400
[0x40];
1899 u8 reserved_at_440
[0x8];
1900 u8 last_acked_psn
[0x18];
1902 u8 reserved_at_460
[0x8];
1905 u8 reserved_at_480
[0x8];
1906 u8 log_rra_max
[0x3];
1907 u8 reserved_at_48b
[0x1];
1908 u8 atomic_mode
[0x4];
1912 u8 reserved_at_493
[0x1];
1913 u8 page_offset
[0x6];
1914 u8 reserved_at_49a
[0x3];
1915 u8 cd_slave_receive
[0x1];
1916 u8 cd_slave_send
[0x1];
1919 u8 reserved_at_4a0
[0x3];
1920 u8 min_rnr_nak
[0x5];
1921 u8 next_rcv_psn
[0x18];
1923 u8 reserved_at_4c0
[0x8];
1926 u8 reserved_at_4e0
[0x8];
1933 u8 reserved_at_560
[0x5];
1937 u8 reserved_at_580
[0x8];
1940 u8 hw_sq_wqebb_counter
[0x10];
1941 u8 sw_sq_wqebb_counter
[0x10];
1943 u8 hw_rq_counter
[0x20];
1945 u8 sw_rq_counter
[0x20];
1947 u8 reserved_at_600
[0x20];
1949 u8 reserved_at_620
[0xf];
1954 u8 dc_access_key
[0x40];
1956 u8 reserved_at_680
[0xc0];
1959 struct mlx5_ifc_roce_addr_layout_bits
{
1960 u8 source_l3_address
[16][0x8];
1962 u8 reserved_at_80
[0x3];
1965 u8 source_mac_47_32
[0x10];
1967 u8 source_mac_31_0
[0x20];
1969 u8 reserved_at_c0
[0x14];
1970 u8 roce_l3_type
[0x4];
1971 u8 roce_version
[0x8];
1973 u8 reserved_at_e0
[0x20];
1976 union mlx5_ifc_hca_cap_union_bits
{
1977 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
1978 struct mlx5_ifc_odp_cap_bits odp_cap
;
1979 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
1980 struct mlx5_ifc_roce_cap_bits roce_cap
;
1981 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
1982 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
1983 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
1984 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
1985 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap
;
1986 u8 reserved_at_0
[0x8000];
1990 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
1991 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
1992 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
1995 struct mlx5_ifc_flow_context_bits
{
1996 u8 reserved_at_0
[0x20];
2000 u8 reserved_at_40
[0x8];
2003 u8 reserved_at_60
[0x10];
2006 u8 reserved_at_80
[0x8];
2007 u8 destination_list_size
[0x18];
2009 u8 reserved_at_a0
[0x160];
2011 struct mlx5_ifc_fte_match_param_bits match_value
;
2013 u8 reserved_at_1200
[0x600];
2015 struct mlx5_ifc_dest_format_struct_bits destination
[0];
2019 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
2020 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
2023 struct mlx5_ifc_xrc_srqc_bits
{
2025 u8 log_xrc_srq_size
[0x4];
2026 u8 reserved_at_8
[0x18];
2028 u8 wq_signature
[0x1];
2030 u8 reserved_at_22
[0x1];
2032 u8 basic_cyclic_rcv_wqe
[0x1];
2033 u8 log_rq_stride
[0x3];
2036 u8 page_offset
[0x6];
2037 u8 reserved_at_46
[0x2];
2040 u8 reserved_at_60
[0x20];
2042 u8 user_index_equal_xrc_srqn
[0x1];
2043 u8 reserved_at_81
[0x1];
2044 u8 log_page_size
[0x6];
2045 u8 user_index
[0x18];
2047 u8 reserved_at_a0
[0x20];
2049 u8 reserved_at_c0
[0x8];
2055 u8 reserved_at_100
[0x40];
2057 u8 db_record_addr_h
[0x20];
2059 u8 db_record_addr_l
[0x1e];
2060 u8 reserved_at_17e
[0x2];
2062 u8 reserved_at_180
[0x80];
2065 struct mlx5_ifc_traffic_counter_bits
{
2071 struct mlx5_ifc_tisc_bits
{
2072 u8 reserved_at_0
[0xc];
2074 u8 reserved_at_10
[0x10];
2076 u8 reserved_at_20
[0x100];
2078 u8 reserved_at_120
[0x8];
2079 u8 transport_domain
[0x18];
2081 u8 reserved_at_140
[0x3c0];
2085 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2086 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2090 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2091 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2095 MLX5_RX_HASH_FN_NONE
= 0x0,
2096 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2097 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2101 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
= 0x1,
2102 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_
= 0x2,
2105 struct mlx5_ifc_tirc_bits
{
2106 u8 reserved_at_0
[0x20];
2109 u8 reserved_at_24
[0x1c];
2111 u8 reserved_at_40
[0x40];
2113 u8 reserved_at_80
[0x4];
2114 u8 lro_timeout_period_usecs
[0x10];
2115 u8 lro_enable_mask
[0x4];
2116 u8 lro_max_ip_payload_size
[0x8];
2118 u8 reserved_at_a0
[0x40];
2120 u8 reserved_at_e0
[0x8];
2121 u8 inline_rqn
[0x18];
2123 u8 rx_hash_symmetric
[0x1];
2124 u8 reserved_at_101
[0x1];
2125 u8 tunneled_offload_en
[0x1];
2126 u8 reserved_at_103
[0x5];
2127 u8 indirect_table
[0x18];
2130 u8 reserved_at_124
[0x2];
2131 u8 self_lb_block
[0x2];
2132 u8 transport_domain
[0x18];
2134 u8 rx_hash_toeplitz_key
[10][0x20];
2136 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2138 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2140 u8 reserved_at_2c0
[0x4c0];
2144 MLX5_SRQC_STATE_GOOD
= 0x0,
2145 MLX5_SRQC_STATE_ERROR
= 0x1,
2148 struct mlx5_ifc_srqc_bits
{
2150 u8 log_srq_size
[0x4];
2151 u8 reserved_at_8
[0x18];
2153 u8 wq_signature
[0x1];
2155 u8 reserved_at_22
[0x1];
2157 u8 reserved_at_24
[0x1];
2158 u8 log_rq_stride
[0x3];
2161 u8 page_offset
[0x6];
2162 u8 reserved_at_46
[0x2];
2165 u8 reserved_at_60
[0x20];
2167 u8 reserved_at_80
[0x2];
2168 u8 log_page_size
[0x6];
2169 u8 reserved_at_88
[0x18];
2171 u8 reserved_at_a0
[0x20];
2173 u8 reserved_at_c0
[0x8];
2179 u8 reserved_at_100
[0x40];
2183 u8 reserved_at_180
[0x80];
2187 MLX5_SQC_STATE_RST
= 0x0,
2188 MLX5_SQC_STATE_RDY
= 0x1,
2189 MLX5_SQC_STATE_ERR
= 0x3,
2192 struct mlx5_ifc_sqc_bits
{
2196 u8 flush_in_error_en
[0x1];
2197 u8 reserved_at_4
[0x4];
2199 u8 reserved_at_c
[0x14];
2201 u8 reserved_at_20
[0x8];
2202 u8 user_index
[0x18];
2204 u8 reserved_at_40
[0x8];
2207 u8 reserved_at_60
[0xa0];
2209 u8 tis_lst_sz
[0x10];
2210 u8 reserved_at_110
[0x10];
2212 u8 reserved_at_120
[0x40];
2214 u8 reserved_at_160
[0x8];
2217 struct mlx5_ifc_wq_bits wq
;
2220 struct mlx5_ifc_rqtc_bits
{
2221 u8 reserved_at_0
[0xa0];
2223 u8 reserved_at_a0
[0x10];
2224 u8 rqt_max_size
[0x10];
2226 u8 reserved_at_c0
[0x10];
2227 u8 rqt_actual_size
[0x10];
2229 u8 reserved_at_e0
[0x6a0];
2231 struct mlx5_ifc_rq_num_bits rq_num
[0];
2235 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
2236 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
2240 MLX5_RQC_STATE_RST
= 0x0,
2241 MLX5_RQC_STATE_RDY
= 0x1,
2242 MLX5_RQC_STATE_ERR
= 0x3,
2245 struct mlx5_ifc_rqc_bits
{
2247 u8 reserved_at_1
[0x2];
2249 u8 mem_rq_type
[0x4];
2251 u8 reserved_at_c
[0x1];
2252 u8 flush_in_error_en
[0x1];
2253 u8 reserved_at_e
[0x12];
2255 u8 reserved_at_20
[0x8];
2256 u8 user_index
[0x18];
2258 u8 reserved_at_40
[0x8];
2261 u8 counter_set_id
[0x8];
2262 u8 reserved_at_68
[0x18];
2264 u8 reserved_at_80
[0x8];
2267 u8 reserved_at_a0
[0xe0];
2269 struct mlx5_ifc_wq_bits wq
;
2273 MLX5_RMPC_STATE_RDY
= 0x1,
2274 MLX5_RMPC_STATE_ERR
= 0x3,
2277 struct mlx5_ifc_rmpc_bits
{
2278 u8 reserved_at_0
[0x8];
2280 u8 reserved_at_c
[0x14];
2282 u8 basic_cyclic_rcv_wqe
[0x1];
2283 u8 reserved_at_21
[0x1f];
2285 u8 reserved_at_40
[0x140];
2287 struct mlx5_ifc_wq_bits wq
;
2290 struct mlx5_ifc_nic_vport_context_bits
{
2291 u8 reserved_at_0
[0x1f];
2294 u8 arm_change_event
[0x1];
2295 u8 reserved_at_21
[0x1a];
2296 u8 event_on_mtu
[0x1];
2297 u8 event_on_promisc_change
[0x1];
2298 u8 event_on_vlan_change
[0x1];
2299 u8 event_on_mc_address_change
[0x1];
2300 u8 event_on_uc_address_change
[0x1];
2302 u8 reserved_at_40
[0xf0];
2306 u8 system_image_guid
[0x40];
2310 u8 reserved_at_200
[0x140];
2311 u8 qkey_violation_counter
[0x10];
2312 u8 reserved_at_350
[0x430];
2316 u8 promisc_all
[0x1];
2317 u8 reserved_at_783
[0x2];
2318 u8 allowed_list_type
[0x3];
2319 u8 reserved_at_788
[0xc];
2320 u8 allowed_list_size
[0xc];
2322 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
2324 u8 reserved_at_7e0
[0x20];
2326 u8 current_uc_mac_address
[0][0x40];
2330 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
2331 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
2332 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
2335 struct mlx5_ifc_mkc_bits
{
2336 u8 reserved_at_0
[0x1];
2338 u8 reserved_at_2
[0xd];
2339 u8 small_fence_on_rdma_read_response
[0x1];
2346 u8 access_mode
[0x2];
2347 u8 reserved_at_18
[0x8];
2352 u8 reserved_at_40
[0x20];
2357 u8 reserved_at_63
[0x2];
2358 u8 expected_sigerr_count
[0x1];
2359 u8 reserved_at_66
[0x1];
2363 u8 start_addr
[0x40];
2367 u8 bsf_octword_size
[0x20];
2369 u8 reserved_at_120
[0x80];
2371 u8 translations_octword_size
[0x20];
2373 u8 reserved_at_1c0
[0x1b];
2374 u8 log_page_size
[0x5];
2376 u8 reserved_at_1e0
[0x20];
2379 struct mlx5_ifc_pkey_bits
{
2380 u8 reserved_at_0
[0x10];
2384 struct mlx5_ifc_array128_auto_bits
{
2385 u8 array128_auto
[16][0x8];
2388 struct mlx5_ifc_hca_vport_context_bits
{
2389 u8 field_select
[0x20];
2391 u8 reserved_at_20
[0xe0];
2393 u8 sm_virt_aware
[0x1];
2396 u8 grh_required
[0x1];
2397 u8 reserved_at_104
[0xc];
2398 u8 port_physical_state
[0x4];
2399 u8 vport_state_policy
[0x4];
2401 u8 vport_state
[0x4];
2403 u8 reserved_at_120
[0x20];
2405 u8 system_image_guid
[0x40];
2413 u8 cap_mask1_field_select
[0x20];
2417 u8 cap_mask2_field_select
[0x20];
2419 u8 reserved_at_280
[0x80];
2422 u8 reserved_at_310
[0x4];
2423 u8 init_type_reply
[0x4];
2425 u8 subnet_timeout
[0x5];
2429 u8 reserved_at_334
[0xc];
2431 u8 qkey_violation_counter
[0x10];
2432 u8 pkey_violation_counter
[0x10];
2434 u8 reserved_at_360
[0xca0];
2437 struct mlx5_ifc_esw_vport_context_bits
{
2438 u8 reserved_at_0
[0x3];
2439 u8 vport_svlan_strip
[0x1];
2440 u8 vport_cvlan_strip
[0x1];
2441 u8 vport_svlan_insert
[0x1];
2442 u8 vport_cvlan_insert
[0x2];
2443 u8 reserved_at_8
[0x18];
2445 u8 reserved_at_20
[0x20];
2454 u8 reserved_at_60
[0x7a0];
2458 MLX5_EQC_STATUS_OK
= 0x0,
2459 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
2463 MLX5_EQC_ST_ARMED
= 0x9,
2464 MLX5_EQC_ST_FIRED
= 0xa,
2467 struct mlx5_ifc_eqc_bits
{
2469 u8 reserved_at_4
[0x9];
2472 u8 reserved_at_f
[0x5];
2474 u8 reserved_at_18
[0x8];
2476 u8 reserved_at_20
[0x20];
2478 u8 reserved_at_40
[0x14];
2479 u8 page_offset
[0x6];
2480 u8 reserved_at_5a
[0x6];
2482 u8 reserved_at_60
[0x3];
2483 u8 log_eq_size
[0x5];
2486 u8 reserved_at_80
[0x20];
2488 u8 reserved_at_a0
[0x18];
2491 u8 reserved_at_c0
[0x3];
2492 u8 log_page_size
[0x5];
2493 u8 reserved_at_c8
[0x18];
2495 u8 reserved_at_e0
[0x60];
2497 u8 reserved_at_140
[0x8];
2498 u8 consumer_counter
[0x18];
2500 u8 reserved_at_160
[0x8];
2501 u8 producer_counter
[0x18];
2503 u8 reserved_at_180
[0x80];
2507 MLX5_DCTC_STATE_ACTIVE
= 0x0,
2508 MLX5_DCTC_STATE_DRAINING
= 0x1,
2509 MLX5_DCTC_STATE_DRAINED
= 0x2,
2513 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
2514 MLX5_DCTC_CS_RES_NA
= 0x1,
2515 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
2519 MLX5_DCTC_MTU_256_BYTES
= 0x1,
2520 MLX5_DCTC_MTU_512_BYTES
= 0x2,
2521 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
2522 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
2523 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
2526 struct mlx5_ifc_dctc_bits
{
2527 u8 reserved_at_0
[0x4];
2529 u8 reserved_at_8
[0x18];
2531 u8 reserved_at_20
[0x8];
2532 u8 user_index
[0x18];
2534 u8 reserved_at_40
[0x8];
2537 u8 counter_set_id
[0x8];
2538 u8 atomic_mode
[0x4];
2542 u8 atomic_like_write_en
[0x1];
2543 u8 latency_sensitive
[0x1];
2546 u8 reserved_at_73
[0xd];
2548 u8 reserved_at_80
[0x8];
2550 u8 reserved_at_90
[0x3];
2551 u8 min_rnr_nak
[0x5];
2552 u8 reserved_at_98
[0x8];
2554 u8 reserved_at_a0
[0x8];
2557 u8 reserved_at_c0
[0x8];
2561 u8 reserved_at_e8
[0x4];
2562 u8 flow_label
[0x14];
2564 u8 dc_access_key
[0x40];
2566 u8 reserved_at_140
[0x5];
2569 u8 pkey_index
[0x10];
2571 u8 reserved_at_160
[0x8];
2572 u8 my_addr_index
[0x8];
2573 u8 reserved_at_170
[0x8];
2576 u8 dc_access_key_violation_count
[0x20];
2578 u8 reserved_at_1a0
[0x14];
2584 u8 reserved_at_1c0
[0x40];
2588 MLX5_CQC_STATUS_OK
= 0x0,
2589 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
2590 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
2594 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
2595 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
2599 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
2600 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
2601 MLX5_CQC_ST_FIRED
= 0xa,
2604 struct mlx5_ifc_cqc_bits
{
2606 u8 reserved_at_4
[0x4];
2609 u8 reserved_at_c
[0x1];
2610 u8 scqe_break_moderation_en
[0x1];
2612 u8 reserved_at_f
[0x2];
2614 u8 mini_cqe_res_format
[0x2];
2616 u8 reserved_at_18
[0x8];
2618 u8 reserved_at_20
[0x20];
2620 u8 reserved_at_40
[0x14];
2621 u8 page_offset
[0x6];
2622 u8 reserved_at_5a
[0x6];
2624 u8 reserved_at_60
[0x3];
2625 u8 log_cq_size
[0x5];
2628 u8 reserved_at_80
[0x4];
2630 u8 cq_max_count
[0x10];
2632 u8 reserved_at_a0
[0x18];
2635 u8 reserved_at_c0
[0x3];
2636 u8 log_page_size
[0x5];
2637 u8 reserved_at_c8
[0x18];
2639 u8 reserved_at_e0
[0x20];
2641 u8 reserved_at_100
[0x8];
2642 u8 last_notified_index
[0x18];
2644 u8 reserved_at_120
[0x8];
2645 u8 last_solicit_index
[0x18];
2647 u8 reserved_at_140
[0x8];
2648 u8 consumer_counter
[0x18];
2650 u8 reserved_at_160
[0x8];
2651 u8 producer_counter
[0x18];
2653 u8 reserved_at_180
[0x40];
2658 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
2659 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
2660 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
2661 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
2662 u8 reserved_at_0
[0x800];
2665 struct mlx5_ifc_query_adapter_param_block_bits
{
2666 u8 reserved_at_0
[0xc0];
2668 u8 reserved_at_c0
[0x8];
2669 u8 ieee_vendor_id
[0x18];
2671 u8 reserved_at_e0
[0x10];
2672 u8 vsd_vendor_id
[0x10];
2676 u8 vsd_contd_psid
[16][0x8];
2679 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
2680 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
2681 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
2682 u8 reserved_at_0
[0x20];
2685 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
2686 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
2687 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
2688 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
2689 u8 reserved_at_0
[0x20];
2692 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
2693 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
2694 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
2695 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
2696 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
2697 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
2698 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
2699 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
2700 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
2701 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
2702 u8 reserved_at_0
[0x7c0];
2705 union mlx5_ifc_event_auto_bits
{
2706 struct mlx5_ifc_comp_event_bits comp_event
;
2707 struct mlx5_ifc_dct_events_bits dct_events
;
2708 struct mlx5_ifc_qp_events_bits qp_events
;
2709 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
2710 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
2711 struct mlx5_ifc_cq_error_bits cq_error
;
2712 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
2713 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
2714 struct mlx5_ifc_gpio_event_bits gpio_event
;
2715 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
2716 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
2717 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
2718 u8 reserved_at_0
[0xe0];
2721 struct mlx5_ifc_health_buffer_bits
{
2722 u8 reserved_at_0
[0x100];
2724 u8 assert_existptr
[0x20];
2726 u8 assert_callra
[0x20];
2728 u8 reserved_at_140
[0x40];
2730 u8 fw_version
[0x20];
2734 u8 reserved_at_1c0
[0x20];
2736 u8 irisc_index
[0x8];
2741 struct mlx5_ifc_register_loopback_control_bits
{
2743 u8 reserved_at_1
[0x7];
2745 u8 reserved_at_10
[0x10];
2747 u8 reserved_at_20
[0x60];
2750 struct mlx5_ifc_teardown_hca_out_bits
{
2752 u8 reserved_at_8
[0x18];
2756 u8 reserved_at_40
[0x40];
2760 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
2761 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE
= 0x1,
2764 struct mlx5_ifc_teardown_hca_in_bits
{
2766 u8 reserved_at_10
[0x10];
2768 u8 reserved_at_20
[0x10];
2771 u8 reserved_at_40
[0x10];
2774 u8 reserved_at_60
[0x20];
2777 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
2779 u8 reserved_at_8
[0x18];
2783 u8 reserved_at_40
[0x40];
2786 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
2788 u8 reserved_at_10
[0x10];
2790 u8 reserved_at_20
[0x10];
2793 u8 reserved_at_40
[0x8];
2796 u8 reserved_at_60
[0x20];
2798 u8 opt_param_mask
[0x20];
2800 u8 reserved_at_a0
[0x20];
2802 struct mlx5_ifc_qpc_bits qpc
;
2804 u8 reserved_at_800
[0x80];
2807 struct mlx5_ifc_sqd2rts_qp_out_bits
{
2809 u8 reserved_at_8
[0x18];
2813 u8 reserved_at_40
[0x40];
2816 struct mlx5_ifc_sqd2rts_qp_in_bits
{
2818 u8 reserved_at_10
[0x10];
2820 u8 reserved_at_20
[0x10];
2823 u8 reserved_at_40
[0x8];
2826 u8 reserved_at_60
[0x20];
2828 u8 opt_param_mask
[0x20];
2830 u8 reserved_at_a0
[0x20];
2832 struct mlx5_ifc_qpc_bits qpc
;
2834 u8 reserved_at_800
[0x80];
2837 struct mlx5_ifc_set_roce_address_out_bits
{
2839 u8 reserved_at_8
[0x18];
2843 u8 reserved_at_40
[0x40];
2846 struct mlx5_ifc_set_roce_address_in_bits
{
2848 u8 reserved_at_10
[0x10];
2850 u8 reserved_at_20
[0x10];
2853 u8 roce_address_index
[0x10];
2854 u8 reserved_at_50
[0x10];
2856 u8 reserved_at_60
[0x20];
2858 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
2861 struct mlx5_ifc_set_mad_demux_out_bits
{
2863 u8 reserved_at_8
[0x18];
2867 u8 reserved_at_40
[0x40];
2871 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
2872 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
2875 struct mlx5_ifc_set_mad_demux_in_bits
{
2877 u8 reserved_at_10
[0x10];
2879 u8 reserved_at_20
[0x10];
2882 u8 reserved_at_40
[0x20];
2884 u8 reserved_at_60
[0x6];
2886 u8 reserved_at_68
[0x18];
2889 struct mlx5_ifc_set_l2_table_entry_out_bits
{
2891 u8 reserved_at_8
[0x18];
2895 u8 reserved_at_40
[0x40];
2898 struct mlx5_ifc_set_l2_table_entry_in_bits
{
2900 u8 reserved_at_10
[0x10];
2902 u8 reserved_at_20
[0x10];
2905 u8 reserved_at_40
[0x60];
2907 u8 reserved_at_a0
[0x8];
2908 u8 table_index
[0x18];
2910 u8 reserved_at_c0
[0x20];
2912 u8 reserved_at_e0
[0x13];
2916 struct mlx5_ifc_mac_address_layout_bits mac_address
;
2918 u8 reserved_at_140
[0xc0];
2921 struct mlx5_ifc_set_issi_out_bits
{
2923 u8 reserved_at_8
[0x18];
2927 u8 reserved_at_40
[0x40];
2930 struct mlx5_ifc_set_issi_in_bits
{
2932 u8 reserved_at_10
[0x10];
2934 u8 reserved_at_20
[0x10];
2937 u8 reserved_at_40
[0x10];
2938 u8 current_issi
[0x10];
2940 u8 reserved_at_60
[0x20];
2943 struct mlx5_ifc_set_hca_cap_out_bits
{
2945 u8 reserved_at_8
[0x18];
2949 u8 reserved_at_40
[0x40];
2952 struct mlx5_ifc_set_hca_cap_in_bits
{
2954 u8 reserved_at_10
[0x10];
2956 u8 reserved_at_20
[0x10];
2959 u8 reserved_at_40
[0x40];
2961 union mlx5_ifc_hca_cap_union_bits capability
;
2965 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
2966 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
2967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
2968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
2971 struct mlx5_ifc_set_fte_out_bits
{
2973 u8 reserved_at_8
[0x18];
2977 u8 reserved_at_40
[0x40];
2980 struct mlx5_ifc_set_fte_in_bits
{
2982 u8 reserved_at_10
[0x10];
2984 u8 reserved_at_20
[0x10];
2987 u8 reserved_at_40
[0x40];
2990 u8 reserved_at_88
[0x18];
2992 u8 reserved_at_a0
[0x8];
2995 u8 reserved_at_c0
[0x18];
2996 u8 modify_enable_mask
[0x8];
2998 u8 reserved_at_e0
[0x20];
3000 u8 flow_index
[0x20];
3002 u8 reserved_at_120
[0xe0];
3004 struct mlx5_ifc_flow_context_bits flow_context
;
3007 struct mlx5_ifc_rts2rts_qp_out_bits
{
3009 u8 reserved_at_8
[0x18];
3013 u8 reserved_at_40
[0x40];
3016 struct mlx5_ifc_rts2rts_qp_in_bits
{
3018 u8 reserved_at_10
[0x10];
3020 u8 reserved_at_20
[0x10];
3023 u8 reserved_at_40
[0x8];
3026 u8 reserved_at_60
[0x20];
3028 u8 opt_param_mask
[0x20];
3030 u8 reserved_at_a0
[0x20];
3032 struct mlx5_ifc_qpc_bits qpc
;
3034 u8 reserved_at_800
[0x80];
3037 struct mlx5_ifc_rtr2rts_qp_out_bits
{
3039 u8 reserved_at_8
[0x18];
3043 u8 reserved_at_40
[0x40];
3046 struct mlx5_ifc_rtr2rts_qp_in_bits
{
3048 u8 reserved_at_10
[0x10];
3050 u8 reserved_at_20
[0x10];
3053 u8 reserved_at_40
[0x8];
3056 u8 reserved_at_60
[0x20];
3058 u8 opt_param_mask
[0x20];
3060 u8 reserved_at_a0
[0x20];
3062 struct mlx5_ifc_qpc_bits qpc
;
3064 u8 reserved_at_800
[0x80];
3067 struct mlx5_ifc_rst2init_qp_out_bits
{
3069 u8 reserved_at_8
[0x18];
3073 u8 reserved_at_40
[0x40];
3076 struct mlx5_ifc_rst2init_qp_in_bits
{
3078 u8 reserved_at_10
[0x10];
3080 u8 reserved_at_20
[0x10];
3083 u8 reserved_at_40
[0x8];
3086 u8 reserved_at_60
[0x20];
3088 u8 opt_param_mask
[0x20];
3090 u8 reserved_at_a0
[0x20];
3092 struct mlx5_ifc_qpc_bits qpc
;
3094 u8 reserved_at_800
[0x80];
3097 struct mlx5_ifc_query_xrc_srq_out_bits
{
3099 u8 reserved_at_8
[0x18];
3103 u8 reserved_at_40
[0x40];
3105 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
3107 u8 reserved_at_280
[0x600];
3112 struct mlx5_ifc_query_xrc_srq_in_bits
{
3114 u8 reserved_at_10
[0x10];
3116 u8 reserved_at_20
[0x10];
3119 u8 reserved_at_40
[0x8];
3122 u8 reserved_at_60
[0x20];
3126 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
3127 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
3130 struct mlx5_ifc_query_vport_state_out_bits
{
3132 u8 reserved_at_8
[0x18];
3136 u8 reserved_at_40
[0x20];
3138 u8 reserved_at_60
[0x18];
3139 u8 admin_state
[0x4];
3144 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
= 0x0,
3145 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT
= 0x1,
3148 struct mlx5_ifc_query_vport_state_in_bits
{
3150 u8 reserved_at_10
[0x10];
3152 u8 reserved_at_20
[0x10];
3155 u8 other_vport
[0x1];
3156 u8 reserved_at_41
[0xf];
3157 u8 vport_number
[0x10];
3159 u8 reserved_at_60
[0x20];
3162 struct mlx5_ifc_query_vport_counter_out_bits
{
3164 u8 reserved_at_8
[0x18];
3168 u8 reserved_at_40
[0x40];
3170 struct mlx5_ifc_traffic_counter_bits received_errors
;
3172 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
3174 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
3176 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
3178 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
3180 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
3182 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
3184 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
3186 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
3188 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
3190 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
3192 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
3194 u8 reserved_at_680
[0xa00];
3198 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
3201 struct mlx5_ifc_query_vport_counter_in_bits
{
3203 u8 reserved_at_10
[0x10];
3205 u8 reserved_at_20
[0x10];
3208 u8 other_vport
[0x1];
3209 u8 reserved_at_41
[0xb];
3211 u8 vport_number
[0x10];
3213 u8 reserved_at_60
[0x60];
3216 u8 reserved_at_c1
[0x1f];
3218 u8 reserved_at_e0
[0x20];
3221 struct mlx5_ifc_query_tis_out_bits
{
3223 u8 reserved_at_8
[0x18];
3227 u8 reserved_at_40
[0x40];
3229 struct mlx5_ifc_tisc_bits tis_context
;
3232 struct mlx5_ifc_query_tis_in_bits
{
3234 u8 reserved_at_10
[0x10];
3236 u8 reserved_at_20
[0x10];
3239 u8 reserved_at_40
[0x8];
3242 u8 reserved_at_60
[0x20];
3245 struct mlx5_ifc_query_tir_out_bits
{
3247 u8 reserved_at_8
[0x18];
3251 u8 reserved_at_40
[0xc0];
3253 struct mlx5_ifc_tirc_bits tir_context
;
3256 struct mlx5_ifc_query_tir_in_bits
{
3258 u8 reserved_at_10
[0x10];
3260 u8 reserved_at_20
[0x10];
3263 u8 reserved_at_40
[0x8];
3266 u8 reserved_at_60
[0x20];
3269 struct mlx5_ifc_query_srq_out_bits
{
3271 u8 reserved_at_8
[0x18];
3275 u8 reserved_at_40
[0x40];
3277 struct mlx5_ifc_srqc_bits srq_context_entry
;
3279 u8 reserved_at_280
[0x600];
3284 struct mlx5_ifc_query_srq_in_bits
{
3286 u8 reserved_at_10
[0x10];
3288 u8 reserved_at_20
[0x10];
3291 u8 reserved_at_40
[0x8];
3294 u8 reserved_at_60
[0x20];
3297 struct mlx5_ifc_query_sq_out_bits
{
3299 u8 reserved_at_8
[0x18];
3303 u8 reserved_at_40
[0xc0];
3305 struct mlx5_ifc_sqc_bits sq_context
;
3308 struct mlx5_ifc_query_sq_in_bits
{
3310 u8 reserved_at_10
[0x10];
3312 u8 reserved_at_20
[0x10];
3315 u8 reserved_at_40
[0x8];
3318 u8 reserved_at_60
[0x20];
3321 struct mlx5_ifc_query_special_contexts_out_bits
{
3323 u8 reserved_at_8
[0x18];
3327 u8 reserved_at_40
[0x20];
3332 struct mlx5_ifc_query_special_contexts_in_bits
{
3334 u8 reserved_at_10
[0x10];
3336 u8 reserved_at_20
[0x10];
3339 u8 reserved_at_40
[0x40];
3342 struct mlx5_ifc_query_rqt_out_bits
{
3344 u8 reserved_at_8
[0x18];
3348 u8 reserved_at_40
[0xc0];
3350 struct mlx5_ifc_rqtc_bits rqt_context
;
3353 struct mlx5_ifc_query_rqt_in_bits
{
3355 u8 reserved_at_10
[0x10];
3357 u8 reserved_at_20
[0x10];
3360 u8 reserved_at_40
[0x8];
3363 u8 reserved_at_60
[0x20];
3366 struct mlx5_ifc_query_rq_out_bits
{
3368 u8 reserved_at_8
[0x18];
3372 u8 reserved_at_40
[0xc0];
3374 struct mlx5_ifc_rqc_bits rq_context
;
3377 struct mlx5_ifc_query_rq_in_bits
{
3379 u8 reserved_at_10
[0x10];
3381 u8 reserved_at_20
[0x10];
3384 u8 reserved_at_40
[0x8];
3387 u8 reserved_at_60
[0x20];
3390 struct mlx5_ifc_query_roce_address_out_bits
{
3392 u8 reserved_at_8
[0x18];
3396 u8 reserved_at_40
[0x40];
3398 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3401 struct mlx5_ifc_query_roce_address_in_bits
{
3403 u8 reserved_at_10
[0x10];
3405 u8 reserved_at_20
[0x10];
3408 u8 roce_address_index
[0x10];
3409 u8 reserved_at_50
[0x10];
3411 u8 reserved_at_60
[0x20];
3414 struct mlx5_ifc_query_rmp_out_bits
{
3416 u8 reserved_at_8
[0x18];
3420 u8 reserved_at_40
[0xc0];
3422 struct mlx5_ifc_rmpc_bits rmp_context
;
3425 struct mlx5_ifc_query_rmp_in_bits
{
3427 u8 reserved_at_10
[0x10];
3429 u8 reserved_at_20
[0x10];
3432 u8 reserved_at_40
[0x8];
3435 u8 reserved_at_60
[0x20];
3438 struct mlx5_ifc_query_qp_out_bits
{
3440 u8 reserved_at_8
[0x18];
3444 u8 reserved_at_40
[0x40];
3446 u8 opt_param_mask
[0x20];
3448 u8 reserved_at_a0
[0x20];
3450 struct mlx5_ifc_qpc_bits qpc
;
3452 u8 reserved_at_800
[0x80];
3457 struct mlx5_ifc_query_qp_in_bits
{
3459 u8 reserved_at_10
[0x10];
3461 u8 reserved_at_20
[0x10];
3464 u8 reserved_at_40
[0x8];
3467 u8 reserved_at_60
[0x20];
3470 struct mlx5_ifc_query_q_counter_out_bits
{
3472 u8 reserved_at_8
[0x18];
3476 u8 reserved_at_40
[0x40];
3478 u8 rx_write_requests
[0x20];
3480 u8 reserved_at_a0
[0x20];
3482 u8 rx_read_requests
[0x20];
3484 u8 reserved_at_e0
[0x20];
3486 u8 rx_atomic_requests
[0x20];
3488 u8 reserved_at_120
[0x20];
3490 u8 rx_dct_connect
[0x20];
3492 u8 reserved_at_160
[0x20];
3494 u8 out_of_buffer
[0x20];
3496 u8 reserved_at_1a0
[0x20];
3498 u8 out_of_sequence
[0x20];
3500 u8 reserved_at_1e0
[0x620];
3503 struct mlx5_ifc_query_q_counter_in_bits
{
3505 u8 reserved_at_10
[0x10];
3507 u8 reserved_at_20
[0x10];
3510 u8 reserved_at_40
[0x80];
3513 u8 reserved_at_c1
[0x1f];
3515 u8 reserved_at_e0
[0x18];
3516 u8 counter_set_id
[0x8];
3519 struct mlx5_ifc_query_pages_out_bits
{
3521 u8 reserved_at_8
[0x18];
3525 u8 reserved_at_40
[0x10];
3526 u8 function_id
[0x10];
3532 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
3533 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
3534 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
3537 struct mlx5_ifc_query_pages_in_bits
{
3539 u8 reserved_at_10
[0x10];
3541 u8 reserved_at_20
[0x10];
3544 u8 reserved_at_40
[0x10];
3545 u8 function_id
[0x10];
3547 u8 reserved_at_60
[0x20];
3550 struct mlx5_ifc_query_nic_vport_context_out_bits
{
3552 u8 reserved_at_8
[0x18];
3556 u8 reserved_at_40
[0x40];
3558 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
3561 struct mlx5_ifc_query_nic_vport_context_in_bits
{
3563 u8 reserved_at_10
[0x10];
3565 u8 reserved_at_20
[0x10];
3568 u8 other_vport
[0x1];
3569 u8 reserved_at_41
[0xf];
3570 u8 vport_number
[0x10];
3572 u8 reserved_at_60
[0x5];
3573 u8 allowed_list_type
[0x3];
3574 u8 reserved_at_68
[0x18];
3577 struct mlx5_ifc_query_mkey_out_bits
{
3579 u8 reserved_at_8
[0x18];
3583 u8 reserved_at_40
[0x40];
3585 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
3587 u8 reserved_at_280
[0x600];
3589 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
3591 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
3594 struct mlx5_ifc_query_mkey_in_bits
{
3596 u8 reserved_at_10
[0x10];
3598 u8 reserved_at_20
[0x10];
3601 u8 reserved_at_40
[0x8];
3602 u8 mkey_index
[0x18];
3605 u8 reserved_at_61
[0x1f];
3608 struct mlx5_ifc_query_mad_demux_out_bits
{
3610 u8 reserved_at_8
[0x18];
3614 u8 reserved_at_40
[0x40];
3616 u8 mad_dumux_parameters_block
[0x20];
3619 struct mlx5_ifc_query_mad_demux_in_bits
{
3621 u8 reserved_at_10
[0x10];
3623 u8 reserved_at_20
[0x10];
3626 u8 reserved_at_40
[0x40];
3629 struct mlx5_ifc_query_l2_table_entry_out_bits
{
3631 u8 reserved_at_8
[0x18];
3635 u8 reserved_at_40
[0xa0];
3637 u8 reserved_at_e0
[0x13];
3641 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3643 u8 reserved_at_140
[0xc0];
3646 struct mlx5_ifc_query_l2_table_entry_in_bits
{
3648 u8 reserved_at_10
[0x10];
3650 u8 reserved_at_20
[0x10];
3653 u8 reserved_at_40
[0x60];
3655 u8 reserved_at_a0
[0x8];
3656 u8 table_index
[0x18];
3658 u8 reserved_at_c0
[0x140];
3661 struct mlx5_ifc_query_issi_out_bits
{
3663 u8 reserved_at_8
[0x18];
3667 u8 reserved_at_40
[0x10];
3668 u8 current_issi
[0x10];
3670 u8 reserved_at_60
[0xa0];
3672 u8 reserved_at_100
[76][0x8];
3673 u8 supported_issi_dw0
[0x20];
3676 struct mlx5_ifc_query_issi_in_bits
{
3678 u8 reserved_at_10
[0x10];
3680 u8 reserved_at_20
[0x10];
3683 u8 reserved_at_40
[0x40];
3686 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
3688 u8 reserved_at_8
[0x18];
3692 u8 reserved_at_40
[0x40];
3694 struct mlx5_ifc_pkey_bits pkey
[0];
3697 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
3699 u8 reserved_at_10
[0x10];
3701 u8 reserved_at_20
[0x10];
3704 u8 other_vport
[0x1];
3705 u8 reserved_at_41
[0xb];
3707 u8 vport_number
[0x10];
3709 u8 reserved_at_60
[0x10];
3710 u8 pkey_index
[0x10];
3714 MLX5_HCA_VPORT_SEL_PORT_GUID
= 1 << 0,
3715 MLX5_HCA_VPORT_SEL_NODE_GUID
= 1 << 1,
3716 MLX5_HCA_VPORT_SEL_STATE_POLICY
= 1 << 2,
3719 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
3721 u8 reserved_at_8
[0x18];
3725 u8 reserved_at_40
[0x20];
3728 u8 reserved_at_70
[0x10];
3730 struct mlx5_ifc_array128_auto_bits gid
[0];
3733 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
3735 u8 reserved_at_10
[0x10];
3737 u8 reserved_at_20
[0x10];
3740 u8 other_vport
[0x1];
3741 u8 reserved_at_41
[0xb];
3743 u8 vport_number
[0x10];
3745 u8 reserved_at_60
[0x10];
3749 struct mlx5_ifc_query_hca_vport_context_out_bits
{
3751 u8 reserved_at_8
[0x18];
3755 u8 reserved_at_40
[0x40];
3757 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
3760 struct mlx5_ifc_query_hca_vport_context_in_bits
{
3762 u8 reserved_at_10
[0x10];
3764 u8 reserved_at_20
[0x10];
3767 u8 other_vport
[0x1];
3768 u8 reserved_at_41
[0xb];
3770 u8 vport_number
[0x10];
3772 u8 reserved_at_60
[0x20];
3775 struct mlx5_ifc_query_hca_cap_out_bits
{
3777 u8 reserved_at_8
[0x18];
3781 u8 reserved_at_40
[0x40];
3783 union mlx5_ifc_hca_cap_union_bits capability
;
3786 struct mlx5_ifc_query_hca_cap_in_bits
{
3788 u8 reserved_at_10
[0x10];
3790 u8 reserved_at_20
[0x10];
3793 u8 reserved_at_40
[0x40];
3796 struct mlx5_ifc_query_flow_table_out_bits
{
3798 u8 reserved_at_8
[0x18];
3802 u8 reserved_at_40
[0x80];
3804 u8 reserved_at_c0
[0x8];
3806 u8 reserved_at_d0
[0x8];
3809 u8 reserved_at_e0
[0x120];
3812 struct mlx5_ifc_query_flow_table_in_bits
{
3814 u8 reserved_at_10
[0x10];
3816 u8 reserved_at_20
[0x10];
3819 u8 reserved_at_40
[0x40];
3822 u8 reserved_at_88
[0x18];
3824 u8 reserved_at_a0
[0x8];
3827 u8 reserved_at_c0
[0x140];
3830 struct mlx5_ifc_query_fte_out_bits
{
3832 u8 reserved_at_8
[0x18];
3836 u8 reserved_at_40
[0x1c0];
3838 struct mlx5_ifc_flow_context_bits flow_context
;
3841 struct mlx5_ifc_query_fte_in_bits
{
3843 u8 reserved_at_10
[0x10];
3845 u8 reserved_at_20
[0x10];
3848 u8 reserved_at_40
[0x40];
3851 u8 reserved_at_88
[0x18];
3853 u8 reserved_at_a0
[0x8];
3856 u8 reserved_at_c0
[0x40];
3858 u8 flow_index
[0x20];
3860 u8 reserved_at_120
[0xe0];
3864 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
3865 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
3866 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
3869 struct mlx5_ifc_query_flow_group_out_bits
{
3871 u8 reserved_at_8
[0x18];
3875 u8 reserved_at_40
[0xa0];
3877 u8 start_flow_index
[0x20];
3879 u8 reserved_at_100
[0x20];
3881 u8 end_flow_index
[0x20];
3883 u8 reserved_at_140
[0xa0];
3885 u8 reserved_at_1e0
[0x18];
3886 u8 match_criteria_enable
[0x8];
3888 struct mlx5_ifc_fte_match_param_bits match_criteria
;
3890 u8 reserved_at_1200
[0xe00];
3893 struct mlx5_ifc_query_flow_group_in_bits
{
3895 u8 reserved_at_10
[0x10];
3897 u8 reserved_at_20
[0x10];
3900 u8 reserved_at_40
[0x40];
3903 u8 reserved_at_88
[0x18];
3905 u8 reserved_at_a0
[0x8];
3910 u8 reserved_at_e0
[0x120];
3913 struct mlx5_ifc_query_esw_vport_context_out_bits
{
3915 u8 reserved_at_8
[0x18];
3919 u8 reserved_at_40
[0x40];
3921 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
3924 struct mlx5_ifc_query_esw_vport_context_in_bits
{
3926 u8 reserved_at_10
[0x10];
3928 u8 reserved_at_20
[0x10];
3931 u8 other_vport
[0x1];
3932 u8 reserved_at_41
[0xf];
3933 u8 vport_number
[0x10];
3935 u8 reserved_at_60
[0x20];
3938 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
3940 u8 reserved_at_8
[0x18];
3944 u8 reserved_at_40
[0x40];
3947 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
3948 u8 reserved_at_0
[0x1c];
3949 u8 vport_cvlan_insert
[0x1];
3950 u8 vport_svlan_insert
[0x1];
3951 u8 vport_cvlan_strip
[0x1];
3952 u8 vport_svlan_strip
[0x1];
3955 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
3957 u8 reserved_at_10
[0x10];
3959 u8 reserved_at_20
[0x10];
3962 u8 other_vport
[0x1];
3963 u8 reserved_at_41
[0xf];
3964 u8 vport_number
[0x10];
3966 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
3968 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
3971 struct mlx5_ifc_query_eq_out_bits
{
3973 u8 reserved_at_8
[0x18];
3977 u8 reserved_at_40
[0x40];
3979 struct mlx5_ifc_eqc_bits eq_context_entry
;
3981 u8 reserved_at_280
[0x40];
3983 u8 event_bitmask
[0x40];
3985 u8 reserved_at_300
[0x580];
3990 struct mlx5_ifc_query_eq_in_bits
{
3992 u8 reserved_at_10
[0x10];
3994 u8 reserved_at_20
[0x10];
3997 u8 reserved_at_40
[0x18];
4000 u8 reserved_at_60
[0x20];
4003 struct mlx5_ifc_query_dct_out_bits
{
4005 u8 reserved_at_8
[0x18];
4009 u8 reserved_at_40
[0x40];
4011 struct mlx5_ifc_dctc_bits dct_context_entry
;
4013 u8 reserved_at_280
[0x180];
4016 struct mlx5_ifc_query_dct_in_bits
{
4018 u8 reserved_at_10
[0x10];
4020 u8 reserved_at_20
[0x10];
4023 u8 reserved_at_40
[0x8];
4026 u8 reserved_at_60
[0x20];
4029 struct mlx5_ifc_query_cq_out_bits
{
4031 u8 reserved_at_8
[0x18];
4035 u8 reserved_at_40
[0x40];
4037 struct mlx5_ifc_cqc_bits cq_context
;
4039 u8 reserved_at_280
[0x600];
4044 struct mlx5_ifc_query_cq_in_bits
{
4046 u8 reserved_at_10
[0x10];
4048 u8 reserved_at_20
[0x10];
4051 u8 reserved_at_40
[0x8];
4054 u8 reserved_at_60
[0x20];
4057 struct mlx5_ifc_query_cong_status_out_bits
{
4059 u8 reserved_at_8
[0x18];
4063 u8 reserved_at_40
[0x20];
4067 u8 reserved_at_62
[0x1e];
4070 struct mlx5_ifc_query_cong_status_in_bits
{
4072 u8 reserved_at_10
[0x10];
4074 u8 reserved_at_20
[0x10];
4077 u8 reserved_at_40
[0x18];
4079 u8 cong_protocol
[0x4];
4081 u8 reserved_at_60
[0x20];
4084 struct mlx5_ifc_query_cong_statistics_out_bits
{
4086 u8 reserved_at_8
[0x18];
4090 u8 reserved_at_40
[0x40];
4096 u8 cnp_ignored_high
[0x20];
4098 u8 cnp_ignored_low
[0x20];
4100 u8 cnp_handled_high
[0x20];
4102 u8 cnp_handled_low
[0x20];
4104 u8 reserved_at_140
[0x100];
4106 u8 time_stamp_high
[0x20];
4108 u8 time_stamp_low
[0x20];
4110 u8 accumulators_period
[0x20];
4112 u8 ecn_marked_roce_packets_high
[0x20];
4114 u8 ecn_marked_roce_packets_low
[0x20];
4116 u8 cnps_sent_high
[0x20];
4118 u8 cnps_sent_low
[0x20];
4120 u8 reserved_at_320
[0x560];
4123 struct mlx5_ifc_query_cong_statistics_in_bits
{
4125 u8 reserved_at_10
[0x10];
4127 u8 reserved_at_20
[0x10];
4131 u8 reserved_at_41
[0x1f];
4133 u8 reserved_at_60
[0x20];
4136 struct mlx5_ifc_query_cong_params_out_bits
{
4138 u8 reserved_at_8
[0x18];
4142 u8 reserved_at_40
[0x40];
4144 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4147 struct mlx5_ifc_query_cong_params_in_bits
{
4149 u8 reserved_at_10
[0x10];
4151 u8 reserved_at_20
[0x10];
4154 u8 reserved_at_40
[0x1c];
4155 u8 cong_protocol
[0x4];
4157 u8 reserved_at_60
[0x20];
4160 struct mlx5_ifc_query_adapter_out_bits
{
4162 u8 reserved_at_8
[0x18];
4166 u8 reserved_at_40
[0x40];
4168 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
4171 struct mlx5_ifc_query_adapter_in_bits
{
4173 u8 reserved_at_10
[0x10];
4175 u8 reserved_at_20
[0x10];
4178 u8 reserved_at_40
[0x40];
4181 struct mlx5_ifc_qp_2rst_out_bits
{
4183 u8 reserved_at_8
[0x18];
4187 u8 reserved_at_40
[0x40];
4190 struct mlx5_ifc_qp_2rst_in_bits
{
4192 u8 reserved_at_10
[0x10];
4194 u8 reserved_at_20
[0x10];
4197 u8 reserved_at_40
[0x8];
4200 u8 reserved_at_60
[0x20];
4203 struct mlx5_ifc_qp_2err_out_bits
{
4205 u8 reserved_at_8
[0x18];
4209 u8 reserved_at_40
[0x40];
4212 struct mlx5_ifc_qp_2err_in_bits
{
4214 u8 reserved_at_10
[0x10];
4216 u8 reserved_at_20
[0x10];
4219 u8 reserved_at_40
[0x8];
4222 u8 reserved_at_60
[0x20];
4225 struct mlx5_ifc_page_fault_resume_out_bits
{
4227 u8 reserved_at_8
[0x18];
4231 u8 reserved_at_40
[0x40];
4234 struct mlx5_ifc_page_fault_resume_in_bits
{
4236 u8 reserved_at_10
[0x10];
4238 u8 reserved_at_20
[0x10];
4242 u8 reserved_at_41
[0x4];
4248 u8 reserved_at_60
[0x20];
4251 struct mlx5_ifc_nop_out_bits
{
4253 u8 reserved_at_8
[0x18];
4257 u8 reserved_at_40
[0x40];
4260 struct mlx5_ifc_nop_in_bits
{
4262 u8 reserved_at_10
[0x10];
4264 u8 reserved_at_20
[0x10];
4267 u8 reserved_at_40
[0x40];
4270 struct mlx5_ifc_modify_vport_state_out_bits
{
4272 u8 reserved_at_8
[0x18];
4276 u8 reserved_at_40
[0x40];
4279 struct mlx5_ifc_modify_vport_state_in_bits
{
4281 u8 reserved_at_10
[0x10];
4283 u8 reserved_at_20
[0x10];
4286 u8 other_vport
[0x1];
4287 u8 reserved_at_41
[0xf];
4288 u8 vport_number
[0x10];
4290 u8 reserved_at_60
[0x18];
4291 u8 admin_state
[0x4];
4292 u8 reserved_at_7c
[0x4];
4295 struct mlx5_ifc_modify_tis_out_bits
{
4297 u8 reserved_at_8
[0x18];
4301 u8 reserved_at_40
[0x40];
4304 struct mlx5_ifc_modify_tis_bitmask_bits
{
4305 u8 reserved_at_0
[0x20];
4307 u8 reserved_at_20
[0x1f];
4311 struct mlx5_ifc_modify_tis_in_bits
{
4313 u8 reserved_at_10
[0x10];
4315 u8 reserved_at_20
[0x10];
4318 u8 reserved_at_40
[0x8];
4321 u8 reserved_at_60
[0x20];
4323 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
4325 u8 reserved_at_c0
[0x40];
4327 struct mlx5_ifc_tisc_bits ctx
;
4330 struct mlx5_ifc_modify_tir_bitmask_bits
{
4331 u8 reserved_at_0
[0x20];
4333 u8 reserved_at_20
[0x1b];
4335 u8 reserved_at_3c
[0x1];
4337 u8 reserved_at_3e
[0x1];
4341 struct mlx5_ifc_modify_tir_out_bits
{
4343 u8 reserved_at_8
[0x18];
4347 u8 reserved_at_40
[0x40];
4350 struct mlx5_ifc_modify_tir_in_bits
{
4352 u8 reserved_at_10
[0x10];
4354 u8 reserved_at_20
[0x10];
4357 u8 reserved_at_40
[0x8];
4360 u8 reserved_at_60
[0x20];
4362 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
4364 u8 reserved_at_c0
[0x40];
4366 struct mlx5_ifc_tirc_bits ctx
;
4369 struct mlx5_ifc_modify_sq_out_bits
{
4371 u8 reserved_at_8
[0x18];
4375 u8 reserved_at_40
[0x40];
4378 struct mlx5_ifc_modify_sq_in_bits
{
4380 u8 reserved_at_10
[0x10];
4382 u8 reserved_at_20
[0x10];
4386 u8 reserved_at_44
[0x4];
4389 u8 reserved_at_60
[0x20];
4391 u8 modify_bitmask
[0x40];
4393 u8 reserved_at_c0
[0x40];
4395 struct mlx5_ifc_sqc_bits ctx
;
4398 struct mlx5_ifc_modify_rqt_out_bits
{
4400 u8 reserved_at_8
[0x18];
4404 u8 reserved_at_40
[0x40];
4407 struct mlx5_ifc_rqt_bitmask_bits
{
4408 u8 reserved_at_0
[0x20];
4410 u8 reserved_at_20
[0x1f];
4414 struct mlx5_ifc_modify_rqt_in_bits
{
4416 u8 reserved_at_10
[0x10];
4418 u8 reserved_at_20
[0x10];
4421 u8 reserved_at_40
[0x8];
4424 u8 reserved_at_60
[0x20];
4426 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
4428 u8 reserved_at_c0
[0x40];
4430 struct mlx5_ifc_rqtc_bits ctx
;
4433 struct mlx5_ifc_modify_rq_out_bits
{
4435 u8 reserved_at_8
[0x18];
4439 u8 reserved_at_40
[0x40];
4442 struct mlx5_ifc_modify_rq_in_bits
{
4444 u8 reserved_at_10
[0x10];
4446 u8 reserved_at_20
[0x10];
4450 u8 reserved_at_44
[0x4];
4453 u8 reserved_at_60
[0x20];
4455 u8 modify_bitmask
[0x40];
4457 u8 reserved_at_c0
[0x40];
4459 struct mlx5_ifc_rqc_bits ctx
;
4462 struct mlx5_ifc_modify_rmp_out_bits
{
4464 u8 reserved_at_8
[0x18];
4468 u8 reserved_at_40
[0x40];
4471 struct mlx5_ifc_rmp_bitmask_bits
{
4472 u8 reserved_at_0
[0x20];
4474 u8 reserved_at_20
[0x1f];
4478 struct mlx5_ifc_modify_rmp_in_bits
{
4480 u8 reserved_at_10
[0x10];
4482 u8 reserved_at_20
[0x10];
4486 u8 reserved_at_44
[0x4];
4489 u8 reserved_at_60
[0x20];
4491 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
4493 u8 reserved_at_c0
[0x40];
4495 struct mlx5_ifc_rmpc_bits ctx
;
4498 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
4500 u8 reserved_at_8
[0x18];
4504 u8 reserved_at_40
[0x40];
4507 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
4508 u8 reserved_at_0
[0x19];
4510 u8 change_event
[0x1];
4512 u8 permanent_address
[0x1];
4513 u8 addresses_list
[0x1];
4515 u8 reserved_at_1f
[0x1];
4518 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
4520 u8 reserved_at_10
[0x10];
4522 u8 reserved_at_20
[0x10];
4525 u8 other_vport
[0x1];
4526 u8 reserved_at_41
[0xf];
4527 u8 vport_number
[0x10];
4529 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
4531 u8 reserved_at_80
[0x780];
4533 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4536 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
4538 u8 reserved_at_8
[0x18];
4542 u8 reserved_at_40
[0x40];
4545 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
4547 u8 reserved_at_10
[0x10];
4549 u8 reserved_at_20
[0x10];
4552 u8 other_vport
[0x1];
4553 u8 reserved_at_41
[0xb];
4555 u8 vport_number
[0x10];
4557 u8 reserved_at_60
[0x20];
4559 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
4562 struct mlx5_ifc_modify_cq_out_bits
{
4564 u8 reserved_at_8
[0x18];
4568 u8 reserved_at_40
[0x40];
4572 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
4573 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
4576 struct mlx5_ifc_modify_cq_in_bits
{
4578 u8 reserved_at_10
[0x10];
4580 u8 reserved_at_20
[0x10];
4583 u8 reserved_at_40
[0x8];
4586 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
4588 struct mlx5_ifc_cqc_bits cq_context
;
4590 u8 reserved_at_280
[0x600];
4595 struct mlx5_ifc_modify_cong_status_out_bits
{
4597 u8 reserved_at_8
[0x18];
4601 u8 reserved_at_40
[0x40];
4604 struct mlx5_ifc_modify_cong_status_in_bits
{
4606 u8 reserved_at_10
[0x10];
4608 u8 reserved_at_20
[0x10];
4611 u8 reserved_at_40
[0x18];
4613 u8 cong_protocol
[0x4];
4617 u8 reserved_at_62
[0x1e];
4620 struct mlx5_ifc_modify_cong_params_out_bits
{
4622 u8 reserved_at_8
[0x18];
4626 u8 reserved_at_40
[0x40];
4629 struct mlx5_ifc_modify_cong_params_in_bits
{
4631 u8 reserved_at_10
[0x10];
4633 u8 reserved_at_20
[0x10];
4636 u8 reserved_at_40
[0x1c];
4637 u8 cong_protocol
[0x4];
4639 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
4641 u8 reserved_at_80
[0x80];
4643 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4646 struct mlx5_ifc_manage_pages_out_bits
{
4648 u8 reserved_at_8
[0x18];
4652 u8 output_num_entries
[0x20];
4654 u8 reserved_at_60
[0x20];
4660 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
4661 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
4662 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
4665 struct mlx5_ifc_manage_pages_in_bits
{
4667 u8 reserved_at_10
[0x10];
4669 u8 reserved_at_20
[0x10];
4672 u8 reserved_at_40
[0x10];
4673 u8 function_id
[0x10];
4675 u8 input_num_entries
[0x20];
4680 struct mlx5_ifc_mad_ifc_out_bits
{
4682 u8 reserved_at_8
[0x18];
4686 u8 reserved_at_40
[0x40];
4688 u8 response_mad_packet
[256][0x8];
4691 struct mlx5_ifc_mad_ifc_in_bits
{
4693 u8 reserved_at_10
[0x10];
4695 u8 reserved_at_20
[0x10];
4698 u8 remote_lid
[0x10];
4699 u8 reserved_at_50
[0x8];
4702 u8 reserved_at_60
[0x20];
4707 struct mlx5_ifc_init_hca_out_bits
{
4709 u8 reserved_at_8
[0x18];
4713 u8 reserved_at_40
[0x40];
4716 struct mlx5_ifc_init_hca_in_bits
{
4718 u8 reserved_at_10
[0x10];
4720 u8 reserved_at_20
[0x10];
4723 u8 reserved_at_40
[0x40];
4726 struct mlx5_ifc_init2rtr_qp_out_bits
{
4728 u8 reserved_at_8
[0x18];
4732 u8 reserved_at_40
[0x40];
4735 struct mlx5_ifc_init2rtr_qp_in_bits
{
4737 u8 reserved_at_10
[0x10];
4739 u8 reserved_at_20
[0x10];
4742 u8 reserved_at_40
[0x8];
4745 u8 reserved_at_60
[0x20];
4747 u8 opt_param_mask
[0x20];
4749 u8 reserved_at_a0
[0x20];
4751 struct mlx5_ifc_qpc_bits qpc
;
4753 u8 reserved_at_800
[0x80];
4756 struct mlx5_ifc_init2init_qp_out_bits
{
4758 u8 reserved_at_8
[0x18];
4762 u8 reserved_at_40
[0x40];
4765 struct mlx5_ifc_init2init_qp_in_bits
{
4767 u8 reserved_at_10
[0x10];
4769 u8 reserved_at_20
[0x10];
4772 u8 reserved_at_40
[0x8];
4775 u8 reserved_at_60
[0x20];
4777 u8 opt_param_mask
[0x20];
4779 u8 reserved_at_a0
[0x20];
4781 struct mlx5_ifc_qpc_bits qpc
;
4783 u8 reserved_at_800
[0x80];
4786 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
4788 u8 reserved_at_8
[0x18];
4792 u8 reserved_at_40
[0x40];
4794 u8 packet_headers_log
[128][0x8];
4796 u8 packet_syndrome
[64][0x8];
4799 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
4801 u8 reserved_at_10
[0x10];
4803 u8 reserved_at_20
[0x10];
4806 u8 reserved_at_40
[0x40];
4809 struct mlx5_ifc_gen_eqe_in_bits
{
4811 u8 reserved_at_10
[0x10];
4813 u8 reserved_at_20
[0x10];
4816 u8 reserved_at_40
[0x18];
4819 u8 reserved_at_60
[0x20];
4824 struct mlx5_ifc_gen_eq_out_bits
{
4826 u8 reserved_at_8
[0x18];
4830 u8 reserved_at_40
[0x40];
4833 struct mlx5_ifc_enable_hca_out_bits
{
4835 u8 reserved_at_8
[0x18];
4839 u8 reserved_at_40
[0x20];
4842 struct mlx5_ifc_enable_hca_in_bits
{
4844 u8 reserved_at_10
[0x10];
4846 u8 reserved_at_20
[0x10];
4849 u8 reserved_at_40
[0x10];
4850 u8 function_id
[0x10];
4852 u8 reserved_at_60
[0x20];
4855 struct mlx5_ifc_drain_dct_out_bits
{
4857 u8 reserved_at_8
[0x18];
4861 u8 reserved_at_40
[0x40];
4864 struct mlx5_ifc_drain_dct_in_bits
{
4866 u8 reserved_at_10
[0x10];
4868 u8 reserved_at_20
[0x10];
4871 u8 reserved_at_40
[0x8];
4874 u8 reserved_at_60
[0x20];
4877 struct mlx5_ifc_disable_hca_out_bits
{
4879 u8 reserved_at_8
[0x18];
4883 u8 reserved_at_40
[0x20];
4886 struct mlx5_ifc_disable_hca_in_bits
{
4888 u8 reserved_at_10
[0x10];
4890 u8 reserved_at_20
[0x10];
4893 u8 reserved_at_40
[0x10];
4894 u8 function_id
[0x10];
4896 u8 reserved_at_60
[0x20];
4899 struct mlx5_ifc_detach_from_mcg_out_bits
{
4901 u8 reserved_at_8
[0x18];
4905 u8 reserved_at_40
[0x40];
4908 struct mlx5_ifc_detach_from_mcg_in_bits
{
4910 u8 reserved_at_10
[0x10];
4912 u8 reserved_at_20
[0x10];
4915 u8 reserved_at_40
[0x8];
4918 u8 reserved_at_60
[0x20];
4920 u8 multicast_gid
[16][0x8];
4923 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
4925 u8 reserved_at_8
[0x18];
4929 u8 reserved_at_40
[0x40];
4932 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
4934 u8 reserved_at_10
[0x10];
4936 u8 reserved_at_20
[0x10];
4939 u8 reserved_at_40
[0x8];
4942 u8 reserved_at_60
[0x20];
4945 struct mlx5_ifc_destroy_tis_out_bits
{
4947 u8 reserved_at_8
[0x18];
4951 u8 reserved_at_40
[0x40];
4954 struct mlx5_ifc_destroy_tis_in_bits
{
4956 u8 reserved_at_10
[0x10];
4958 u8 reserved_at_20
[0x10];
4961 u8 reserved_at_40
[0x8];
4964 u8 reserved_at_60
[0x20];
4967 struct mlx5_ifc_destroy_tir_out_bits
{
4969 u8 reserved_at_8
[0x18];
4973 u8 reserved_at_40
[0x40];
4976 struct mlx5_ifc_destroy_tir_in_bits
{
4978 u8 reserved_at_10
[0x10];
4980 u8 reserved_at_20
[0x10];
4983 u8 reserved_at_40
[0x8];
4986 u8 reserved_at_60
[0x20];
4989 struct mlx5_ifc_destroy_srq_out_bits
{
4991 u8 reserved_at_8
[0x18];
4995 u8 reserved_at_40
[0x40];
4998 struct mlx5_ifc_destroy_srq_in_bits
{
5000 u8 reserved_at_10
[0x10];
5002 u8 reserved_at_20
[0x10];
5005 u8 reserved_at_40
[0x8];
5008 u8 reserved_at_60
[0x20];
5011 struct mlx5_ifc_destroy_sq_out_bits
{
5013 u8 reserved_at_8
[0x18];
5017 u8 reserved_at_40
[0x40];
5020 struct mlx5_ifc_destroy_sq_in_bits
{
5022 u8 reserved_at_10
[0x10];
5024 u8 reserved_at_20
[0x10];
5027 u8 reserved_at_40
[0x8];
5030 u8 reserved_at_60
[0x20];
5033 struct mlx5_ifc_destroy_rqt_out_bits
{
5035 u8 reserved_at_8
[0x18];
5039 u8 reserved_at_40
[0x40];
5042 struct mlx5_ifc_destroy_rqt_in_bits
{
5044 u8 reserved_at_10
[0x10];
5046 u8 reserved_at_20
[0x10];
5049 u8 reserved_at_40
[0x8];
5052 u8 reserved_at_60
[0x20];
5055 struct mlx5_ifc_destroy_rq_out_bits
{
5057 u8 reserved_at_8
[0x18];
5061 u8 reserved_at_40
[0x40];
5064 struct mlx5_ifc_destroy_rq_in_bits
{
5066 u8 reserved_at_10
[0x10];
5068 u8 reserved_at_20
[0x10];
5071 u8 reserved_at_40
[0x8];
5074 u8 reserved_at_60
[0x20];
5077 struct mlx5_ifc_destroy_rmp_out_bits
{
5079 u8 reserved_at_8
[0x18];
5083 u8 reserved_at_40
[0x40];
5086 struct mlx5_ifc_destroy_rmp_in_bits
{
5088 u8 reserved_at_10
[0x10];
5090 u8 reserved_at_20
[0x10];
5093 u8 reserved_at_40
[0x8];
5096 u8 reserved_at_60
[0x20];
5099 struct mlx5_ifc_destroy_qp_out_bits
{
5101 u8 reserved_at_8
[0x18];
5105 u8 reserved_at_40
[0x40];
5108 struct mlx5_ifc_destroy_qp_in_bits
{
5110 u8 reserved_at_10
[0x10];
5112 u8 reserved_at_20
[0x10];
5115 u8 reserved_at_40
[0x8];
5118 u8 reserved_at_60
[0x20];
5121 struct mlx5_ifc_destroy_psv_out_bits
{
5123 u8 reserved_at_8
[0x18];
5127 u8 reserved_at_40
[0x40];
5130 struct mlx5_ifc_destroy_psv_in_bits
{
5132 u8 reserved_at_10
[0x10];
5134 u8 reserved_at_20
[0x10];
5137 u8 reserved_at_40
[0x8];
5140 u8 reserved_at_60
[0x20];
5143 struct mlx5_ifc_destroy_mkey_out_bits
{
5145 u8 reserved_at_8
[0x18];
5149 u8 reserved_at_40
[0x40];
5152 struct mlx5_ifc_destroy_mkey_in_bits
{
5154 u8 reserved_at_10
[0x10];
5156 u8 reserved_at_20
[0x10];
5159 u8 reserved_at_40
[0x8];
5160 u8 mkey_index
[0x18];
5162 u8 reserved_at_60
[0x20];
5165 struct mlx5_ifc_destroy_flow_table_out_bits
{
5167 u8 reserved_at_8
[0x18];
5171 u8 reserved_at_40
[0x40];
5174 struct mlx5_ifc_destroy_flow_table_in_bits
{
5176 u8 reserved_at_10
[0x10];
5178 u8 reserved_at_20
[0x10];
5181 u8 reserved_at_40
[0x40];
5184 u8 reserved_at_88
[0x18];
5186 u8 reserved_at_a0
[0x8];
5189 u8 reserved_at_c0
[0x140];
5192 struct mlx5_ifc_destroy_flow_group_out_bits
{
5194 u8 reserved_at_8
[0x18];
5198 u8 reserved_at_40
[0x40];
5201 struct mlx5_ifc_destroy_flow_group_in_bits
{
5203 u8 reserved_at_10
[0x10];
5205 u8 reserved_at_20
[0x10];
5208 u8 reserved_at_40
[0x40];
5211 u8 reserved_at_88
[0x18];
5213 u8 reserved_at_a0
[0x8];
5218 u8 reserved_at_e0
[0x120];
5221 struct mlx5_ifc_destroy_eq_out_bits
{
5223 u8 reserved_at_8
[0x18];
5227 u8 reserved_at_40
[0x40];
5230 struct mlx5_ifc_destroy_eq_in_bits
{
5232 u8 reserved_at_10
[0x10];
5234 u8 reserved_at_20
[0x10];
5237 u8 reserved_at_40
[0x18];
5240 u8 reserved_at_60
[0x20];
5243 struct mlx5_ifc_destroy_dct_out_bits
{
5245 u8 reserved_at_8
[0x18];
5249 u8 reserved_at_40
[0x40];
5252 struct mlx5_ifc_destroy_dct_in_bits
{
5254 u8 reserved_at_10
[0x10];
5256 u8 reserved_at_20
[0x10];
5259 u8 reserved_at_40
[0x8];
5262 u8 reserved_at_60
[0x20];
5265 struct mlx5_ifc_destroy_cq_out_bits
{
5267 u8 reserved_at_8
[0x18];
5271 u8 reserved_at_40
[0x40];
5274 struct mlx5_ifc_destroy_cq_in_bits
{
5276 u8 reserved_at_10
[0x10];
5278 u8 reserved_at_20
[0x10];
5281 u8 reserved_at_40
[0x8];
5284 u8 reserved_at_60
[0x20];
5287 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
5289 u8 reserved_at_8
[0x18];
5293 u8 reserved_at_40
[0x40];
5296 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
5298 u8 reserved_at_10
[0x10];
5300 u8 reserved_at_20
[0x10];
5303 u8 reserved_at_40
[0x20];
5305 u8 reserved_at_60
[0x10];
5306 u8 vxlan_udp_port
[0x10];
5309 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
5311 u8 reserved_at_8
[0x18];
5315 u8 reserved_at_40
[0x40];
5318 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
5320 u8 reserved_at_10
[0x10];
5322 u8 reserved_at_20
[0x10];
5325 u8 reserved_at_40
[0x60];
5327 u8 reserved_at_a0
[0x8];
5328 u8 table_index
[0x18];
5330 u8 reserved_at_c0
[0x140];
5333 struct mlx5_ifc_delete_fte_out_bits
{
5335 u8 reserved_at_8
[0x18];
5339 u8 reserved_at_40
[0x40];
5342 struct mlx5_ifc_delete_fte_in_bits
{
5344 u8 reserved_at_10
[0x10];
5346 u8 reserved_at_20
[0x10];
5349 u8 reserved_at_40
[0x40];
5352 u8 reserved_at_88
[0x18];
5354 u8 reserved_at_a0
[0x8];
5357 u8 reserved_at_c0
[0x40];
5359 u8 flow_index
[0x20];
5361 u8 reserved_at_120
[0xe0];
5364 struct mlx5_ifc_dealloc_xrcd_out_bits
{
5366 u8 reserved_at_8
[0x18];
5370 u8 reserved_at_40
[0x40];
5373 struct mlx5_ifc_dealloc_xrcd_in_bits
{
5375 u8 reserved_at_10
[0x10];
5377 u8 reserved_at_20
[0x10];
5380 u8 reserved_at_40
[0x8];
5383 u8 reserved_at_60
[0x20];
5386 struct mlx5_ifc_dealloc_uar_out_bits
{
5388 u8 reserved_at_8
[0x18];
5392 u8 reserved_at_40
[0x40];
5395 struct mlx5_ifc_dealloc_uar_in_bits
{
5397 u8 reserved_at_10
[0x10];
5399 u8 reserved_at_20
[0x10];
5402 u8 reserved_at_40
[0x8];
5405 u8 reserved_at_60
[0x20];
5408 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
5410 u8 reserved_at_8
[0x18];
5414 u8 reserved_at_40
[0x40];
5417 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
5419 u8 reserved_at_10
[0x10];
5421 u8 reserved_at_20
[0x10];
5424 u8 reserved_at_40
[0x8];
5425 u8 transport_domain
[0x18];
5427 u8 reserved_at_60
[0x20];
5430 struct mlx5_ifc_dealloc_q_counter_out_bits
{
5432 u8 reserved_at_8
[0x18];
5436 u8 reserved_at_40
[0x40];
5439 struct mlx5_ifc_dealloc_q_counter_in_bits
{
5441 u8 reserved_at_10
[0x10];
5443 u8 reserved_at_20
[0x10];
5446 u8 reserved_at_40
[0x18];
5447 u8 counter_set_id
[0x8];
5449 u8 reserved_at_60
[0x20];
5452 struct mlx5_ifc_dealloc_pd_out_bits
{
5454 u8 reserved_at_8
[0x18];
5458 u8 reserved_at_40
[0x40];
5461 struct mlx5_ifc_dealloc_pd_in_bits
{
5463 u8 reserved_at_10
[0x10];
5465 u8 reserved_at_20
[0x10];
5468 u8 reserved_at_40
[0x8];
5471 u8 reserved_at_60
[0x20];
5474 struct mlx5_ifc_create_xrc_srq_out_bits
{
5476 u8 reserved_at_8
[0x18];
5480 u8 reserved_at_40
[0x8];
5483 u8 reserved_at_60
[0x20];
5486 struct mlx5_ifc_create_xrc_srq_in_bits
{
5488 u8 reserved_at_10
[0x10];
5490 u8 reserved_at_20
[0x10];
5493 u8 reserved_at_40
[0x40];
5495 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
5497 u8 reserved_at_280
[0x600];
5502 struct mlx5_ifc_create_tis_out_bits
{
5504 u8 reserved_at_8
[0x18];
5508 u8 reserved_at_40
[0x8];
5511 u8 reserved_at_60
[0x20];
5514 struct mlx5_ifc_create_tis_in_bits
{
5516 u8 reserved_at_10
[0x10];
5518 u8 reserved_at_20
[0x10];
5521 u8 reserved_at_40
[0xc0];
5523 struct mlx5_ifc_tisc_bits ctx
;
5526 struct mlx5_ifc_create_tir_out_bits
{
5528 u8 reserved_at_8
[0x18];
5532 u8 reserved_at_40
[0x8];
5535 u8 reserved_at_60
[0x20];
5538 struct mlx5_ifc_create_tir_in_bits
{
5540 u8 reserved_at_10
[0x10];
5542 u8 reserved_at_20
[0x10];
5545 u8 reserved_at_40
[0xc0];
5547 struct mlx5_ifc_tirc_bits ctx
;
5550 struct mlx5_ifc_create_srq_out_bits
{
5552 u8 reserved_at_8
[0x18];
5556 u8 reserved_at_40
[0x8];
5559 u8 reserved_at_60
[0x20];
5562 struct mlx5_ifc_create_srq_in_bits
{
5564 u8 reserved_at_10
[0x10];
5566 u8 reserved_at_20
[0x10];
5569 u8 reserved_at_40
[0x40];
5571 struct mlx5_ifc_srqc_bits srq_context_entry
;
5573 u8 reserved_at_280
[0x600];
5578 struct mlx5_ifc_create_sq_out_bits
{
5580 u8 reserved_at_8
[0x18];
5584 u8 reserved_at_40
[0x8];
5587 u8 reserved_at_60
[0x20];
5590 struct mlx5_ifc_create_sq_in_bits
{
5592 u8 reserved_at_10
[0x10];
5594 u8 reserved_at_20
[0x10];
5597 u8 reserved_at_40
[0xc0];
5599 struct mlx5_ifc_sqc_bits ctx
;
5602 struct mlx5_ifc_create_rqt_out_bits
{
5604 u8 reserved_at_8
[0x18];
5608 u8 reserved_at_40
[0x8];
5611 u8 reserved_at_60
[0x20];
5614 struct mlx5_ifc_create_rqt_in_bits
{
5616 u8 reserved_at_10
[0x10];
5618 u8 reserved_at_20
[0x10];
5621 u8 reserved_at_40
[0xc0];
5623 struct mlx5_ifc_rqtc_bits rqt_context
;
5626 struct mlx5_ifc_create_rq_out_bits
{
5628 u8 reserved_at_8
[0x18];
5632 u8 reserved_at_40
[0x8];
5635 u8 reserved_at_60
[0x20];
5638 struct mlx5_ifc_create_rq_in_bits
{
5640 u8 reserved_at_10
[0x10];
5642 u8 reserved_at_20
[0x10];
5645 u8 reserved_at_40
[0xc0];
5647 struct mlx5_ifc_rqc_bits ctx
;
5650 struct mlx5_ifc_create_rmp_out_bits
{
5652 u8 reserved_at_8
[0x18];
5656 u8 reserved_at_40
[0x8];
5659 u8 reserved_at_60
[0x20];
5662 struct mlx5_ifc_create_rmp_in_bits
{
5664 u8 reserved_at_10
[0x10];
5666 u8 reserved_at_20
[0x10];
5669 u8 reserved_at_40
[0xc0];
5671 struct mlx5_ifc_rmpc_bits ctx
;
5674 struct mlx5_ifc_create_qp_out_bits
{
5676 u8 reserved_at_8
[0x18];
5680 u8 reserved_at_40
[0x8];
5683 u8 reserved_at_60
[0x20];
5686 struct mlx5_ifc_create_qp_in_bits
{
5688 u8 reserved_at_10
[0x10];
5690 u8 reserved_at_20
[0x10];
5693 u8 reserved_at_40
[0x40];
5695 u8 opt_param_mask
[0x20];
5697 u8 reserved_at_a0
[0x20];
5699 struct mlx5_ifc_qpc_bits qpc
;
5701 u8 reserved_at_800
[0x80];
5706 struct mlx5_ifc_create_psv_out_bits
{
5708 u8 reserved_at_8
[0x18];
5712 u8 reserved_at_40
[0x40];
5714 u8 reserved_at_80
[0x8];
5715 u8 psv0_index
[0x18];
5717 u8 reserved_at_a0
[0x8];
5718 u8 psv1_index
[0x18];
5720 u8 reserved_at_c0
[0x8];
5721 u8 psv2_index
[0x18];
5723 u8 reserved_at_e0
[0x8];
5724 u8 psv3_index
[0x18];
5727 struct mlx5_ifc_create_psv_in_bits
{
5729 u8 reserved_at_10
[0x10];
5731 u8 reserved_at_20
[0x10];
5735 u8 reserved_at_44
[0x4];
5738 u8 reserved_at_60
[0x20];
5741 struct mlx5_ifc_create_mkey_out_bits
{
5743 u8 reserved_at_8
[0x18];
5747 u8 reserved_at_40
[0x8];
5748 u8 mkey_index
[0x18];
5750 u8 reserved_at_60
[0x20];
5753 struct mlx5_ifc_create_mkey_in_bits
{
5755 u8 reserved_at_10
[0x10];
5757 u8 reserved_at_20
[0x10];
5760 u8 reserved_at_40
[0x20];
5763 u8 reserved_at_61
[0x1f];
5765 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
5767 u8 reserved_at_280
[0x80];
5769 u8 translations_octword_actual_size
[0x20];
5771 u8 reserved_at_320
[0x560];
5773 u8 klm_pas_mtt
[0][0x20];
5776 struct mlx5_ifc_create_flow_table_out_bits
{
5778 u8 reserved_at_8
[0x18];
5782 u8 reserved_at_40
[0x8];
5785 u8 reserved_at_60
[0x20];
5788 struct mlx5_ifc_create_flow_table_in_bits
{
5790 u8 reserved_at_10
[0x10];
5792 u8 reserved_at_20
[0x10];
5795 u8 reserved_at_40
[0x40];
5798 u8 reserved_at_88
[0x18];
5800 u8 reserved_at_a0
[0x20];
5802 u8 reserved_at_c0
[0x4];
5803 u8 table_miss_mode
[0x4];
5805 u8 reserved_at_d0
[0x8];
5808 u8 reserved_at_e0
[0x8];
5809 u8 table_miss_id
[0x18];
5811 u8 reserved_at_100
[0x100];
5814 struct mlx5_ifc_create_flow_group_out_bits
{
5816 u8 reserved_at_8
[0x18];
5820 u8 reserved_at_40
[0x8];
5823 u8 reserved_at_60
[0x20];
5827 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
5828 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
5829 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
5832 struct mlx5_ifc_create_flow_group_in_bits
{
5834 u8 reserved_at_10
[0x10];
5836 u8 reserved_at_20
[0x10];
5839 u8 reserved_at_40
[0x40];
5842 u8 reserved_at_88
[0x18];
5844 u8 reserved_at_a0
[0x8];
5847 u8 reserved_at_c0
[0x20];
5849 u8 start_flow_index
[0x20];
5851 u8 reserved_at_100
[0x20];
5853 u8 end_flow_index
[0x20];
5855 u8 reserved_at_140
[0xa0];
5857 u8 reserved_at_1e0
[0x18];
5858 u8 match_criteria_enable
[0x8];
5860 struct mlx5_ifc_fte_match_param_bits match_criteria
;
5862 u8 reserved_at_1200
[0xe00];
5865 struct mlx5_ifc_create_eq_out_bits
{
5867 u8 reserved_at_8
[0x18];
5871 u8 reserved_at_40
[0x18];
5874 u8 reserved_at_60
[0x20];
5877 struct mlx5_ifc_create_eq_in_bits
{
5879 u8 reserved_at_10
[0x10];
5881 u8 reserved_at_20
[0x10];
5884 u8 reserved_at_40
[0x40];
5886 struct mlx5_ifc_eqc_bits eq_context_entry
;
5888 u8 reserved_at_280
[0x40];
5890 u8 event_bitmask
[0x40];
5892 u8 reserved_at_300
[0x580];
5897 struct mlx5_ifc_create_dct_out_bits
{
5899 u8 reserved_at_8
[0x18];
5903 u8 reserved_at_40
[0x8];
5906 u8 reserved_at_60
[0x20];
5909 struct mlx5_ifc_create_dct_in_bits
{
5911 u8 reserved_at_10
[0x10];
5913 u8 reserved_at_20
[0x10];
5916 u8 reserved_at_40
[0x40];
5918 struct mlx5_ifc_dctc_bits dct_context_entry
;
5920 u8 reserved_at_280
[0x180];
5923 struct mlx5_ifc_create_cq_out_bits
{
5925 u8 reserved_at_8
[0x18];
5929 u8 reserved_at_40
[0x8];
5932 u8 reserved_at_60
[0x20];
5935 struct mlx5_ifc_create_cq_in_bits
{
5937 u8 reserved_at_10
[0x10];
5939 u8 reserved_at_20
[0x10];
5942 u8 reserved_at_40
[0x40];
5944 struct mlx5_ifc_cqc_bits cq_context
;
5946 u8 reserved_at_280
[0x600];
5951 struct mlx5_ifc_config_int_moderation_out_bits
{
5953 u8 reserved_at_8
[0x18];
5957 u8 reserved_at_40
[0x4];
5959 u8 int_vector
[0x10];
5961 u8 reserved_at_60
[0x20];
5965 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
5966 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
5969 struct mlx5_ifc_config_int_moderation_in_bits
{
5971 u8 reserved_at_10
[0x10];
5973 u8 reserved_at_20
[0x10];
5976 u8 reserved_at_40
[0x4];
5978 u8 int_vector
[0x10];
5980 u8 reserved_at_60
[0x20];
5983 struct mlx5_ifc_attach_to_mcg_out_bits
{
5985 u8 reserved_at_8
[0x18];
5989 u8 reserved_at_40
[0x40];
5992 struct mlx5_ifc_attach_to_mcg_in_bits
{
5994 u8 reserved_at_10
[0x10];
5996 u8 reserved_at_20
[0x10];
5999 u8 reserved_at_40
[0x8];
6002 u8 reserved_at_60
[0x20];
6004 u8 multicast_gid
[16][0x8];
6007 struct mlx5_ifc_arm_xrc_srq_out_bits
{
6009 u8 reserved_at_8
[0x18];
6013 u8 reserved_at_40
[0x40];
6017 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
6020 struct mlx5_ifc_arm_xrc_srq_in_bits
{
6022 u8 reserved_at_10
[0x10];
6024 u8 reserved_at_20
[0x10];
6027 u8 reserved_at_40
[0x8];
6030 u8 reserved_at_60
[0x10];
6034 struct mlx5_ifc_arm_rq_out_bits
{
6036 u8 reserved_at_8
[0x18];
6040 u8 reserved_at_40
[0x40];
6044 MLX5_ARM_RQ_IN_OP_MOD_SRQ_
= 0x1,
6047 struct mlx5_ifc_arm_rq_in_bits
{
6049 u8 reserved_at_10
[0x10];
6051 u8 reserved_at_20
[0x10];
6054 u8 reserved_at_40
[0x8];
6055 u8 srq_number
[0x18];
6057 u8 reserved_at_60
[0x10];
6061 struct mlx5_ifc_arm_dct_out_bits
{
6063 u8 reserved_at_8
[0x18];
6067 u8 reserved_at_40
[0x40];
6070 struct mlx5_ifc_arm_dct_in_bits
{
6072 u8 reserved_at_10
[0x10];
6074 u8 reserved_at_20
[0x10];
6077 u8 reserved_at_40
[0x8];
6078 u8 dct_number
[0x18];
6080 u8 reserved_at_60
[0x20];
6083 struct mlx5_ifc_alloc_xrcd_out_bits
{
6085 u8 reserved_at_8
[0x18];
6089 u8 reserved_at_40
[0x8];
6092 u8 reserved_at_60
[0x20];
6095 struct mlx5_ifc_alloc_xrcd_in_bits
{
6097 u8 reserved_at_10
[0x10];
6099 u8 reserved_at_20
[0x10];
6102 u8 reserved_at_40
[0x40];
6105 struct mlx5_ifc_alloc_uar_out_bits
{
6107 u8 reserved_at_8
[0x18];
6111 u8 reserved_at_40
[0x8];
6114 u8 reserved_at_60
[0x20];
6117 struct mlx5_ifc_alloc_uar_in_bits
{
6119 u8 reserved_at_10
[0x10];
6121 u8 reserved_at_20
[0x10];
6124 u8 reserved_at_40
[0x40];
6127 struct mlx5_ifc_alloc_transport_domain_out_bits
{
6129 u8 reserved_at_8
[0x18];
6133 u8 reserved_at_40
[0x8];
6134 u8 transport_domain
[0x18];
6136 u8 reserved_at_60
[0x20];
6139 struct mlx5_ifc_alloc_transport_domain_in_bits
{
6141 u8 reserved_at_10
[0x10];
6143 u8 reserved_at_20
[0x10];
6146 u8 reserved_at_40
[0x40];
6149 struct mlx5_ifc_alloc_q_counter_out_bits
{
6151 u8 reserved_at_8
[0x18];
6155 u8 reserved_at_40
[0x18];
6156 u8 counter_set_id
[0x8];
6158 u8 reserved_at_60
[0x20];
6161 struct mlx5_ifc_alloc_q_counter_in_bits
{
6163 u8 reserved_at_10
[0x10];
6165 u8 reserved_at_20
[0x10];
6168 u8 reserved_at_40
[0x40];
6171 struct mlx5_ifc_alloc_pd_out_bits
{
6173 u8 reserved_at_8
[0x18];
6177 u8 reserved_at_40
[0x8];
6180 u8 reserved_at_60
[0x20];
6183 struct mlx5_ifc_alloc_pd_in_bits
{
6185 u8 reserved_at_10
[0x10];
6187 u8 reserved_at_20
[0x10];
6190 u8 reserved_at_40
[0x40];
6193 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
6195 u8 reserved_at_8
[0x18];
6199 u8 reserved_at_40
[0x40];
6202 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
6204 u8 reserved_at_10
[0x10];
6206 u8 reserved_at_20
[0x10];
6209 u8 reserved_at_40
[0x20];
6211 u8 reserved_at_60
[0x10];
6212 u8 vxlan_udp_port
[0x10];
6215 struct mlx5_ifc_access_register_out_bits
{
6217 u8 reserved_at_8
[0x18];
6221 u8 reserved_at_40
[0x40];
6223 u8 register_data
[0][0x20];
6227 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
6228 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
6231 struct mlx5_ifc_access_register_in_bits
{
6233 u8 reserved_at_10
[0x10];
6235 u8 reserved_at_20
[0x10];
6238 u8 reserved_at_40
[0x10];
6239 u8 register_id
[0x10];
6243 u8 register_data
[0][0x20];
6246 struct mlx5_ifc_sltp_reg_bits
{
6251 u8 reserved_at_12
[0x2];
6253 u8 reserved_at_18
[0x8];
6255 u8 reserved_at_20
[0x20];
6257 u8 reserved_at_40
[0x7];
6263 u8 reserved_at_60
[0xc];
6264 u8 ob_preemp_mode
[0x4];
6268 u8 reserved_at_80
[0x20];
6271 struct mlx5_ifc_slrg_reg_bits
{
6276 u8 reserved_at_12
[0x2];
6278 u8 reserved_at_18
[0x8];
6280 u8 time_to_link_up
[0x10];
6281 u8 reserved_at_30
[0xc];
6282 u8 grade_lane_speed
[0x4];
6284 u8 grade_version
[0x8];
6287 u8 reserved_at_60
[0x4];
6288 u8 height_grade_type
[0x4];
6289 u8 height_grade
[0x18];
6294 u8 reserved_at_a0
[0x10];
6295 u8 height_sigma
[0x10];
6297 u8 reserved_at_c0
[0x20];
6299 u8 reserved_at_e0
[0x4];
6300 u8 phase_grade_type
[0x4];
6301 u8 phase_grade
[0x18];
6303 u8 reserved_at_100
[0x8];
6304 u8 phase_eo_pos
[0x8];
6305 u8 reserved_at_110
[0x8];
6306 u8 phase_eo_neg
[0x8];
6308 u8 ffe_set_tested
[0x10];
6309 u8 test_errors_per_lane
[0x10];
6312 struct mlx5_ifc_pvlc_reg_bits
{
6313 u8 reserved_at_0
[0x8];
6315 u8 reserved_at_10
[0x10];
6317 u8 reserved_at_20
[0x1c];
6320 u8 reserved_at_40
[0x1c];
6323 u8 reserved_at_60
[0x1c];
6324 u8 vl_operational
[0x4];
6327 struct mlx5_ifc_pude_reg_bits
{
6330 u8 reserved_at_10
[0x4];
6331 u8 admin_status
[0x4];
6332 u8 reserved_at_18
[0x4];
6333 u8 oper_status
[0x4];
6335 u8 reserved_at_20
[0x60];
6338 struct mlx5_ifc_ptys_reg_bits
{
6339 u8 reserved_at_0
[0x8];
6341 u8 reserved_at_10
[0xd];
6344 u8 reserved_at_20
[0x40];
6346 u8 eth_proto_capability
[0x20];
6348 u8 ib_link_width_capability
[0x10];
6349 u8 ib_proto_capability
[0x10];
6351 u8 reserved_at_a0
[0x20];
6353 u8 eth_proto_admin
[0x20];
6355 u8 ib_link_width_admin
[0x10];
6356 u8 ib_proto_admin
[0x10];
6358 u8 reserved_at_100
[0x20];
6360 u8 eth_proto_oper
[0x20];
6362 u8 ib_link_width_oper
[0x10];
6363 u8 ib_proto_oper
[0x10];
6365 u8 reserved_at_160
[0x20];
6367 u8 eth_proto_lp_advertise
[0x20];
6369 u8 reserved_at_1a0
[0x60];
6372 struct mlx5_ifc_ptas_reg_bits
{
6373 u8 reserved_at_0
[0x20];
6375 u8 algorithm_options
[0x10];
6376 u8 reserved_at_30
[0x4];
6377 u8 repetitions_mode
[0x4];
6378 u8 num_of_repetitions
[0x8];
6380 u8 grade_version
[0x8];
6381 u8 height_grade_type
[0x4];
6382 u8 phase_grade_type
[0x4];
6383 u8 height_grade_weight
[0x8];
6384 u8 phase_grade_weight
[0x8];
6386 u8 gisim_measure_bits
[0x10];
6387 u8 adaptive_tap_measure_bits
[0x10];
6389 u8 ber_bath_high_error_threshold
[0x10];
6390 u8 ber_bath_mid_error_threshold
[0x10];
6392 u8 ber_bath_low_error_threshold
[0x10];
6393 u8 one_ratio_high_threshold
[0x10];
6395 u8 one_ratio_high_mid_threshold
[0x10];
6396 u8 one_ratio_low_mid_threshold
[0x10];
6398 u8 one_ratio_low_threshold
[0x10];
6399 u8 ndeo_error_threshold
[0x10];
6401 u8 mixer_offset_step_size
[0x10];
6402 u8 reserved_at_110
[0x8];
6403 u8 mix90_phase_for_voltage_bath
[0x8];
6405 u8 mixer_offset_start
[0x10];
6406 u8 mixer_offset_end
[0x10];
6408 u8 reserved_at_140
[0x15];
6409 u8 ber_test_time
[0xb];
6412 struct mlx5_ifc_pspa_reg_bits
{
6416 u8 reserved_at_18
[0x8];
6418 u8 reserved_at_20
[0x20];
6421 struct mlx5_ifc_pqdr_reg_bits
{
6422 u8 reserved_at_0
[0x8];
6424 u8 reserved_at_10
[0x5];
6426 u8 reserved_at_18
[0x6];
6429 u8 reserved_at_20
[0x20];
6431 u8 reserved_at_40
[0x10];
6432 u8 min_threshold
[0x10];
6434 u8 reserved_at_60
[0x10];
6435 u8 max_threshold
[0x10];
6437 u8 reserved_at_80
[0x10];
6438 u8 mark_probability_denominator
[0x10];
6440 u8 reserved_at_a0
[0x60];
6443 struct mlx5_ifc_ppsc_reg_bits
{
6444 u8 reserved_at_0
[0x8];
6446 u8 reserved_at_10
[0x10];
6448 u8 reserved_at_20
[0x60];
6450 u8 reserved_at_80
[0x1c];
6453 u8 reserved_at_a0
[0x1c];
6454 u8 wrps_status
[0x4];
6456 u8 reserved_at_c0
[0x8];
6457 u8 up_threshold
[0x8];
6458 u8 reserved_at_d0
[0x8];
6459 u8 down_threshold
[0x8];
6461 u8 reserved_at_e0
[0x20];
6463 u8 reserved_at_100
[0x1c];
6466 u8 reserved_at_120
[0x1c];
6467 u8 srps_status
[0x4];
6469 u8 reserved_at_140
[0x40];
6472 struct mlx5_ifc_pplr_reg_bits
{
6473 u8 reserved_at_0
[0x8];
6475 u8 reserved_at_10
[0x10];
6477 u8 reserved_at_20
[0x8];
6479 u8 reserved_at_30
[0x8];
6483 struct mlx5_ifc_pplm_reg_bits
{
6484 u8 reserved_at_0
[0x8];
6486 u8 reserved_at_10
[0x10];
6488 u8 reserved_at_20
[0x20];
6490 u8 port_profile_mode
[0x8];
6491 u8 static_port_profile
[0x8];
6492 u8 active_port_profile
[0x8];
6493 u8 reserved_at_58
[0x8];
6495 u8 retransmission_active
[0x8];
6496 u8 fec_mode_active
[0x18];
6498 u8 reserved_at_80
[0x20];
6501 struct mlx5_ifc_ppcnt_reg_bits
{
6505 u8 reserved_at_12
[0x8];
6509 u8 reserved_at_21
[0x1c];
6512 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
6515 struct mlx5_ifc_ppad_reg_bits
{
6516 u8 reserved_at_0
[0x3];
6518 u8 reserved_at_4
[0x4];
6524 u8 reserved_at_40
[0x40];
6527 struct mlx5_ifc_pmtu_reg_bits
{
6528 u8 reserved_at_0
[0x8];
6530 u8 reserved_at_10
[0x10];
6533 u8 reserved_at_30
[0x10];
6536 u8 reserved_at_50
[0x10];
6539 u8 reserved_at_70
[0x10];
6542 struct mlx5_ifc_pmpr_reg_bits
{
6543 u8 reserved_at_0
[0x8];
6545 u8 reserved_at_10
[0x10];
6547 u8 reserved_at_20
[0x18];
6548 u8 attenuation_5g
[0x8];
6550 u8 reserved_at_40
[0x18];
6551 u8 attenuation_7g
[0x8];
6553 u8 reserved_at_60
[0x18];
6554 u8 attenuation_12g
[0x8];
6557 struct mlx5_ifc_pmpe_reg_bits
{
6558 u8 reserved_at_0
[0x8];
6560 u8 reserved_at_10
[0xc];
6561 u8 module_status
[0x4];
6563 u8 reserved_at_20
[0x60];
6566 struct mlx5_ifc_pmpc_reg_bits
{
6567 u8 module_state_updated
[32][0x8];
6570 struct mlx5_ifc_pmlpn_reg_bits
{
6571 u8 reserved_at_0
[0x4];
6572 u8 mlpn_status
[0x4];
6574 u8 reserved_at_10
[0x10];
6577 u8 reserved_at_21
[0x1f];
6580 struct mlx5_ifc_pmlp_reg_bits
{
6582 u8 reserved_at_1
[0x7];
6584 u8 reserved_at_10
[0x8];
6587 u8 lane0_module_mapping
[0x20];
6589 u8 lane1_module_mapping
[0x20];
6591 u8 lane2_module_mapping
[0x20];
6593 u8 lane3_module_mapping
[0x20];
6595 u8 reserved_at_a0
[0x160];
6598 struct mlx5_ifc_pmaos_reg_bits
{
6599 u8 reserved_at_0
[0x8];
6601 u8 reserved_at_10
[0x4];
6602 u8 admin_status
[0x4];
6603 u8 reserved_at_18
[0x4];
6604 u8 oper_status
[0x4];
6608 u8 reserved_at_22
[0x1c];
6611 u8 reserved_at_40
[0x40];
6614 struct mlx5_ifc_plpc_reg_bits
{
6615 u8 reserved_at_0
[0x4];
6617 u8 reserved_at_10
[0x4];
6619 u8 reserved_at_18
[0x8];
6621 u8 reserved_at_20
[0x10];
6622 u8 lane_speed
[0x10];
6624 u8 reserved_at_40
[0x17];
6626 u8 fec_mode_policy
[0x8];
6628 u8 retransmission_capability
[0x8];
6629 u8 fec_mode_capability
[0x18];
6631 u8 retransmission_support_admin
[0x8];
6632 u8 fec_mode_support_admin
[0x18];
6634 u8 retransmission_request_admin
[0x8];
6635 u8 fec_mode_request_admin
[0x18];
6637 u8 reserved_at_c0
[0x80];
6640 struct mlx5_ifc_plib_reg_bits
{
6641 u8 reserved_at_0
[0x8];
6643 u8 reserved_at_10
[0x8];
6646 u8 reserved_at_20
[0x60];
6649 struct mlx5_ifc_plbf_reg_bits
{
6650 u8 reserved_at_0
[0x8];
6652 u8 reserved_at_10
[0xd];
6655 u8 reserved_at_20
[0x20];
6658 struct mlx5_ifc_pipg_reg_bits
{
6659 u8 reserved_at_0
[0x8];
6661 u8 reserved_at_10
[0x10];
6664 u8 reserved_at_21
[0x19];
6666 u8 reserved_at_3e
[0x2];
6669 struct mlx5_ifc_pifr_reg_bits
{
6670 u8 reserved_at_0
[0x8];
6672 u8 reserved_at_10
[0x10];
6674 u8 reserved_at_20
[0xe0];
6676 u8 port_filter
[8][0x20];
6678 u8 port_filter_update_en
[8][0x20];
6681 struct mlx5_ifc_pfcc_reg_bits
{
6682 u8 reserved_at_0
[0x8];
6684 u8 reserved_at_10
[0x10];
6687 u8 reserved_at_24
[0x4];
6688 u8 prio_mask_tx
[0x8];
6689 u8 reserved_at_30
[0x8];
6690 u8 prio_mask_rx
[0x8];
6694 u8 reserved_at_42
[0x6];
6696 u8 reserved_at_50
[0x10];
6700 u8 reserved_at_62
[0x6];
6702 u8 reserved_at_70
[0x10];
6704 u8 reserved_at_80
[0x80];
6707 struct mlx5_ifc_pelc_reg_bits
{
6709 u8 reserved_at_4
[0x4];
6711 u8 reserved_at_10
[0x10];
6714 u8 op_capability
[0x8];
6720 u8 capability
[0x40];
6726 u8 reserved_at_140
[0x80];
6729 struct mlx5_ifc_peir_reg_bits
{
6730 u8 reserved_at_0
[0x8];
6732 u8 reserved_at_10
[0x10];
6734 u8 reserved_at_20
[0xc];
6735 u8 error_count
[0x4];
6736 u8 reserved_at_30
[0x10];
6738 u8 reserved_at_40
[0xc];
6740 u8 reserved_at_50
[0x8];
6744 struct mlx5_ifc_pcap_reg_bits
{
6745 u8 reserved_at_0
[0x8];
6747 u8 reserved_at_10
[0x10];
6749 u8 port_capability_mask
[4][0x20];
6752 struct mlx5_ifc_paos_reg_bits
{
6755 u8 reserved_at_10
[0x4];
6756 u8 admin_status
[0x4];
6757 u8 reserved_at_18
[0x4];
6758 u8 oper_status
[0x4];
6762 u8 reserved_at_22
[0x1c];
6765 u8 reserved_at_40
[0x40];
6768 struct mlx5_ifc_pamp_reg_bits
{
6769 u8 reserved_at_0
[0x8];
6770 u8 opamp_group
[0x8];
6771 u8 reserved_at_10
[0xc];
6772 u8 opamp_group_type
[0x4];
6774 u8 start_index
[0x10];
6775 u8 reserved_at_30
[0x4];
6776 u8 num_of_indices
[0xc];
6778 u8 index_data
[18][0x10];
6781 struct mlx5_ifc_lane_2_module_mapping_bits
{
6782 u8 reserved_at_0
[0x6];
6784 u8 reserved_at_8
[0x6];
6786 u8 reserved_at_10
[0x8];
6790 struct mlx5_ifc_bufferx_reg_bits
{
6791 u8 reserved_at_0
[0x6];
6794 u8 reserved_at_8
[0xc];
6797 u8 xoff_threshold
[0x10];
6798 u8 xon_threshold
[0x10];
6801 struct mlx5_ifc_set_node_in_bits
{
6802 u8 node_description
[64][0x8];
6805 struct mlx5_ifc_register_power_settings_bits
{
6806 u8 reserved_at_0
[0x18];
6807 u8 power_settings_level
[0x8];
6809 u8 reserved_at_20
[0x60];
6812 struct mlx5_ifc_register_host_endianness_bits
{
6814 u8 reserved_at_1
[0x1f];
6816 u8 reserved_at_20
[0x60];
6819 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
6820 u8 reserved_at_0
[0x20];
6824 u8 addressh_63_32
[0x20];
6826 u8 addressl_31_0
[0x20];
6829 struct mlx5_ifc_ud_adrs_vector_bits
{
6833 u8 reserved_at_41
[0x7];
6834 u8 destination_qp_dct
[0x18];
6836 u8 static_rate
[0x4];
6837 u8 sl_eth_prio
[0x4];
6840 u8 rlid_udp_sport
[0x10];
6842 u8 reserved_at_80
[0x20];
6844 u8 rmac_47_16
[0x20];
6850 u8 reserved_at_e0
[0x1];
6852 u8 reserved_at_e2
[0x2];
6853 u8 src_addr_index
[0x8];
6854 u8 flow_label
[0x14];
6856 u8 rgid_rip
[16][0x8];
6859 struct mlx5_ifc_pages_req_event_bits
{
6860 u8 reserved_at_0
[0x10];
6861 u8 function_id
[0x10];
6865 u8 reserved_at_40
[0xa0];
6868 struct mlx5_ifc_eqe_bits
{
6869 u8 reserved_at_0
[0x8];
6871 u8 reserved_at_10
[0x8];
6872 u8 event_sub_type
[0x8];
6874 u8 reserved_at_20
[0xe0];
6876 union mlx5_ifc_event_auto_bits event_data
;
6878 u8 reserved_at_1e0
[0x10];
6880 u8 reserved_at_1f8
[0x7];
6885 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
6888 struct mlx5_ifc_cmd_queue_entry_bits
{
6890 u8 reserved_at_8
[0x18];
6892 u8 input_length
[0x20];
6894 u8 input_mailbox_pointer_63_32
[0x20];
6896 u8 input_mailbox_pointer_31_9
[0x17];
6897 u8 reserved_at_77
[0x9];
6899 u8 command_input_inline_data
[16][0x8];
6901 u8 command_output_inline_data
[16][0x8];
6903 u8 output_mailbox_pointer_63_32
[0x20];
6905 u8 output_mailbox_pointer_31_9
[0x17];
6906 u8 reserved_at_1b7
[0x9];
6908 u8 output_length
[0x20];
6912 u8 reserved_at_1f0
[0x8];
6917 struct mlx5_ifc_cmd_out_bits
{
6919 u8 reserved_at_8
[0x18];
6923 u8 command_output
[0x20];
6926 struct mlx5_ifc_cmd_in_bits
{
6928 u8 reserved_at_10
[0x10];
6930 u8 reserved_at_20
[0x10];
6933 u8 command
[0][0x20];
6936 struct mlx5_ifc_cmd_if_box_bits
{
6937 u8 mailbox_data
[512][0x8];
6939 u8 reserved_at_1000
[0x180];
6941 u8 next_pointer_63_32
[0x20];
6943 u8 next_pointer_31_10
[0x16];
6944 u8 reserved_at_11b6
[0xa];
6946 u8 block_number
[0x20];
6948 u8 reserved_at_11e0
[0x8];
6950 u8 ctrl_signature
[0x8];
6954 struct mlx5_ifc_mtt_bits
{
6955 u8 ptag_63_32
[0x20];
6958 u8 reserved_at_38
[0x6];
6963 struct mlx5_ifc_query_wol_rol_out_bits
{
6965 u8 reserved_at_8
[0x18];
6969 u8 reserved_at_40
[0x10];
6973 u8 reserved_at_60
[0x20];
6976 struct mlx5_ifc_query_wol_rol_in_bits
{
6978 u8 reserved_at_10
[0x10];
6980 u8 reserved_at_20
[0x10];
6983 u8 reserved_at_40
[0x40];
6986 struct mlx5_ifc_set_wol_rol_out_bits
{
6988 u8 reserved_at_8
[0x18];
6992 u8 reserved_at_40
[0x40];
6995 struct mlx5_ifc_set_wol_rol_in_bits
{
6997 u8 reserved_at_10
[0x10];
6999 u8 reserved_at_20
[0x10];
7002 u8 rol_mode_valid
[0x1];
7003 u8 wol_mode_valid
[0x1];
7004 u8 reserved_at_42
[0xe];
7008 u8 reserved_at_60
[0x20];
7012 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
7013 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
7014 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
7018 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
7019 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
7020 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
7024 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
7025 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
7026 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
7027 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
7028 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
7029 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
7030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
7031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
7032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
7033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
7034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
7037 struct mlx5_ifc_initial_seg_bits
{
7038 u8 fw_rev_minor
[0x10];
7039 u8 fw_rev_major
[0x10];
7041 u8 cmd_interface_rev
[0x10];
7042 u8 fw_rev_subminor
[0x10];
7044 u8 reserved_at_40
[0x40];
7046 u8 cmdq_phy_addr_63_32
[0x20];
7048 u8 cmdq_phy_addr_31_12
[0x14];
7049 u8 reserved_at_b4
[0x2];
7050 u8 nic_interface
[0x2];
7051 u8 log_cmdq_size
[0x4];
7052 u8 log_cmdq_stride
[0x4];
7054 u8 command_doorbell_vector
[0x20];
7056 u8 reserved_at_e0
[0xf00];
7058 u8 initializing
[0x1];
7059 u8 reserved_at_fe1
[0x4];
7060 u8 nic_interface_supported
[0x3];
7061 u8 reserved_at_fe8
[0x18];
7063 struct mlx5_ifc_health_buffer_bits health_buffer
;
7065 u8 no_dram_nic_offset
[0x20];
7067 u8 reserved_at_1220
[0x6e40];
7069 u8 reserved_at_8060
[0x1f];
7072 u8 health_syndrome
[0x8];
7073 u8 health_counter
[0x18];
7075 u8 reserved_at_80a0
[0x17fc0];
7078 union mlx5_ifc_ports_control_registers_document_bits
{
7079 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
7080 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
7081 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
7082 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
7083 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
7084 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
7085 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
7086 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
7087 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
7088 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
7089 struct mlx5_ifc_paos_reg_bits paos_reg
;
7090 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
7091 struct mlx5_ifc_peir_reg_bits peir_reg
;
7092 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
7093 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
7094 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
7095 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
7096 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
7097 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
7098 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
7099 struct mlx5_ifc_plib_reg_bits plib_reg
;
7100 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
7101 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
7102 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
7103 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
7104 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
7105 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
7106 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
7107 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
7108 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
7109 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
7110 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
7111 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
7112 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
7113 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
7114 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
7115 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
7116 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
7117 struct mlx5_ifc_pude_reg_bits pude_reg
;
7118 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
7119 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
7120 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
7121 u8 reserved_at_0
[0x60e0];
7124 union mlx5_ifc_debug_enhancements_document_bits
{
7125 struct mlx5_ifc_health_buffer_bits health_buffer
;
7126 u8 reserved_at_0
[0x200];
7129 union mlx5_ifc_uplink_pci_interface_document_bits
{
7130 struct mlx5_ifc_initial_seg_bits initial_seg
;
7131 u8 reserved_at_0
[0x20060];
7134 struct mlx5_ifc_set_flow_table_root_out_bits
{
7136 u8 reserved_at_8
[0x18];
7140 u8 reserved_at_40
[0x40];
7143 struct mlx5_ifc_set_flow_table_root_in_bits
{
7145 u8 reserved_at_10
[0x10];
7147 u8 reserved_at_20
[0x10];
7150 u8 reserved_at_40
[0x40];
7153 u8 reserved_at_88
[0x18];
7155 u8 reserved_at_a0
[0x8];
7158 u8 reserved_at_c0
[0x140];
7162 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= 0x1,
7165 struct mlx5_ifc_modify_flow_table_out_bits
{
7167 u8 reserved_at_8
[0x18];
7171 u8 reserved_at_40
[0x40];
7174 struct mlx5_ifc_modify_flow_table_in_bits
{
7176 u8 reserved_at_10
[0x10];
7178 u8 reserved_at_20
[0x10];
7181 u8 reserved_at_40
[0x20];
7183 u8 reserved_at_60
[0x10];
7184 u8 modify_field_select
[0x10];
7187 u8 reserved_at_88
[0x18];
7189 u8 reserved_at_a0
[0x8];
7192 u8 reserved_at_c0
[0x4];
7193 u8 table_miss_mode
[0x4];
7194 u8 reserved_at_c8
[0x18];
7196 u8 reserved_at_e0
[0x8];
7197 u8 table_miss_id
[0x18];
7199 u8 reserved_at_100
[0x100];
7202 struct mlx5_ifc_ets_tcn_config_reg_bits
{
7206 u8 reserved_at_3
[0x9];
7208 u8 reserved_at_10
[0x9];
7209 u8 bw_allocation
[0x7];
7211 u8 reserved_at_20
[0xc];
7212 u8 max_bw_units
[0x4];
7213 u8 reserved_at_30
[0x8];
7214 u8 max_bw_value
[0x8];
7217 struct mlx5_ifc_ets_global_config_reg_bits
{
7218 u8 reserved_at_0
[0x2];
7220 u8 reserved_at_3
[0x1d];
7222 u8 reserved_at_20
[0xc];
7223 u8 max_bw_units
[0x4];
7224 u8 reserved_at_30
[0x8];
7225 u8 max_bw_value
[0x8];
7228 struct mlx5_ifc_qetc_reg_bits
{
7229 u8 reserved_at_0
[0x8];
7230 u8 port_number
[0x8];
7231 u8 reserved_at_10
[0x30];
7233 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration
[0x8];
7234 struct mlx5_ifc_ets_global_config_reg_bits global_configuration
;
7237 struct mlx5_ifc_qtct_reg_bits
{
7238 u8 reserved_at_0
[0x8];
7239 u8 port_number
[0x8];
7240 u8 reserved_at_10
[0xd];
7243 u8 reserved_at_20
[0x1d];
7247 #endif /* MLX5_IFC_H */