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Merge branches 'cxgb4' and 'mlx5' into k.o/for-4.8
[deliverable/linux.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60 };
61
62 enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67 };
68
69 enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72 };
73
74 enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
148 MLX5_CMD_OP_ALLOC_PD = 0x800,
149 MLX5_CMD_OP_DEALLOC_PD = 0x801,
150 MLX5_CMD_OP_ALLOC_UAR = 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
155 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
160 MLX5_CMD_OP_NOP = 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
177 MLX5_CMD_OP_CREATE_TIR = 0x900,
178 MLX5_CMD_OP_MODIFY_TIR = 0x901,
179 MLX5_CMD_OP_DESTROY_TIR = 0x902,
180 MLX5_CMD_OP_QUERY_TIR = 0x903,
181 MLX5_CMD_OP_CREATE_SQ = 0x904,
182 MLX5_CMD_OP_MODIFY_SQ = 0x905,
183 MLX5_CMD_OP_DESTROY_SQ = 0x906,
184 MLX5_CMD_OP_QUERY_SQ = 0x907,
185 MLX5_CMD_OP_CREATE_RQ = 0x908,
186 MLX5_CMD_OP_MODIFY_RQ = 0x909,
187 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
188 MLX5_CMD_OP_QUERY_RQ = 0x90b,
189 MLX5_CMD_OP_CREATE_RMP = 0x90c,
190 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
191 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
192 MLX5_CMD_OP_QUERY_RMP = 0x90f,
193 MLX5_CMD_OP_CREATE_TIS = 0x912,
194 MLX5_CMD_OP_MODIFY_TIS = 0x913,
195 MLX5_CMD_OP_DESTROY_TIS = 0x914,
196 MLX5_CMD_OP_QUERY_TIS = 0x915,
197 MLX5_CMD_OP_CREATE_RQT = 0x916,
198 MLX5_CMD_OP_MODIFY_RQT = 0x917,
199 MLX5_CMD_OP_DESTROY_RQT = 0x918,
200 MLX5_CMD_OP_QUERY_RQT = 0x919,
201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
202 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
203 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
204 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
205 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
206 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
207 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
215 MLX5_CMD_OP_MAX
216 };
217
218 struct mlx5_ifc_flow_table_fields_supported_bits {
219 u8 outer_dmac[0x1];
220 u8 outer_smac[0x1];
221 u8 outer_ether_type[0x1];
222 u8 reserved_at_3[0x1];
223 u8 outer_first_prio[0x1];
224 u8 outer_first_cfi[0x1];
225 u8 outer_first_vid[0x1];
226 u8 reserved_at_7[0x1];
227 u8 outer_second_prio[0x1];
228 u8 outer_second_cfi[0x1];
229 u8 outer_second_vid[0x1];
230 u8 reserved_at_b[0x1];
231 u8 outer_sip[0x1];
232 u8 outer_dip[0x1];
233 u8 outer_frag[0x1];
234 u8 outer_ip_protocol[0x1];
235 u8 outer_ip_ecn[0x1];
236 u8 outer_ip_dscp[0x1];
237 u8 outer_udp_sport[0x1];
238 u8 outer_udp_dport[0x1];
239 u8 outer_tcp_sport[0x1];
240 u8 outer_tcp_dport[0x1];
241 u8 outer_tcp_flags[0x1];
242 u8 outer_gre_protocol[0x1];
243 u8 outer_gre_key[0x1];
244 u8 outer_vxlan_vni[0x1];
245 u8 reserved_at_1a[0x5];
246 u8 source_eswitch_port[0x1];
247
248 u8 inner_dmac[0x1];
249 u8 inner_smac[0x1];
250 u8 inner_ether_type[0x1];
251 u8 reserved_at_23[0x1];
252 u8 inner_first_prio[0x1];
253 u8 inner_first_cfi[0x1];
254 u8 inner_first_vid[0x1];
255 u8 reserved_at_27[0x1];
256 u8 inner_second_prio[0x1];
257 u8 inner_second_cfi[0x1];
258 u8 inner_second_vid[0x1];
259 u8 reserved_at_2b[0x1];
260 u8 inner_sip[0x1];
261 u8 inner_dip[0x1];
262 u8 inner_frag[0x1];
263 u8 inner_ip_protocol[0x1];
264 u8 inner_ip_ecn[0x1];
265 u8 inner_ip_dscp[0x1];
266 u8 inner_udp_sport[0x1];
267 u8 inner_udp_dport[0x1];
268 u8 inner_tcp_sport[0x1];
269 u8 inner_tcp_dport[0x1];
270 u8 inner_tcp_flags[0x1];
271 u8 reserved_at_37[0x9];
272
273 u8 reserved_at_40[0x40];
274 };
275
276 struct mlx5_ifc_flow_table_prop_layout_bits {
277 u8 ft_support[0x1];
278 u8 reserved_at_1[0x1];
279 u8 flow_counter[0x1];
280 u8 flow_modify_en[0x1];
281 u8 modify_root[0x1];
282 u8 identified_miss_table_mode[0x1];
283 u8 flow_table_modify[0x1];
284 u8 reserved_at_7[0x19];
285
286 u8 reserved_at_20[0x2];
287 u8 log_max_ft_size[0x6];
288 u8 reserved_at_28[0x10];
289 u8 max_ft_level[0x8];
290
291 u8 reserved_at_40[0x20];
292
293 u8 reserved_at_60[0x18];
294 u8 log_max_ft_num[0x8];
295
296 u8 reserved_at_80[0x18];
297 u8 log_max_destination[0x8];
298
299 u8 reserved_at_a0[0x18];
300 u8 log_max_flow[0x8];
301
302 u8 reserved_at_c0[0x40];
303
304 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
305
306 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
307 };
308
309 struct mlx5_ifc_odp_per_transport_service_cap_bits {
310 u8 send[0x1];
311 u8 receive[0x1];
312 u8 write[0x1];
313 u8 read[0x1];
314 u8 reserved_at_4[0x1];
315 u8 srq_receive[0x1];
316 u8 reserved_at_6[0x1a];
317 };
318
319 struct mlx5_ifc_ipv4_layout_bits {
320 u8 reserved_at_0[0x60];
321
322 u8 ipv4[0x20];
323 };
324
325 struct mlx5_ifc_ipv6_layout_bits {
326 u8 ipv6[16][0x8];
327 };
328
329 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
330 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
331 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
332 u8 reserved_at_0[0x80];
333 };
334
335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
336 u8 smac_47_16[0x20];
337
338 u8 smac_15_0[0x10];
339 u8 ethertype[0x10];
340
341 u8 dmac_47_16[0x20];
342
343 u8 dmac_15_0[0x10];
344 u8 first_prio[0x3];
345 u8 first_cfi[0x1];
346 u8 first_vid[0xc];
347
348 u8 ip_protocol[0x8];
349 u8 ip_dscp[0x6];
350 u8 ip_ecn[0x2];
351 u8 vlan_tag[0x1];
352 u8 reserved_at_91[0x1];
353 u8 frag[0x1];
354 u8 reserved_at_93[0x4];
355 u8 tcp_flags[0x9];
356
357 u8 tcp_sport[0x10];
358 u8 tcp_dport[0x10];
359
360 u8 reserved_at_c0[0x20];
361
362 u8 udp_sport[0x10];
363 u8 udp_dport[0x10];
364
365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
366
367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
368 };
369
370 struct mlx5_ifc_fte_match_set_misc_bits {
371 u8 reserved_at_0[0x8];
372 u8 source_sqn[0x18];
373
374 u8 reserved_at_20[0x10];
375 u8 source_port[0x10];
376
377 u8 outer_second_prio[0x3];
378 u8 outer_second_cfi[0x1];
379 u8 outer_second_vid[0xc];
380 u8 inner_second_prio[0x3];
381 u8 inner_second_cfi[0x1];
382 u8 inner_second_vid[0xc];
383
384 u8 outer_second_vlan_tag[0x1];
385 u8 inner_second_vlan_tag[0x1];
386 u8 reserved_at_62[0xe];
387 u8 gre_protocol[0x10];
388
389 u8 gre_key_h[0x18];
390 u8 gre_key_l[0x8];
391
392 u8 vxlan_vni[0x18];
393 u8 reserved_at_b8[0x8];
394
395 u8 reserved_at_c0[0x20];
396
397 u8 reserved_at_e0[0xc];
398 u8 outer_ipv6_flow_label[0x14];
399
400 u8 reserved_at_100[0xc];
401 u8 inner_ipv6_flow_label[0x14];
402
403 u8 reserved_at_120[0xe0];
404 };
405
406 struct mlx5_ifc_cmd_pas_bits {
407 u8 pa_h[0x20];
408
409 u8 pa_l[0x14];
410 u8 reserved_at_34[0xc];
411 };
412
413 struct mlx5_ifc_uint64_bits {
414 u8 hi[0x20];
415
416 u8 lo[0x20];
417 };
418
419 enum {
420 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
421 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
422 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
423 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
424 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
425 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
426 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
427 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
428 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
429 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
430 };
431
432 struct mlx5_ifc_ads_bits {
433 u8 fl[0x1];
434 u8 free_ar[0x1];
435 u8 reserved_at_2[0xe];
436 u8 pkey_index[0x10];
437
438 u8 reserved_at_20[0x8];
439 u8 grh[0x1];
440 u8 mlid[0x7];
441 u8 rlid[0x10];
442
443 u8 ack_timeout[0x5];
444 u8 reserved_at_45[0x3];
445 u8 src_addr_index[0x8];
446 u8 reserved_at_50[0x4];
447 u8 stat_rate[0x4];
448 u8 hop_limit[0x8];
449
450 u8 reserved_at_60[0x4];
451 u8 tclass[0x8];
452 u8 flow_label[0x14];
453
454 u8 rgid_rip[16][0x8];
455
456 u8 reserved_at_100[0x4];
457 u8 f_dscp[0x1];
458 u8 f_ecn[0x1];
459 u8 reserved_at_106[0x1];
460 u8 f_eth_prio[0x1];
461 u8 ecn[0x2];
462 u8 dscp[0x6];
463 u8 udp_sport[0x10];
464
465 u8 dei_cfi[0x1];
466 u8 eth_prio[0x3];
467 u8 sl[0x4];
468 u8 port[0x8];
469 u8 rmac_47_32[0x10];
470
471 u8 rmac_31_0[0x20];
472 };
473
474 struct mlx5_ifc_flow_table_nic_cap_bits {
475 u8 nic_rx_multi_path_tirs[0x1];
476 u8 reserved_at_1[0x1ff];
477
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
479
480 u8 reserved_at_400[0x200];
481
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
483
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
485
486 u8 reserved_at_a00[0x200];
487
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
489
490 u8 reserved_at_e00[0x7200];
491 };
492
493 struct mlx5_ifc_flow_table_eswitch_cap_bits {
494 u8 reserved_at_0[0x200];
495
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
497
498 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
499
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
501
502 u8 reserved_at_800[0x7800];
503 };
504
505 struct mlx5_ifc_e_switch_cap_bits {
506 u8 vport_svlan_strip[0x1];
507 u8 vport_cvlan_strip[0x1];
508 u8 vport_svlan_insert[0x1];
509 u8 vport_cvlan_insert_if_not_exist[0x1];
510 u8 vport_cvlan_insert_overwrite[0x1];
511 u8 reserved_at_5[0x19];
512 u8 nic_vport_node_guid_modify[0x1];
513 u8 nic_vport_port_guid_modify[0x1];
514
515 u8 reserved_at_20[0x7e0];
516 };
517
518 struct mlx5_ifc_qos_cap_bits {
519 u8 packet_pacing[0x1];
520 u8 reserved_0[0x1f];
521 u8 reserved_1[0x20];
522 u8 packet_pacing_max_rate[0x20];
523 u8 packet_pacing_min_rate[0x20];
524 u8 reserved_2[0x10];
525 u8 packet_pacing_rate_table_size[0x10];
526 u8 reserved_3[0x760];
527 };
528
529 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
530 u8 csum_cap[0x1];
531 u8 vlan_cap[0x1];
532 u8 lro_cap[0x1];
533 u8 lro_psh_flag[0x1];
534 u8 lro_time_stamp[0x1];
535 u8 reserved_at_5[0x3];
536 u8 self_lb_en_modifiable[0x1];
537 u8 reserved_at_9[0x2];
538 u8 max_lso_cap[0x5];
539 u8 reserved_at_10[0x4];
540 u8 rss_ind_tbl_cap[0x4];
541 u8 reg_umr_sq[0x1];
542 u8 scatter_fcs[0x1];
543 u8 reserved_at_1a[0x1];
544 u8 tunnel_lso_const_out_ip_id[0x1];
545 u8 reserved_at_1c[0x2];
546 u8 tunnel_statless_gre[0x1];
547 u8 tunnel_stateless_vxlan[0x1];
548
549 u8 reserved_at_20[0x20];
550
551 u8 reserved_at_40[0x10];
552 u8 lro_min_mss_size[0x10];
553
554 u8 reserved_at_60[0x120];
555
556 u8 lro_timer_supported_periods[4][0x20];
557
558 u8 reserved_at_200[0x600];
559 };
560
561 struct mlx5_ifc_roce_cap_bits {
562 u8 roce_apm[0x1];
563 u8 reserved_at_1[0x1f];
564
565 u8 reserved_at_20[0x60];
566
567 u8 reserved_at_80[0xc];
568 u8 l3_type[0x4];
569 u8 reserved_at_90[0x8];
570 u8 roce_version[0x8];
571
572 u8 reserved_at_a0[0x10];
573 u8 r_roce_dest_udp_port[0x10];
574
575 u8 r_roce_max_src_udp_port[0x10];
576 u8 r_roce_min_src_udp_port[0x10];
577
578 u8 reserved_at_e0[0x10];
579 u8 roce_address_table_size[0x10];
580
581 u8 reserved_at_100[0x700];
582 };
583
584 enum {
585 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
588 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
589 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
590 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
591 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
592 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
593 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
594 };
595
596 enum {
597 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
606 };
607
608 struct mlx5_ifc_atomic_caps_bits {
609 u8 reserved_at_0[0x40];
610
611 u8 atomic_req_8B_endianess_mode[0x2];
612 u8 reserved_at_42[0x4];
613 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
614
615 u8 reserved_at_47[0x19];
616
617 u8 reserved_at_60[0x20];
618
619 u8 reserved_at_80[0x10];
620 u8 atomic_operations[0x10];
621
622 u8 reserved_at_a0[0x10];
623 u8 atomic_size_qp[0x10];
624
625 u8 reserved_at_c0[0x10];
626 u8 atomic_size_dc[0x10];
627
628 u8 reserved_at_e0[0x720];
629 };
630
631 struct mlx5_ifc_odp_cap_bits {
632 u8 reserved_at_0[0x40];
633
634 u8 sig[0x1];
635 u8 reserved_at_41[0x1f];
636
637 u8 reserved_at_60[0x20];
638
639 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
640
641 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
642
643 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
644
645 u8 reserved_at_e0[0x720];
646 };
647
648 struct mlx5_ifc_calc_op {
649 u8 reserved_at_0[0x10];
650 u8 reserved_at_10[0x9];
651 u8 op_swap_endianness[0x1];
652 u8 op_min[0x1];
653 u8 op_xor[0x1];
654 u8 op_or[0x1];
655 u8 op_and[0x1];
656 u8 op_max[0x1];
657 u8 op_add[0x1];
658 };
659
660 struct mlx5_ifc_vector_calc_cap_bits {
661 u8 calc_matrix[0x1];
662 u8 reserved_at_1[0x1f];
663 u8 reserved_at_20[0x8];
664 u8 max_vec_count[0x8];
665 u8 reserved_at_30[0xd];
666 u8 max_chunk_size[0x3];
667 struct mlx5_ifc_calc_op calc0;
668 struct mlx5_ifc_calc_op calc1;
669 struct mlx5_ifc_calc_op calc2;
670 struct mlx5_ifc_calc_op calc3;
671
672 u8 reserved_at_e0[0x720];
673 };
674
675 enum {
676 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
677 MLX5_WQ_TYPE_CYCLIC = 0x1,
678 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
679 };
680
681 enum {
682 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
683 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
684 };
685
686 enum {
687 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
688 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
689 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
690 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
691 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
692 };
693
694 enum {
695 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
696 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
697 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
698 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
699 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
700 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
701 };
702
703 enum {
704 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
705 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
706 };
707
708 enum {
709 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
710 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
711 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
712 };
713
714 enum {
715 MLX5_CAP_PORT_TYPE_IB = 0x0,
716 MLX5_CAP_PORT_TYPE_ETH = 0x1,
717 };
718
719 struct mlx5_ifc_cmd_hca_cap_bits {
720 u8 reserved_at_0[0x80];
721
722 u8 log_max_srq_sz[0x8];
723 u8 log_max_qp_sz[0x8];
724 u8 reserved_at_90[0xb];
725 u8 log_max_qp[0x5];
726
727 u8 reserved_at_a0[0xb];
728 u8 log_max_srq[0x5];
729 u8 reserved_at_b0[0x10];
730
731 u8 reserved_at_c0[0x8];
732 u8 log_max_cq_sz[0x8];
733 u8 reserved_at_d0[0xb];
734 u8 log_max_cq[0x5];
735
736 u8 log_max_eq_sz[0x8];
737 u8 reserved_at_e8[0x2];
738 u8 log_max_mkey[0x6];
739 u8 reserved_at_f0[0xc];
740 u8 log_max_eq[0x4];
741
742 u8 max_indirection[0x8];
743 u8 reserved_at_108[0x1];
744 u8 log_max_mrw_sz[0x7];
745 u8 reserved_at_110[0x2];
746 u8 log_max_bsf_list_size[0x6];
747 u8 reserved_at_118[0x2];
748 u8 log_max_klm_list_size[0x6];
749
750 u8 reserved_at_120[0xa];
751 u8 log_max_ra_req_dc[0x6];
752 u8 reserved_at_130[0xa];
753 u8 log_max_ra_res_dc[0x6];
754
755 u8 reserved_at_140[0xa];
756 u8 log_max_ra_req_qp[0x6];
757 u8 reserved_at_150[0xa];
758 u8 log_max_ra_res_qp[0x6];
759
760 u8 pad_cap[0x1];
761 u8 cc_query_allowed[0x1];
762 u8 cc_modify_allowed[0x1];
763 u8 reserved_at_163[0xd];
764 u8 gid_table_size[0x10];
765
766 u8 out_of_seq_cnt[0x1];
767 u8 vport_counters[0x1];
768 u8 retransmission_q_counters[0x1];
769 u8 reserved_at_183[0x3];
770 u8 max_qp_cnt[0xa];
771 u8 pkey_table_size[0x10];
772
773 u8 vport_group_manager[0x1];
774 u8 vhca_group_manager[0x1];
775 u8 ib_virt[0x1];
776 u8 eth_virt[0x1];
777 u8 reserved_at_1a4[0x1];
778 u8 ets[0x1];
779 u8 nic_flow_table[0x1];
780 u8 eswitch_flow_table[0x1];
781 u8 early_vf_enable[0x1];
782 u8 reserved_at_1a9[0x2];
783 u8 local_ca_ack_delay[0x5];
784 u8 reserved_at_1af[0x2];
785 u8 ports_check[0x1];
786 u8 reserved_at_1b2[0x1];
787 u8 disable_link_up[0x1];
788 u8 beacon_led[0x1];
789 u8 port_type[0x2];
790 u8 num_ports[0x8];
791
792 u8 reserved_at_1c0[0x3];
793 u8 log_max_msg[0x5];
794 u8 reserved_at_1c8[0x4];
795 u8 max_tc[0x4];
796 u8 reserved_at_1d0[0x1];
797 u8 dcbx[0x1];
798 u8 reserved_at_1d2[0x4];
799 u8 rol_s[0x1];
800 u8 rol_g[0x1];
801 u8 reserved_at_1d8[0x1];
802 u8 wol_s[0x1];
803 u8 wol_g[0x1];
804 u8 wol_a[0x1];
805 u8 wol_b[0x1];
806 u8 wol_m[0x1];
807 u8 wol_u[0x1];
808 u8 wol_p[0x1];
809
810 u8 stat_rate_support[0x10];
811 u8 reserved_at_1f0[0xc];
812 u8 cqe_version[0x4];
813
814 u8 compact_address_vector[0x1];
815 u8 striding_rq[0x1];
816 u8 reserved_at_201[0x2];
817 u8 ipoib_basic_offloads[0x1];
818 u8 reserved_at_205[0xa];
819 u8 drain_sigerr[0x1];
820 u8 cmdif_checksum[0x2];
821 u8 sigerr_cqe[0x1];
822 u8 reserved_at_213[0x1];
823 u8 wq_signature[0x1];
824 u8 sctr_data_cqe[0x1];
825 u8 reserved_at_216[0x1];
826 u8 sho[0x1];
827 u8 tph[0x1];
828 u8 rf[0x1];
829 u8 dct[0x1];
830 u8 qos[0x1];
831 u8 eth_net_offloads[0x1];
832 u8 roce[0x1];
833 u8 atomic[0x1];
834 u8 reserved_at_21f[0x1];
835
836 u8 cq_oi[0x1];
837 u8 cq_resize[0x1];
838 u8 cq_moderation[0x1];
839 u8 reserved_at_223[0x3];
840 u8 cq_eq_remap[0x1];
841 u8 pg[0x1];
842 u8 block_lb_mc[0x1];
843 u8 reserved_at_229[0x1];
844 u8 scqe_break_moderation[0x1];
845 u8 cq_period_start_from_cqe[0x1];
846 u8 cd[0x1];
847 u8 reserved_at_22d[0x1];
848 u8 apm[0x1];
849 u8 vector_calc[0x1];
850 u8 umr_ptr_rlky[0x1];
851 u8 imaicl[0x1];
852 u8 reserved_at_232[0x4];
853 u8 qkv[0x1];
854 u8 pkv[0x1];
855 u8 set_deth_sqpn[0x1];
856 u8 reserved_at_239[0x3];
857 u8 xrc[0x1];
858 u8 ud[0x1];
859 u8 uc[0x1];
860 u8 rc[0x1];
861
862 u8 reserved_at_240[0xa];
863 u8 uar_sz[0x6];
864 u8 reserved_at_250[0x8];
865 u8 log_pg_sz[0x8];
866
867 u8 bf[0x1];
868 u8 reserved_at_261[0x1];
869 u8 pad_tx_eth_packet[0x1];
870 u8 reserved_at_263[0x8];
871 u8 log_bf_reg_size[0x5];
872 u8 reserved_at_270[0x10];
873
874 u8 reserved_at_280[0x10];
875 u8 max_wqe_sz_sq[0x10];
876
877 u8 reserved_at_2a0[0x10];
878 u8 max_wqe_sz_rq[0x10];
879
880 u8 reserved_at_2c0[0x10];
881 u8 max_wqe_sz_sq_dc[0x10];
882
883 u8 reserved_at_2e0[0x7];
884 u8 max_qp_mcg[0x19];
885
886 u8 reserved_at_300[0x18];
887 u8 log_max_mcg[0x8];
888
889 u8 reserved_at_320[0x3];
890 u8 log_max_transport_domain[0x5];
891 u8 reserved_at_328[0x3];
892 u8 log_max_pd[0x5];
893 u8 reserved_at_330[0xb];
894 u8 log_max_xrcd[0x5];
895
896 u8 reserved_at_340[0x20];
897
898 u8 reserved_at_360[0x3];
899 u8 log_max_rq[0x5];
900 u8 reserved_at_368[0x3];
901 u8 log_max_sq[0x5];
902 u8 reserved_at_370[0x3];
903 u8 log_max_tir[0x5];
904 u8 reserved_at_378[0x3];
905 u8 log_max_tis[0x5];
906
907 u8 basic_cyclic_rcv_wqe[0x1];
908 u8 reserved_at_381[0x2];
909 u8 log_max_rmp[0x5];
910 u8 reserved_at_388[0x3];
911 u8 log_max_rqt[0x5];
912 u8 reserved_at_390[0x3];
913 u8 log_max_rqt_size[0x5];
914 u8 reserved_at_398[0x3];
915 u8 log_max_tis_per_sq[0x5];
916
917 u8 reserved_at_3a0[0x3];
918 u8 log_max_stride_sz_rq[0x5];
919 u8 reserved_at_3a8[0x3];
920 u8 log_min_stride_sz_rq[0x5];
921 u8 reserved_at_3b0[0x3];
922 u8 log_max_stride_sz_sq[0x5];
923 u8 reserved_at_3b8[0x3];
924 u8 log_min_stride_sz_sq[0x5];
925
926 u8 reserved_at_3c0[0x1b];
927 u8 log_max_wq_sz[0x5];
928
929 u8 nic_vport_change_event[0x1];
930 u8 reserved_at_3e1[0xa];
931 u8 log_max_vlan_list[0x5];
932 u8 reserved_at_3f0[0x3];
933 u8 log_max_current_mc_list[0x5];
934 u8 reserved_at_3f8[0x3];
935 u8 log_max_current_uc_list[0x5];
936
937 u8 reserved_at_400[0x80];
938
939 u8 reserved_at_480[0x3];
940 u8 log_max_l2_table[0x5];
941 u8 reserved_at_488[0x8];
942 u8 log_uar_page_sz[0x10];
943
944 u8 reserved_at_4a0[0x20];
945 u8 device_frequency_mhz[0x20];
946 u8 device_frequency_khz[0x20];
947
948 u8 reserved_at_500[0x80];
949
950 u8 reserved_at_580[0x3f];
951 u8 cqe_compression[0x1];
952
953 u8 cqe_compression_timeout[0x10];
954 u8 cqe_compression_max_num[0x10];
955
956 u8 reserved_at_5e0[0x10];
957 u8 tag_matching[0x1];
958 u8 rndv_offload_rc[0x1];
959 u8 rndv_offload_dc[0x1];
960 u8 log_tag_matching_list_sz[0x5];
961 u8 reserved_at_5e8[0x3];
962 u8 log_max_xrq[0x5];
963
964 u8 reserved_at_5f0[0x200];
965 };
966
967 enum mlx5_flow_destination_type {
968 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
969 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
970 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
971
972 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
973 };
974
975 struct mlx5_ifc_dest_format_struct_bits {
976 u8 destination_type[0x8];
977 u8 destination_id[0x18];
978
979 u8 reserved_at_20[0x20];
980 };
981
982 struct mlx5_ifc_flow_counter_list_bits {
983 u8 reserved_at_0[0x10];
984 u8 flow_counter_id[0x10];
985
986 u8 reserved_at_20[0x20];
987 };
988
989 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
990 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
991 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
992 u8 reserved_at_0[0x40];
993 };
994
995 struct mlx5_ifc_fte_match_param_bits {
996 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
997
998 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
999
1000 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1001
1002 u8 reserved_at_600[0xa00];
1003 };
1004
1005 enum {
1006 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1007 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1008 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1009 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1010 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1011 };
1012
1013 struct mlx5_ifc_rx_hash_field_select_bits {
1014 u8 l3_prot_type[0x1];
1015 u8 l4_prot_type[0x1];
1016 u8 selected_fields[0x1e];
1017 };
1018
1019 enum {
1020 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1021 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1022 };
1023
1024 enum {
1025 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1026 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1027 };
1028
1029 struct mlx5_ifc_wq_bits {
1030 u8 wq_type[0x4];
1031 u8 wq_signature[0x1];
1032 u8 end_padding_mode[0x2];
1033 u8 cd_slave[0x1];
1034 u8 reserved_at_8[0x18];
1035
1036 u8 hds_skip_first_sge[0x1];
1037 u8 log2_hds_buf_size[0x3];
1038 u8 reserved_at_24[0x7];
1039 u8 page_offset[0x5];
1040 u8 lwm[0x10];
1041
1042 u8 reserved_at_40[0x8];
1043 u8 pd[0x18];
1044
1045 u8 reserved_at_60[0x8];
1046 u8 uar_page[0x18];
1047
1048 u8 dbr_addr[0x40];
1049
1050 u8 hw_counter[0x20];
1051
1052 u8 sw_counter[0x20];
1053
1054 u8 reserved_at_100[0xc];
1055 u8 log_wq_stride[0x4];
1056 u8 reserved_at_110[0x3];
1057 u8 log_wq_pg_sz[0x5];
1058 u8 reserved_at_118[0x3];
1059 u8 log_wq_sz[0x5];
1060
1061 u8 reserved_at_120[0x15];
1062 u8 log_wqe_num_of_strides[0x3];
1063 u8 two_byte_shift_en[0x1];
1064 u8 reserved_at_139[0x4];
1065 u8 log_wqe_stride_size[0x3];
1066
1067 u8 reserved_at_140[0x4c0];
1068
1069 struct mlx5_ifc_cmd_pas_bits pas[0];
1070 };
1071
1072 struct mlx5_ifc_rq_num_bits {
1073 u8 reserved_at_0[0x8];
1074 u8 rq_num[0x18];
1075 };
1076
1077 struct mlx5_ifc_mac_address_layout_bits {
1078 u8 reserved_at_0[0x10];
1079 u8 mac_addr_47_32[0x10];
1080
1081 u8 mac_addr_31_0[0x20];
1082 };
1083
1084 struct mlx5_ifc_vlan_layout_bits {
1085 u8 reserved_at_0[0x14];
1086 u8 vlan[0x0c];
1087
1088 u8 reserved_at_20[0x20];
1089 };
1090
1091 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1092 u8 reserved_at_0[0xa0];
1093
1094 u8 min_time_between_cnps[0x20];
1095
1096 u8 reserved_at_c0[0x12];
1097 u8 cnp_dscp[0x6];
1098 u8 reserved_at_d8[0x5];
1099 u8 cnp_802p_prio[0x3];
1100
1101 u8 reserved_at_e0[0x720];
1102 };
1103
1104 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1105 u8 reserved_at_0[0x60];
1106
1107 u8 reserved_at_60[0x4];
1108 u8 clamp_tgt_rate[0x1];
1109 u8 reserved_at_65[0x3];
1110 u8 clamp_tgt_rate_after_time_inc[0x1];
1111 u8 reserved_at_69[0x17];
1112
1113 u8 reserved_at_80[0x20];
1114
1115 u8 rpg_time_reset[0x20];
1116
1117 u8 rpg_byte_reset[0x20];
1118
1119 u8 rpg_threshold[0x20];
1120
1121 u8 rpg_max_rate[0x20];
1122
1123 u8 rpg_ai_rate[0x20];
1124
1125 u8 rpg_hai_rate[0x20];
1126
1127 u8 rpg_gd[0x20];
1128
1129 u8 rpg_min_dec_fac[0x20];
1130
1131 u8 rpg_min_rate[0x20];
1132
1133 u8 reserved_at_1c0[0xe0];
1134
1135 u8 rate_to_set_on_first_cnp[0x20];
1136
1137 u8 dce_tcp_g[0x20];
1138
1139 u8 dce_tcp_rtt[0x20];
1140
1141 u8 rate_reduce_monitor_period[0x20];
1142
1143 u8 reserved_at_320[0x20];
1144
1145 u8 initial_alpha_value[0x20];
1146
1147 u8 reserved_at_360[0x4a0];
1148 };
1149
1150 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1151 u8 reserved_at_0[0x80];
1152
1153 u8 rppp_max_rps[0x20];
1154
1155 u8 rpg_time_reset[0x20];
1156
1157 u8 rpg_byte_reset[0x20];
1158
1159 u8 rpg_threshold[0x20];
1160
1161 u8 rpg_max_rate[0x20];
1162
1163 u8 rpg_ai_rate[0x20];
1164
1165 u8 rpg_hai_rate[0x20];
1166
1167 u8 rpg_gd[0x20];
1168
1169 u8 rpg_min_dec_fac[0x20];
1170
1171 u8 rpg_min_rate[0x20];
1172
1173 u8 reserved_at_1c0[0x640];
1174 };
1175
1176 enum {
1177 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1178 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1179 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1180 };
1181
1182 struct mlx5_ifc_resize_field_select_bits {
1183 u8 resize_field_select[0x20];
1184 };
1185
1186 enum {
1187 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1188 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1189 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1190 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1191 };
1192
1193 struct mlx5_ifc_modify_field_select_bits {
1194 u8 modify_field_select[0x20];
1195 };
1196
1197 struct mlx5_ifc_field_select_r_roce_np_bits {
1198 u8 field_select_r_roce_np[0x20];
1199 };
1200
1201 struct mlx5_ifc_field_select_r_roce_rp_bits {
1202 u8 field_select_r_roce_rp[0x20];
1203 };
1204
1205 enum {
1206 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1207 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1208 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1209 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1210 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1216 };
1217
1218 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1219 u8 field_select_8021qaurp[0x20];
1220 };
1221
1222 struct mlx5_ifc_phys_layer_cntrs_bits {
1223 u8 time_since_last_clear_high[0x20];
1224
1225 u8 time_since_last_clear_low[0x20];
1226
1227 u8 symbol_errors_high[0x20];
1228
1229 u8 symbol_errors_low[0x20];
1230
1231 u8 sync_headers_errors_high[0x20];
1232
1233 u8 sync_headers_errors_low[0x20];
1234
1235 u8 edpl_bip_errors_lane0_high[0x20];
1236
1237 u8 edpl_bip_errors_lane0_low[0x20];
1238
1239 u8 edpl_bip_errors_lane1_high[0x20];
1240
1241 u8 edpl_bip_errors_lane1_low[0x20];
1242
1243 u8 edpl_bip_errors_lane2_high[0x20];
1244
1245 u8 edpl_bip_errors_lane2_low[0x20];
1246
1247 u8 edpl_bip_errors_lane3_high[0x20];
1248
1249 u8 edpl_bip_errors_lane3_low[0x20];
1250
1251 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1252
1253 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1254
1255 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1256
1257 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1258
1259 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1260
1261 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1262
1263 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1264
1265 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1266
1267 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1268
1269 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1270
1271 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1272
1273 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1274
1275 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1276
1277 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1278
1279 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1280
1281 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1282
1283 u8 rs_fec_corrected_blocks_high[0x20];
1284
1285 u8 rs_fec_corrected_blocks_low[0x20];
1286
1287 u8 rs_fec_uncorrectable_blocks_high[0x20];
1288
1289 u8 rs_fec_uncorrectable_blocks_low[0x20];
1290
1291 u8 rs_fec_no_errors_blocks_high[0x20];
1292
1293 u8 rs_fec_no_errors_blocks_low[0x20];
1294
1295 u8 rs_fec_single_error_blocks_high[0x20];
1296
1297 u8 rs_fec_single_error_blocks_low[0x20];
1298
1299 u8 rs_fec_corrected_symbols_total_high[0x20];
1300
1301 u8 rs_fec_corrected_symbols_total_low[0x20];
1302
1303 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1304
1305 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1306
1307 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1308
1309 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1310
1311 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1312
1313 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1314
1315 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1316
1317 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1318
1319 u8 link_down_events[0x20];
1320
1321 u8 successful_recovery_events[0x20];
1322
1323 u8 reserved_at_640[0x180];
1324 };
1325
1326 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1327 u8 symbol_error_counter[0x10];
1328
1329 u8 link_error_recovery_counter[0x8];
1330
1331 u8 link_downed_counter[0x8];
1332
1333 u8 port_rcv_errors[0x10];
1334
1335 u8 port_rcv_remote_physical_errors[0x10];
1336
1337 u8 port_rcv_switch_relay_errors[0x10];
1338
1339 u8 port_xmit_discards[0x10];
1340
1341 u8 port_xmit_constraint_errors[0x8];
1342
1343 u8 port_rcv_constraint_errors[0x8];
1344
1345 u8 reserved_at_70[0x8];
1346
1347 u8 link_overrun_errors[0x8];
1348
1349 u8 reserved_at_80[0x10];
1350
1351 u8 vl_15_dropped[0x10];
1352
1353 u8 reserved_at_a0[0xa0];
1354 };
1355
1356 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1357 u8 transmit_queue_high[0x20];
1358
1359 u8 transmit_queue_low[0x20];
1360
1361 u8 reserved_at_40[0x780];
1362 };
1363
1364 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1365 u8 rx_octets_high[0x20];
1366
1367 u8 rx_octets_low[0x20];
1368
1369 u8 reserved_at_40[0xc0];
1370
1371 u8 rx_frames_high[0x20];
1372
1373 u8 rx_frames_low[0x20];
1374
1375 u8 tx_octets_high[0x20];
1376
1377 u8 tx_octets_low[0x20];
1378
1379 u8 reserved_at_180[0xc0];
1380
1381 u8 tx_frames_high[0x20];
1382
1383 u8 tx_frames_low[0x20];
1384
1385 u8 rx_pause_high[0x20];
1386
1387 u8 rx_pause_low[0x20];
1388
1389 u8 rx_pause_duration_high[0x20];
1390
1391 u8 rx_pause_duration_low[0x20];
1392
1393 u8 tx_pause_high[0x20];
1394
1395 u8 tx_pause_low[0x20];
1396
1397 u8 tx_pause_duration_high[0x20];
1398
1399 u8 tx_pause_duration_low[0x20];
1400
1401 u8 rx_pause_transition_high[0x20];
1402
1403 u8 rx_pause_transition_low[0x20];
1404
1405 u8 reserved_at_3c0[0x400];
1406 };
1407
1408 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1409 u8 port_transmit_wait_high[0x20];
1410
1411 u8 port_transmit_wait_low[0x20];
1412
1413 u8 reserved_at_40[0x780];
1414 };
1415
1416 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1417 u8 dot3stats_alignment_errors_high[0x20];
1418
1419 u8 dot3stats_alignment_errors_low[0x20];
1420
1421 u8 dot3stats_fcs_errors_high[0x20];
1422
1423 u8 dot3stats_fcs_errors_low[0x20];
1424
1425 u8 dot3stats_single_collision_frames_high[0x20];
1426
1427 u8 dot3stats_single_collision_frames_low[0x20];
1428
1429 u8 dot3stats_multiple_collision_frames_high[0x20];
1430
1431 u8 dot3stats_multiple_collision_frames_low[0x20];
1432
1433 u8 dot3stats_sqe_test_errors_high[0x20];
1434
1435 u8 dot3stats_sqe_test_errors_low[0x20];
1436
1437 u8 dot3stats_deferred_transmissions_high[0x20];
1438
1439 u8 dot3stats_deferred_transmissions_low[0x20];
1440
1441 u8 dot3stats_late_collisions_high[0x20];
1442
1443 u8 dot3stats_late_collisions_low[0x20];
1444
1445 u8 dot3stats_excessive_collisions_high[0x20];
1446
1447 u8 dot3stats_excessive_collisions_low[0x20];
1448
1449 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1450
1451 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1452
1453 u8 dot3stats_carrier_sense_errors_high[0x20];
1454
1455 u8 dot3stats_carrier_sense_errors_low[0x20];
1456
1457 u8 dot3stats_frame_too_longs_high[0x20];
1458
1459 u8 dot3stats_frame_too_longs_low[0x20];
1460
1461 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1462
1463 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1464
1465 u8 dot3stats_symbol_errors_high[0x20];
1466
1467 u8 dot3stats_symbol_errors_low[0x20];
1468
1469 u8 dot3control_in_unknown_opcodes_high[0x20];
1470
1471 u8 dot3control_in_unknown_opcodes_low[0x20];
1472
1473 u8 dot3in_pause_frames_high[0x20];
1474
1475 u8 dot3in_pause_frames_low[0x20];
1476
1477 u8 dot3out_pause_frames_high[0x20];
1478
1479 u8 dot3out_pause_frames_low[0x20];
1480
1481 u8 reserved_at_400[0x3c0];
1482 };
1483
1484 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1485 u8 ether_stats_drop_events_high[0x20];
1486
1487 u8 ether_stats_drop_events_low[0x20];
1488
1489 u8 ether_stats_octets_high[0x20];
1490
1491 u8 ether_stats_octets_low[0x20];
1492
1493 u8 ether_stats_pkts_high[0x20];
1494
1495 u8 ether_stats_pkts_low[0x20];
1496
1497 u8 ether_stats_broadcast_pkts_high[0x20];
1498
1499 u8 ether_stats_broadcast_pkts_low[0x20];
1500
1501 u8 ether_stats_multicast_pkts_high[0x20];
1502
1503 u8 ether_stats_multicast_pkts_low[0x20];
1504
1505 u8 ether_stats_crc_align_errors_high[0x20];
1506
1507 u8 ether_stats_crc_align_errors_low[0x20];
1508
1509 u8 ether_stats_undersize_pkts_high[0x20];
1510
1511 u8 ether_stats_undersize_pkts_low[0x20];
1512
1513 u8 ether_stats_oversize_pkts_high[0x20];
1514
1515 u8 ether_stats_oversize_pkts_low[0x20];
1516
1517 u8 ether_stats_fragments_high[0x20];
1518
1519 u8 ether_stats_fragments_low[0x20];
1520
1521 u8 ether_stats_jabbers_high[0x20];
1522
1523 u8 ether_stats_jabbers_low[0x20];
1524
1525 u8 ether_stats_collisions_high[0x20];
1526
1527 u8 ether_stats_collisions_low[0x20];
1528
1529 u8 ether_stats_pkts64octets_high[0x20];
1530
1531 u8 ether_stats_pkts64octets_low[0x20];
1532
1533 u8 ether_stats_pkts65to127octets_high[0x20];
1534
1535 u8 ether_stats_pkts65to127octets_low[0x20];
1536
1537 u8 ether_stats_pkts128to255octets_high[0x20];
1538
1539 u8 ether_stats_pkts128to255octets_low[0x20];
1540
1541 u8 ether_stats_pkts256to511octets_high[0x20];
1542
1543 u8 ether_stats_pkts256to511octets_low[0x20];
1544
1545 u8 ether_stats_pkts512to1023octets_high[0x20];
1546
1547 u8 ether_stats_pkts512to1023octets_low[0x20];
1548
1549 u8 ether_stats_pkts1024to1518octets_high[0x20];
1550
1551 u8 ether_stats_pkts1024to1518octets_low[0x20];
1552
1553 u8 ether_stats_pkts1519to2047octets_high[0x20];
1554
1555 u8 ether_stats_pkts1519to2047octets_low[0x20];
1556
1557 u8 ether_stats_pkts2048to4095octets_high[0x20];
1558
1559 u8 ether_stats_pkts2048to4095octets_low[0x20];
1560
1561 u8 ether_stats_pkts4096to8191octets_high[0x20];
1562
1563 u8 ether_stats_pkts4096to8191octets_low[0x20];
1564
1565 u8 ether_stats_pkts8192to10239octets_high[0x20];
1566
1567 u8 ether_stats_pkts8192to10239octets_low[0x20];
1568
1569 u8 reserved_at_540[0x280];
1570 };
1571
1572 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1573 u8 if_in_octets_high[0x20];
1574
1575 u8 if_in_octets_low[0x20];
1576
1577 u8 if_in_ucast_pkts_high[0x20];
1578
1579 u8 if_in_ucast_pkts_low[0x20];
1580
1581 u8 if_in_discards_high[0x20];
1582
1583 u8 if_in_discards_low[0x20];
1584
1585 u8 if_in_errors_high[0x20];
1586
1587 u8 if_in_errors_low[0x20];
1588
1589 u8 if_in_unknown_protos_high[0x20];
1590
1591 u8 if_in_unknown_protos_low[0x20];
1592
1593 u8 if_out_octets_high[0x20];
1594
1595 u8 if_out_octets_low[0x20];
1596
1597 u8 if_out_ucast_pkts_high[0x20];
1598
1599 u8 if_out_ucast_pkts_low[0x20];
1600
1601 u8 if_out_discards_high[0x20];
1602
1603 u8 if_out_discards_low[0x20];
1604
1605 u8 if_out_errors_high[0x20];
1606
1607 u8 if_out_errors_low[0x20];
1608
1609 u8 if_in_multicast_pkts_high[0x20];
1610
1611 u8 if_in_multicast_pkts_low[0x20];
1612
1613 u8 if_in_broadcast_pkts_high[0x20];
1614
1615 u8 if_in_broadcast_pkts_low[0x20];
1616
1617 u8 if_out_multicast_pkts_high[0x20];
1618
1619 u8 if_out_multicast_pkts_low[0x20];
1620
1621 u8 if_out_broadcast_pkts_high[0x20];
1622
1623 u8 if_out_broadcast_pkts_low[0x20];
1624
1625 u8 reserved_at_340[0x480];
1626 };
1627
1628 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1629 u8 a_frames_transmitted_ok_high[0x20];
1630
1631 u8 a_frames_transmitted_ok_low[0x20];
1632
1633 u8 a_frames_received_ok_high[0x20];
1634
1635 u8 a_frames_received_ok_low[0x20];
1636
1637 u8 a_frame_check_sequence_errors_high[0x20];
1638
1639 u8 a_frame_check_sequence_errors_low[0x20];
1640
1641 u8 a_alignment_errors_high[0x20];
1642
1643 u8 a_alignment_errors_low[0x20];
1644
1645 u8 a_octets_transmitted_ok_high[0x20];
1646
1647 u8 a_octets_transmitted_ok_low[0x20];
1648
1649 u8 a_octets_received_ok_high[0x20];
1650
1651 u8 a_octets_received_ok_low[0x20];
1652
1653 u8 a_multicast_frames_xmitted_ok_high[0x20];
1654
1655 u8 a_multicast_frames_xmitted_ok_low[0x20];
1656
1657 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1658
1659 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1660
1661 u8 a_multicast_frames_received_ok_high[0x20];
1662
1663 u8 a_multicast_frames_received_ok_low[0x20];
1664
1665 u8 a_broadcast_frames_received_ok_high[0x20];
1666
1667 u8 a_broadcast_frames_received_ok_low[0x20];
1668
1669 u8 a_in_range_length_errors_high[0x20];
1670
1671 u8 a_in_range_length_errors_low[0x20];
1672
1673 u8 a_out_of_range_length_field_high[0x20];
1674
1675 u8 a_out_of_range_length_field_low[0x20];
1676
1677 u8 a_frame_too_long_errors_high[0x20];
1678
1679 u8 a_frame_too_long_errors_low[0x20];
1680
1681 u8 a_symbol_error_during_carrier_high[0x20];
1682
1683 u8 a_symbol_error_during_carrier_low[0x20];
1684
1685 u8 a_mac_control_frames_transmitted_high[0x20];
1686
1687 u8 a_mac_control_frames_transmitted_low[0x20];
1688
1689 u8 a_mac_control_frames_received_high[0x20];
1690
1691 u8 a_mac_control_frames_received_low[0x20];
1692
1693 u8 a_unsupported_opcodes_received_high[0x20];
1694
1695 u8 a_unsupported_opcodes_received_low[0x20];
1696
1697 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1698
1699 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1700
1701 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1702
1703 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1704
1705 u8 reserved_at_4c0[0x300];
1706 };
1707
1708 struct mlx5_ifc_cmd_inter_comp_event_bits {
1709 u8 command_completion_vector[0x20];
1710
1711 u8 reserved_at_20[0xc0];
1712 };
1713
1714 struct mlx5_ifc_stall_vl_event_bits {
1715 u8 reserved_at_0[0x18];
1716 u8 port_num[0x1];
1717 u8 reserved_at_19[0x3];
1718 u8 vl[0x4];
1719
1720 u8 reserved_at_20[0xa0];
1721 };
1722
1723 struct mlx5_ifc_db_bf_congestion_event_bits {
1724 u8 event_subtype[0x8];
1725 u8 reserved_at_8[0x8];
1726 u8 congestion_level[0x8];
1727 u8 reserved_at_18[0x8];
1728
1729 u8 reserved_at_20[0xa0];
1730 };
1731
1732 struct mlx5_ifc_gpio_event_bits {
1733 u8 reserved_at_0[0x60];
1734
1735 u8 gpio_event_hi[0x20];
1736
1737 u8 gpio_event_lo[0x20];
1738
1739 u8 reserved_at_a0[0x40];
1740 };
1741
1742 struct mlx5_ifc_port_state_change_event_bits {
1743 u8 reserved_at_0[0x40];
1744
1745 u8 port_num[0x4];
1746 u8 reserved_at_44[0x1c];
1747
1748 u8 reserved_at_60[0x80];
1749 };
1750
1751 struct mlx5_ifc_dropped_packet_logged_bits {
1752 u8 reserved_at_0[0xe0];
1753 };
1754
1755 enum {
1756 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1757 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1758 };
1759
1760 struct mlx5_ifc_cq_error_bits {
1761 u8 reserved_at_0[0x8];
1762 u8 cqn[0x18];
1763
1764 u8 reserved_at_20[0x20];
1765
1766 u8 reserved_at_40[0x18];
1767 u8 syndrome[0x8];
1768
1769 u8 reserved_at_60[0x80];
1770 };
1771
1772 struct mlx5_ifc_rdma_page_fault_event_bits {
1773 u8 bytes_committed[0x20];
1774
1775 u8 r_key[0x20];
1776
1777 u8 reserved_at_40[0x10];
1778 u8 packet_len[0x10];
1779
1780 u8 rdma_op_len[0x20];
1781
1782 u8 rdma_va[0x40];
1783
1784 u8 reserved_at_c0[0x5];
1785 u8 rdma[0x1];
1786 u8 write[0x1];
1787 u8 requestor[0x1];
1788 u8 qp_number[0x18];
1789 };
1790
1791 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1792 u8 bytes_committed[0x20];
1793
1794 u8 reserved_at_20[0x10];
1795 u8 wqe_index[0x10];
1796
1797 u8 reserved_at_40[0x10];
1798 u8 len[0x10];
1799
1800 u8 reserved_at_60[0x60];
1801
1802 u8 reserved_at_c0[0x5];
1803 u8 rdma[0x1];
1804 u8 write_read[0x1];
1805 u8 requestor[0x1];
1806 u8 qpn[0x18];
1807 };
1808
1809 struct mlx5_ifc_qp_events_bits {
1810 u8 reserved_at_0[0xa0];
1811
1812 u8 type[0x8];
1813 u8 reserved_at_a8[0x18];
1814
1815 u8 reserved_at_c0[0x8];
1816 u8 qpn_rqn_sqn[0x18];
1817 };
1818
1819 struct mlx5_ifc_dct_events_bits {
1820 u8 reserved_at_0[0xc0];
1821
1822 u8 reserved_at_c0[0x8];
1823 u8 dct_number[0x18];
1824 };
1825
1826 struct mlx5_ifc_comp_event_bits {
1827 u8 reserved_at_0[0xc0];
1828
1829 u8 reserved_at_c0[0x8];
1830 u8 cq_number[0x18];
1831 };
1832
1833 enum {
1834 MLX5_QPC_STATE_RST = 0x0,
1835 MLX5_QPC_STATE_INIT = 0x1,
1836 MLX5_QPC_STATE_RTR = 0x2,
1837 MLX5_QPC_STATE_RTS = 0x3,
1838 MLX5_QPC_STATE_SQER = 0x4,
1839 MLX5_QPC_STATE_ERR = 0x6,
1840 MLX5_QPC_STATE_SQD = 0x7,
1841 MLX5_QPC_STATE_SUSPENDED = 0x9,
1842 };
1843
1844 enum {
1845 MLX5_QPC_ST_RC = 0x0,
1846 MLX5_QPC_ST_UC = 0x1,
1847 MLX5_QPC_ST_UD = 0x2,
1848 MLX5_QPC_ST_XRC = 0x3,
1849 MLX5_QPC_ST_DCI = 0x5,
1850 MLX5_QPC_ST_QP0 = 0x7,
1851 MLX5_QPC_ST_QP1 = 0x8,
1852 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1853 MLX5_QPC_ST_REG_UMR = 0xc,
1854 };
1855
1856 enum {
1857 MLX5_QPC_PM_STATE_ARMED = 0x0,
1858 MLX5_QPC_PM_STATE_REARM = 0x1,
1859 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1860 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1861 };
1862
1863 enum {
1864 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1865 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1866 };
1867
1868 enum {
1869 MLX5_QPC_MTU_256_BYTES = 0x1,
1870 MLX5_QPC_MTU_512_BYTES = 0x2,
1871 MLX5_QPC_MTU_1K_BYTES = 0x3,
1872 MLX5_QPC_MTU_2K_BYTES = 0x4,
1873 MLX5_QPC_MTU_4K_BYTES = 0x5,
1874 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1875 };
1876
1877 enum {
1878 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1879 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1880 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1881 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1882 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1883 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1884 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1885 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1886 };
1887
1888 enum {
1889 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1890 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1891 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1892 };
1893
1894 enum {
1895 MLX5_QPC_CS_RES_DISABLE = 0x0,
1896 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1897 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1898 };
1899
1900 struct mlx5_ifc_qpc_bits {
1901 u8 state[0x4];
1902 u8 reserved_at_4[0x4];
1903 u8 st[0x8];
1904 u8 reserved_at_10[0x3];
1905 u8 pm_state[0x2];
1906 u8 reserved_at_15[0x7];
1907 u8 end_padding_mode[0x2];
1908 u8 reserved_at_1e[0x2];
1909
1910 u8 wq_signature[0x1];
1911 u8 block_lb_mc[0x1];
1912 u8 atomic_like_write_en[0x1];
1913 u8 latency_sensitive[0x1];
1914 u8 reserved_at_24[0x1];
1915 u8 drain_sigerr[0x1];
1916 u8 reserved_at_26[0x2];
1917 u8 pd[0x18];
1918
1919 u8 mtu[0x3];
1920 u8 log_msg_max[0x5];
1921 u8 reserved_at_48[0x1];
1922 u8 log_rq_size[0x4];
1923 u8 log_rq_stride[0x3];
1924 u8 no_sq[0x1];
1925 u8 log_sq_size[0x4];
1926 u8 reserved_at_55[0x6];
1927 u8 rlky[0x1];
1928 u8 ulp_stateless_offload_mode[0x4];
1929
1930 u8 counter_set_id[0x8];
1931 u8 uar_page[0x18];
1932
1933 u8 reserved_at_80[0x8];
1934 u8 user_index[0x18];
1935
1936 u8 reserved_at_a0[0x3];
1937 u8 log_page_size[0x5];
1938 u8 remote_qpn[0x18];
1939
1940 struct mlx5_ifc_ads_bits primary_address_path;
1941
1942 struct mlx5_ifc_ads_bits secondary_address_path;
1943
1944 u8 log_ack_req_freq[0x4];
1945 u8 reserved_at_384[0x4];
1946 u8 log_sra_max[0x3];
1947 u8 reserved_at_38b[0x2];
1948 u8 retry_count[0x3];
1949 u8 rnr_retry[0x3];
1950 u8 reserved_at_393[0x1];
1951 u8 fre[0x1];
1952 u8 cur_rnr_retry[0x3];
1953 u8 cur_retry_count[0x3];
1954 u8 reserved_at_39b[0x5];
1955
1956 u8 reserved_at_3a0[0x20];
1957
1958 u8 reserved_at_3c0[0x8];
1959 u8 next_send_psn[0x18];
1960
1961 u8 reserved_at_3e0[0x8];
1962 u8 cqn_snd[0x18];
1963
1964 u8 reserved_at_400[0x40];
1965
1966 u8 reserved_at_440[0x8];
1967 u8 last_acked_psn[0x18];
1968
1969 u8 reserved_at_460[0x8];
1970 u8 ssn[0x18];
1971
1972 u8 reserved_at_480[0x8];
1973 u8 log_rra_max[0x3];
1974 u8 reserved_at_48b[0x1];
1975 u8 atomic_mode[0x4];
1976 u8 rre[0x1];
1977 u8 rwe[0x1];
1978 u8 rae[0x1];
1979 u8 reserved_at_493[0x1];
1980 u8 page_offset[0x6];
1981 u8 reserved_at_49a[0x3];
1982 u8 cd_slave_receive[0x1];
1983 u8 cd_slave_send[0x1];
1984 u8 cd_master[0x1];
1985
1986 u8 reserved_at_4a0[0x3];
1987 u8 min_rnr_nak[0x5];
1988 u8 next_rcv_psn[0x18];
1989
1990 u8 reserved_at_4c0[0x8];
1991 u8 xrcd[0x18];
1992
1993 u8 reserved_at_4e0[0x8];
1994 u8 cqn_rcv[0x18];
1995
1996 u8 dbr_addr[0x40];
1997
1998 u8 q_key[0x20];
1999
2000 u8 reserved_at_560[0x5];
2001 u8 rq_type[0x3];
2002 u8 srqn_rmpn_xrqn[0x18];
2003
2004 u8 reserved_at_580[0x8];
2005 u8 rmsn[0x18];
2006
2007 u8 hw_sq_wqebb_counter[0x10];
2008 u8 sw_sq_wqebb_counter[0x10];
2009
2010 u8 hw_rq_counter[0x20];
2011
2012 u8 sw_rq_counter[0x20];
2013
2014 u8 reserved_at_600[0x20];
2015
2016 u8 reserved_at_620[0xf];
2017 u8 cgs[0x1];
2018 u8 cs_req[0x8];
2019 u8 cs_res[0x8];
2020
2021 u8 dc_access_key[0x40];
2022
2023 u8 reserved_at_680[0xc0];
2024 };
2025
2026 struct mlx5_ifc_roce_addr_layout_bits {
2027 u8 source_l3_address[16][0x8];
2028
2029 u8 reserved_at_80[0x3];
2030 u8 vlan_valid[0x1];
2031 u8 vlan_id[0xc];
2032 u8 source_mac_47_32[0x10];
2033
2034 u8 source_mac_31_0[0x20];
2035
2036 u8 reserved_at_c0[0x14];
2037 u8 roce_l3_type[0x4];
2038 u8 roce_version[0x8];
2039
2040 u8 reserved_at_e0[0x20];
2041 };
2042
2043 union mlx5_ifc_hca_cap_union_bits {
2044 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2045 struct mlx5_ifc_odp_cap_bits odp_cap;
2046 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2047 struct mlx5_ifc_roce_cap_bits roce_cap;
2048 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2049 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2050 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2051 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2052 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2053 struct mlx5_ifc_qos_cap_bits qos_cap;
2054 u8 reserved_at_0[0x8000];
2055 };
2056
2057 enum {
2058 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2059 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2060 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2061 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2062 };
2063
2064 struct mlx5_ifc_flow_context_bits {
2065 u8 reserved_at_0[0x20];
2066
2067 u8 group_id[0x20];
2068
2069 u8 reserved_at_40[0x8];
2070 u8 flow_tag[0x18];
2071
2072 u8 reserved_at_60[0x10];
2073 u8 action[0x10];
2074
2075 u8 reserved_at_80[0x8];
2076 u8 destination_list_size[0x18];
2077
2078 u8 reserved_at_a0[0x8];
2079 u8 flow_counter_list_size[0x18];
2080
2081 u8 reserved_at_c0[0x140];
2082
2083 struct mlx5_ifc_fte_match_param_bits match_value;
2084
2085 u8 reserved_at_1200[0x600];
2086
2087 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2088 };
2089
2090 enum {
2091 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2092 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2093 };
2094
2095 struct mlx5_ifc_xrc_srqc_bits {
2096 u8 state[0x4];
2097 u8 log_xrc_srq_size[0x4];
2098 u8 reserved_at_8[0x18];
2099
2100 u8 wq_signature[0x1];
2101 u8 cont_srq[0x1];
2102 u8 reserved_at_22[0x1];
2103 u8 rlky[0x1];
2104 u8 basic_cyclic_rcv_wqe[0x1];
2105 u8 log_rq_stride[0x3];
2106 u8 xrcd[0x18];
2107
2108 u8 page_offset[0x6];
2109 u8 reserved_at_46[0x2];
2110 u8 cqn[0x18];
2111
2112 u8 reserved_at_60[0x20];
2113
2114 u8 user_index_equal_xrc_srqn[0x1];
2115 u8 reserved_at_81[0x1];
2116 u8 log_page_size[0x6];
2117 u8 user_index[0x18];
2118
2119 u8 reserved_at_a0[0x20];
2120
2121 u8 reserved_at_c0[0x8];
2122 u8 pd[0x18];
2123
2124 u8 lwm[0x10];
2125 u8 wqe_cnt[0x10];
2126
2127 u8 reserved_at_100[0x40];
2128
2129 u8 db_record_addr_h[0x20];
2130
2131 u8 db_record_addr_l[0x1e];
2132 u8 reserved_at_17e[0x2];
2133
2134 u8 reserved_at_180[0x80];
2135 };
2136
2137 struct mlx5_ifc_traffic_counter_bits {
2138 u8 packets[0x40];
2139
2140 u8 octets[0x40];
2141 };
2142
2143 struct mlx5_ifc_tisc_bits {
2144 u8 reserved_at_0[0xc];
2145 u8 prio[0x4];
2146 u8 reserved_at_10[0x10];
2147
2148 u8 reserved_at_20[0x100];
2149
2150 u8 reserved_at_120[0x8];
2151 u8 transport_domain[0x18];
2152
2153 u8 reserved_at_140[0x3c0];
2154 };
2155
2156 enum {
2157 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2158 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2159 };
2160
2161 enum {
2162 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2163 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2164 };
2165
2166 enum {
2167 MLX5_RX_HASH_FN_NONE = 0x0,
2168 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2169 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2170 };
2171
2172 enum {
2173 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2174 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2175 };
2176
2177 struct mlx5_ifc_tirc_bits {
2178 u8 reserved_at_0[0x20];
2179
2180 u8 disp_type[0x4];
2181 u8 reserved_at_24[0x1c];
2182
2183 u8 reserved_at_40[0x40];
2184
2185 u8 reserved_at_80[0x4];
2186 u8 lro_timeout_period_usecs[0x10];
2187 u8 lro_enable_mask[0x4];
2188 u8 lro_max_ip_payload_size[0x8];
2189
2190 u8 reserved_at_a0[0x40];
2191
2192 u8 reserved_at_e0[0x8];
2193 u8 inline_rqn[0x18];
2194
2195 u8 rx_hash_symmetric[0x1];
2196 u8 reserved_at_101[0x1];
2197 u8 tunneled_offload_en[0x1];
2198 u8 reserved_at_103[0x5];
2199 u8 indirect_table[0x18];
2200
2201 u8 rx_hash_fn[0x4];
2202 u8 reserved_at_124[0x2];
2203 u8 self_lb_block[0x2];
2204 u8 transport_domain[0x18];
2205
2206 u8 rx_hash_toeplitz_key[10][0x20];
2207
2208 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2209
2210 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2211
2212 u8 reserved_at_2c0[0x4c0];
2213 };
2214
2215 enum {
2216 MLX5_SRQC_STATE_GOOD = 0x0,
2217 MLX5_SRQC_STATE_ERROR = 0x1,
2218 };
2219
2220 struct mlx5_ifc_srqc_bits {
2221 u8 state[0x4];
2222 u8 log_srq_size[0x4];
2223 u8 reserved_at_8[0x18];
2224
2225 u8 wq_signature[0x1];
2226 u8 cont_srq[0x1];
2227 u8 reserved_at_22[0x1];
2228 u8 rlky[0x1];
2229 u8 reserved_at_24[0x1];
2230 u8 log_rq_stride[0x3];
2231 u8 xrcd[0x18];
2232
2233 u8 page_offset[0x6];
2234 u8 reserved_at_46[0x2];
2235 u8 cqn[0x18];
2236
2237 u8 reserved_at_60[0x20];
2238
2239 u8 reserved_at_80[0x2];
2240 u8 log_page_size[0x6];
2241 u8 reserved_at_88[0x18];
2242
2243 u8 reserved_at_a0[0x20];
2244
2245 u8 reserved_at_c0[0x8];
2246 u8 pd[0x18];
2247
2248 u8 lwm[0x10];
2249 u8 wqe_cnt[0x10];
2250
2251 u8 reserved_at_100[0x40];
2252
2253 u8 dbr_addr[0x40];
2254
2255 u8 reserved_at_180[0x80];
2256 };
2257
2258 enum {
2259 MLX5_SQC_STATE_RST = 0x0,
2260 MLX5_SQC_STATE_RDY = 0x1,
2261 MLX5_SQC_STATE_ERR = 0x3,
2262 };
2263
2264 struct mlx5_ifc_sqc_bits {
2265 u8 rlky[0x1];
2266 u8 cd_master[0x1];
2267 u8 fre[0x1];
2268 u8 flush_in_error_en[0x1];
2269 u8 reserved_at_4[0x4];
2270 u8 state[0x4];
2271 u8 reg_umr[0x1];
2272 u8 reserved_at_d[0x13];
2273
2274 u8 reserved_at_20[0x8];
2275 u8 user_index[0x18];
2276
2277 u8 reserved_at_40[0x8];
2278 u8 cqn[0x18];
2279
2280 u8 reserved_at_60[0x90];
2281
2282 u8 packet_pacing_rate_limit_index[0x10];
2283 u8 tis_lst_sz[0x10];
2284 u8 reserved_at_110[0x10];
2285
2286 u8 reserved_at_120[0x40];
2287
2288 u8 reserved_at_160[0x8];
2289 u8 tis_num_0[0x18];
2290
2291 struct mlx5_ifc_wq_bits wq;
2292 };
2293
2294 struct mlx5_ifc_rqtc_bits {
2295 u8 reserved_at_0[0xa0];
2296
2297 u8 reserved_at_a0[0x10];
2298 u8 rqt_max_size[0x10];
2299
2300 u8 reserved_at_c0[0x10];
2301 u8 rqt_actual_size[0x10];
2302
2303 u8 reserved_at_e0[0x6a0];
2304
2305 struct mlx5_ifc_rq_num_bits rq_num[0];
2306 };
2307
2308 enum {
2309 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2310 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2311 };
2312
2313 enum {
2314 MLX5_RQC_STATE_RST = 0x0,
2315 MLX5_RQC_STATE_RDY = 0x1,
2316 MLX5_RQC_STATE_ERR = 0x3,
2317 };
2318
2319 struct mlx5_ifc_rqc_bits {
2320 u8 rlky[0x1];
2321 u8 reserved_at_1[0x1];
2322 u8 scatter_fcs[0x1];
2323 u8 vsd[0x1];
2324 u8 mem_rq_type[0x4];
2325 u8 state[0x4];
2326 u8 reserved_at_c[0x1];
2327 u8 flush_in_error_en[0x1];
2328 u8 reserved_at_e[0x12];
2329
2330 u8 reserved_at_20[0x8];
2331 u8 user_index[0x18];
2332
2333 u8 reserved_at_40[0x8];
2334 u8 cqn[0x18];
2335
2336 u8 counter_set_id[0x8];
2337 u8 reserved_at_68[0x18];
2338
2339 u8 reserved_at_80[0x8];
2340 u8 rmpn[0x18];
2341
2342 u8 reserved_at_a0[0xe0];
2343
2344 struct mlx5_ifc_wq_bits wq;
2345 };
2346
2347 enum {
2348 MLX5_RMPC_STATE_RDY = 0x1,
2349 MLX5_RMPC_STATE_ERR = 0x3,
2350 };
2351
2352 struct mlx5_ifc_rmpc_bits {
2353 u8 reserved_at_0[0x8];
2354 u8 state[0x4];
2355 u8 reserved_at_c[0x14];
2356
2357 u8 basic_cyclic_rcv_wqe[0x1];
2358 u8 reserved_at_21[0x1f];
2359
2360 u8 reserved_at_40[0x140];
2361
2362 struct mlx5_ifc_wq_bits wq;
2363 };
2364
2365 struct mlx5_ifc_nic_vport_context_bits {
2366 u8 reserved_at_0[0x1f];
2367 u8 roce_en[0x1];
2368
2369 u8 arm_change_event[0x1];
2370 u8 reserved_at_21[0x1a];
2371 u8 event_on_mtu[0x1];
2372 u8 event_on_promisc_change[0x1];
2373 u8 event_on_vlan_change[0x1];
2374 u8 event_on_mc_address_change[0x1];
2375 u8 event_on_uc_address_change[0x1];
2376
2377 u8 reserved_at_40[0xf0];
2378
2379 u8 mtu[0x10];
2380
2381 u8 system_image_guid[0x40];
2382 u8 port_guid[0x40];
2383 u8 node_guid[0x40];
2384
2385 u8 reserved_at_200[0x140];
2386 u8 qkey_violation_counter[0x10];
2387 u8 reserved_at_350[0x430];
2388
2389 u8 promisc_uc[0x1];
2390 u8 promisc_mc[0x1];
2391 u8 promisc_all[0x1];
2392 u8 reserved_at_783[0x2];
2393 u8 allowed_list_type[0x3];
2394 u8 reserved_at_788[0xc];
2395 u8 allowed_list_size[0xc];
2396
2397 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2398
2399 u8 reserved_at_7e0[0x20];
2400
2401 u8 current_uc_mac_address[0][0x40];
2402 };
2403
2404 enum {
2405 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2406 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2407 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2408 };
2409
2410 struct mlx5_ifc_mkc_bits {
2411 u8 reserved_at_0[0x1];
2412 u8 free[0x1];
2413 u8 reserved_at_2[0xd];
2414 u8 small_fence_on_rdma_read_response[0x1];
2415 u8 umr_en[0x1];
2416 u8 a[0x1];
2417 u8 rw[0x1];
2418 u8 rr[0x1];
2419 u8 lw[0x1];
2420 u8 lr[0x1];
2421 u8 access_mode[0x2];
2422 u8 reserved_at_18[0x8];
2423
2424 u8 qpn[0x18];
2425 u8 mkey_7_0[0x8];
2426
2427 u8 reserved_at_40[0x20];
2428
2429 u8 length64[0x1];
2430 u8 bsf_en[0x1];
2431 u8 sync_umr[0x1];
2432 u8 reserved_at_63[0x2];
2433 u8 expected_sigerr_count[0x1];
2434 u8 reserved_at_66[0x1];
2435 u8 en_rinval[0x1];
2436 u8 pd[0x18];
2437
2438 u8 start_addr[0x40];
2439
2440 u8 len[0x40];
2441
2442 u8 bsf_octword_size[0x20];
2443
2444 u8 reserved_at_120[0x80];
2445
2446 u8 translations_octword_size[0x20];
2447
2448 u8 reserved_at_1c0[0x1b];
2449 u8 log_page_size[0x5];
2450
2451 u8 reserved_at_1e0[0x20];
2452 };
2453
2454 struct mlx5_ifc_pkey_bits {
2455 u8 reserved_at_0[0x10];
2456 u8 pkey[0x10];
2457 };
2458
2459 struct mlx5_ifc_array128_auto_bits {
2460 u8 array128_auto[16][0x8];
2461 };
2462
2463 struct mlx5_ifc_hca_vport_context_bits {
2464 u8 field_select[0x20];
2465
2466 u8 reserved_at_20[0xe0];
2467
2468 u8 sm_virt_aware[0x1];
2469 u8 has_smi[0x1];
2470 u8 has_raw[0x1];
2471 u8 grh_required[0x1];
2472 u8 reserved_at_104[0xc];
2473 u8 port_physical_state[0x4];
2474 u8 vport_state_policy[0x4];
2475 u8 port_state[0x4];
2476 u8 vport_state[0x4];
2477
2478 u8 reserved_at_120[0x20];
2479
2480 u8 system_image_guid[0x40];
2481
2482 u8 port_guid[0x40];
2483
2484 u8 node_guid[0x40];
2485
2486 u8 cap_mask1[0x20];
2487
2488 u8 cap_mask1_field_select[0x20];
2489
2490 u8 cap_mask2[0x20];
2491
2492 u8 cap_mask2_field_select[0x20];
2493
2494 u8 reserved_at_280[0x80];
2495
2496 u8 lid[0x10];
2497 u8 reserved_at_310[0x4];
2498 u8 init_type_reply[0x4];
2499 u8 lmc[0x3];
2500 u8 subnet_timeout[0x5];
2501
2502 u8 sm_lid[0x10];
2503 u8 sm_sl[0x4];
2504 u8 reserved_at_334[0xc];
2505
2506 u8 qkey_violation_counter[0x10];
2507 u8 pkey_violation_counter[0x10];
2508
2509 u8 reserved_at_360[0xca0];
2510 };
2511
2512 struct mlx5_ifc_esw_vport_context_bits {
2513 u8 reserved_at_0[0x3];
2514 u8 vport_svlan_strip[0x1];
2515 u8 vport_cvlan_strip[0x1];
2516 u8 vport_svlan_insert[0x1];
2517 u8 vport_cvlan_insert[0x2];
2518 u8 reserved_at_8[0x18];
2519
2520 u8 reserved_at_20[0x20];
2521
2522 u8 svlan_cfi[0x1];
2523 u8 svlan_pcp[0x3];
2524 u8 svlan_id[0xc];
2525 u8 cvlan_cfi[0x1];
2526 u8 cvlan_pcp[0x3];
2527 u8 cvlan_id[0xc];
2528
2529 u8 reserved_at_60[0x7a0];
2530 };
2531
2532 enum {
2533 MLX5_EQC_STATUS_OK = 0x0,
2534 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2535 };
2536
2537 enum {
2538 MLX5_EQC_ST_ARMED = 0x9,
2539 MLX5_EQC_ST_FIRED = 0xa,
2540 };
2541
2542 struct mlx5_ifc_eqc_bits {
2543 u8 status[0x4];
2544 u8 reserved_at_4[0x9];
2545 u8 ec[0x1];
2546 u8 oi[0x1];
2547 u8 reserved_at_f[0x5];
2548 u8 st[0x4];
2549 u8 reserved_at_18[0x8];
2550
2551 u8 reserved_at_20[0x20];
2552
2553 u8 reserved_at_40[0x14];
2554 u8 page_offset[0x6];
2555 u8 reserved_at_5a[0x6];
2556
2557 u8 reserved_at_60[0x3];
2558 u8 log_eq_size[0x5];
2559 u8 uar_page[0x18];
2560
2561 u8 reserved_at_80[0x20];
2562
2563 u8 reserved_at_a0[0x18];
2564 u8 intr[0x8];
2565
2566 u8 reserved_at_c0[0x3];
2567 u8 log_page_size[0x5];
2568 u8 reserved_at_c8[0x18];
2569
2570 u8 reserved_at_e0[0x60];
2571
2572 u8 reserved_at_140[0x8];
2573 u8 consumer_counter[0x18];
2574
2575 u8 reserved_at_160[0x8];
2576 u8 producer_counter[0x18];
2577
2578 u8 reserved_at_180[0x80];
2579 };
2580
2581 enum {
2582 MLX5_DCTC_STATE_ACTIVE = 0x0,
2583 MLX5_DCTC_STATE_DRAINING = 0x1,
2584 MLX5_DCTC_STATE_DRAINED = 0x2,
2585 };
2586
2587 enum {
2588 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2589 MLX5_DCTC_CS_RES_NA = 0x1,
2590 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2591 };
2592
2593 enum {
2594 MLX5_DCTC_MTU_256_BYTES = 0x1,
2595 MLX5_DCTC_MTU_512_BYTES = 0x2,
2596 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2597 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2598 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2599 };
2600
2601 struct mlx5_ifc_dctc_bits {
2602 u8 reserved_at_0[0x4];
2603 u8 state[0x4];
2604 u8 reserved_at_8[0x18];
2605
2606 u8 reserved_at_20[0x8];
2607 u8 user_index[0x18];
2608
2609 u8 reserved_at_40[0x8];
2610 u8 cqn[0x18];
2611
2612 u8 counter_set_id[0x8];
2613 u8 atomic_mode[0x4];
2614 u8 rre[0x1];
2615 u8 rwe[0x1];
2616 u8 rae[0x1];
2617 u8 atomic_like_write_en[0x1];
2618 u8 latency_sensitive[0x1];
2619 u8 rlky[0x1];
2620 u8 free_ar[0x1];
2621 u8 reserved_at_73[0xd];
2622
2623 u8 reserved_at_80[0x8];
2624 u8 cs_res[0x8];
2625 u8 reserved_at_90[0x3];
2626 u8 min_rnr_nak[0x5];
2627 u8 reserved_at_98[0x8];
2628
2629 u8 reserved_at_a0[0x8];
2630 u8 srqn_xrqn[0x18];
2631
2632 u8 reserved_at_c0[0x8];
2633 u8 pd[0x18];
2634
2635 u8 tclass[0x8];
2636 u8 reserved_at_e8[0x4];
2637 u8 flow_label[0x14];
2638
2639 u8 dc_access_key[0x40];
2640
2641 u8 reserved_at_140[0x5];
2642 u8 mtu[0x3];
2643 u8 port[0x8];
2644 u8 pkey_index[0x10];
2645
2646 u8 reserved_at_160[0x8];
2647 u8 my_addr_index[0x8];
2648 u8 reserved_at_170[0x8];
2649 u8 hop_limit[0x8];
2650
2651 u8 dc_access_key_violation_count[0x20];
2652
2653 u8 reserved_at_1a0[0x14];
2654 u8 dei_cfi[0x1];
2655 u8 eth_prio[0x3];
2656 u8 ecn[0x2];
2657 u8 dscp[0x6];
2658
2659 u8 reserved_at_1c0[0x40];
2660 };
2661
2662 enum {
2663 MLX5_CQC_STATUS_OK = 0x0,
2664 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2665 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2666 };
2667
2668 enum {
2669 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2670 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2671 };
2672
2673 enum {
2674 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2675 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2676 MLX5_CQC_ST_FIRED = 0xa,
2677 };
2678
2679 enum {
2680 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2681 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2682 MLX5_CQ_PERIOD_NUM_MODES
2683 };
2684
2685 struct mlx5_ifc_cqc_bits {
2686 u8 status[0x4];
2687 u8 reserved_at_4[0x4];
2688 u8 cqe_sz[0x3];
2689 u8 cc[0x1];
2690 u8 reserved_at_c[0x1];
2691 u8 scqe_break_moderation_en[0x1];
2692 u8 oi[0x1];
2693 u8 cq_period_mode[0x2];
2694 u8 cqe_comp_en[0x1];
2695 u8 mini_cqe_res_format[0x2];
2696 u8 st[0x4];
2697 u8 reserved_at_18[0x8];
2698
2699 u8 reserved_at_20[0x20];
2700
2701 u8 reserved_at_40[0x14];
2702 u8 page_offset[0x6];
2703 u8 reserved_at_5a[0x6];
2704
2705 u8 reserved_at_60[0x3];
2706 u8 log_cq_size[0x5];
2707 u8 uar_page[0x18];
2708
2709 u8 reserved_at_80[0x4];
2710 u8 cq_period[0xc];
2711 u8 cq_max_count[0x10];
2712
2713 u8 reserved_at_a0[0x18];
2714 u8 c_eqn[0x8];
2715
2716 u8 reserved_at_c0[0x3];
2717 u8 log_page_size[0x5];
2718 u8 reserved_at_c8[0x18];
2719
2720 u8 reserved_at_e0[0x20];
2721
2722 u8 reserved_at_100[0x8];
2723 u8 last_notified_index[0x18];
2724
2725 u8 reserved_at_120[0x8];
2726 u8 last_solicit_index[0x18];
2727
2728 u8 reserved_at_140[0x8];
2729 u8 consumer_counter[0x18];
2730
2731 u8 reserved_at_160[0x8];
2732 u8 producer_counter[0x18];
2733
2734 u8 reserved_at_180[0x40];
2735
2736 u8 dbr_addr[0x40];
2737 };
2738
2739 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2740 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2741 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2742 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2743 u8 reserved_at_0[0x800];
2744 };
2745
2746 struct mlx5_ifc_query_adapter_param_block_bits {
2747 u8 reserved_at_0[0xc0];
2748
2749 u8 reserved_at_c0[0x8];
2750 u8 ieee_vendor_id[0x18];
2751
2752 u8 reserved_at_e0[0x10];
2753 u8 vsd_vendor_id[0x10];
2754
2755 u8 vsd[208][0x8];
2756
2757 u8 vsd_contd_psid[16][0x8];
2758 };
2759
2760 enum {
2761 MLX5_XRQC_STATE_GOOD = 0x0,
2762 MLX5_XRQC_STATE_ERROR = 0x1,
2763 };
2764
2765 enum {
2766 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2767 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2768 };
2769
2770 enum {
2771 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2772 };
2773
2774 struct mlx5_ifc_tag_matching_topology_context_bits {
2775 u8 log_matching_list_sz[0x4];
2776 u8 reserved_at_4[0xc];
2777 u8 append_next_index[0x10];
2778
2779 u8 sw_phase_cnt[0x10];
2780 u8 hw_phase_cnt[0x10];
2781
2782 u8 reserved_at_40[0x40];
2783 };
2784
2785 struct mlx5_ifc_xrqc_bits {
2786 u8 state[0x4];
2787 u8 rlkey[0x1];
2788 u8 reserved_at_5[0xf];
2789 u8 topology[0x4];
2790 u8 reserved_at_18[0x4];
2791 u8 offload[0x4];
2792
2793 u8 reserved_at_20[0x8];
2794 u8 user_index[0x18];
2795
2796 u8 reserved_at_40[0x8];
2797 u8 cqn[0x18];
2798
2799 u8 reserved_at_60[0xa0];
2800
2801 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2802
2803 u8 reserved_at_180[0x180];
2804
2805 struct mlx5_ifc_wq_bits wq;
2806 };
2807
2808 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2809 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2810 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2811 u8 reserved_at_0[0x20];
2812 };
2813
2814 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2815 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2816 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2817 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2818 u8 reserved_at_0[0x20];
2819 };
2820
2821 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2822 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2823 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2824 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2825 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2826 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2827 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2828 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2829 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2830 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2831 u8 reserved_at_0[0x7c0];
2832 };
2833
2834 union mlx5_ifc_event_auto_bits {
2835 struct mlx5_ifc_comp_event_bits comp_event;
2836 struct mlx5_ifc_dct_events_bits dct_events;
2837 struct mlx5_ifc_qp_events_bits qp_events;
2838 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2839 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2840 struct mlx5_ifc_cq_error_bits cq_error;
2841 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2842 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2843 struct mlx5_ifc_gpio_event_bits gpio_event;
2844 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2845 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2846 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2847 u8 reserved_at_0[0xe0];
2848 };
2849
2850 struct mlx5_ifc_health_buffer_bits {
2851 u8 reserved_at_0[0x100];
2852
2853 u8 assert_existptr[0x20];
2854
2855 u8 assert_callra[0x20];
2856
2857 u8 reserved_at_140[0x40];
2858
2859 u8 fw_version[0x20];
2860
2861 u8 hw_id[0x20];
2862
2863 u8 reserved_at_1c0[0x20];
2864
2865 u8 irisc_index[0x8];
2866 u8 synd[0x8];
2867 u8 ext_synd[0x10];
2868 };
2869
2870 struct mlx5_ifc_register_loopback_control_bits {
2871 u8 no_lb[0x1];
2872 u8 reserved_at_1[0x7];
2873 u8 port[0x8];
2874 u8 reserved_at_10[0x10];
2875
2876 u8 reserved_at_20[0x60];
2877 };
2878
2879 struct mlx5_ifc_teardown_hca_out_bits {
2880 u8 status[0x8];
2881 u8 reserved_at_8[0x18];
2882
2883 u8 syndrome[0x20];
2884
2885 u8 reserved_at_40[0x40];
2886 };
2887
2888 enum {
2889 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2890 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2891 };
2892
2893 struct mlx5_ifc_teardown_hca_in_bits {
2894 u8 opcode[0x10];
2895 u8 reserved_at_10[0x10];
2896
2897 u8 reserved_at_20[0x10];
2898 u8 op_mod[0x10];
2899
2900 u8 reserved_at_40[0x10];
2901 u8 profile[0x10];
2902
2903 u8 reserved_at_60[0x20];
2904 };
2905
2906 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2907 u8 status[0x8];
2908 u8 reserved_at_8[0x18];
2909
2910 u8 syndrome[0x20];
2911
2912 u8 reserved_at_40[0x40];
2913 };
2914
2915 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2916 u8 opcode[0x10];
2917 u8 reserved_at_10[0x10];
2918
2919 u8 reserved_at_20[0x10];
2920 u8 op_mod[0x10];
2921
2922 u8 reserved_at_40[0x8];
2923 u8 qpn[0x18];
2924
2925 u8 reserved_at_60[0x20];
2926
2927 u8 opt_param_mask[0x20];
2928
2929 u8 reserved_at_a0[0x20];
2930
2931 struct mlx5_ifc_qpc_bits qpc;
2932
2933 u8 reserved_at_800[0x80];
2934 };
2935
2936 struct mlx5_ifc_sqd2rts_qp_out_bits {
2937 u8 status[0x8];
2938 u8 reserved_at_8[0x18];
2939
2940 u8 syndrome[0x20];
2941
2942 u8 reserved_at_40[0x40];
2943 };
2944
2945 struct mlx5_ifc_sqd2rts_qp_in_bits {
2946 u8 opcode[0x10];
2947 u8 reserved_at_10[0x10];
2948
2949 u8 reserved_at_20[0x10];
2950 u8 op_mod[0x10];
2951
2952 u8 reserved_at_40[0x8];
2953 u8 qpn[0x18];
2954
2955 u8 reserved_at_60[0x20];
2956
2957 u8 opt_param_mask[0x20];
2958
2959 u8 reserved_at_a0[0x20];
2960
2961 struct mlx5_ifc_qpc_bits qpc;
2962
2963 u8 reserved_at_800[0x80];
2964 };
2965
2966 struct mlx5_ifc_set_roce_address_out_bits {
2967 u8 status[0x8];
2968 u8 reserved_at_8[0x18];
2969
2970 u8 syndrome[0x20];
2971
2972 u8 reserved_at_40[0x40];
2973 };
2974
2975 struct mlx5_ifc_set_roce_address_in_bits {
2976 u8 opcode[0x10];
2977 u8 reserved_at_10[0x10];
2978
2979 u8 reserved_at_20[0x10];
2980 u8 op_mod[0x10];
2981
2982 u8 roce_address_index[0x10];
2983 u8 reserved_at_50[0x10];
2984
2985 u8 reserved_at_60[0x20];
2986
2987 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2988 };
2989
2990 struct mlx5_ifc_set_mad_demux_out_bits {
2991 u8 status[0x8];
2992 u8 reserved_at_8[0x18];
2993
2994 u8 syndrome[0x20];
2995
2996 u8 reserved_at_40[0x40];
2997 };
2998
2999 enum {
3000 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3001 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3002 };
3003
3004 struct mlx5_ifc_set_mad_demux_in_bits {
3005 u8 opcode[0x10];
3006 u8 reserved_at_10[0x10];
3007
3008 u8 reserved_at_20[0x10];
3009 u8 op_mod[0x10];
3010
3011 u8 reserved_at_40[0x20];
3012
3013 u8 reserved_at_60[0x6];
3014 u8 demux_mode[0x2];
3015 u8 reserved_at_68[0x18];
3016 };
3017
3018 struct mlx5_ifc_set_l2_table_entry_out_bits {
3019 u8 status[0x8];
3020 u8 reserved_at_8[0x18];
3021
3022 u8 syndrome[0x20];
3023
3024 u8 reserved_at_40[0x40];
3025 };
3026
3027 struct mlx5_ifc_set_l2_table_entry_in_bits {
3028 u8 opcode[0x10];
3029 u8 reserved_at_10[0x10];
3030
3031 u8 reserved_at_20[0x10];
3032 u8 op_mod[0x10];
3033
3034 u8 reserved_at_40[0x60];
3035
3036 u8 reserved_at_a0[0x8];
3037 u8 table_index[0x18];
3038
3039 u8 reserved_at_c0[0x20];
3040
3041 u8 reserved_at_e0[0x13];
3042 u8 vlan_valid[0x1];
3043 u8 vlan[0xc];
3044
3045 struct mlx5_ifc_mac_address_layout_bits mac_address;
3046
3047 u8 reserved_at_140[0xc0];
3048 };
3049
3050 struct mlx5_ifc_set_issi_out_bits {
3051 u8 status[0x8];
3052 u8 reserved_at_8[0x18];
3053
3054 u8 syndrome[0x20];
3055
3056 u8 reserved_at_40[0x40];
3057 };
3058
3059 struct mlx5_ifc_set_issi_in_bits {
3060 u8 opcode[0x10];
3061 u8 reserved_at_10[0x10];
3062
3063 u8 reserved_at_20[0x10];
3064 u8 op_mod[0x10];
3065
3066 u8 reserved_at_40[0x10];
3067 u8 current_issi[0x10];
3068
3069 u8 reserved_at_60[0x20];
3070 };
3071
3072 struct mlx5_ifc_set_hca_cap_out_bits {
3073 u8 status[0x8];
3074 u8 reserved_at_8[0x18];
3075
3076 u8 syndrome[0x20];
3077
3078 u8 reserved_at_40[0x40];
3079 };
3080
3081 struct mlx5_ifc_set_hca_cap_in_bits {
3082 u8 opcode[0x10];
3083 u8 reserved_at_10[0x10];
3084
3085 u8 reserved_at_20[0x10];
3086 u8 op_mod[0x10];
3087
3088 u8 reserved_at_40[0x40];
3089
3090 union mlx5_ifc_hca_cap_union_bits capability;
3091 };
3092
3093 enum {
3094 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3095 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3096 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3097 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3098 };
3099
3100 struct mlx5_ifc_set_fte_out_bits {
3101 u8 status[0x8];
3102 u8 reserved_at_8[0x18];
3103
3104 u8 syndrome[0x20];
3105
3106 u8 reserved_at_40[0x40];
3107 };
3108
3109 struct mlx5_ifc_set_fte_in_bits {
3110 u8 opcode[0x10];
3111 u8 reserved_at_10[0x10];
3112
3113 u8 reserved_at_20[0x10];
3114 u8 op_mod[0x10];
3115
3116 u8 other_vport[0x1];
3117 u8 reserved_at_41[0xf];
3118 u8 vport_number[0x10];
3119
3120 u8 reserved_at_60[0x20];
3121
3122 u8 table_type[0x8];
3123 u8 reserved_at_88[0x18];
3124
3125 u8 reserved_at_a0[0x8];
3126 u8 table_id[0x18];
3127
3128 u8 reserved_at_c0[0x18];
3129 u8 modify_enable_mask[0x8];
3130
3131 u8 reserved_at_e0[0x20];
3132
3133 u8 flow_index[0x20];
3134
3135 u8 reserved_at_120[0xe0];
3136
3137 struct mlx5_ifc_flow_context_bits flow_context;
3138 };
3139
3140 struct mlx5_ifc_rts2rts_qp_out_bits {
3141 u8 status[0x8];
3142 u8 reserved_at_8[0x18];
3143
3144 u8 syndrome[0x20];
3145
3146 u8 reserved_at_40[0x40];
3147 };
3148
3149 struct mlx5_ifc_rts2rts_qp_in_bits {
3150 u8 opcode[0x10];
3151 u8 reserved_at_10[0x10];
3152
3153 u8 reserved_at_20[0x10];
3154 u8 op_mod[0x10];
3155
3156 u8 reserved_at_40[0x8];
3157 u8 qpn[0x18];
3158
3159 u8 reserved_at_60[0x20];
3160
3161 u8 opt_param_mask[0x20];
3162
3163 u8 reserved_at_a0[0x20];
3164
3165 struct mlx5_ifc_qpc_bits qpc;
3166
3167 u8 reserved_at_800[0x80];
3168 };
3169
3170 struct mlx5_ifc_rtr2rts_qp_out_bits {
3171 u8 status[0x8];
3172 u8 reserved_at_8[0x18];
3173
3174 u8 syndrome[0x20];
3175
3176 u8 reserved_at_40[0x40];
3177 };
3178
3179 struct mlx5_ifc_rtr2rts_qp_in_bits {
3180 u8 opcode[0x10];
3181 u8 reserved_at_10[0x10];
3182
3183 u8 reserved_at_20[0x10];
3184 u8 op_mod[0x10];
3185
3186 u8 reserved_at_40[0x8];
3187 u8 qpn[0x18];
3188
3189 u8 reserved_at_60[0x20];
3190
3191 u8 opt_param_mask[0x20];
3192
3193 u8 reserved_at_a0[0x20];
3194
3195 struct mlx5_ifc_qpc_bits qpc;
3196
3197 u8 reserved_at_800[0x80];
3198 };
3199
3200 struct mlx5_ifc_rst2init_qp_out_bits {
3201 u8 status[0x8];
3202 u8 reserved_at_8[0x18];
3203
3204 u8 syndrome[0x20];
3205
3206 u8 reserved_at_40[0x40];
3207 };
3208
3209 struct mlx5_ifc_rst2init_qp_in_bits {
3210 u8 opcode[0x10];
3211 u8 reserved_at_10[0x10];
3212
3213 u8 reserved_at_20[0x10];
3214 u8 op_mod[0x10];
3215
3216 u8 reserved_at_40[0x8];
3217 u8 qpn[0x18];
3218
3219 u8 reserved_at_60[0x20];
3220
3221 u8 opt_param_mask[0x20];
3222
3223 u8 reserved_at_a0[0x20];
3224
3225 struct mlx5_ifc_qpc_bits qpc;
3226
3227 u8 reserved_at_800[0x80];
3228 };
3229
3230 struct mlx5_ifc_query_xrq_out_bits {
3231 u8 status[0x8];
3232 u8 reserved_at_8[0x18];
3233
3234 u8 syndrome[0x20];
3235
3236 u8 reserved_at_40[0x40];
3237
3238 struct mlx5_ifc_xrqc_bits xrq_context;
3239 };
3240
3241 struct mlx5_ifc_query_xrq_in_bits {
3242 u8 opcode[0x10];
3243 u8 reserved_at_10[0x10];
3244
3245 u8 reserved_at_20[0x10];
3246 u8 op_mod[0x10];
3247
3248 u8 reserved_at_40[0x8];
3249 u8 xrqn[0x18];
3250
3251 u8 reserved_at_60[0x20];
3252 };
3253
3254 struct mlx5_ifc_query_xrc_srq_out_bits {
3255 u8 status[0x8];
3256 u8 reserved_at_8[0x18];
3257
3258 u8 syndrome[0x20];
3259
3260 u8 reserved_at_40[0x40];
3261
3262 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3263
3264 u8 reserved_at_280[0x600];
3265
3266 u8 pas[0][0x40];
3267 };
3268
3269 struct mlx5_ifc_query_xrc_srq_in_bits {
3270 u8 opcode[0x10];
3271 u8 reserved_at_10[0x10];
3272
3273 u8 reserved_at_20[0x10];
3274 u8 op_mod[0x10];
3275
3276 u8 reserved_at_40[0x8];
3277 u8 xrc_srqn[0x18];
3278
3279 u8 reserved_at_60[0x20];
3280 };
3281
3282 enum {
3283 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3284 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3285 };
3286
3287 struct mlx5_ifc_query_vport_state_out_bits {
3288 u8 status[0x8];
3289 u8 reserved_at_8[0x18];
3290
3291 u8 syndrome[0x20];
3292
3293 u8 reserved_at_40[0x20];
3294
3295 u8 reserved_at_60[0x18];
3296 u8 admin_state[0x4];
3297 u8 state[0x4];
3298 };
3299
3300 enum {
3301 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3302 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3303 };
3304
3305 struct mlx5_ifc_query_vport_state_in_bits {
3306 u8 opcode[0x10];
3307 u8 reserved_at_10[0x10];
3308
3309 u8 reserved_at_20[0x10];
3310 u8 op_mod[0x10];
3311
3312 u8 other_vport[0x1];
3313 u8 reserved_at_41[0xf];
3314 u8 vport_number[0x10];
3315
3316 u8 reserved_at_60[0x20];
3317 };
3318
3319 struct mlx5_ifc_query_vport_counter_out_bits {
3320 u8 status[0x8];
3321 u8 reserved_at_8[0x18];
3322
3323 u8 syndrome[0x20];
3324
3325 u8 reserved_at_40[0x40];
3326
3327 struct mlx5_ifc_traffic_counter_bits received_errors;
3328
3329 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3330
3331 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3332
3333 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3334
3335 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3336
3337 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3338
3339 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3340
3341 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3342
3343 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3344
3345 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3346
3347 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3348
3349 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3350
3351 u8 reserved_at_680[0xa00];
3352 };
3353
3354 enum {
3355 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3356 };
3357
3358 struct mlx5_ifc_query_vport_counter_in_bits {
3359 u8 opcode[0x10];
3360 u8 reserved_at_10[0x10];
3361
3362 u8 reserved_at_20[0x10];
3363 u8 op_mod[0x10];
3364
3365 u8 other_vport[0x1];
3366 u8 reserved_at_41[0xb];
3367 u8 port_num[0x4];
3368 u8 vport_number[0x10];
3369
3370 u8 reserved_at_60[0x60];
3371
3372 u8 clear[0x1];
3373 u8 reserved_at_c1[0x1f];
3374
3375 u8 reserved_at_e0[0x20];
3376 };
3377
3378 struct mlx5_ifc_query_tis_out_bits {
3379 u8 status[0x8];
3380 u8 reserved_at_8[0x18];
3381
3382 u8 syndrome[0x20];
3383
3384 u8 reserved_at_40[0x40];
3385
3386 struct mlx5_ifc_tisc_bits tis_context;
3387 };
3388
3389 struct mlx5_ifc_query_tis_in_bits {
3390 u8 opcode[0x10];
3391 u8 reserved_at_10[0x10];
3392
3393 u8 reserved_at_20[0x10];
3394 u8 op_mod[0x10];
3395
3396 u8 reserved_at_40[0x8];
3397 u8 tisn[0x18];
3398
3399 u8 reserved_at_60[0x20];
3400 };
3401
3402 struct mlx5_ifc_query_tir_out_bits {
3403 u8 status[0x8];
3404 u8 reserved_at_8[0x18];
3405
3406 u8 syndrome[0x20];
3407
3408 u8 reserved_at_40[0xc0];
3409
3410 struct mlx5_ifc_tirc_bits tir_context;
3411 };
3412
3413 struct mlx5_ifc_query_tir_in_bits {
3414 u8 opcode[0x10];
3415 u8 reserved_at_10[0x10];
3416
3417 u8 reserved_at_20[0x10];
3418 u8 op_mod[0x10];
3419
3420 u8 reserved_at_40[0x8];
3421 u8 tirn[0x18];
3422
3423 u8 reserved_at_60[0x20];
3424 };
3425
3426 struct mlx5_ifc_query_srq_out_bits {
3427 u8 status[0x8];
3428 u8 reserved_at_8[0x18];
3429
3430 u8 syndrome[0x20];
3431
3432 u8 reserved_at_40[0x40];
3433
3434 struct mlx5_ifc_srqc_bits srq_context_entry;
3435
3436 u8 reserved_at_280[0x600];
3437
3438 u8 pas[0][0x40];
3439 };
3440
3441 struct mlx5_ifc_query_srq_in_bits {
3442 u8 opcode[0x10];
3443 u8 reserved_at_10[0x10];
3444
3445 u8 reserved_at_20[0x10];
3446 u8 op_mod[0x10];
3447
3448 u8 reserved_at_40[0x8];
3449 u8 srqn[0x18];
3450
3451 u8 reserved_at_60[0x20];
3452 };
3453
3454 struct mlx5_ifc_query_sq_out_bits {
3455 u8 status[0x8];
3456 u8 reserved_at_8[0x18];
3457
3458 u8 syndrome[0x20];
3459
3460 u8 reserved_at_40[0xc0];
3461
3462 struct mlx5_ifc_sqc_bits sq_context;
3463 };
3464
3465 struct mlx5_ifc_query_sq_in_bits {
3466 u8 opcode[0x10];
3467 u8 reserved_at_10[0x10];
3468
3469 u8 reserved_at_20[0x10];
3470 u8 op_mod[0x10];
3471
3472 u8 reserved_at_40[0x8];
3473 u8 sqn[0x18];
3474
3475 u8 reserved_at_60[0x20];
3476 };
3477
3478 struct mlx5_ifc_query_special_contexts_out_bits {
3479 u8 status[0x8];
3480 u8 reserved_at_8[0x18];
3481
3482 u8 syndrome[0x20];
3483
3484 u8 reserved_at_40[0x20];
3485
3486 u8 resd_lkey[0x20];
3487 };
3488
3489 struct mlx5_ifc_query_special_contexts_in_bits {
3490 u8 opcode[0x10];
3491 u8 reserved_at_10[0x10];
3492
3493 u8 reserved_at_20[0x10];
3494 u8 op_mod[0x10];
3495
3496 u8 reserved_at_40[0x40];
3497 };
3498
3499 struct mlx5_ifc_query_rqt_out_bits {
3500 u8 status[0x8];
3501 u8 reserved_at_8[0x18];
3502
3503 u8 syndrome[0x20];
3504
3505 u8 reserved_at_40[0xc0];
3506
3507 struct mlx5_ifc_rqtc_bits rqt_context;
3508 };
3509
3510 struct mlx5_ifc_query_rqt_in_bits {
3511 u8 opcode[0x10];
3512 u8 reserved_at_10[0x10];
3513
3514 u8 reserved_at_20[0x10];
3515 u8 op_mod[0x10];
3516
3517 u8 reserved_at_40[0x8];
3518 u8 rqtn[0x18];
3519
3520 u8 reserved_at_60[0x20];
3521 };
3522
3523 struct mlx5_ifc_query_rq_out_bits {
3524 u8 status[0x8];
3525 u8 reserved_at_8[0x18];
3526
3527 u8 syndrome[0x20];
3528
3529 u8 reserved_at_40[0xc0];
3530
3531 struct mlx5_ifc_rqc_bits rq_context;
3532 };
3533
3534 struct mlx5_ifc_query_rq_in_bits {
3535 u8 opcode[0x10];
3536 u8 reserved_at_10[0x10];
3537
3538 u8 reserved_at_20[0x10];
3539 u8 op_mod[0x10];
3540
3541 u8 reserved_at_40[0x8];
3542 u8 rqn[0x18];
3543
3544 u8 reserved_at_60[0x20];
3545 };
3546
3547 struct mlx5_ifc_query_roce_address_out_bits {
3548 u8 status[0x8];
3549 u8 reserved_at_8[0x18];
3550
3551 u8 syndrome[0x20];
3552
3553 u8 reserved_at_40[0x40];
3554
3555 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3556 };
3557
3558 struct mlx5_ifc_query_roce_address_in_bits {
3559 u8 opcode[0x10];
3560 u8 reserved_at_10[0x10];
3561
3562 u8 reserved_at_20[0x10];
3563 u8 op_mod[0x10];
3564
3565 u8 roce_address_index[0x10];
3566 u8 reserved_at_50[0x10];
3567
3568 u8 reserved_at_60[0x20];
3569 };
3570
3571 struct mlx5_ifc_query_rmp_out_bits {
3572 u8 status[0x8];
3573 u8 reserved_at_8[0x18];
3574
3575 u8 syndrome[0x20];
3576
3577 u8 reserved_at_40[0xc0];
3578
3579 struct mlx5_ifc_rmpc_bits rmp_context;
3580 };
3581
3582 struct mlx5_ifc_query_rmp_in_bits {
3583 u8 opcode[0x10];
3584 u8 reserved_at_10[0x10];
3585
3586 u8 reserved_at_20[0x10];
3587 u8 op_mod[0x10];
3588
3589 u8 reserved_at_40[0x8];
3590 u8 rmpn[0x18];
3591
3592 u8 reserved_at_60[0x20];
3593 };
3594
3595 struct mlx5_ifc_query_qp_out_bits {
3596 u8 status[0x8];
3597 u8 reserved_at_8[0x18];
3598
3599 u8 syndrome[0x20];
3600
3601 u8 reserved_at_40[0x40];
3602
3603 u8 opt_param_mask[0x20];
3604
3605 u8 reserved_at_a0[0x20];
3606
3607 struct mlx5_ifc_qpc_bits qpc;
3608
3609 u8 reserved_at_800[0x80];
3610
3611 u8 pas[0][0x40];
3612 };
3613
3614 struct mlx5_ifc_query_qp_in_bits {
3615 u8 opcode[0x10];
3616 u8 reserved_at_10[0x10];
3617
3618 u8 reserved_at_20[0x10];
3619 u8 op_mod[0x10];
3620
3621 u8 reserved_at_40[0x8];
3622 u8 qpn[0x18];
3623
3624 u8 reserved_at_60[0x20];
3625 };
3626
3627 struct mlx5_ifc_query_q_counter_out_bits {
3628 u8 status[0x8];
3629 u8 reserved_at_8[0x18];
3630
3631 u8 syndrome[0x20];
3632
3633 u8 reserved_at_40[0x40];
3634
3635 u8 rx_write_requests[0x20];
3636
3637 u8 reserved_at_a0[0x20];
3638
3639 u8 rx_read_requests[0x20];
3640
3641 u8 reserved_at_e0[0x20];
3642
3643 u8 rx_atomic_requests[0x20];
3644
3645 u8 reserved_at_120[0x20];
3646
3647 u8 rx_dct_connect[0x20];
3648
3649 u8 reserved_at_160[0x20];
3650
3651 u8 out_of_buffer[0x20];
3652
3653 u8 reserved_at_1a0[0x20];
3654
3655 u8 out_of_sequence[0x20];
3656
3657 u8 reserved_at_1e0[0x20];
3658
3659 u8 duplicate_request[0x20];
3660
3661 u8 reserved_at_220[0x20];
3662
3663 u8 rnr_nak_retry_err[0x20];
3664
3665 u8 reserved_at_260[0x20];
3666
3667 u8 packet_seq_err[0x20];
3668
3669 u8 reserved_at_2a0[0x20];
3670
3671 u8 implied_nak_seq_err[0x20];
3672
3673 u8 reserved_at_2e0[0x20];
3674
3675 u8 local_ack_timeout_err[0x20];
3676
3677 u8 reserved_at_320[0x4e0];
3678 };
3679
3680 struct mlx5_ifc_query_q_counter_in_bits {
3681 u8 opcode[0x10];
3682 u8 reserved_at_10[0x10];
3683
3684 u8 reserved_at_20[0x10];
3685 u8 op_mod[0x10];
3686
3687 u8 reserved_at_40[0x80];
3688
3689 u8 clear[0x1];
3690 u8 reserved_at_c1[0x1f];
3691
3692 u8 reserved_at_e0[0x18];
3693 u8 counter_set_id[0x8];
3694 };
3695
3696 struct mlx5_ifc_query_pages_out_bits {
3697 u8 status[0x8];
3698 u8 reserved_at_8[0x18];
3699
3700 u8 syndrome[0x20];
3701
3702 u8 reserved_at_40[0x10];
3703 u8 function_id[0x10];
3704
3705 u8 num_pages[0x20];
3706 };
3707
3708 enum {
3709 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3710 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3711 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3712 };
3713
3714 struct mlx5_ifc_query_pages_in_bits {
3715 u8 opcode[0x10];
3716 u8 reserved_at_10[0x10];
3717
3718 u8 reserved_at_20[0x10];
3719 u8 op_mod[0x10];
3720
3721 u8 reserved_at_40[0x10];
3722 u8 function_id[0x10];
3723
3724 u8 reserved_at_60[0x20];
3725 };
3726
3727 struct mlx5_ifc_query_nic_vport_context_out_bits {
3728 u8 status[0x8];
3729 u8 reserved_at_8[0x18];
3730
3731 u8 syndrome[0x20];
3732
3733 u8 reserved_at_40[0x40];
3734
3735 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3736 };
3737
3738 struct mlx5_ifc_query_nic_vport_context_in_bits {
3739 u8 opcode[0x10];
3740 u8 reserved_at_10[0x10];
3741
3742 u8 reserved_at_20[0x10];
3743 u8 op_mod[0x10];
3744
3745 u8 other_vport[0x1];
3746 u8 reserved_at_41[0xf];
3747 u8 vport_number[0x10];
3748
3749 u8 reserved_at_60[0x5];
3750 u8 allowed_list_type[0x3];
3751 u8 reserved_at_68[0x18];
3752 };
3753
3754 struct mlx5_ifc_query_mkey_out_bits {
3755 u8 status[0x8];
3756 u8 reserved_at_8[0x18];
3757
3758 u8 syndrome[0x20];
3759
3760 u8 reserved_at_40[0x40];
3761
3762 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3763
3764 u8 reserved_at_280[0x600];
3765
3766 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3767
3768 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3769 };
3770
3771 struct mlx5_ifc_query_mkey_in_bits {
3772 u8 opcode[0x10];
3773 u8 reserved_at_10[0x10];
3774
3775 u8 reserved_at_20[0x10];
3776 u8 op_mod[0x10];
3777
3778 u8 reserved_at_40[0x8];
3779 u8 mkey_index[0x18];
3780
3781 u8 pg_access[0x1];
3782 u8 reserved_at_61[0x1f];
3783 };
3784
3785 struct mlx5_ifc_query_mad_demux_out_bits {
3786 u8 status[0x8];
3787 u8 reserved_at_8[0x18];
3788
3789 u8 syndrome[0x20];
3790
3791 u8 reserved_at_40[0x40];
3792
3793 u8 mad_dumux_parameters_block[0x20];
3794 };
3795
3796 struct mlx5_ifc_query_mad_demux_in_bits {
3797 u8 opcode[0x10];
3798 u8 reserved_at_10[0x10];
3799
3800 u8 reserved_at_20[0x10];
3801 u8 op_mod[0x10];
3802
3803 u8 reserved_at_40[0x40];
3804 };
3805
3806 struct mlx5_ifc_query_l2_table_entry_out_bits {
3807 u8 status[0x8];
3808 u8 reserved_at_8[0x18];
3809
3810 u8 syndrome[0x20];
3811
3812 u8 reserved_at_40[0xa0];
3813
3814 u8 reserved_at_e0[0x13];
3815 u8 vlan_valid[0x1];
3816 u8 vlan[0xc];
3817
3818 struct mlx5_ifc_mac_address_layout_bits mac_address;
3819
3820 u8 reserved_at_140[0xc0];
3821 };
3822
3823 struct mlx5_ifc_query_l2_table_entry_in_bits {
3824 u8 opcode[0x10];
3825 u8 reserved_at_10[0x10];
3826
3827 u8 reserved_at_20[0x10];
3828 u8 op_mod[0x10];
3829
3830 u8 reserved_at_40[0x60];
3831
3832 u8 reserved_at_a0[0x8];
3833 u8 table_index[0x18];
3834
3835 u8 reserved_at_c0[0x140];
3836 };
3837
3838 struct mlx5_ifc_query_issi_out_bits {
3839 u8 status[0x8];
3840 u8 reserved_at_8[0x18];
3841
3842 u8 syndrome[0x20];
3843
3844 u8 reserved_at_40[0x10];
3845 u8 current_issi[0x10];
3846
3847 u8 reserved_at_60[0xa0];
3848
3849 u8 reserved_at_100[76][0x8];
3850 u8 supported_issi_dw0[0x20];
3851 };
3852
3853 struct mlx5_ifc_query_issi_in_bits {
3854 u8 opcode[0x10];
3855 u8 reserved_at_10[0x10];
3856
3857 u8 reserved_at_20[0x10];
3858 u8 op_mod[0x10];
3859
3860 u8 reserved_at_40[0x40];
3861 };
3862
3863 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3864 u8 status[0x8];
3865 u8 reserved_at_8[0x18];
3866
3867 u8 syndrome[0x20];
3868
3869 u8 reserved_at_40[0x40];
3870
3871 struct mlx5_ifc_pkey_bits pkey[0];
3872 };
3873
3874 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3875 u8 opcode[0x10];
3876 u8 reserved_at_10[0x10];
3877
3878 u8 reserved_at_20[0x10];
3879 u8 op_mod[0x10];
3880
3881 u8 other_vport[0x1];
3882 u8 reserved_at_41[0xb];
3883 u8 port_num[0x4];
3884 u8 vport_number[0x10];
3885
3886 u8 reserved_at_60[0x10];
3887 u8 pkey_index[0x10];
3888 };
3889
3890 enum {
3891 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3892 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3893 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3894 };
3895
3896 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3897 u8 status[0x8];
3898 u8 reserved_at_8[0x18];
3899
3900 u8 syndrome[0x20];
3901
3902 u8 reserved_at_40[0x20];
3903
3904 u8 gids_num[0x10];
3905 u8 reserved_at_70[0x10];
3906
3907 struct mlx5_ifc_array128_auto_bits gid[0];
3908 };
3909
3910 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3911 u8 opcode[0x10];
3912 u8 reserved_at_10[0x10];
3913
3914 u8 reserved_at_20[0x10];
3915 u8 op_mod[0x10];
3916
3917 u8 other_vport[0x1];
3918 u8 reserved_at_41[0xb];
3919 u8 port_num[0x4];
3920 u8 vport_number[0x10];
3921
3922 u8 reserved_at_60[0x10];
3923 u8 gid_index[0x10];
3924 };
3925
3926 struct mlx5_ifc_query_hca_vport_context_out_bits {
3927 u8 status[0x8];
3928 u8 reserved_at_8[0x18];
3929
3930 u8 syndrome[0x20];
3931
3932 u8 reserved_at_40[0x40];
3933
3934 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3935 };
3936
3937 struct mlx5_ifc_query_hca_vport_context_in_bits {
3938 u8 opcode[0x10];
3939 u8 reserved_at_10[0x10];
3940
3941 u8 reserved_at_20[0x10];
3942 u8 op_mod[0x10];
3943
3944 u8 other_vport[0x1];
3945 u8 reserved_at_41[0xb];
3946 u8 port_num[0x4];
3947 u8 vport_number[0x10];
3948
3949 u8 reserved_at_60[0x20];
3950 };
3951
3952 struct mlx5_ifc_query_hca_cap_out_bits {
3953 u8 status[0x8];
3954 u8 reserved_at_8[0x18];
3955
3956 u8 syndrome[0x20];
3957
3958 u8 reserved_at_40[0x40];
3959
3960 union mlx5_ifc_hca_cap_union_bits capability;
3961 };
3962
3963 struct mlx5_ifc_query_hca_cap_in_bits {
3964 u8 opcode[0x10];
3965 u8 reserved_at_10[0x10];
3966
3967 u8 reserved_at_20[0x10];
3968 u8 op_mod[0x10];
3969
3970 u8 reserved_at_40[0x40];
3971 };
3972
3973 struct mlx5_ifc_query_flow_table_out_bits {
3974 u8 status[0x8];
3975 u8 reserved_at_8[0x18];
3976
3977 u8 syndrome[0x20];
3978
3979 u8 reserved_at_40[0x80];
3980
3981 u8 reserved_at_c0[0x8];
3982 u8 level[0x8];
3983 u8 reserved_at_d0[0x8];
3984 u8 log_size[0x8];
3985
3986 u8 reserved_at_e0[0x120];
3987 };
3988
3989 struct mlx5_ifc_query_flow_table_in_bits {
3990 u8 opcode[0x10];
3991 u8 reserved_at_10[0x10];
3992
3993 u8 reserved_at_20[0x10];
3994 u8 op_mod[0x10];
3995
3996 u8 reserved_at_40[0x40];
3997
3998 u8 table_type[0x8];
3999 u8 reserved_at_88[0x18];
4000
4001 u8 reserved_at_a0[0x8];
4002 u8 table_id[0x18];
4003
4004 u8 reserved_at_c0[0x140];
4005 };
4006
4007 struct mlx5_ifc_query_fte_out_bits {
4008 u8 status[0x8];
4009 u8 reserved_at_8[0x18];
4010
4011 u8 syndrome[0x20];
4012
4013 u8 reserved_at_40[0x1c0];
4014
4015 struct mlx5_ifc_flow_context_bits flow_context;
4016 };
4017
4018 struct mlx5_ifc_query_fte_in_bits {
4019 u8 opcode[0x10];
4020 u8 reserved_at_10[0x10];
4021
4022 u8 reserved_at_20[0x10];
4023 u8 op_mod[0x10];
4024
4025 u8 reserved_at_40[0x40];
4026
4027 u8 table_type[0x8];
4028 u8 reserved_at_88[0x18];
4029
4030 u8 reserved_at_a0[0x8];
4031 u8 table_id[0x18];
4032
4033 u8 reserved_at_c0[0x40];
4034
4035 u8 flow_index[0x20];
4036
4037 u8 reserved_at_120[0xe0];
4038 };
4039
4040 enum {
4041 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4042 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4043 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4044 };
4045
4046 struct mlx5_ifc_query_flow_group_out_bits {
4047 u8 status[0x8];
4048 u8 reserved_at_8[0x18];
4049
4050 u8 syndrome[0x20];
4051
4052 u8 reserved_at_40[0xa0];
4053
4054 u8 start_flow_index[0x20];
4055
4056 u8 reserved_at_100[0x20];
4057
4058 u8 end_flow_index[0x20];
4059
4060 u8 reserved_at_140[0xa0];
4061
4062 u8 reserved_at_1e0[0x18];
4063 u8 match_criteria_enable[0x8];
4064
4065 struct mlx5_ifc_fte_match_param_bits match_criteria;
4066
4067 u8 reserved_at_1200[0xe00];
4068 };
4069
4070 struct mlx5_ifc_query_flow_group_in_bits {
4071 u8 opcode[0x10];
4072 u8 reserved_at_10[0x10];
4073
4074 u8 reserved_at_20[0x10];
4075 u8 op_mod[0x10];
4076
4077 u8 reserved_at_40[0x40];
4078
4079 u8 table_type[0x8];
4080 u8 reserved_at_88[0x18];
4081
4082 u8 reserved_at_a0[0x8];
4083 u8 table_id[0x18];
4084
4085 u8 group_id[0x20];
4086
4087 u8 reserved_at_e0[0x120];
4088 };
4089
4090 struct mlx5_ifc_query_flow_counter_out_bits {
4091 u8 status[0x8];
4092 u8 reserved_at_8[0x18];
4093
4094 u8 syndrome[0x20];
4095
4096 u8 reserved_at_40[0x40];
4097
4098 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4099 };
4100
4101 struct mlx5_ifc_query_flow_counter_in_bits {
4102 u8 opcode[0x10];
4103 u8 reserved_at_10[0x10];
4104
4105 u8 reserved_at_20[0x10];
4106 u8 op_mod[0x10];
4107
4108 u8 reserved_at_40[0x80];
4109
4110 u8 clear[0x1];
4111 u8 reserved_at_c1[0xf];
4112 u8 num_of_counters[0x10];
4113
4114 u8 reserved_at_e0[0x10];
4115 u8 flow_counter_id[0x10];
4116 };
4117
4118 struct mlx5_ifc_query_esw_vport_context_out_bits {
4119 u8 status[0x8];
4120 u8 reserved_at_8[0x18];
4121
4122 u8 syndrome[0x20];
4123
4124 u8 reserved_at_40[0x40];
4125
4126 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4127 };
4128
4129 struct mlx5_ifc_query_esw_vport_context_in_bits {
4130 u8 opcode[0x10];
4131 u8 reserved_at_10[0x10];
4132
4133 u8 reserved_at_20[0x10];
4134 u8 op_mod[0x10];
4135
4136 u8 other_vport[0x1];
4137 u8 reserved_at_41[0xf];
4138 u8 vport_number[0x10];
4139
4140 u8 reserved_at_60[0x20];
4141 };
4142
4143 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4144 u8 status[0x8];
4145 u8 reserved_at_8[0x18];
4146
4147 u8 syndrome[0x20];
4148
4149 u8 reserved_at_40[0x40];
4150 };
4151
4152 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4153 u8 reserved_at_0[0x1c];
4154 u8 vport_cvlan_insert[0x1];
4155 u8 vport_svlan_insert[0x1];
4156 u8 vport_cvlan_strip[0x1];
4157 u8 vport_svlan_strip[0x1];
4158 };
4159
4160 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4161 u8 opcode[0x10];
4162 u8 reserved_at_10[0x10];
4163
4164 u8 reserved_at_20[0x10];
4165 u8 op_mod[0x10];
4166
4167 u8 other_vport[0x1];
4168 u8 reserved_at_41[0xf];
4169 u8 vport_number[0x10];
4170
4171 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4172
4173 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4174 };
4175
4176 struct mlx5_ifc_query_eq_out_bits {
4177 u8 status[0x8];
4178 u8 reserved_at_8[0x18];
4179
4180 u8 syndrome[0x20];
4181
4182 u8 reserved_at_40[0x40];
4183
4184 struct mlx5_ifc_eqc_bits eq_context_entry;
4185
4186 u8 reserved_at_280[0x40];
4187
4188 u8 event_bitmask[0x40];
4189
4190 u8 reserved_at_300[0x580];
4191
4192 u8 pas[0][0x40];
4193 };
4194
4195 struct mlx5_ifc_query_eq_in_bits {
4196 u8 opcode[0x10];
4197 u8 reserved_at_10[0x10];
4198
4199 u8 reserved_at_20[0x10];
4200 u8 op_mod[0x10];
4201
4202 u8 reserved_at_40[0x18];
4203 u8 eq_number[0x8];
4204
4205 u8 reserved_at_60[0x20];
4206 };
4207
4208 struct mlx5_ifc_query_dct_out_bits {
4209 u8 status[0x8];
4210 u8 reserved_at_8[0x18];
4211
4212 u8 syndrome[0x20];
4213
4214 u8 reserved_at_40[0x40];
4215
4216 struct mlx5_ifc_dctc_bits dct_context_entry;
4217
4218 u8 reserved_at_280[0x180];
4219 };
4220
4221 struct mlx5_ifc_query_dct_in_bits {
4222 u8 opcode[0x10];
4223 u8 reserved_at_10[0x10];
4224
4225 u8 reserved_at_20[0x10];
4226 u8 op_mod[0x10];
4227
4228 u8 reserved_at_40[0x8];
4229 u8 dctn[0x18];
4230
4231 u8 reserved_at_60[0x20];
4232 };
4233
4234 struct mlx5_ifc_query_cq_out_bits {
4235 u8 status[0x8];
4236 u8 reserved_at_8[0x18];
4237
4238 u8 syndrome[0x20];
4239
4240 u8 reserved_at_40[0x40];
4241
4242 struct mlx5_ifc_cqc_bits cq_context;
4243
4244 u8 reserved_at_280[0x600];
4245
4246 u8 pas[0][0x40];
4247 };
4248
4249 struct mlx5_ifc_query_cq_in_bits {
4250 u8 opcode[0x10];
4251 u8 reserved_at_10[0x10];
4252
4253 u8 reserved_at_20[0x10];
4254 u8 op_mod[0x10];
4255
4256 u8 reserved_at_40[0x8];
4257 u8 cqn[0x18];
4258
4259 u8 reserved_at_60[0x20];
4260 };
4261
4262 struct mlx5_ifc_query_cong_status_out_bits {
4263 u8 status[0x8];
4264 u8 reserved_at_8[0x18];
4265
4266 u8 syndrome[0x20];
4267
4268 u8 reserved_at_40[0x20];
4269
4270 u8 enable[0x1];
4271 u8 tag_enable[0x1];
4272 u8 reserved_at_62[0x1e];
4273 };
4274
4275 struct mlx5_ifc_query_cong_status_in_bits {
4276 u8 opcode[0x10];
4277 u8 reserved_at_10[0x10];
4278
4279 u8 reserved_at_20[0x10];
4280 u8 op_mod[0x10];
4281
4282 u8 reserved_at_40[0x18];
4283 u8 priority[0x4];
4284 u8 cong_protocol[0x4];
4285
4286 u8 reserved_at_60[0x20];
4287 };
4288
4289 struct mlx5_ifc_query_cong_statistics_out_bits {
4290 u8 status[0x8];
4291 u8 reserved_at_8[0x18];
4292
4293 u8 syndrome[0x20];
4294
4295 u8 reserved_at_40[0x40];
4296
4297 u8 cur_flows[0x20];
4298
4299 u8 sum_flows[0x20];
4300
4301 u8 cnp_ignored_high[0x20];
4302
4303 u8 cnp_ignored_low[0x20];
4304
4305 u8 cnp_handled_high[0x20];
4306
4307 u8 cnp_handled_low[0x20];
4308
4309 u8 reserved_at_140[0x100];
4310
4311 u8 time_stamp_high[0x20];
4312
4313 u8 time_stamp_low[0x20];
4314
4315 u8 accumulators_period[0x20];
4316
4317 u8 ecn_marked_roce_packets_high[0x20];
4318
4319 u8 ecn_marked_roce_packets_low[0x20];
4320
4321 u8 cnps_sent_high[0x20];
4322
4323 u8 cnps_sent_low[0x20];
4324
4325 u8 reserved_at_320[0x560];
4326 };
4327
4328 struct mlx5_ifc_query_cong_statistics_in_bits {
4329 u8 opcode[0x10];
4330 u8 reserved_at_10[0x10];
4331
4332 u8 reserved_at_20[0x10];
4333 u8 op_mod[0x10];
4334
4335 u8 clear[0x1];
4336 u8 reserved_at_41[0x1f];
4337
4338 u8 reserved_at_60[0x20];
4339 };
4340
4341 struct mlx5_ifc_query_cong_params_out_bits {
4342 u8 status[0x8];
4343 u8 reserved_at_8[0x18];
4344
4345 u8 syndrome[0x20];
4346
4347 u8 reserved_at_40[0x40];
4348
4349 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4350 };
4351
4352 struct mlx5_ifc_query_cong_params_in_bits {
4353 u8 opcode[0x10];
4354 u8 reserved_at_10[0x10];
4355
4356 u8 reserved_at_20[0x10];
4357 u8 op_mod[0x10];
4358
4359 u8 reserved_at_40[0x1c];
4360 u8 cong_protocol[0x4];
4361
4362 u8 reserved_at_60[0x20];
4363 };
4364
4365 struct mlx5_ifc_query_adapter_out_bits {
4366 u8 status[0x8];
4367 u8 reserved_at_8[0x18];
4368
4369 u8 syndrome[0x20];
4370
4371 u8 reserved_at_40[0x40];
4372
4373 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4374 };
4375
4376 struct mlx5_ifc_query_adapter_in_bits {
4377 u8 opcode[0x10];
4378 u8 reserved_at_10[0x10];
4379
4380 u8 reserved_at_20[0x10];
4381 u8 op_mod[0x10];
4382
4383 u8 reserved_at_40[0x40];
4384 };
4385
4386 struct mlx5_ifc_qp_2rst_out_bits {
4387 u8 status[0x8];
4388 u8 reserved_at_8[0x18];
4389
4390 u8 syndrome[0x20];
4391
4392 u8 reserved_at_40[0x40];
4393 };
4394
4395 struct mlx5_ifc_qp_2rst_in_bits {
4396 u8 opcode[0x10];
4397 u8 reserved_at_10[0x10];
4398
4399 u8 reserved_at_20[0x10];
4400 u8 op_mod[0x10];
4401
4402 u8 reserved_at_40[0x8];
4403 u8 qpn[0x18];
4404
4405 u8 reserved_at_60[0x20];
4406 };
4407
4408 struct mlx5_ifc_qp_2err_out_bits {
4409 u8 status[0x8];
4410 u8 reserved_at_8[0x18];
4411
4412 u8 syndrome[0x20];
4413
4414 u8 reserved_at_40[0x40];
4415 };
4416
4417 struct mlx5_ifc_qp_2err_in_bits {
4418 u8 opcode[0x10];
4419 u8 reserved_at_10[0x10];
4420
4421 u8 reserved_at_20[0x10];
4422 u8 op_mod[0x10];
4423
4424 u8 reserved_at_40[0x8];
4425 u8 qpn[0x18];
4426
4427 u8 reserved_at_60[0x20];
4428 };
4429
4430 struct mlx5_ifc_page_fault_resume_out_bits {
4431 u8 status[0x8];
4432 u8 reserved_at_8[0x18];
4433
4434 u8 syndrome[0x20];
4435
4436 u8 reserved_at_40[0x40];
4437 };
4438
4439 struct mlx5_ifc_page_fault_resume_in_bits {
4440 u8 opcode[0x10];
4441 u8 reserved_at_10[0x10];
4442
4443 u8 reserved_at_20[0x10];
4444 u8 op_mod[0x10];
4445
4446 u8 error[0x1];
4447 u8 reserved_at_41[0x4];
4448 u8 rdma[0x1];
4449 u8 read_write[0x1];
4450 u8 req_res[0x1];
4451 u8 qpn[0x18];
4452
4453 u8 reserved_at_60[0x20];
4454 };
4455
4456 struct mlx5_ifc_nop_out_bits {
4457 u8 status[0x8];
4458 u8 reserved_at_8[0x18];
4459
4460 u8 syndrome[0x20];
4461
4462 u8 reserved_at_40[0x40];
4463 };
4464
4465 struct mlx5_ifc_nop_in_bits {
4466 u8 opcode[0x10];
4467 u8 reserved_at_10[0x10];
4468
4469 u8 reserved_at_20[0x10];
4470 u8 op_mod[0x10];
4471
4472 u8 reserved_at_40[0x40];
4473 };
4474
4475 struct mlx5_ifc_modify_vport_state_out_bits {
4476 u8 status[0x8];
4477 u8 reserved_at_8[0x18];
4478
4479 u8 syndrome[0x20];
4480
4481 u8 reserved_at_40[0x40];
4482 };
4483
4484 struct mlx5_ifc_modify_vport_state_in_bits {
4485 u8 opcode[0x10];
4486 u8 reserved_at_10[0x10];
4487
4488 u8 reserved_at_20[0x10];
4489 u8 op_mod[0x10];
4490
4491 u8 other_vport[0x1];
4492 u8 reserved_at_41[0xf];
4493 u8 vport_number[0x10];
4494
4495 u8 reserved_at_60[0x18];
4496 u8 admin_state[0x4];
4497 u8 reserved_at_7c[0x4];
4498 };
4499
4500 struct mlx5_ifc_modify_tis_out_bits {
4501 u8 status[0x8];
4502 u8 reserved_at_8[0x18];
4503
4504 u8 syndrome[0x20];
4505
4506 u8 reserved_at_40[0x40];
4507 };
4508
4509 struct mlx5_ifc_modify_tis_bitmask_bits {
4510 u8 reserved_at_0[0x20];
4511
4512 u8 reserved_at_20[0x1f];
4513 u8 prio[0x1];
4514 };
4515
4516 struct mlx5_ifc_modify_tis_in_bits {
4517 u8 opcode[0x10];
4518 u8 reserved_at_10[0x10];
4519
4520 u8 reserved_at_20[0x10];
4521 u8 op_mod[0x10];
4522
4523 u8 reserved_at_40[0x8];
4524 u8 tisn[0x18];
4525
4526 u8 reserved_at_60[0x20];
4527
4528 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4529
4530 u8 reserved_at_c0[0x40];
4531
4532 struct mlx5_ifc_tisc_bits ctx;
4533 };
4534
4535 struct mlx5_ifc_modify_tir_bitmask_bits {
4536 u8 reserved_at_0[0x20];
4537
4538 u8 reserved_at_20[0x1b];
4539 u8 self_lb_en[0x1];
4540 u8 reserved_at_3c[0x1];
4541 u8 hash[0x1];
4542 u8 reserved_at_3e[0x1];
4543 u8 lro[0x1];
4544 };
4545
4546 struct mlx5_ifc_modify_tir_out_bits {
4547 u8 status[0x8];
4548 u8 reserved_at_8[0x18];
4549
4550 u8 syndrome[0x20];
4551
4552 u8 reserved_at_40[0x40];
4553 };
4554
4555 struct mlx5_ifc_modify_tir_in_bits {
4556 u8 opcode[0x10];
4557 u8 reserved_at_10[0x10];
4558
4559 u8 reserved_at_20[0x10];
4560 u8 op_mod[0x10];
4561
4562 u8 reserved_at_40[0x8];
4563 u8 tirn[0x18];
4564
4565 u8 reserved_at_60[0x20];
4566
4567 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4568
4569 u8 reserved_at_c0[0x40];
4570
4571 struct mlx5_ifc_tirc_bits ctx;
4572 };
4573
4574 struct mlx5_ifc_modify_sq_out_bits {
4575 u8 status[0x8];
4576 u8 reserved_at_8[0x18];
4577
4578 u8 syndrome[0x20];
4579
4580 u8 reserved_at_40[0x40];
4581 };
4582
4583 struct mlx5_ifc_modify_sq_in_bits {
4584 u8 opcode[0x10];
4585 u8 reserved_at_10[0x10];
4586
4587 u8 reserved_at_20[0x10];
4588 u8 op_mod[0x10];
4589
4590 u8 sq_state[0x4];
4591 u8 reserved_at_44[0x4];
4592 u8 sqn[0x18];
4593
4594 u8 reserved_at_60[0x20];
4595
4596 u8 modify_bitmask[0x40];
4597
4598 u8 reserved_at_c0[0x40];
4599
4600 struct mlx5_ifc_sqc_bits ctx;
4601 };
4602
4603 struct mlx5_ifc_modify_rqt_out_bits {
4604 u8 status[0x8];
4605 u8 reserved_at_8[0x18];
4606
4607 u8 syndrome[0x20];
4608
4609 u8 reserved_at_40[0x40];
4610 };
4611
4612 struct mlx5_ifc_rqt_bitmask_bits {
4613 u8 reserved_at_0[0x20];
4614
4615 u8 reserved_at_20[0x1f];
4616 u8 rqn_list[0x1];
4617 };
4618
4619 struct mlx5_ifc_modify_rqt_in_bits {
4620 u8 opcode[0x10];
4621 u8 reserved_at_10[0x10];
4622
4623 u8 reserved_at_20[0x10];
4624 u8 op_mod[0x10];
4625
4626 u8 reserved_at_40[0x8];
4627 u8 rqtn[0x18];
4628
4629 u8 reserved_at_60[0x20];
4630
4631 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4632
4633 u8 reserved_at_c0[0x40];
4634
4635 struct mlx5_ifc_rqtc_bits ctx;
4636 };
4637
4638 struct mlx5_ifc_modify_rq_out_bits {
4639 u8 status[0x8];
4640 u8 reserved_at_8[0x18];
4641
4642 u8 syndrome[0x20];
4643
4644 u8 reserved_at_40[0x40];
4645 };
4646
4647 struct mlx5_ifc_modify_rq_in_bits {
4648 u8 opcode[0x10];
4649 u8 reserved_at_10[0x10];
4650
4651 u8 reserved_at_20[0x10];
4652 u8 op_mod[0x10];
4653
4654 u8 rq_state[0x4];
4655 u8 reserved_at_44[0x4];
4656 u8 rqn[0x18];
4657
4658 u8 reserved_at_60[0x20];
4659
4660 u8 modify_bitmask[0x40];
4661
4662 u8 reserved_at_c0[0x40];
4663
4664 struct mlx5_ifc_rqc_bits ctx;
4665 };
4666
4667 struct mlx5_ifc_modify_rmp_out_bits {
4668 u8 status[0x8];
4669 u8 reserved_at_8[0x18];
4670
4671 u8 syndrome[0x20];
4672
4673 u8 reserved_at_40[0x40];
4674 };
4675
4676 struct mlx5_ifc_rmp_bitmask_bits {
4677 u8 reserved_at_0[0x20];
4678
4679 u8 reserved_at_20[0x1f];
4680 u8 lwm[0x1];
4681 };
4682
4683 struct mlx5_ifc_modify_rmp_in_bits {
4684 u8 opcode[0x10];
4685 u8 reserved_at_10[0x10];
4686
4687 u8 reserved_at_20[0x10];
4688 u8 op_mod[0x10];
4689
4690 u8 rmp_state[0x4];
4691 u8 reserved_at_44[0x4];
4692 u8 rmpn[0x18];
4693
4694 u8 reserved_at_60[0x20];
4695
4696 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4697
4698 u8 reserved_at_c0[0x40];
4699
4700 struct mlx5_ifc_rmpc_bits ctx;
4701 };
4702
4703 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4704 u8 status[0x8];
4705 u8 reserved_at_8[0x18];
4706
4707 u8 syndrome[0x20];
4708
4709 u8 reserved_at_40[0x40];
4710 };
4711
4712 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4713 u8 reserved_at_0[0x16];
4714 u8 node_guid[0x1];
4715 u8 port_guid[0x1];
4716 u8 reserved_at_18[0x1];
4717 u8 mtu[0x1];
4718 u8 change_event[0x1];
4719 u8 promisc[0x1];
4720 u8 permanent_address[0x1];
4721 u8 addresses_list[0x1];
4722 u8 roce_en[0x1];
4723 u8 reserved_at_1f[0x1];
4724 };
4725
4726 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4727 u8 opcode[0x10];
4728 u8 reserved_at_10[0x10];
4729
4730 u8 reserved_at_20[0x10];
4731 u8 op_mod[0x10];
4732
4733 u8 other_vport[0x1];
4734 u8 reserved_at_41[0xf];
4735 u8 vport_number[0x10];
4736
4737 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4738
4739 u8 reserved_at_80[0x780];
4740
4741 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4742 };
4743
4744 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4745 u8 status[0x8];
4746 u8 reserved_at_8[0x18];
4747
4748 u8 syndrome[0x20];
4749
4750 u8 reserved_at_40[0x40];
4751 };
4752
4753 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4754 u8 opcode[0x10];
4755 u8 reserved_at_10[0x10];
4756
4757 u8 reserved_at_20[0x10];
4758 u8 op_mod[0x10];
4759
4760 u8 other_vport[0x1];
4761 u8 reserved_at_41[0xb];
4762 u8 port_num[0x4];
4763 u8 vport_number[0x10];
4764
4765 u8 reserved_at_60[0x20];
4766
4767 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4768 };
4769
4770 struct mlx5_ifc_modify_cq_out_bits {
4771 u8 status[0x8];
4772 u8 reserved_at_8[0x18];
4773
4774 u8 syndrome[0x20];
4775
4776 u8 reserved_at_40[0x40];
4777 };
4778
4779 enum {
4780 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4781 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4782 };
4783
4784 struct mlx5_ifc_modify_cq_in_bits {
4785 u8 opcode[0x10];
4786 u8 reserved_at_10[0x10];
4787
4788 u8 reserved_at_20[0x10];
4789 u8 op_mod[0x10];
4790
4791 u8 reserved_at_40[0x8];
4792 u8 cqn[0x18];
4793
4794 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4795
4796 struct mlx5_ifc_cqc_bits cq_context;
4797
4798 u8 reserved_at_280[0x600];
4799
4800 u8 pas[0][0x40];
4801 };
4802
4803 struct mlx5_ifc_modify_cong_status_out_bits {
4804 u8 status[0x8];
4805 u8 reserved_at_8[0x18];
4806
4807 u8 syndrome[0x20];
4808
4809 u8 reserved_at_40[0x40];
4810 };
4811
4812 struct mlx5_ifc_modify_cong_status_in_bits {
4813 u8 opcode[0x10];
4814 u8 reserved_at_10[0x10];
4815
4816 u8 reserved_at_20[0x10];
4817 u8 op_mod[0x10];
4818
4819 u8 reserved_at_40[0x18];
4820 u8 priority[0x4];
4821 u8 cong_protocol[0x4];
4822
4823 u8 enable[0x1];
4824 u8 tag_enable[0x1];
4825 u8 reserved_at_62[0x1e];
4826 };
4827
4828 struct mlx5_ifc_modify_cong_params_out_bits {
4829 u8 status[0x8];
4830 u8 reserved_at_8[0x18];
4831
4832 u8 syndrome[0x20];
4833
4834 u8 reserved_at_40[0x40];
4835 };
4836
4837 struct mlx5_ifc_modify_cong_params_in_bits {
4838 u8 opcode[0x10];
4839 u8 reserved_at_10[0x10];
4840
4841 u8 reserved_at_20[0x10];
4842 u8 op_mod[0x10];
4843
4844 u8 reserved_at_40[0x1c];
4845 u8 cong_protocol[0x4];
4846
4847 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4848
4849 u8 reserved_at_80[0x80];
4850
4851 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4852 };
4853
4854 struct mlx5_ifc_manage_pages_out_bits {
4855 u8 status[0x8];
4856 u8 reserved_at_8[0x18];
4857
4858 u8 syndrome[0x20];
4859
4860 u8 output_num_entries[0x20];
4861
4862 u8 reserved_at_60[0x20];
4863
4864 u8 pas[0][0x40];
4865 };
4866
4867 enum {
4868 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4869 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4870 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4871 };
4872
4873 struct mlx5_ifc_manage_pages_in_bits {
4874 u8 opcode[0x10];
4875 u8 reserved_at_10[0x10];
4876
4877 u8 reserved_at_20[0x10];
4878 u8 op_mod[0x10];
4879
4880 u8 reserved_at_40[0x10];
4881 u8 function_id[0x10];
4882
4883 u8 input_num_entries[0x20];
4884
4885 u8 pas[0][0x40];
4886 };
4887
4888 struct mlx5_ifc_mad_ifc_out_bits {
4889 u8 status[0x8];
4890 u8 reserved_at_8[0x18];
4891
4892 u8 syndrome[0x20];
4893
4894 u8 reserved_at_40[0x40];
4895
4896 u8 response_mad_packet[256][0x8];
4897 };
4898
4899 struct mlx5_ifc_mad_ifc_in_bits {
4900 u8 opcode[0x10];
4901 u8 reserved_at_10[0x10];
4902
4903 u8 reserved_at_20[0x10];
4904 u8 op_mod[0x10];
4905
4906 u8 remote_lid[0x10];
4907 u8 reserved_at_50[0x8];
4908 u8 port[0x8];
4909
4910 u8 reserved_at_60[0x20];
4911
4912 u8 mad[256][0x8];
4913 };
4914
4915 struct mlx5_ifc_init_hca_out_bits {
4916 u8 status[0x8];
4917 u8 reserved_at_8[0x18];
4918
4919 u8 syndrome[0x20];
4920
4921 u8 reserved_at_40[0x40];
4922 };
4923
4924 struct mlx5_ifc_init_hca_in_bits {
4925 u8 opcode[0x10];
4926 u8 reserved_at_10[0x10];
4927
4928 u8 reserved_at_20[0x10];
4929 u8 op_mod[0x10];
4930
4931 u8 reserved_at_40[0x40];
4932 };
4933
4934 struct mlx5_ifc_init2rtr_qp_out_bits {
4935 u8 status[0x8];
4936 u8 reserved_at_8[0x18];
4937
4938 u8 syndrome[0x20];
4939
4940 u8 reserved_at_40[0x40];
4941 };
4942
4943 struct mlx5_ifc_init2rtr_qp_in_bits {
4944 u8 opcode[0x10];
4945 u8 reserved_at_10[0x10];
4946
4947 u8 reserved_at_20[0x10];
4948 u8 op_mod[0x10];
4949
4950 u8 reserved_at_40[0x8];
4951 u8 qpn[0x18];
4952
4953 u8 reserved_at_60[0x20];
4954
4955 u8 opt_param_mask[0x20];
4956
4957 u8 reserved_at_a0[0x20];
4958
4959 struct mlx5_ifc_qpc_bits qpc;
4960
4961 u8 reserved_at_800[0x80];
4962 };
4963
4964 struct mlx5_ifc_init2init_qp_out_bits {
4965 u8 status[0x8];
4966 u8 reserved_at_8[0x18];
4967
4968 u8 syndrome[0x20];
4969
4970 u8 reserved_at_40[0x40];
4971 };
4972
4973 struct mlx5_ifc_init2init_qp_in_bits {
4974 u8 opcode[0x10];
4975 u8 reserved_at_10[0x10];
4976
4977 u8 reserved_at_20[0x10];
4978 u8 op_mod[0x10];
4979
4980 u8 reserved_at_40[0x8];
4981 u8 qpn[0x18];
4982
4983 u8 reserved_at_60[0x20];
4984
4985 u8 opt_param_mask[0x20];
4986
4987 u8 reserved_at_a0[0x20];
4988
4989 struct mlx5_ifc_qpc_bits qpc;
4990
4991 u8 reserved_at_800[0x80];
4992 };
4993
4994 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4995 u8 status[0x8];
4996 u8 reserved_at_8[0x18];
4997
4998 u8 syndrome[0x20];
4999
5000 u8 reserved_at_40[0x40];
5001
5002 u8 packet_headers_log[128][0x8];
5003
5004 u8 packet_syndrome[64][0x8];
5005 };
5006
5007 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5008 u8 opcode[0x10];
5009 u8 reserved_at_10[0x10];
5010
5011 u8 reserved_at_20[0x10];
5012 u8 op_mod[0x10];
5013
5014 u8 reserved_at_40[0x40];
5015 };
5016
5017 struct mlx5_ifc_gen_eqe_in_bits {
5018 u8 opcode[0x10];
5019 u8 reserved_at_10[0x10];
5020
5021 u8 reserved_at_20[0x10];
5022 u8 op_mod[0x10];
5023
5024 u8 reserved_at_40[0x18];
5025 u8 eq_number[0x8];
5026
5027 u8 reserved_at_60[0x20];
5028
5029 u8 eqe[64][0x8];
5030 };
5031
5032 struct mlx5_ifc_gen_eq_out_bits {
5033 u8 status[0x8];
5034 u8 reserved_at_8[0x18];
5035
5036 u8 syndrome[0x20];
5037
5038 u8 reserved_at_40[0x40];
5039 };
5040
5041 struct mlx5_ifc_enable_hca_out_bits {
5042 u8 status[0x8];
5043 u8 reserved_at_8[0x18];
5044
5045 u8 syndrome[0x20];
5046
5047 u8 reserved_at_40[0x20];
5048 };
5049
5050 struct mlx5_ifc_enable_hca_in_bits {
5051 u8 opcode[0x10];
5052 u8 reserved_at_10[0x10];
5053
5054 u8 reserved_at_20[0x10];
5055 u8 op_mod[0x10];
5056
5057 u8 reserved_at_40[0x10];
5058 u8 function_id[0x10];
5059
5060 u8 reserved_at_60[0x20];
5061 };
5062
5063 struct mlx5_ifc_drain_dct_out_bits {
5064 u8 status[0x8];
5065 u8 reserved_at_8[0x18];
5066
5067 u8 syndrome[0x20];
5068
5069 u8 reserved_at_40[0x40];
5070 };
5071
5072 struct mlx5_ifc_drain_dct_in_bits {
5073 u8 opcode[0x10];
5074 u8 reserved_at_10[0x10];
5075
5076 u8 reserved_at_20[0x10];
5077 u8 op_mod[0x10];
5078
5079 u8 reserved_at_40[0x8];
5080 u8 dctn[0x18];
5081
5082 u8 reserved_at_60[0x20];
5083 };
5084
5085 struct mlx5_ifc_disable_hca_out_bits {
5086 u8 status[0x8];
5087 u8 reserved_at_8[0x18];
5088
5089 u8 syndrome[0x20];
5090
5091 u8 reserved_at_40[0x20];
5092 };
5093
5094 struct mlx5_ifc_disable_hca_in_bits {
5095 u8 opcode[0x10];
5096 u8 reserved_at_10[0x10];
5097
5098 u8 reserved_at_20[0x10];
5099 u8 op_mod[0x10];
5100
5101 u8 reserved_at_40[0x10];
5102 u8 function_id[0x10];
5103
5104 u8 reserved_at_60[0x20];
5105 };
5106
5107 struct mlx5_ifc_detach_from_mcg_out_bits {
5108 u8 status[0x8];
5109 u8 reserved_at_8[0x18];
5110
5111 u8 syndrome[0x20];
5112
5113 u8 reserved_at_40[0x40];
5114 };
5115
5116 struct mlx5_ifc_detach_from_mcg_in_bits {
5117 u8 opcode[0x10];
5118 u8 reserved_at_10[0x10];
5119
5120 u8 reserved_at_20[0x10];
5121 u8 op_mod[0x10];
5122
5123 u8 reserved_at_40[0x8];
5124 u8 qpn[0x18];
5125
5126 u8 reserved_at_60[0x20];
5127
5128 u8 multicast_gid[16][0x8];
5129 };
5130
5131 struct mlx5_ifc_destroy_xrq_out_bits {
5132 u8 status[0x8];
5133 u8 reserved_at_8[0x18];
5134
5135 u8 syndrome[0x20];
5136
5137 u8 reserved_at_40[0x40];
5138 };
5139
5140 struct mlx5_ifc_destroy_xrq_in_bits {
5141 u8 opcode[0x10];
5142 u8 reserved_at_10[0x10];
5143
5144 u8 reserved_at_20[0x10];
5145 u8 op_mod[0x10];
5146
5147 u8 reserved_at_40[0x8];
5148 u8 xrqn[0x18];
5149
5150 u8 reserved_at_60[0x20];
5151 };
5152
5153 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5154 u8 status[0x8];
5155 u8 reserved_at_8[0x18];
5156
5157 u8 syndrome[0x20];
5158
5159 u8 reserved_at_40[0x40];
5160 };
5161
5162 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5163 u8 opcode[0x10];
5164 u8 reserved_at_10[0x10];
5165
5166 u8 reserved_at_20[0x10];
5167 u8 op_mod[0x10];
5168
5169 u8 reserved_at_40[0x8];
5170 u8 xrc_srqn[0x18];
5171
5172 u8 reserved_at_60[0x20];
5173 };
5174
5175 struct mlx5_ifc_destroy_tis_out_bits {
5176 u8 status[0x8];
5177 u8 reserved_at_8[0x18];
5178
5179 u8 syndrome[0x20];
5180
5181 u8 reserved_at_40[0x40];
5182 };
5183
5184 struct mlx5_ifc_destroy_tis_in_bits {
5185 u8 opcode[0x10];
5186 u8 reserved_at_10[0x10];
5187
5188 u8 reserved_at_20[0x10];
5189 u8 op_mod[0x10];
5190
5191 u8 reserved_at_40[0x8];
5192 u8 tisn[0x18];
5193
5194 u8 reserved_at_60[0x20];
5195 };
5196
5197 struct mlx5_ifc_destroy_tir_out_bits {
5198 u8 status[0x8];
5199 u8 reserved_at_8[0x18];
5200
5201 u8 syndrome[0x20];
5202
5203 u8 reserved_at_40[0x40];
5204 };
5205
5206 struct mlx5_ifc_destroy_tir_in_bits {
5207 u8 opcode[0x10];
5208 u8 reserved_at_10[0x10];
5209
5210 u8 reserved_at_20[0x10];
5211 u8 op_mod[0x10];
5212
5213 u8 reserved_at_40[0x8];
5214 u8 tirn[0x18];
5215
5216 u8 reserved_at_60[0x20];
5217 };
5218
5219 struct mlx5_ifc_destroy_srq_out_bits {
5220 u8 status[0x8];
5221 u8 reserved_at_8[0x18];
5222
5223 u8 syndrome[0x20];
5224
5225 u8 reserved_at_40[0x40];
5226 };
5227
5228 struct mlx5_ifc_destroy_srq_in_bits {
5229 u8 opcode[0x10];
5230 u8 reserved_at_10[0x10];
5231
5232 u8 reserved_at_20[0x10];
5233 u8 op_mod[0x10];
5234
5235 u8 reserved_at_40[0x8];
5236 u8 srqn[0x18];
5237
5238 u8 reserved_at_60[0x20];
5239 };
5240
5241 struct mlx5_ifc_destroy_sq_out_bits {
5242 u8 status[0x8];
5243 u8 reserved_at_8[0x18];
5244
5245 u8 syndrome[0x20];
5246
5247 u8 reserved_at_40[0x40];
5248 };
5249
5250 struct mlx5_ifc_destroy_sq_in_bits {
5251 u8 opcode[0x10];
5252 u8 reserved_at_10[0x10];
5253
5254 u8 reserved_at_20[0x10];
5255 u8 op_mod[0x10];
5256
5257 u8 reserved_at_40[0x8];
5258 u8 sqn[0x18];
5259
5260 u8 reserved_at_60[0x20];
5261 };
5262
5263 struct mlx5_ifc_destroy_rqt_out_bits {
5264 u8 status[0x8];
5265 u8 reserved_at_8[0x18];
5266
5267 u8 syndrome[0x20];
5268
5269 u8 reserved_at_40[0x40];
5270 };
5271
5272 struct mlx5_ifc_destroy_rqt_in_bits {
5273 u8 opcode[0x10];
5274 u8 reserved_at_10[0x10];
5275
5276 u8 reserved_at_20[0x10];
5277 u8 op_mod[0x10];
5278
5279 u8 reserved_at_40[0x8];
5280 u8 rqtn[0x18];
5281
5282 u8 reserved_at_60[0x20];
5283 };
5284
5285 struct mlx5_ifc_destroy_rq_out_bits {
5286 u8 status[0x8];
5287 u8 reserved_at_8[0x18];
5288
5289 u8 syndrome[0x20];
5290
5291 u8 reserved_at_40[0x40];
5292 };
5293
5294 struct mlx5_ifc_destroy_rq_in_bits {
5295 u8 opcode[0x10];
5296 u8 reserved_at_10[0x10];
5297
5298 u8 reserved_at_20[0x10];
5299 u8 op_mod[0x10];
5300
5301 u8 reserved_at_40[0x8];
5302 u8 rqn[0x18];
5303
5304 u8 reserved_at_60[0x20];
5305 };
5306
5307 struct mlx5_ifc_destroy_rmp_out_bits {
5308 u8 status[0x8];
5309 u8 reserved_at_8[0x18];
5310
5311 u8 syndrome[0x20];
5312
5313 u8 reserved_at_40[0x40];
5314 };
5315
5316 struct mlx5_ifc_destroy_rmp_in_bits {
5317 u8 opcode[0x10];
5318 u8 reserved_at_10[0x10];
5319
5320 u8 reserved_at_20[0x10];
5321 u8 op_mod[0x10];
5322
5323 u8 reserved_at_40[0x8];
5324 u8 rmpn[0x18];
5325
5326 u8 reserved_at_60[0x20];
5327 };
5328
5329 struct mlx5_ifc_destroy_qp_out_bits {
5330 u8 status[0x8];
5331 u8 reserved_at_8[0x18];
5332
5333 u8 syndrome[0x20];
5334
5335 u8 reserved_at_40[0x40];
5336 };
5337
5338 struct mlx5_ifc_destroy_qp_in_bits {
5339 u8 opcode[0x10];
5340 u8 reserved_at_10[0x10];
5341
5342 u8 reserved_at_20[0x10];
5343 u8 op_mod[0x10];
5344
5345 u8 reserved_at_40[0x8];
5346 u8 qpn[0x18];
5347
5348 u8 reserved_at_60[0x20];
5349 };
5350
5351 struct mlx5_ifc_destroy_psv_out_bits {
5352 u8 status[0x8];
5353 u8 reserved_at_8[0x18];
5354
5355 u8 syndrome[0x20];
5356
5357 u8 reserved_at_40[0x40];
5358 };
5359
5360 struct mlx5_ifc_destroy_psv_in_bits {
5361 u8 opcode[0x10];
5362 u8 reserved_at_10[0x10];
5363
5364 u8 reserved_at_20[0x10];
5365 u8 op_mod[0x10];
5366
5367 u8 reserved_at_40[0x8];
5368 u8 psvn[0x18];
5369
5370 u8 reserved_at_60[0x20];
5371 };
5372
5373 struct mlx5_ifc_destroy_mkey_out_bits {
5374 u8 status[0x8];
5375 u8 reserved_at_8[0x18];
5376
5377 u8 syndrome[0x20];
5378
5379 u8 reserved_at_40[0x40];
5380 };
5381
5382 struct mlx5_ifc_destroy_mkey_in_bits {
5383 u8 opcode[0x10];
5384 u8 reserved_at_10[0x10];
5385
5386 u8 reserved_at_20[0x10];
5387 u8 op_mod[0x10];
5388
5389 u8 reserved_at_40[0x8];
5390 u8 mkey_index[0x18];
5391
5392 u8 reserved_at_60[0x20];
5393 };
5394
5395 struct mlx5_ifc_destroy_flow_table_out_bits {
5396 u8 status[0x8];
5397 u8 reserved_at_8[0x18];
5398
5399 u8 syndrome[0x20];
5400
5401 u8 reserved_at_40[0x40];
5402 };
5403
5404 struct mlx5_ifc_destroy_flow_table_in_bits {
5405 u8 opcode[0x10];
5406 u8 reserved_at_10[0x10];
5407
5408 u8 reserved_at_20[0x10];
5409 u8 op_mod[0x10];
5410
5411 u8 other_vport[0x1];
5412 u8 reserved_at_41[0xf];
5413 u8 vport_number[0x10];
5414
5415 u8 reserved_at_60[0x20];
5416
5417 u8 table_type[0x8];
5418 u8 reserved_at_88[0x18];
5419
5420 u8 reserved_at_a0[0x8];
5421 u8 table_id[0x18];
5422
5423 u8 reserved_at_c0[0x140];
5424 };
5425
5426 struct mlx5_ifc_destroy_flow_group_out_bits {
5427 u8 status[0x8];
5428 u8 reserved_at_8[0x18];
5429
5430 u8 syndrome[0x20];
5431
5432 u8 reserved_at_40[0x40];
5433 };
5434
5435 struct mlx5_ifc_destroy_flow_group_in_bits {
5436 u8 opcode[0x10];
5437 u8 reserved_at_10[0x10];
5438
5439 u8 reserved_at_20[0x10];
5440 u8 op_mod[0x10];
5441
5442 u8 other_vport[0x1];
5443 u8 reserved_at_41[0xf];
5444 u8 vport_number[0x10];
5445
5446 u8 reserved_at_60[0x20];
5447
5448 u8 table_type[0x8];
5449 u8 reserved_at_88[0x18];
5450
5451 u8 reserved_at_a0[0x8];
5452 u8 table_id[0x18];
5453
5454 u8 group_id[0x20];
5455
5456 u8 reserved_at_e0[0x120];
5457 };
5458
5459 struct mlx5_ifc_destroy_eq_out_bits {
5460 u8 status[0x8];
5461 u8 reserved_at_8[0x18];
5462
5463 u8 syndrome[0x20];
5464
5465 u8 reserved_at_40[0x40];
5466 };
5467
5468 struct mlx5_ifc_destroy_eq_in_bits {
5469 u8 opcode[0x10];
5470 u8 reserved_at_10[0x10];
5471
5472 u8 reserved_at_20[0x10];
5473 u8 op_mod[0x10];
5474
5475 u8 reserved_at_40[0x18];
5476 u8 eq_number[0x8];
5477
5478 u8 reserved_at_60[0x20];
5479 };
5480
5481 struct mlx5_ifc_destroy_dct_out_bits {
5482 u8 status[0x8];
5483 u8 reserved_at_8[0x18];
5484
5485 u8 syndrome[0x20];
5486
5487 u8 reserved_at_40[0x40];
5488 };
5489
5490 struct mlx5_ifc_destroy_dct_in_bits {
5491 u8 opcode[0x10];
5492 u8 reserved_at_10[0x10];
5493
5494 u8 reserved_at_20[0x10];
5495 u8 op_mod[0x10];
5496
5497 u8 reserved_at_40[0x8];
5498 u8 dctn[0x18];
5499
5500 u8 reserved_at_60[0x20];
5501 };
5502
5503 struct mlx5_ifc_destroy_cq_out_bits {
5504 u8 status[0x8];
5505 u8 reserved_at_8[0x18];
5506
5507 u8 syndrome[0x20];
5508
5509 u8 reserved_at_40[0x40];
5510 };
5511
5512 struct mlx5_ifc_destroy_cq_in_bits {
5513 u8 opcode[0x10];
5514 u8 reserved_at_10[0x10];
5515
5516 u8 reserved_at_20[0x10];
5517 u8 op_mod[0x10];
5518
5519 u8 reserved_at_40[0x8];
5520 u8 cqn[0x18];
5521
5522 u8 reserved_at_60[0x20];
5523 };
5524
5525 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5526 u8 status[0x8];
5527 u8 reserved_at_8[0x18];
5528
5529 u8 syndrome[0x20];
5530
5531 u8 reserved_at_40[0x40];
5532 };
5533
5534 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5535 u8 opcode[0x10];
5536 u8 reserved_at_10[0x10];
5537
5538 u8 reserved_at_20[0x10];
5539 u8 op_mod[0x10];
5540
5541 u8 reserved_at_40[0x20];
5542
5543 u8 reserved_at_60[0x10];
5544 u8 vxlan_udp_port[0x10];
5545 };
5546
5547 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5548 u8 status[0x8];
5549 u8 reserved_at_8[0x18];
5550
5551 u8 syndrome[0x20];
5552
5553 u8 reserved_at_40[0x40];
5554 };
5555
5556 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5557 u8 opcode[0x10];
5558 u8 reserved_at_10[0x10];
5559
5560 u8 reserved_at_20[0x10];
5561 u8 op_mod[0x10];
5562
5563 u8 reserved_at_40[0x60];
5564
5565 u8 reserved_at_a0[0x8];
5566 u8 table_index[0x18];
5567
5568 u8 reserved_at_c0[0x140];
5569 };
5570
5571 struct mlx5_ifc_delete_fte_out_bits {
5572 u8 status[0x8];
5573 u8 reserved_at_8[0x18];
5574
5575 u8 syndrome[0x20];
5576
5577 u8 reserved_at_40[0x40];
5578 };
5579
5580 struct mlx5_ifc_delete_fte_in_bits {
5581 u8 opcode[0x10];
5582 u8 reserved_at_10[0x10];
5583
5584 u8 reserved_at_20[0x10];
5585 u8 op_mod[0x10];
5586
5587 u8 other_vport[0x1];
5588 u8 reserved_at_41[0xf];
5589 u8 vport_number[0x10];
5590
5591 u8 reserved_at_60[0x20];
5592
5593 u8 table_type[0x8];
5594 u8 reserved_at_88[0x18];
5595
5596 u8 reserved_at_a0[0x8];
5597 u8 table_id[0x18];
5598
5599 u8 reserved_at_c0[0x40];
5600
5601 u8 flow_index[0x20];
5602
5603 u8 reserved_at_120[0xe0];
5604 };
5605
5606 struct mlx5_ifc_dealloc_xrcd_out_bits {
5607 u8 status[0x8];
5608 u8 reserved_at_8[0x18];
5609
5610 u8 syndrome[0x20];
5611
5612 u8 reserved_at_40[0x40];
5613 };
5614
5615 struct mlx5_ifc_dealloc_xrcd_in_bits {
5616 u8 opcode[0x10];
5617 u8 reserved_at_10[0x10];
5618
5619 u8 reserved_at_20[0x10];
5620 u8 op_mod[0x10];
5621
5622 u8 reserved_at_40[0x8];
5623 u8 xrcd[0x18];
5624
5625 u8 reserved_at_60[0x20];
5626 };
5627
5628 struct mlx5_ifc_dealloc_uar_out_bits {
5629 u8 status[0x8];
5630 u8 reserved_at_8[0x18];
5631
5632 u8 syndrome[0x20];
5633
5634 u8 reserved_at_40[0x40];
5635 };
5636
5637 struct mlx5_ifc_dealloc_uar_in_bits {
5638 u8 opcode[0x10];
5639 u8 reserved_at_10[0x10];
5640
5641 u8 reserved_at_20[0x10];
5642 u8 op_mod[0x10];
5643
5644 u8 reserved_at_40[0x8];
5645 u8 uar[0x18];
5646
5647 u8 reserved_at_60[0x20];
5648 };
5649
5650 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5651 u8 status[0x8];
5652 u8 reserved_at_8[0x18];
5653
5654 u8 syndrome[0x20];
5655
5656 u8 reserved_at_40[0x40];
5657 };
5658
5659 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5660 u8 opcode[0x10];
5661 u8 reserved_at_10[0x10];
5662
5663 u8 reserved_at_20[0x10];
5664 u8 op_mod[0x10];
5665
5666 u8 reserved_at_40[0x8];
5667 u8 transport_domain[0x18];
5668
5669 u8 reserved_at_60[0x20];
5670 };
5671
5672 struct mlx5_ifc_dealloc_q_counter_out_bits {
5673 u8 status[0x8];
5674 u8 reserved_at_8[0x18];
5675
5676 u8 syndrome[0x20];
5677
5678 u8 reserved_at_40[0x40];
5679 };
5680
5681 struct mlx5_ifc_dealloc_q_counter_in_bits {
5682 u8 opcode[0x10];
5683 u8 reserved_at_10[0x10];
5684
5685 u8 reserved_at_20[0x10];
5686 u8 op_mod[0x10];
5687
5688 u8 reserved_at_40[0x18];
5689 u8 counter_set_id[0x8];
5690
5691 u8 reserved_at_60[0x20];
5692 };
5693
5694 struct mlx5_ifc_dealloc_pd_out_bits {
5695 u8 status[0x8];
5696 u8 reserved_at_8[0x18];
5697
5698 u8 syndrome[0x20];
5699
5700 u8 reserved_at_40[0x40];
5701 };
5702
5703 struct mlx5_ifc_dealloc_pd_in_bits {
5704 u8 opcode[0x10];
5705 u8 reserved_at_10[0x10];
5706
5707 u8 reserved_at_20[0x10];
5708 u8 op_mod[0x10];
5709
5710 u8 reserved_at_40[0x8];
5711 u8 pd[0x18];
5712
5713 u8 reserved_at_60[0x20];
5714 };
5715
5716 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5717 u8 status[0x8];
5718 u8 reserved_at_8[0x18];
5719
5720 u8 syndrome[0x20];
5721
5722 u8 reserved_at_40[0x40];
5723 };
5724
5725 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5726 u8 opcode[0x10];
5727 u8 reserved_at_10[0x10];
5728
5729 u8 reserved_at_20[0x10];
5730 u8 op_mod[0x10];
5731
5732 u8 reserved_at_40[0x10];
5733 u8 flow_counter_id[0x10];
5734
5735 u8 reserved_at_60[0x20];
5736 };
5737
5738 struct mlx5_ifc_create_xrq_out_bits {
5739 u8 status[0x8];
5740 u8 reserved_at_8[0x18];
5741
5742 u8 syndrome[0x20];
5743
5744 u8 reserved_at_40[0x8];
5745 u8 xrqn[0x18];
5746
5747 u8 reserved_at_60[0x20];
5748 };
5749
5750 struct mlx5_ifc_create_xrq_in_bits {
5751 u8 opcode[0x10];
5752 u8 reserved_at_10[0x10];
5753
5754 u8 reserved_at_20[0x10];
5755 u8 op_mod[0x10];
5756
5757 u8 reserved_at_40[0x40];
5758
5759 struct mlx5_ifc_xrqc_bits xrq_context;
5760 };
5761
5762 struct mlx5_ifc_create_xrc_srq_out_bits {
5763 u8 status[0x8];
5764 u8 reserved_at_8[0x18];
5765
5766 u8 syndrome[0x20];
5767
5768 u8 reserved_at_40[0x8];
5769 u8 xrc_srqn[0x18];
5770
5771 u8 reserved_at_60[0x20];
5772 };
5773
5774 struct mlx5_ifc_create_xrc_srq_in_bits {
5775 u8 opcode[0x10];
5776 u8 reserved_at_10[0x10];
5777
5778 u8 reserved_at_20[0x10];
5779 u8 op_mod[0x10];
5780
5781 u8 reserved_at_40[0x40];
5782
5783 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5784
5785 u8 reserved_at_280[0x600];
5786
5787 u8 pas[0][0x40];
5788 };
5789
5790 struct mlx5_ifc_create_tis_out_bits {
5791 u8 status[0x8];
5792 u8 reserved_at_8[0x18];
5793
5794 u8 syndrome[0x20];
5795
5796 u8 reserved_at_40[0x8];
5797 u8 tisn[0x18];
5798
5799 u8 reserved_at_60[0x20];
5800 };
5801
5802 struct mlx5_ifc_create_tis_in_bits {
5803 u8 opcode[0x10];
5804 u8 reserved_at_10[0x10];
5805
5806 u8 reserved_at_20[0x10];
5807 u8 op_mod[0x10];
5808
5809 u8 reserved_at_40[0xc0];
5810
5811 struct mlx5_ifc_tisc_bits ctx;
5812 };
5813
5814 struct mlx5_ifc_create_tir_out_bits {
5815 u8 status[0x8];
5816 u8 reserved_at_8[0x18];
5817
5818 u8 syndrome[0x20];
5819
5820 u8 reserved_at_40[0x8];
5821 u8 tirn[0x18];
5822
5823 u8 reserved_at_60[0x20];
5824 };
5825
5826 struct mlx5_ifc_create_tir_in_bits {
5827 u8 opcode[0x10];
5828 u8 reserved_at_10[0x10];
5829
5830 u8 reserved_at_20[0x10];
5831 u8 op_mod[0x10];
5832
5833 u8 reserved_at_40[0xc0];
5834
5835 struct mlx5_ifc_tirc_bits ctx;
5836 };
5837
5838 struct mlx5_ifc_create_srq_out_bits {
5839 u8 status[0x8];
5840 u8 reserved_at_8[0x18];
5841
5842 u8 syndrome[0x20];
5843
5844 u8 reserved_at_40[0x8];
5845 u8 srqn[0x18];
5846
5847 u8 reserved_at_60[0x20];
5848 };
5849
5850 struct mlx5_ifc_create_srq_in_bits {
5851 u8 opcode[0x10];
5852 u8 reserved_at_10[0x10];
5853
5854 u8 reserved_at_20[0x10];
5855 u8 op_mod[0x10];
5856
5857 u8 reserved_at_40[0x40];
5858
5859 struct mlx5_ifc_srqc_bits srq_context_entry;
5860
5861 u8 reserved_at_280[0x600];
5862
5863 u8 pas[0][0x40];
5864 };
5865
5866 struct mlx5_ifc_create_sq_out_bits {
5867 u8 status[0x8];
5868 u8 reserved_at_8[0x18];
5869
5870 u8 syndrome[0x20];
5871
5872 u8 reserved_at_40[0x8];
5873 u8 sqn[0x18];
5874
5875 u8 reserved_at_60[0x20];
5876 };
5877
5878 struct mlx5_ifc_create_sq_in_bits {
5879 u8 opcode[0x10];
5880 u8 reserved_at_10[0x10];
5881
5882 u8 reserved_at_20[0x10];
5883 u8 op_mod[0x10];
5884
5885 u8 reserved_at_40[0xc0];
5886
5887 struct mlx5_ifc_sqc_bits ctx;
5888 };
5889
5890 struct mlx5_ifc_create_rqt_out_bits {
5891 u8 status[0x8];
5892 u8 reserved_at_8[0x18];
5893
5894 u8 syndrome[0x20];
5895
5896 u8 reserved_at_40[0x8];
5897 u8 rqtn[0x18];
5898
5899 u8 reserved_at_60[0x20];
5900 };
5901
5902 struct mlx5_ifc_create_rqt_in_bits {
5903 u8 opcode[0x10];
5904 u8 reserved_at_10[0x10];
5905
5906 u8 reserved_at_20[0x10];
5907 u8 op_mod[0x10];
5908
5909 u8 reserved_at_40[0xc0];
5910
5911 struct mlx5_ifc_rqtc_bits rqt_context;
5912 };
5913
5914 struct mlx5_ifc_create_rq_out_bits {
5915 u8 status[0x8];
5916 u8 reserved_at_8[0x18];
5917
5918 u8 syndrome[0x20];
5919
5920 u8 reserved_at_40[0x8];
5921 u8 rqn[0x18];
5922
5923 u8 reserved_at_60[0x20];
5924 };
5925
5926 struct mlx5_ifc_create_rq_in_bits {
5927 u8 opcode[0x10];
5928 u8 reserved_at_10[0x10];
5929
5930 u8 reserved_at_20[0x10];
5931 u8 op_mod[0x10];
5932
5933 u8 reserved_at_40[0xc0];
5934
5935 struct mlx5_ifc_rqc_bits ctx;
5936 };
5937
5938 struct mlx5_ifc_create_rmp_out_bits {
5939 u8 status[0x8];
5940 u8 reserved_at_8[0x18];
5941
5942 u8 syndrome[0x20];
5943
5944 u8 reserved_at_40[0x8];
5945 u8 rmpn[0x18];
5946
5947 u8 reserved_at_60[0x20];
5948 };
5949
5950 struct mlx5_ifc_create_rmp_in_bits {
5951 u8 opcode[0x10];
5952 u8 reserved_at_10[0x10];
5953
5954 u8 reserved_at_20[0x10];
5955 u8 op_mod[0x10];
5956
5957 u8 reserved_at_40[0xc0];
5958
5959 struct mlx5_ifc_rmpc_bits ctx;
5960 };
5961
5962 struct mlx5_ifc_create_qp_out_bits {
5963 u8 status[0x8];
5964 u8 reserved_at_8[0x18];
5965
5966 u8 syndrome[0x20];
5967
5968 u8 reserved_at_40[0x8];
5969 u8 qpn[0x18];
5970
5971 u8 reserved_at_60[0x20];
5972 };
5973
5974 struct mlx5_ifc_create_qp_in_bits {
5975 u8 opcode[0x10];
5976 u8 reserved_at_10[0x10];
5977
5978 u8 reserved_at_20[0x10];
5979 u8 op_mod[0x10];
5980
5981 u8 reserved_at_40[0x40];
5982
5983 u8 opt_param_mask[0x20];
5984
5985 u8 reserved_at_a0[0x20];
5986
5987 struct mlx5_ifc_qpc_bits qpc;
5988
5989 u8 reserved_at_800[0x80];
5990
5991 u8 pas[0][0x40];
5992 };
5993
5994 struct mlx5_ifc_create_psv_out_bits {
5995 u8 status[0x8];
5996 u8 reserved_at_8[0x18];
5997
5998 u8 syndrome[0x20];
5999
6000 u8 reserved_at_40[0x40];
6001
6002 u8 reserved_at_80[0x8];
6003 u8 psv0_index[0x18];
6004
6005 u8 reserved_at_a0[0x8];
6006 u8 psv1_index[0x18];
6007
6008 u8 reserved_at_c0[0x8];
6009 u8 psv2_index[0x18];
6010
6011 u8 reserved_at_e0[0x8];
6012 u8 psv3_index[0x18];
6013 };
6014
6015 struct mlx5_ifc_create_psv_in_bits {
6016 u8 opcode[0x10];
6017 u8 reserved_at_10[0x10];
6018
6019 u8 reserved_at_20[0x10];
6020 u8 op_mod[0x10];
6021
6022 u8 num_psv[0x4];
6023 u8 reserved_at_44[0x4];
6024 u8 pd[0x18];
6025
6026 u8 reserved_at_60[0x20];
6027 };
6028
6029 struct mlx5_ifc_create_mkey_out_bits {
6030 u8 status[0x8];
6031 u8 reserved_at_8[0x18];
6032
6033 u8 syndrome[0x20];
6034
6035 u8 reserved_at_40[0x8];
6036 u8 mkey_index[0x18];
6037
6038 u8 reserved_at_60[0x20];
6039 };
6040
6041 struct mlx5_ifc_create_mkey_in_bits {
6042 u8 opcode[0x10];
6043 u8 reserved_at_10[0x10];
6044
6045 u8 reserved_at_20[0x10];
6046 u8 op_mod[0x10];
6047
6048 u8 reserved_at_40[0x20];
6049
6050 u8 pg_access[0x1];
6051 u8 reserved_at_61[0x1f];
6052
6053 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6054
6055 u8 reserved_at_280[0x80];
6056
6057 u8 translations_octword_actual_size[0x20];
6058
6059 u8 reserved_at_320[0x560];
6060
6061 u8 klm_pas_mtt[0][0x20];
6062 };
6063
6064 struct mlx5_ifc_create_flow_table_out_bits {
6065 u8 status[0x8];
6066 u8 reserved_at_8[0x18];
6067
6068 u8 syndrome[0x20];
6069
6070 u8 reserved_at_40[0x8];
6071 u8 table_id[0x18];
6072
6073 u8 reserved_at_60[0x20];
6074 };
6075
6076 struct mlx5_ifc_create_flow_table_in_bits {
6077 u8 opcode[0x10];
6078 u8 reserved_at_10[0x10];
6079
6080 u8 reserved_at_20[0x10];
6081 u8 op_mod[0x10];
6082
6083 u8 other_vport[0x1];
6084 u8 reserved_at_41[0xf];
6085 u8 vport_number[0x10];
6086
6087 u8 reserved_at_60[0x20];
6088
6089 u8 table_type[0x8];
6090 u8 reserved_at_88[0x18];
6091
6092 u8 reserved_at_a0[0x20];
6093
6094 u8 reserved_at_c0[0x4];
6095 u8 table_miss_mode[0x4];
6096 u8 level[0x8];
6097 u8 reserved_at_d0[0x8];
6098 u8 log_size[0x8];
6099
6100 u8 reserved_at_e0[0x8];
6101 u8 table_miss_id[0x18];
6102
6103 u8 reserved_at_100[0x100];
6104 };
6105
6106 struct mlx5_ifc_create_flow_group_out_bits {
6107 u8 status[0x8];
6108 u8 reserved_at_8[0x18];
6109
6110 u8 syndrome[0x20];
6111
6112 u8 reserved_at_40[0x8];
6113 u8 group_id[0x18];
6114
6115 u8 reserved_at_60[0x20];
6116 };
6117
6118 enum {
6119 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6120 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6121 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6122 };
6123
6124 struct mlx5_ifc_create_flow_group_in_bits {
6125 u8 opcode[0x10];
6126 u8 reserved_at_10[0x10];
6127
6128 u8 reserved_at_20[0x10];
6129 u8 op_mod[0x10];
6130
6131 u8 other_vport[0x1];
6132 u8 reserved_at_41[0xf];
6133 u8 vport_number[0x10];
6134
6135 u8 reserved_at_60[0x20];
6136
6137 u8 table_type[0x8];
6138 u8 reserved_at_88[0x18];
6139
6140 u8 reserved_at_a0[0x8];
6141 u8 table_id[0x18];
6142
6143 u8 reserved_at_c0[0x20];
6144
6145 u8 start_flow_index[0x20];
6146
6147 u8 reserved_at_100[0x20];
6148
6149 u8 end_flow_index[0x20];
6150
6151 u8 reserved_at_140[0xa0];
6152
6153 u8 reserved_at_1e0[0x18];
6154 u8 match_criteria_enable[0x8];
6155
6156 struct mlx5_ifc_fte_match_param_bits match_criteria;
6157
6158 u8 reserved_at_1200[0xe00];
6159 };
6160
6161 struct mlx5_ifc_create_eq_out_bits {
6162 u8 status[0x8];
6163 u8 reserved_at_8[0x18];
6164
6165 u8 syndrome[0x20];
6166
6167 u8 reserved_at_40[0x18];
6168 u8 eq_number[0x8];
6169
6170 u8 reserved_at_60[0x20];
6171 };
6172
6173 struct mlx5_ifc_create_eq_in_bits {
6174 u8 opcode[0x10];
6175 u8 reserved_at_10[0x10];
6176
6177 u8 reserved_at_20[0x10];
6178 u8 op_mod[0x10];
6179
6180 u8 reserved_at_40[0x40];
6181
6182 struct mlx5_ifc_eqc_bits eq_context_entry;
6183
6184 u8 reserved_at_280[0x40];
6185
6186 u8 event_bitmask[0x40];
6187
6188 u8 reserved_at_300[0x580];
6189
6190 u8 pas[0][0x40];
6191 };
6192
6193 struct mlx5_ifc_create_dct_out_bits {
6194 u8 status[0x8];
6195 u8 reserved_at_8[0x18];
6196
6197 u8 syndrome[0x20];
6198
6199 u8 reserved_at_40[0x8];
6200 u8 dctn[0x18];
6201
6202 u8 reserved_at_60[0x20];
6203 };
6204
6205 struct mlx5_ifc_create_dct_in_bits {
6206 u8 opcode[0x10];
6207 u8 reserved_at_10[0x10];
6208
6209 u8 reserved_at_20[0x10];
6210 u8 op_mod[0x10];
6211
6212 u8 reserved_at_40[0x40];
6213
6214 struct mlx5_ifc_dctc_bits dct_context_entry;
6215
6216 u8 reserved_at_280[0x180];
6217 };
6218
6219 struct mlx5_ifc_create_cq_out_bits {
6220 u8 status[0x8];
6221 u8 reserved_at_8[0x18];
6222
6223 u8 syndrome[0x20];
6224
6225 u8 reserved_at_40[0x8];
6226 u8 cqn[0x18];
6227
6228 u8 reserved_at_60[0x20];
6229 };
6230
6231 struct mlx5_ifc_create_cq_in_bits {
6232 u8 opcode[0x10];
6233 u8 reserved_at_10[0x10];
6234
6235 u8 reserved_at_20[0x10];
6236 u8 op_mod[0x10];
6237
6238 u8 reserved_at_40[0x40];
6239
6240 struct mlx5_ifc_cqc_bits cq_context;
6241
6242 u8 reserved_at_280[0x600];
6243
6244 u8 pas[0][0x40];
6245 };
6246
6247 struct mlx5_ifc_config_int_moderation_out_bits {
6248 u8 status[0x8];
6249 u8 reserved_at_8[0x18];
6250
6251 u8 syndrome[0x20];
6252
6253 u8 reserved_at_40[0x4];
6254 u8 min_delay[0xc];
6255 u8 int_vector[0x10];
6256
6257 u8 reserved_at_60[0x20];
6258 };
6259
6260 enum {
6261 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6262 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6263 };
6264
6265 struct mlx5_ifc_config_int_moderation_in_bits {
6266 u8 opcode[0x10];
6267 u8 reserved_at_10[0x10];
6268
6269 u8 reserved_at_20[0x10];
6270 u8 op_mod[0x10];
6271
6272 u8 reserved_at_40[0x4];
6273 u8 min_delay[0xc];
6274 u8 int_vector[0x10];
6275
6276 u8 reserved_at_60[0x20];
6277 };
6278
6279 struct mlx5_ifc_attach_to_mcg_out_bits {
6280 u8 status[0x8];
6281 u8 reserved_at_8[0x18];
6282
6283 u8 syndrome[0x20];
6284
6285 u8 reserved_at_40[0x40];
6286 };
6287
6288 struct mlx5_ifc_attach_to_mcg_in_bits {
6289 u8 opcode[0x10];
6290 u8 reserved_at_10[0x10];
6291
6292 u8 reserved_at_20[0x10];
6293 u8 op_mod[0x10];
6294
6295 u8 reserved_at_40[0x8];
6296 u8 qpn[0x18];
6297
6298 u8 reserved_at_60[0x20];
6299
6300 u8 multicast_gid[16][0x8];
6301 };
6302
6303 struct mlx5_ifc_arm_xrq_out_bits {
6304 u8 status[0x8];
6305 u8 reserved_at_8[0x18];
6306
6307 u8 syndrome[0x20];
6308
6309 u8 reserved_at_40[0x40];
6310 };
6311
6312 struct mlx5_ifc_arm_xrq_in_bits {
6313 u8 opcode[0x10];
6314 u8 reserved_at_10[0x10];
6315
6316 u8 reserved_at_20[0x10];
6317 u8 op_mod[0x10];
6318
6319 u8 reserved_at_40[0x8];
6320 u8 xrqn[0x18];
6321
6322 u8 reserved_at_60[0x10];
6323 u8 lwm[0x10];
6324 };
6325
6326 struct mlx5_ifc_arm_xrc_srq_out_bits {
6327 u8 status[0x8];
6328 u8 reserved_at_8[0x18];
6329
6330 u8 syndrome[0x20];
6331
6332 u8 reserved_at_40[0x40];
6333 };
6334
6335 enum {
6336 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6337 };
6338
6339 struct mlx5_ifc_arm_xrc_srq_in_bits {
6340 u8 opcode[0x10];
6341 u8 reserved_at_10[0x10];
6342
6343 u8 reserved_at_20[0x10];
6344 u8 op_mod[0x10];
6345
6346 u8 reserved_at_40[0x8];
6347 u8 xrc_srqn[0x18];
6348
6349 u8 reserved_at_60[0x10];
6350 u8 lwm[0x10];
6351 };
6352
6353 struct mlx5_ifc_arm_rq_out_bits {
6354 u8 status[0x8];
6355 u8 reserved_at_8[0x18];
6356
6357 u8 syndrome[0x20];
6358
6359 u8 reserved_at_40[0x40];
6360 };
6361
6362 enum {
6363 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6364 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6365 };
6366
6367 struct mlx5_ifc_arm_rq_in_bits {
6368 u8 opcode[0x10];
6369 u8 reserved_at_10[0x10];
6370
6371 u8 reserved_at_20[0x10];
6372 u8 op_mod[0x10];
6373
6374 u8 reserved_at_40[0x8];
6375 u8 srq_number[0x18];
6376
6377 u8 reserved_at_60[0x10];
6378 u8 lwm[0x10];
6379 };
6380
6381 struct mlx5_ifc_arm_dct_out_bits {
6382 u8 status[0x8];
6383 u8 reserved_at_8[0x18];
6384
6385 u8 syndrome[0x20];
6386
6387 u8 reserved_at_40[0x40];
6388 };
6389
6390 struct mlx5_ifc_arm_dct_in_bits {
6391 u8 opcode[0x10];
6392 u8 reserved_at_10[0x10];
6393
6394 u8 reserved_at_20[0x10];
6395 u8 op_mod[0x10];
6396
6397 u8 reserved_at_40[0x8];
6398 u8 dct_number[0x18];
6399
6400 u8 reserved_at_60[0x20];
6401 };
6402
6403 struct mlx5_ifc_alloc_xrcd_out_bits {
6404 u8 status[0x8];
6405 u8 reserved_at_8[0x18];
6406
6407 u8 syndrome[0x20];
6408
6409 u8 reserved_at_40[0x8];
6410 u8 xrcd[0x18];
6411
6412 u8 reserved_at_60[0x20];
6413 };
6414
6415 struct mlx5_ifc_alloc_xrcd_in_bits {
6416 u8 opcode[0x10];
6417 u8 reserved_at_10[0x10];
6418
6419 u8 reserved_at_20[0x10];
6420 u8 op_mod[0x10];
6421
6422 u8 reserved_at_40[0x40];
6423 };
6424
6425 struct mlx5_ifc_alloc_uar_out_bits {
6426 u8 status[0x8];
6427 u8 reserved_at_8[0x18];
6428
6429 u8 syndrome[0x20];
6430
6431 u8 reserved_at_40[0x8];
6432 u8 uar[0x18];
6433
6434 u8 reserved_at_60[0x20];
6435 };
6436
6437 struct mlx5_ifc_alloc_uar_in_bits {
6438 u8 opcode[0x10];
6439 u8 reserved_at_10[0x10];
6440
6441 u8 reserved_at_20[0x10];
6442 u8 op_mod[0x10];
6443
6444 u8 reserved_at_40[0x40];
6445 };
6446
6447 struct mlx5_ifc_alloc_transport_domain_out_bits {
6448 u8 status[0x8];
6449 u8 reserved_at_8[0x18];
6450
6451 u8 syndrome[0x20];
6452
6453 u8 reserved_at_40[0x8];
6454 u8 transport_domain[0x18];
6455
6456 u8 reserved_at_60[0x20];
6457 };
6458
6459 struct mlx5_ifc_alloc_transport_domain_in_bits {
6460 u8 opcode[0x10];
6461 u8 reserved_at_10[0x10];
6462
6463 u8 reserved_at_20[0x10];
6464 u8 op_mod[0x10];
6465
6466 u8 reserved_at_40[0x40];
6467 };
6468
6469 struct mlx5_ifc_alloc_q_counter_out_bits {
6470 u8 status[0x8];
6471 u8 reserved_at_8[0x18];
6472
6473 u8 syndrome[0x20];
6474
6475 u8 reserved_at_40[0x18];
6476 u8 counter_set_id[0x8];
6477
6478 u8 reserved_at_60[0x20];
6479 };
6480
6481 struct mlx5_ifc_alloc_q_counter_in_bits {
6482 u8 opcode[0x10];
6483 u8 reserved_at_10[0x10];
6484
6485 u8 reserved_at_20[0x10];
6486 u8 op_mod[0x10];
6487
6488 u8 reserved_at_40[0x40];
6489 };
6490
6491 struct mlx5_ifc_alloc_pd_out_bits {
6492 u8 status[0x8];
6493 u8 reserved_at_8[0x18];
6494
6495 u8 syndrome[0x20];
6496
6497 u8 reserved_at_40[0x8];
6498 u8 pd[0x18];
6499
6500 u8 reserved_at_60[0x20];
6501 };
6502
6503 struct mlx5_ifc_alloc_pd_in_bits {
6504 u8 opcode[0x10];
6505 u8 reserved_at_10[0x10];
6506
6507 u8 reserved_at_20[0x10];
6508 u8 op_mod[0x10];
6509
6510 u8 reserved_at_40[0x40];
6511 };
6512
6513 struct mlx5_ifc_alloc_flow_counter_out_bits {
6514 u8 status[0x8];
6515 u8 reserved_at_8[0x18];
6516
6517 u8 syndrome[0x20];
6518
6519 u8 reserved_at_40[0x10];
6520 u8 flow_counter_id[0x10];
6521
6522 u8 reserved_at_60[0x20];
6523 };
6524
6525 struct mlx5_ifc_alloc_flow_counter_in_bits {
6526 u8 opcode[0x10];
6527 u8 reserved_at_10[0x10];
6528
6529 u8 reserved_at_20[0x10];
6530 u8 op_mod[0x10];
6531
6532 u8 reserved_at_40[0x40];
6533 };
6534
6535 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6536 u8 status[0x8];
6537 u8 reserved_at_8[0x18];
6538
6539 u8 syndrome[0x20];
6540
6541 u8 reserved_at_40[0x40];
6542 };
6543
6544 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6545 u8 opcode[0x10];
6546 u8 reserved_at_10[0x10];
6547
6548 u8 reserved_at_20[0x10];
6549 u8 op_mod[0x10];
6550
6551 u8 reserved_at_40[0x20];
6552
6553 u8 reserved_at_60[0x10];
6554 u8 vxlan_udp_port[0x10];
6555 };
6556
6557 struct mlx5_ifc_set_rate_limit_out_bits {
6558 u8 status[0x8];
6559 u8 reserved_at_8[0x18];
6560
6561 u8 syndrome[0x20];
6562
6563 u8 reserved_at_40[0x40];
6564 };
6565
6566 struct mlx5_ifc_set_rate_limit_in_bits {
6567 u8 opcode[0x10];
6568 u8 reserved_at_10[0x10];
6569
6570 u8 reserved_at_20[0x10];
6571 u8 op_mod[0x10];
6572
6573 u8 reserved_at_40[0x10];
6574 u8 rate_limit_index[0x10];
6575
6576 u8 reserved_at_60[0x20];
6577
6578 u8 rate_limit[0x20];
6579 };
6580
6581 struct mlx5_ifc_access_register_out_bits {
6582 u8 status[0x8];
6583 u8 reserved_at_8[0x18];
6584
6585 u8 syndrome[0x20];
6586
6587 u8 reserved_at_40[0x40];
6588
6589 u8 register_data[0][0x20];
6590 };
6591
6592 enum {
6593 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6594 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6595 };
6596
6597 struct mlx5_ifc_access_register_in_bits {
6598 u8 opcode[0x10];
6599 u8 reserved_at_10[0x10];
6600
6601 u8 reserved_at_20[0x10];
6602 u8 op_mod[0x10];
6603
6604 u8 reserved_at_40[0x10];
6605 u8 register_id[0x10];
6606
6607 u8 argument[0x20];
6608
6609 u8 register_data[0][0x20];
6610 };
6611
6612 struct mlx5_ifc_sltp_reg_bits {
6613 u8 status[0x4];
6614 u8 version[0x4];
6615 u8 local_port[0x8];
6616 u8 pnat[0x2];
6617 u8 reserved_at_12[0x2];
6618 u8 lane[0x4];
6619 u8 reserved_at_18[0x8];
6620
6621 u8 reserved_at_20[0x20];
6622
6623 u8 reserved_at_40[0x7];
6624 u8 polarity[0x1];
6625 u8 ob_tap0[0x8];
6626 u8 ob_tap1[0x8];
6627 u8 ob_tap2[0x8];
6628
6629 u8 reserved_at_60[0xc];
6630 u8 ob_preemp_mode[0x4];
6631 u8 ob_reg[0x8];
6632 u8 ob_bias[0x8];
6633
6634 u8 reserved_at_80[0x20];
6635 };
6636
6637 struct mlx5_ifc_slrg_reg_bits {
6638 u8 status[0x4];
6639 u8 version[0x4];
6640 u8 local_port[0x8];
6641 u8 pnat[0x2];
6642 u8 reserved_at_12[0x2];
6643 u8 lane[0x4];
6644 u8 reserved_at_18[0x8];
6645
6646 u8 time_to_link_up[0x10];
6647 u8 reserved_at_30[0xc];
6648 u8 grade_lane_speed[0x4];
6649
6650 u8 grade_version[0x8];
6651 u8 grade[0x18];
6652
6653 u8 reserved_at_60[0x4];
6654 u8 height_grade_type[0x4];
6655 u8 height_grade[0x18];
6656
6657 u8 height_dz[0x10];
6658 u8 height_dv[0x10];
6659
6660 u8 reserved_at_a0[0x10];
6661 u8 height_sigma[0x10];
6662
6663 u8 reserved_at_c0[0x20];
6664
6665 u8 reserved_at_e0[0x4];
6666 u8 phase_grade_type[0x4];
6667 u8 phase_grade[0x18];
6668
6669 u8 reserved_at_100[0x8];
6670 u8 phase_eo_pos[0x8];
6671 u8 reserved_at_110[0x8];
6672 u8 phase_eo_neg[0x8];
6673
6674 u8 ffe_set_tested[0x10];
6675 u8 test_errors_per_lane[0x10];
6676 };
6677
6678 struct mlx5_ifc_pvlc_reg_bits {
6679 u8 reserved_at_0[0x8];
6680 u8 local_port[0x8];
6681 u8 reserved_at_10[0x10];
6682
6683 u8 reserved_at_20[0x1c];
6684 u8 vl_hw_cap[0x4];
6685
6686 u8 reserved_at_40[0x1c];
6687 u8 vl_admin[0x4];
6688
6689 u8 reserved_at_60[0x1c];
6690 u8 vl_operational[0x4];
6691 };
6692
6693 struct mlx5_ifc_pude_reg_bits {
6694 u8 swid[0x8];
6695 u8 local_port[0x8];
6696 u8 reserved_at_10[0x4];
6697 u8 admin_status[0x4];
6698 u8 reserved_at_18[0x4];
6699 u8 oper_status[0x4];
6700
6701 u8 reserved_at_20[0x60];
6702 };
6703
6704 struct mlx5_ifc_ptys_reg_bits {
6705 u8 an_disable_cap[0x1];
6706 u8 an_disable_admin[0x1];
6707 u8 reserved_at_2[0x6];
6708 u8 local_port[0x8];
6709 u8 reserved_at_10[0xd];
6710 u8 proto_mask[0x3];
6711
6712 u8 an_status[0x4];
6713 u8 reserved_at_24[0x3c];
6714
6715 u8 eth_proto_capability[0x20];
6716
6717 u8 ib_link_width_capability[0x10];
6718 u8 ib_proto_capability[0x10];
6719
6720 u8 reserved_at_a0[0x20];
6721
6722 u8 eth_proto_admin[0x20];
6723
6724 u8 ib_link_width_admin[0x10];
6725 u8 ib_proto_admin[0x10];
6726
6727 u8 reserved_at_100[0x20];
6728
6729 u8 eth_proto_oper[0x20];
6730
6731 u8 ib_link_width_oper[0x10];
6732 u8 ib_proto_oper[0x10];
6733
6734 u8 reserved_at_160[0x20];
6735
6736 u8 eth_proto_lp_advertise[0x20];
6737
6738 u8 reserved_at_1a0[0x60];
6739 };
6740
6741 struct mlx5_ifc_mlcr_reg_bits {
6742 u8 reserved_at_0[0x8];
6743 u8 local_port[0x8];
6744 u8 reserved_at_10[0x20];
6745
6746 u8 beacon_duration[0x10];
6747 u8 reserved_at_40[0x10];
6748
6749 u8 beacon_remain[0x10];
6750 };
6751
6752 struct mlx5_ifc_ptas_reg_bits {
6753 u8 reserved_at_0[0x20];
6754
6755 u8 algorithm_options[0x10];
6756 u8 reserved_at_30[0x4];
6757 u8 repetitions_mode[0x4];
6758 u8 num_of_repetitions[0x8];
6759
6760 u8 grade_version[0x8];
6761 u8 height_grade_type[0x4];
6762 u8 phase_grade_type[0x4];
6763 u8 height_grade_weight[0x8];
6764 u8 phase_grade_weight[0x8];
6765
6766 u8 gisim_measure_bits[0x10];
6767 u8 adaptive_tap_measure_bits[0x10];
6768
6769 u8 ber_bath_high_error_threshold[0x10];
6770 u8 ber_bath_mid_error_threshold[0x10];
6771
6772 u8 ber_bath_low_error_threshold[0x10];
6773 u8 one_ratio_high_threshold[0x10];
6774
6775 u8 one_ratio_high_mid_threshold[0x10];
6776 u8 one_ratio_low_mid_threshold[0x10];
6777
6778 u8 one_ratio_low_threshold[0x10];
6779 u8 ndeo_error_threshold[0x10];
6780
6781 u8 mixer_offset_step_size[0x10];
6782 u8 reserved_at_110[0x8];
6783 u8 mix90_phase_for_voltage_bath[0x8];
6784
6785 u8 mixer_offset_start[0x10];
6786 u8 mixer_offset_end[0x10];
6787
6788 u8 reserved_at_140[0x15];
6789 u8 ber_test_time[0xb];
6790 };
6791
6792 struct mlx5_ifc_pspa_reg_bits {
6793 u8 swid[0x8];
6794 u8 local_port[0x8];
6795 u8 sub_port[0x8];
6796 u8 reserved_at_18[0x8];
6797
6798 u8 reserved_at_20[0x20];
6799 };
6800
6801 struct mlx5_ifc_pqdr_reg_bits {
6802 u8 reserved_at_0[0x8];
6803 u8 local_port[0x8];
6804 u8 reserved_at_10[0x5];
6805 u8 prio[0x3];
6806 u8 reserved_at_18[0x6];
6807 u8 mode[0x2];
6808
6809 u8 reserved_at_20[0x20];
6810
6811 u8 reserved_at_40[0x10];
6812 u8 min_threshold[0x10];
6813
6814 u8 reserved_at_60[0x10];
6815 u8 max_threshold[0x10];
6816
6817 u8 reserved_at_80[0x10];
6818 u8 mark_probability_denominator[0x10];
6819
6820 u8 reserved_at_a0[0x60];
6821 };
6822
6823 struct mlx5_ifc_ppsc_reg_bits {
6824 u8 reserved_at_0[0x8];
6825 u8 local_port[0x8];
6826 u8 reserved_at_10[0x10];
6827
6828 u8 reserved_at_20[0x60];
6829
6830 u8 reserved_at_80[0x1c];
6831 u8 wrps_admin[0x4];
6832
6833 u8 reserved_at_a0[0x1c];
6834 u8 wrps_status[0x4];
6835
6836 u8 reserved_at_c0[0x8];
6837 u8 up_threshold[0x8];
6838 u8 reserved_at_d0[0x8];
6839 u8 down_threshold[0x8];
6840
6841 u8 reserved_at_e0[0x20];
6842
6843 u8 reserved_at_100[0x1c];
6844 u8 srps_admin[0x4];
6845
6846 u8 reserved_at_120[0x1c];
6847 u8 srps_status[0x4];
6848
6849 u8 reserved_at_140[0x40];
6850 };
6851
6852 struct mlx5_ifc_pplr_reg_bits {
6853 u8 reserved_at_0[0x8];
6854 u8 local_port[0x8];
6855 u8 reserved_at_10[0x10];
6856
6857 u8 reserved_at_20[0x8];
6858 u8 lb_cap[0x8];
6859 u8 reserved_at_30[0x8];
6860 u8 lb_en[0x8];
6861 };
6862
6863 struct mlx5_ifc_pplm_reg_bits {
6864 u8 reserved_at_0[0x8];
6865 u8 local_port[0x8];
6866 u8 reserved_at_10[0x10];
6867
6868 u8 reserved_at_20[0x20];
6869
6870 u8 port_profile_mode[0x8];
6871 u8 static_port_profile[0x8];
6872 u8 active_port_profile[0x8];
6873 u8 reserved_at_58[0x8];
6874
6875 u8 retransmission_active[0x8];
6876 u8 fec_mode_active[0x18];
6877
6878 u8 reserved_at_80[0x20];
6879 };
6880
6881 struct mlx5_ifc_ppcnt_reg_bits {
6882 u8 swid[0x8];
6883 u8 local_port[0x8];
6884 u8 pnat[0x2];
6885 u8 reserved_at_12[0x8];
6886 u8 grp[0x6];
6887
6888 u8 clr[0x1];
6889 u8 reserved_at_21[0x1c];
6890 u8 prio_tc[0x3];
6891
6892 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6893 };
6894
6895 struct mlx5_ifc_ppad_reg_bits {
6896 u8 reserved_at_0[0x3];
6897 u8 single_mac[0x1];
6898 u8 reserved_at_4[0x4];
6899 u8 local_port[0x8];
6900 u8 mac_47_32[0x10];
6901
6902 u8 mac_31_0[0x20];
6903
6904 u8 reserved_at_40[0x40];
6905 };
6906
6907 struct mlx5_ifc_pmtu_reg_bits {
6908 u8 reserved_at_0[0x8];
6909 u8 local_port[0x8];
6910 u8 reserved_at_10[0x10];
6911
6912 u8 max_mtu[0x10];
6913 u8 reserved_at_30[0x10];
6914
6915 u8 admin_mtu[0x10];
6916 u8 reserved_at_50[0x10];
6917
6918 u8 oper_mtu[0x10];
6919 u8 reserved_at_70[0x10];
6920 };
6921
6922 struct mlx5_ifc_pmpr_reg_bits {
6923 u8 reserved_at_0[0x8];
6924 u8 module[0x8];
6925 u8 reserved_at_10[0x10];
6926
6927 u8 reserved_at_20[0x18];
6928 u8 attenuation_5g[0x8];
6929
6930 u8 reserved_at_40[0x18];
6931 u8 attenuation_7g[0x8];
6932
6933 u8 reserved_at_60[0x18];
6934 u8 attenuation_12g[0x8];
6935 };
6936
6937 struct mlx5_ifc_pmpe_reg_bits {
6938 u8 reserved_at_0[0x8];
6939 u8 module[0x8];
6940 u8 reserved_at_10[0xc];
6941 u8 module_status[0x4];
6942
6943 u8 reserved_at_20[0x60];
6944 };
6945
6946 struct mlx5_ifc_pmpc_reg_bits {
6947 u8 module_state_updated[32][0x8];
6948 };
6949
6950 struct mlx5_ifc_pmlpn_reg_bits {
6951 u8 reserved_at_0[0x4];
6952 u8 mlpn_status[0x4];
6953 u8 local_port[0x8];
6954 u8 reserved_at_10[0x10];
6955
6956 u8 e[0x1];
6957 u8 reserved_at_21[0x1f];
6958 };
6959
6960 struct mlx5_ifc_pmlp_reg_bits {
6961 u8 rxtx[0x1];
6962 u8 reserved_at_1[0x7];
6963 u8 local_port[0x8];
6964 u8 reserved_at_10[0x8];
6965 u8 width[0x8];
6966
6967 u8 lane0_module_mapping[0x20];
6968
6969 u8 lane1_module_mapping[0x20];
6970
6971 u8 lane2_module_mapping[0x20];
6972
6973 u8 lane3_module_mapping[0x20];
6974
6975 u8 reserved_at_a0[0x160];
6976 };
6977
6978 struct mlx5_ifc_pmaos_reg_bits {
6979 u8 reserved_at_0[0x8];
6980 u8 module[0x8];
6981 u8 reserved_at_10[0x4];
6982 u8 admin_status[0x4];
6983 u8 reserved_at_18[0x4];
6984 u8 oper_status[0x4];
6985
6986 u8 ase[0x1];
6987 u8 ee[0x1];
6988 u8 reserved_at_22[0x1c];
6989 u8 e[0x2];
6990
6991 u8 reserved_at_40[0x40];
6992 };
6993
6994 struct mlx5_ifc_plpc_reg_bits {
6995 u8 reserved_at_0[0x4];
6996 u8 profile_id[0xc];
6997 u8 reserved_at_10[0x4];
6998 u8 proto_mask[0x4];
6999 u8 reserved_at_18[0x8];
7000
7001 u8 reserved_at_20[0x10];
7002 u8 lane_speed[0x10];
7003
7004 u8 reserved_at_40[0x17];
7005 u8 lpbf[0x1];
7006 u8 fec_mode_policy[0x8];
7007
7008 u8 retransmission_capability[0x8];
7009 u8 fec_mode_capability[0x18];
7010
7011 u8 retransmission_support_admin[0x8];
7012 u8 fec_mode_support_admin[0x18];
7013
7014 u8 retransmission_request_admin[0x8];
7015 u8 fec_mode_request_admin[0x18];
7016
7017 u8 reserved_at_c0[0x80];
7018 };
7019
7020 struct mlx5_ifc_plib_reg_bits {
7021 u8 reserved_at_0[0x8];
7022 u8 local_port[0x8];
7023 u8 reserved_at_10[0x8];
7024 u8 ib_port[0x8];
7025
7026 u8 reserved_at_20[0x60];
7027 };
7028
7029 struct mlx5_ifc_plbf_reg_bits {
7030 u8 reserved_at_0[0x8];
7031 u8 local_port[0x8];
7032 u8 reserved_at_10[0xd];
7033 u8 lbf_mode[0x3];
7034
7035 u8 reserved_at_20[0x20];
7036 };
7037
7038 struct mlx5_ifc_pipg_reg_bits {
7039 u8 reserved_at_0[0x8];
7040 u8 local_port[0x8];
7041 u8 reserved_at_10[0x10];
7042
7043 u8 dic[0x1];
7044 u8 reserved_at_21[0x19];
7045 u8 ipg[0x4];
7046 u8 reserved_at_3e[0x2];
7047 };
7048
7049 struct mlx5_ifc_pifr_reg_bits {
7050 u8 reserved_at_0[0x8];
7051 u8 local_port[0x8];
7052 u8 reserved_at_10[0x10];
7053
7054 u8 reserved_at_20[0xe0];
7055
7056 u8 port_filter[8][0x20];
7057
7058 u8 port_filter_update_en[8][0x20];
7059 };
7060
7061 struct mlx5_ifc_pfcc_reg_bits {
7062 u8 reserved_at_0[0x8];
7063 u8 local_port[0x8];
7064 u8 reserved_at_10[0x10];
7065
7066 u8 ppan[0x4];
7067 u8 reserved_at_24[0x4];
7068 u8 prio_mask_tx[0x8];
7069 u8 reserved_at_30[0x8];
7070 u8 prio_mask_rx[0x8];
7071
7072 u8 pptx[0x1];
7073 u8 aptx[0x1];
7074 u8 reserved_at_42[0x6];
7075 u8 pfctx[0x8];
7076 u8 reserved_at_50[0x10];
7077
7078 u8 pprx[0x1];
7079 u8 aprx[0x1];
7080 u8 reserved_at_62[0x6];
7081 u8 pfcrx[0x8];
7082 u8 reserved_at_70[0x10];
7083
7084 u8 reserved_at_80[0x80];
7085 };
7086
7087 struct mlx5_ifc_pelc_reg_bits {
7088 u8 op[0x4];
7089 u8 reserved_at_4[0x4];
7090 u8 local_port[0x8];
7091 u8 reserved_at_10[0x10];
7092
7093 u8 op_admin[0x8];
7094 u8 op_capability[0x8];
7095 u8 op_request[0x8];
7096 u8 op_active[0x8];
7097
7098 u8 admin[0x40];
7099
7100 u8 capability[0x40];
7101
7102 u8 request[0x40];
7103
7104 u8 active[0x40];
7105
7106 u8 reserved_at_140[0x80];
7107 };
7108
7109 struct mlx5_ifc_peir_reg_bits {
7110 u8 reserved_at_0[0x8];
7111 u8 local_port[0x8];
7112 u8 reserved_at_10[0x10];
7113
7114 u8 reserved_at_20[0xc];
7115 u8 error_count[0x4];
7116 u8 reserved_at_30[0x10];
7117
7118 u8 reserved_at_40[0xc];
7119 u8 lane[0x4];
7120 u8 reserved_at_50[0x8];
7121 u8 error_type[0x8];
7122 };
7123
7124 struct mlx5_ifc_pcap_reg_bits {
7125 u8 reserved_at_0[0x8];
7126 u8 local_port[0x8];
7127 u8 reserved_at_10[0x10];
7128
7129 u8 port_capability_mask[4][0x20];
7130 };
7131
7132 struct mlx5_ifc_paos_reg_bits {
7133 u8 swid[0x8];
7134 u8 local_port[0x8];
7135 u8 reserved_at_10[0x4];
7136 u8 admin_status[0x4];
7137 u8 reserved_at_18[0x4];
7138 u8 oper_status[0x4];
7139
7140 u8 ase[0x1];
7141 u8 ee[0x1];
7142 u8 reserved_at_22[0x1c];
7143 u8 e[0x2];
7144
7145 u8 reserved_at_40[0x40];
7146 };
7147
7148 struct mlx5_ifc_pamp_reg_bits {
7149 u8 reserved_at_0[0x8];
7150 u8 opamp_group[0x8];
7151 u8 reserved_at_10[0xc];
7152 u8 opamp_group_type[0x4];
7153
7154 u8 start_index[0x10];
7155 u8 reserved_at_30[0x4];
7156 u8 num_of_indices[0xc];
7157
7158 u8 index_data[18][0x10];
7159 };
7160
7161 struct mlx5_ifc_pcmr_reg_bits {
7162 u8 reserved_at_0[0x8];
7163 u8 local_port[0x8];
7164 u8 reserved_at_10[0x2e];
7165 u8 fcs_cap[0x1];
7166 u8 reserved_at_3f[0x1f];
7167 u8 fcs_chk[0x1];
7168 u8 reserved_at_5f[0x1];
7169 };
7170
7171 struct mlx5_ifc_lane_2_module_mapping_bits {
7172 u8 reserved_at_0[0x6];
7173 u8 rx_lane[0x2];
7174 u8 reserved_at_8[0x6];
7175 u8 tx_lane[0x2];
7176 u8 reserved_at_10[0x8];
7177 u8 module[0x8];
7178 };
7179
7180 struct mlx5_ifc_bufferx_reg_bits {
7181 u8 reserved_at_0[0x6];
7182 u8 lossy[0x1];
7183 u8 epsb[0x1];
7184 u8 reserved_at_8[0xc];
7185 u8 size[0xc];
7186
7187 u8 xoff_threshold[0x10];
7188 u8 xon_threshold[0x10];
7189 };
7190
7191 struct mlx5_ifc_set_node_in_bits {
7192 u8 node_description[64][0x8];
7193 };
7194
7195 struct mlx5_ifc_register_power_settings_bits {
7196 u8 reserved_at_0[0x18];
7197 u8 power_settings_level[0x8];
7198
7199 u8 reserved_at_20[0x60];
7200 };
7201
7202 struct mlx5_ifc_register_host_endianness_bits {
7203 u8 he[0x1];
7204 u8 reserved_at_1[0x1f];
7205
7206 u8 reserved_at_20[0x60];
7207 };
7208
7209 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7210 u8 reserved_at_0[0x20];
7211
7212 u8 mkey[0x20];
7213
7214 u8 addressh_63_32[0x20];
7215
7216 u8 addressl_31_0[0x20];
7217 };
7218
7219 struct mlx5_ifc_ud_adrs_vector_bits {
7220 u8 dc_key[0x40];
7221
7222 u8 ext[0x1];
7223 u8 reserved_at_41[0x7];
7224 u8 destination_qp_dct[0x18];
7225
7226 u8 static_rate[0x4];
7227 u8 sl_eth_prio[0x4];
7228 u8 fl[0x1];
7229 u8 mlid[0x7];
7230 u8 rlid_udp_sport[0x10];
7231
7232 u8 reserved_at_80[0x20];
7233
7234 u8 rmac_47_16[0x20];
7235
7236 u8 rmac_15_0[0x10];
7237 u8 tclass[0x8];
7238 u8 hop_limit[0x8];
7239
7240 u8 reserved_at_e0[0x1];
7241 u8 grh[0x1];
7242 u8 reserved_at_e2[0x2];
7243 u8 src_addr_index[0x8];
7244 u8 flow_label[0x14];
7245
7246 u8 rgid_rip[16][0x8];
7247 };
7248
7249 struct mlx5_ifc_pages_req_event_bits {
7250 u8 reserved_at_0[0x10];
7251 u8 function_id[0x10];
7252
7253 u8 num_pages[0x20];
7254
7255 u8 reserved_at_40[0xa0];
7256 };
7257
7258 struct mlx5_ifc_eqe_bits {
7259 u8 reserved_at_0[0x8];
7260 u8 event_type[0x8];
7261 u8 reserved_at_10[0x8];
7262 u8 event_sub_type[0x8];
7263
7264 u8 reserved_at_20[0xe0];
7265
7266 union mlx5_ifc_event_auto_bits event_data;
7267
7268 u8 reserved_at_1e0[0x10];
7269 u8 signature[0x8];
7270 u8 reserved_at_1f8[0x7];
7271 u8 owner[0x1];
7272 };
7273
7274 enum {
7275 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7276 };
7277
7278 struct mlx5_ifc_cmd_queue_entry_bits {
7279 u8 type[0x8];
7280 u8 reserved_at_8[0x18];
7281
7282 u8 input_length[0x20];
7283
7284 u8 input_mailbox_pointer_63_32[0x20];
7285
7286 u8 input_mailbox_pointer_31_9[0x17];
7287 u8 reserved_at_77[0x9];
7288
7289 u8 command_input_inline_data[16][0x8];
7290
7291 u8 command_output_inline_data[16][0x8];
7292
7293 u8 output_mailbox_pointer_63_32[0x20];
7294
7295 u8 output_mailbox_pointer_31_9[0x17];
7296 u8 reserved_at_1b7[0x9];
7297
7298 u8 output_length[0x20];
7299
7300 u8 token[0x8];
7301 u8 signature[0x8];
7302 u8 reserved_at_1f0[0x8];
7303 u8 status[0x7];
7304 u8 ownership[0x1];
7305 };
7306
7307 struct mlx5_ifc_cmd_out_bits {
7308 u8 status[0x8];
7309 u8 reserved_at_8[0x18];
7310
7311 u8 syndrome[0x20];
7312
7313 u8 command_output[0x20];
7314 };
7315
7316 struct mlx5_ifc_cmd_in_bits {
7317 u8 opcode[0x10];
7318 u8 reserved_at_10[0x10];
7319
7320 u8 reserved_at_20[0x10];
7321 u8 op_mod[0x10];
7322
7323 u8 command[0][0x20];
7324 };
7325
7326 struct mlx5_ifc_cmd_if_box_bits {
7327 u8 mailbox_data[512][0x8];
7328
7329 u8 reserved_at_1000[0x180];
7330
7331 u8 next_pointer_63_32[0x20];
7332
7333 u8 next_pointer_31_10[0x16];
7334 u8 reserved_at_11b6[0xa];
7335
7336 u8 block_number[0x20];
7337
7338 u8 reserved_at_11e0[0x8];
7339 u8 token[0x8];
7340 u8 ctrl_signature[0x8];
7341 u8 signature[0x8];
7342 };
7343
7344 struct mlx5_ifc_mtt_bits {
7345 u8 ptag_63_32[0x20];
7346
7347 u8 ptag_31_8[0x18];
7348 u8 reserved_at_38[0x6];
7349 u8 wr_en[0x1];
7350 u8 rd_en[0x1];
7351 };
7352
7353 struct mlx5_ifc_query_wol_rol_out_bits {
7354 u8 status[0x8];
7355 u8 reserved_at_8[0x18];
7356
7357 u8 syndrome[0x20];
7358
7359 u8 reserved_at_40[0x10];
7360 u8 rol_mode[0x8];
7361 u8 wol_mode[0x8];
7362
7363 u8 reserved_at_60[0x20];
7364 };
7365
7366 struct mlx5_ifc_query_wol_rol_in_bits {
7367 u8 opcode[0x10];
7368 u8 reserved_at_10[0x10];
7369
7370 u8 reserved_at_20[0x10];
7371 u8 op_mod[0x10];
7372
7373 u8 reserved_at_40[0x40];
7374 };
7375
7376 struct mlx5_ifc_set_wol_rol_out_bits {
7377 u8 status[0x8];
7378 u8 reserved_at_8[0x18];
7379
7380 u8 syndrome[0x20];
7381
7382 u8 reserved_at_40[0x40];
7383 };
7384
7385 struct mlx5_ifc_set_wol_rol_in_bits {
7386 u8 opcode[0x10];
7387 u8 reserved_at_10[0x10];
7388
7389 u8 reserved_at_20[0x10];
7390 u8 op_mod[0x10];
7391
7392 u8 rol_mode_valid[0x1];
7393 u8 wol_mode_valid[0x1];
7394 u8 reserved_at_42[0xe];
7395 u8 rol_mode[0x8];
7396 u8 wol_mode[0x8];
7397
7398 u8 reserved_at_60[0x20];
7399 };
7400
7401 enum {
7402 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7403 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7404 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7405 };
7406
7407 enum {
7408 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7409 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7410 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7411 };
7412
7413 enum {
7414 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7425 };
7426
7427 struct mlx5_ifc_initial_seg_bits {
7428 u8 fw_rev_minor[0x10];
7429 u8 fw_rev_major[0x10];
7430
7431 u8 cmd_interface_rev[0x10];
7432 u8 fw_rev_subminor[0x10];
7433
7434 u8 reserved_at_40[0x40];
7435
7436 u8 cmdq_phy_addr_63_32[0x20];
7437
7438 u8 cmdq_phy_addr_31_12[0x14];
7439 u8 reserved_at_b4[0x2];
7440 u8 nic_interface[0x2];
7441 u8 log_cmdq_size[0x4];
7442 u8 log_cmdq_stride[0x4];
7443
7444 u8 command_doorbell_vector[0x20];
7445
7446 u8 reserved_at_e0[0xf00];
7447
7448 u8 initializing[0x1];
7449 u8 reserved_at_fe1[0x4];
7450 u8 nic_interface_supported[0x3];
7451 u8 reserved_at_fe8[0x18];
7452
7453 struct mlx5_ifc_health_buffer_bits health_buffer;
7454
7455 u8 no_dram_nic_offset[0x20];
7456
7457 u8 reserved_at_1220[0x6e40];
7458
7459 u8 reserved_at_8060[0x1f];
7460 u8 clear_int[0x1];
7461
7462 u8 health_syndrome[0x8];
7463 u8 health_counter[0x18];
7464
7465 u8 reserved_at_80a0[0x17fc0];
7466 };
7467
7468 union mlx5_ifc_ports_control_registers_document_bits {
7469 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7470 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7471 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7472 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7473 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7474 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7475 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7476 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7477 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7478 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7479 struct mlx5_ifc_paos_reg_bits paos_reg;
7480 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7481 struct mlx5_ifc_peir_reg_bits peir_reg;
7482 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7483 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7484 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7485 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7486 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7487 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7488 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7489 struct mlx5_ifc_plib_reg_bits plib_reg;
7490 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7491 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7492 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7493 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7494 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7495 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7496 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7497 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7498 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7499 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7500 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7501 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7502 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7503 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7504 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7505 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7506 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7507 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7508 struct mlx5_ifc_pude_reg_bits pude_reg;
7509 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7510 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7511 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7512 u8 reserved_at_0[0x60e0];
7513 };
7514
7515 union mlx5_ifc_debug_enhancements_document_bits {
7516 struct mlx5_ifc_health_buffer_bits health_buffer;
7517 u8 reserved_at_0[0x200];
7518 };
7519
7520 union mlx5_ifc_uplink_pci_interface_document_bits {
7521 struct mlx5_ifc_initial_seg_bits initial_seg;
7522 u8 reserved_at_0[0x20060];
7523 };
7524
7525 struct mlx5_ifc_set_flow_table_root_out_bits {
7526 u8 status[0x8];
7527 u8 reserved_at_8[0x18];
7528
7529 u8 syndrome[0x20];
7530
7531 u8 reserved_at_40[0x40];
7532 };
7533
7534 struct mlx5_ifc_set_flow_table_root_in_bits {
7535 u8 opcode[0x10];
7536 u8 reserved_at_10[0x10];
7537
7538 u8 reserved_at_20[0x10];
7539 u8 op_mod[0x10];
7540
7541 u8 other_vport[0x1];
7542 u8 reserved_at_41[0xf];
7543 u8 vport_number[0x10];
7544
7545 u8 reserved_at_60[0x20];
7546
7547 u8 table_type[0x8];
7548 u8 reserved_at_88[0x18];
7549
7550 u8 reserved_at_a0[0x8];
7551 u8 table_id[0x18];
7552
7553 u8 reserved_at_c0[0x140];
7554 };
7555
7556 enum {
7557 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7558 };
7559
7560 struct mlx5_ifc_modify_flow_table_out_bits {
7561 u8 status[0x8];
7562 u8 reserved_at_8[0x18];
7563
7564 u8 syndrome[0x20];
7565
7566 u8 reserved_at_40[0x40];
7567 };
7568
7569 struct mlx5_ifc_modify_flow_table_in_bits {
7570 u8 opcode[0x10];
7571 u8 reserved_at_10[0x10];
7572
7573 u8 reserved_at_20[0x10];
7574 u8 op_mod[0x10];
7575
7576 u8 other_vport[0x1];
7577 u8 reserved_at_41[0xf];
7578 u8 vport_number[0x10];
7579
7580 u8 reserved_at_60[0x10];
7581 u8 modify_field_select[0x10];
7582
7583 u8 table_type[0x8];
7584 u8 reserved_at_88[0x18];
7585
7586 u8 reserved_at_a0[0x8];
7587 u8 table_id[0x18];
7588
7589 u8 reserved_at_c0[0x4];
7590 u8 table_miss_mode[0x4];
7591 u8 reserved_at_c8[0x18];
7592
7593 u8 reserved_at_e0[0x8];
7594 u8 table_miss_id[0x18];
7595
7596 u8 reserved_at_100[0x100];
7597 };
7598
7599 struct mlx5_ifc_ets_tcn_config_reg_bits {
7600 u8 g[0x1];
7601 u8 b[0x1];
7602 u8 r[0x1];
7603 u8 reserved_at_3[0x9];
7604 u8 group[0x4];
7605 u8 reserved_at_10[0x9];
7606 u8 bw_allocation[0x7];
7607
7608 u8 reserved_at_20[0xc];
7609 u8 max_bw_units[0x4];
7610 u8 reserved_at_30[0x8];
7611 u8 max_bw_value[0x8];
7612 };
7613
7614 struct mlx5_ifc_ets_global_config_reg_bits {
7615 u8 reserved_at_0[0x2];
7616 u8 r[0x1];
7617 u8 reserved_at_3[0x1d];
7618
7619 u8 reserved_at_20[0xc];
7620 u8 max_bw_units[0x4];
7621 u8 reserved_at_30[0x8];
7622 u8 max_bw_value[0x8];
7623 };
7624
7625 struct mlx5_ifc_qetc_reg_bits {
7626 u8 reserved_at_0[0x8];
7627 u8 port_number[0x8];
7628 u8 reserved_at_10[0x30];
7629
7630 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7631 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7632 };
7633
7634 struct mlx5_ifc_qtct_reg_bits {
7635 u8 reserved_at_0[0x8];
7636 u8 port_number[0x8];
7637 u8 reserved_at_10[0xd];
7638 u8 prio[0x3];
7639
7640 u8 reserved_at_20[0x1d];
7641 u8 tclass[0x3];
7642 };
7643
7644 struct mlx5_ifc_mcia_reg_bits {
7645 u8 l[0x1];
7646 u8 reserved_at_1[0x7];
7647 u8 module[0x8];
7648 u8 reserved_at_10[0x8];
7649 u8 status[0x8];
7650
7651 u8 i2c_device_address[0x8];
7652 u8 page_number[0x8];
7653 u8 device_address[0x10];
7654
7655 u8 reserved_at_40[0x10];
7656 u8 size[0x10];
7657
7658 u8 reserved_at_60[0x20];
7659
7660 u8 dword_0[0x20];
7661 u8 dword_1[0x20];
7662 u8 dword_2[0x20];
7663 u8 dword_3[0x20];
7664 u8 dword_4[0x20];
7665 u8 dword_5[0x20];
7666 u8 dword_6[0x20];
7667 u8 dword_7[0x20];
7668 u8 dword_8[0x20];
7669 u8 dword_9[0x20];
7670 u8 dword_10[0x20];
7671 u8 dword_11[0x20];
7672 };
7673
7674 struct mlx5_ifc_dcbx_param_bits {
7675 u8 dcbx_cee_cap[0x1];
7676 u8 dcbx_ieee_cap[0x1];
7677 u8 dcbx_standby_cap[0x1];
7678 u8 reserved_at_0[0x5];
7679 u8 port_number[0x8];
7680 u8 reserved_at_10[0xa];
7681 u8 max_application_table_size[6];
7682 u8 reserved_at_20[0x15];
7683 u8 version_oper[0x3];
7684 u8 reserved_at_38[5];
7685 u8 version_admin[0x3];
7686 u8 willing_admin[0x1];
7687 u8 reserved_at_41[0x3];
7688 u8 pfc_cap_oper[0x4];
7689 u8 reserved_at_48[0x4];
7690 u8 pfc_cap_admin[0x4];
7691 u8 reserved_at_50[0x4];
7692 u8 num_of_tc_oper[0x4];
7693 u8 reserved_at_58[0x4];
7694 u8 num_of_tc_admin[0x4];
7695 u8 remote_willing[0x1];
7696 u8 reserved_at_61[3];
7697 u8 remote_pfc_cap[4];
7698 u8 reserved_at_68[0x14];
7699 u8 remote_num_of_tc[0x4];
7700 u8 reserved_at_80[0x18];
7701 u8 error[0x8];
7702 u8 reserved_at_a0[0x160];
7703 };
7704 #endif /* MLX5_IFC_H */
Linux kernel - Deliverables
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