2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
77 MLX5_CMD_OP_INIT_HCA
= 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
79 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
80 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
81 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
84 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
85 MLX5_CMD_OP_SET_ISSI
= 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
87 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
91 MLX5_CMD_OP_CREATE_EQ
= 0x301,
92 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
93 MLX5_CMD_OP_QUERY_EQ
= 0x303,
94 MLX5_CMD_OP_GEN_EQE
= 0x304,
95 MLX5_CMD_OP_CREATE_CQ
= 0x400,
96 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
97 MLX5_CMD_OP_QUERY_CQ
= 0x402,
98 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
99 MLX5_CMD_OP_CREATE_QP
= 0x500,
100 MLX5_CMD_OP_DESTROY_QP
= 0x501,
101 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
106 MLX5_CMD_OP_2ERR_QP
= 0x507,
107 MLX5_CMD_OP_2RST_QP
= 0x50a,
108 MLX5_CMD_OP_QUERY_QP
= 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
111 MLX5_CMD_OP_CREATE_PSV
= 0x600,
112 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
113 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
115 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
116 MLX5_CMD_OP_ARM_RQ
= 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
121 MLX5_CMD_OP_CREATE_DCT
= 0x710,
122 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
123 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
124 MLX5_CMD_OP_QUERY_DCT
= 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
142 MLX5_CMD_OP_ALLOC_PD
= 0x800,
143 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
144 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
147 MLX5_CMD_OP_ACCESS_REG
= 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG
= 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
151 MLX5_CMD_OP_MAD_IFC
= 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
154 MLX5_CMD_OP_NOP
= 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
169 MLX5_CMD_OP_CREATE_TIR
= 0x900,
170 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
171 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
172 MLX5_CMD_OP_QUERY_TIR
= 0x903,
173 MLX5_CMD_OP_CREATE_SQ
= 0x904,
174 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
175 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
176 MLX5_CMD_OP_QUERY_SQ
= 0x907,
177 MLX5_CMD_OP_CREATE_RQ
= 0x908,
178 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
179 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
180 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
181 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
182 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
183 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
184 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
185 MLX5_CMD_OP_CREATE_TIS
= 0x912,
186 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
187 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
188 MLX5_CMD_OP_QUERY_TIS
= 0x915,
189 MLX5_CMD_OP_CREATE_RQT
= 0x916,
190 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
191 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
192 MLX5_CMD_OP_QUERY_RQT
= 0x919,
193 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
194 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
195 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
196 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
197 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
198 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
199 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
200 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
201 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
202 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
203 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c
206 struct mlx5_ifc_flow_table_fields_supported_bits
{
209 u8 outer_ether_type
[0x1];
211 u8 outer_first_prio
[0x1];
212 u8 outer_first_cfi
[0x1];
213 u8 outer_first_vid
[0x1];
215 u8 outer_second_prio
[0x1];
216 u8 outer_second_cfi
[0x1];
217 u8 outer_second_vid
[0x1];
222 u8 outer_ip_protocol
[0x1];
223 u8 outer_ip_ecn
[0x1];
224 u8 outer_ip_dscp
[0x1];
225 u8 outer_udp_sport
[0x1];
226 u8 outer_udp_dport
[0x1];
227 u8 outer_tcp_sport
[0x1];
228 u8 outer_tcp_dport
[0x1];
229 u8 outer_tcp_flags
[0x1];
230 u8 outer_gre_protocol
[0x1];
231 u8 outer_gre_key
[0x1];
232 u8 outer_vxlan_vni
[0x1];
234 u8 source_eswitch_port
[0x1];
238 u8 inner_ether_type
[0x1];
240 u8 inner_first_prio
[0x1];
241 u8 inner_first_cfi
[0x1];
242 u8 inner_first_vid
[0x1];
244 u8 inner_second_prio
[0x1];
245 u8 inner_second_cfi
[0x1];
246 u8 inner_second_vid
[0x1];
251 u8 inner_ip_protocol
[0x1];
252 u8 inner_ip_ecn
[0x1];
253 u8 inner_ip_dscp
[0x1];
254 u8 inner_udp_sport
[0x1];
255 u8 inner_udp_dport
[0x1];
256 u8 inner_tcp_sport
[0x1];
257 u8 inner_tcp_dport
[0x1];
258 u8 inner_tcp_flags
[0x1];
264 struct mlx5_ifc_flow_table_prop_layout_bits
{
267 u8 flow_modify_en
[0x1];
269 u8 identified_miss_table_mode
[0x1];
270 u8 flow_table_modify
[0x1];
274 u8 log_max_ft_size
[0x6];
276 u8 max_ft_level
[0x8];
281 u8 log_max_ft_num
[0x8];
284 u8 log_max_destination
[0x8];
287 u8 log_max_flow
[0x8];
291 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
296 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
306 struct mlx5_ifc_ipv4_layout_bits
{
312 struct mlx5_ifc_ipv6_layout_bits
{
316 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits
{
317 struct mlx5_ifc_ipv6_layout_bits ipv6_layout
;
318 struct mlx5_ifc_ipv4_layout_bits ipv4_layout
;
322 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
357 struct mlx5_ifc_fte_match_set_misc_bits
{
361 u8 source_port
[0x10];
363 u8 outer_second_prio
[0x3];
364 u8 outer_second_cfi
[0x1];
365 u8 outer_second_vid
[0xc];
366 u8 inner_second_prio
[0x3];
367 u8 inner_second_cfi
[0x1];
368 u8 inner_second_vid
[0xc];
370 u8 outer_second_vlan_tag
[0x1];
371 u8 inner_second_vlan_tag
[0x1];
373 u8 gre_protocol
[0x10];
384 u8 outer_ipv6_flow_label
[0x14];
387 u8 inner_ipv6_flow_label
[0x14];
392 struct mlx5_ifc_cmd_pas_bits
{
399 struct mlx5_ifc_uint64_bits
{
406 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
407 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
408 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
409 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
410 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
411 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
412 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
413 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
414 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
415 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
418 struct mlx5_ifc_ads_bits
{
431 u8 src_addr_index
[0x8];
440 u8 rgid_rip
[16][0x8];
460 struct mlx5_ifc_flow_table_nic_cap_bits
{
461 u8 reserved_0
[0x200];
463 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
465 u8 reserved_1
[0x200];
467 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
469 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
471 u8 reserved_2
[0x200];
473 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
475 u8 reserved_3
[0x7200];
478 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
479 u8 reserved_0
[0x200];
481 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
483 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
485 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
487 u8 reserved_1
[0x7800];
490 struct mlx5_ifc_e_switch_cap_bits
{
491 u8 vport_svlan_strip
[0x1];
492 u8 vport_cvlan_strip
[0x1];
493 u8 vport_svlan_insert
[0x1];
494 u8 vport_cvlan_insert_if_not_exist
[0x1];
495 u8 vport_cvlan_insert_overwrite
[0x1];
498 u8 reserved_1
[0x7e0];
501 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
505 u8 lro_psh_flag
[0x1];
506 u8 lro_time_stamp
[0x1];
508 u8 self_lb_en_modifiable
[0x1];
512 u8 rss_ind_tbl_cap
[0x4];
514 u8 tunnel_lso_const_out_ip_id
[0x1];
516 u8 tunnel_statless_gre
[0x1];
517 u8 tunnel_stateless_vxlan
[0x1];
522 u8 lro_min_mss_size
[0x10];
524 u8 reserved_7
[0x120];
526 u8 lro_timer_supported_periods
[4][0x20];
528 u8 reserved_8
[0x600];
531 struct mlx5_ifc_roce_cap_bits
{
540 u8 roce_version
[0x8];
543 u8 r_roce_dest_udp_port
[0x10];
545 u8 r_roce_max_src_udp_port
[0x10];
546 u8 r_roce_min_src_udp_port
[0x10];
549 u8 roce_address_table_size
[0x10];
551 u8 reserved_6
[0x700];
555 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
556 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
578 struct mlx5_ifc_atomic_caps_bits
{
581 u8 atomic_req_8B_endianess_mode
[0x2];
583 u8 supported_atomic_req_8B_endianess_mode_1
[0x1];
590 u8 atomic_operations
[0x10];
593 u8 atomic_size_qp
[0x10];
596 u8 atomic_size_dc
[0x10];
598 u8 reserved_7
[0x720];
601 struct mlx5_ifc_odp_cap_bits
{
609 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
611 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
613 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
615 u8 reserved_3
[0x720];
619 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
620 MLX5_WQ_TYPE_CYCLIC
= 0x1,
621 MLX5_WQ_TYPE_STRQ
= 0x2,
625 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
626 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
630 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
631 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
632 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
633 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
634 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
638 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
639 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
640 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
641 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
642 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
643 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
647 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
648 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
652 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
653 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
654 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
658 MLX5_CAP_PORT_TYPE_IB
= 0x0,
659 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
662 struct mlx5_ifc_cmd_hca_cap_bits
{
665 u8 log_max_srq_sz
[0x8];
666 u8 log_max_qp_sz
[0x8];
675 u8 log_max_cq_sz
[0x8];
679 u8 log_max_eq_sz
[0x8];
681 u8 log_max_mkey
[0x6];
685 u8 max_indirection
[0x8];
687 u8 log_max_mrw_sz
[0x7];
689 u8 log_max_bsf_list_size
[0x6];
691 u8 log_max_klm_list_size
[0x6];
694 u8 log_max_ra_req_dc
[0x6];
696 u8 log_max_ra_res_dc
[0x6];
699 u8 log_max_ra_req_qp
[0x6];
701 u8 log_max_ra_res_qp
[0x6];
704 u8 cc_query_allowed
[0x1];
705 u8 cc_modify_allowed
[0x1];
707 u8 gid_table_size
[0x10];
709 u8 out_of_seq_cnt
[0x1];
710 u8 vport_counters
[0x1];
713 u8 pkey_table_size
[0x10];
715 u8 vport_group_manager
[0x1];
716 u8 vhca_group_manager
[0x1];
721 u8 nic_flow_table
[0x1];
722 u8 eswitch_flow_table
[0x1];
725 u8 local_ca_ack_delay
[0x5];
732 u8 reserved_21
[0x18];
734 u8 stat_rate_support
[0x10];
738 u8 compact_address_vector
[0x1];
740 u8 drain_sigerr
[0x1];
741 u8 cmdif_checksum
[0x2];
744 u8 wq_signature
[0x1];
745 u8 sctr_data_cqe
[0x1];
752 u8 eth_net_offloads
[0x1];
759 u8 cq_moderation
[0x1];
765 u8 scqe_break_moderation
[0x1];
786 u8 pad_tx_eth_packet
[0x1];
788 u8 log_bf_reg_size
[0x5];
789 u8 reserved_38
[0x10];
791 u8 reserved_39
[0x10];
792 u8 max_wqe_sz_sq
[0x10];
794 u8 reserved_40
[0x10];
795 u8 max_wqe_sz_rq
[0x10];
797 u8 reserved_41
[0x10];
798 u8 max_wqe_sz_sq_dc
[0x10];
803 u8 reserved_43
[0x18];
807 u8 log_max_transport_domain
[0x5];
811 u8 log_max_xrcd
[0x5];
813 u8 reserved_47
[0x20];
824 u8 basic_cyclic_rcv_wqe
[0x1];
830 u8 log_max_rqt_size
[0x5];
832 u8 log_max_tis_per_sq
[0x5];
835 u8 log_max_stride_sz_rq
[0x5];
837 u8 log_min_stride_sz_rq
[0x5];
839 u8 log_max_stride_sz_sq
[0x5];
841 u8 log_min_stride_sz_sq
[0x5];
843 u8 reserved_60
[0x1b];
844 u8 log_max_wq_sz
[0x5];
846 u8 nic_vport_change_event
[0x1];
848 u8 log_max_vlan_list
[0x5];
850 u8 log_max_current_mc_list
[0x5];
852 u8 log_max_current_uc_list
[0x5];
854 u8 reserved_64
[0x80];
857 u8 log_max_l2_table
[0x5];
859 u8 log_uar_page_sz
[0x10];
861 u8 reserved_67
[0x20];
862 u8 device_frequency_mhz
[0x20];
863 u8 device_frequency_khz
[0x20];
864 u8 reserved_68
[0x5f];
867 u8 cqe_zip_timeout
[0x10];
868 u8 cqe_zip_max_num
[0x10];
870 u8 reserved_69
[0x220];
873 enum mlx5_flow_destination_type
{
874 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
875 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
876 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
879 struct mlx5_ifc_dest_format_struct_bits
{
880 u8 destination_type
[0x8];
881 u8 destination_id
[0x18];
886 struct mlx5_ifc_fte_match_param_bits
{
887 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
889 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
891 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
893 u8 reserved_0
[0xa00];
897 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
898 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
899 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
900 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
901 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
904 struct mlx5_ifc_rx_hash_field_select_bits
{
905 u8 l3_prot_type
[0x1];
906 u8 l4_prot_type
[0x1];
907 u8 selected_fields
[0x1e];
911 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
912 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
916 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
917 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
920 struct mlx5_ifc_wq_bits
{
922 u8 wq_signature
[0x1];
923 u8 end_padding_mode
[0x2];
927 u8 hds_skip_first_sge
[0x1];
928 u8 log2_hds_buf_size
[0x3];
946 u8 log_wq_stride
[0x4];
948 u8 log_wq_pg_sz
[0x5];
952 u8 reserved_7
[0x4e0];
954 struct mlx5_ifc_cmd_pas_bits pas
[0];
957 struct mlx5_ifc_rq_num_bits
{
962 struct mlx5_ifc_mac_address_layout_bits
{
964 u8 mac_addr_47_32
[0x10];
966 u8 mac_addr_31_0
[0x20];
969 struct mlx5_ifc_vlan_layout_bits
{
976 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
979 u8 min_time_between_cnps
[0x20];
984 u8 cnp_802p_prio
[0x3];
986 u8 reserved_3
[0x720];
989 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
993 u8 clamp_tgt_rate
[0x1];
995 u8 clamp_tgt_rate_after_time_inc
[0x1];
1000 u8 rpg_time_reset
[0x20];
1002 u8 rpg_byte_reset
[0x20];
1004 u8 rpg_threshold
[0x20];
1006 u8 rpg_max_rate
[0x20];
1008 u8 rpg_ai_rate
[0x20];
1010 u8 rpg_hai_rate
[0x20];
1014 u8 rpg_min_dec_fac
[0x20];
1016 u8 rpg_min_rate
[0x20];
1018 u8 reserved_5
[0xe0];
1020 u8 rate_to_set_on_first_cnp
[0x20];
1024 u8 dce_tcp_rtt
[0x20];
1026 u8 rate_reduce_monitor_period
[0x20];
1028 u8 reserved_6
[0x20];
1030 u8 initial_alpha_value
[0x20];
1032 u8 reserved_7
[0x4a0];
1035 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1036 u8 reserved_0
[0x80];
1038 u8 rppp_max_rps
[0x20];
1040 u8 rpg_time_reset
[0x20];
1042 u8 rpg_byte_reset
[0x20];
1044 u8 rpg_threshold
[0x20];
1046 u8 rpg_max_rate
[0x20];
1048 u8 rpg_ai_rate
[0x20];
1050 u8 rpg_hai_rate
[0x20];
1054 u8 rpg_min_dec_fac
[0x20];
1056 u8 rpg_min_rate
[0x20];
1058 u8 reserved_1
[0x640];
1062 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1063 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1064 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1067 struct mlx5_ifc_resize_field_select_bits
{
1068 u8 resize_field_select
[0x20];
1072 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1073 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1074 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1075 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1078 struct mlx5_ifc_modify_field_select_bits
{
1079 u8 modify_field_select
[0x20];
1082 struct mlx5_ifc_field_select_r_roce_np_bits
{
1083 u8 field_select_r_roce_np
[0x20];
1086 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1087 u8 field_select_r_roce_rp
[0x20];
1091 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1092 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1093 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1094 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1095 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1096 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1097 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1098 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1099 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1100 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1103 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1104 u8 field_select_8021qaurp
[0x20];
1107 struct mlx5_ifc_phys_layer_cntrs_bits
{
1108 u8 time_since_last_clear_high
[0x20];
1110 u8 time_since_last_clear_low
[0x20];
1112 u8 symbol_errors_high
[0x20];
1114 u8 symbol_errors_low
[0x20];
1116 u8 sync_headers_errors_high
[0x20];
1118 u8 sync_headers_errors_low
[0x20];
1120 u8 edpl_bip_errors_lane0_high
[0x20];
1122 u8 edpl_bip_errors_lane0_low
[0x20];
1124 u8 edpl_bip_errors_lane1_high
[0x20];
1126 u8 edpl_bip_errors_lane1_low
[0x20];
1128 u8 edpl_bip_errors_lane2_high
[0x20];
1130 u8 edpl_bip_errors_lane2_low
[0x20];
1132 u8 edpl_bip_errors_lane3_high
[0x20];
1134 u8 edpl_bip_errors_lane3_low
[0x20];
1136 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1138 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1140 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1142 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1144 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1146 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1148 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1150 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1152 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1154 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1156 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1158 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1160 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1162 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1164 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1166 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1168 u8 rs_fec_corrected_blocks_high
[0x20];
1170 u8 rs_fec_corrected_blocks_low
[0x20];
1172 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1174 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1176 u8 rs_fec_no_errors_blocks_high
[0x20];
1178 u8 rs_fec_no_errors_blocks_low
[0x20];
1180 u8 rs_fec_single_error_blocks_high
[0x20];
1182 u8 rs_fec_single_error_blocks_low
[0x20];
1184 u8 rs_fec_corrected_symbols_total_high
[0x20];
1186 u8 rs_fec_corrected_symbols_total_low
[0x20];
1188 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1190 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1192 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1194 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1196 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1198 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1200 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1202 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1204 u8 link_down_events
[0x20];
1206 u8 successful_recovery_events
[0x20];
1208 u8 reserved_0
[0x180];
1211 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits
{
1212 u8 transmit_queue_high
[0x20];
1214 u8 transmit_queue_low
[0x20];
1216 u8 reserved_0
[0x780];
1219 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1220 u8 rx_octets_high
[0x20];
1222 u8 rx_octets_low
[0x20];
1224 u8 reserved_0
[0xc0];
1226 u8 rx_frames_high
[0x20];
1228 u8 rx_frames_low
[0x20];
1230 u8 tx_octets_high
[0x20];
1232 u8 tx_octets_low
[0x20];
1234 u8 reserved_1
[0xc0];
1236 u8 tx_frames_high
[0x20];
1238 u8 tx_frames_low
[0x20];
1240 u8 rx_pause_high
[0x20];
1242 u8 rx_pause_low
[0x20];
1244 u8 rx_pause_duration_high
[0x20];
1246 u8 rx_pause_duration_low
[0x20];
1248 u8 tx_pause_high
[0x20];
1250 u8 tx_pause_low
[0x20];
1252 u8 tx_pause_duration_high
[0x20];
1254 u8 tx_pause_duration_low
[0x20];
1256 u8 rx_pause_transition_high
[0x20];
1258 u8 rx_pause_transition_low
[0x20];
1260 u8 reserved_2
[0x400];
1263 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
1264 u8 port_transmit_wait_high
[0x20];
1266 u8 port_transmit_wait_low
[0x20];
1268 u8 reserved_0
[0x780];
1271 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
1272 u8 dot3stats_alignment_errors_high
[0x20];
1274 u8 dot3stats_alignment_errors_low
[0x20];
1276 u8 dot3stats_fcs_errors_high
[0x20];
1278 u8 dot3stats_fcs_errors_low
[0x20];
1280 u8 dot3stats_single_collision_frames_high
[0x20];
1282 u8 dot3stats_single_collision_frames_low
[0x20];
1284 u8 dot3stats_multiple_collision_frames_high
[0x20];
1286 u8 dot3stats_multiple_collision_frames_low
[0x20];
1288 u8 dot3stats_sqe_test_errors_high
[0x20];
1290 u8 dot3stats_sqe_test_errors_low
[0x20];
1292 u8 dot3stats_deferred_transmissions_high
[0x20];
1294 u8 dot3stats_deferred_transmissions_low
[0x20];
1296 u8 dot3stats_late_collisions_high
[0x20];
1298 u8 dot3stats_late_collisions_low
[0x20];
1300 u8 dot3stats_excessive_collisions_high
[0x20];
1302 u8 dot3stats_excessive_collisions_low
[0x20];
1304 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
1306 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
1308 u8 dot3stats_carrier_sense_errors_high
[0x20];
1310 u8 dot3stats_carrier_sense_errors_low
[0x20];
1312 u8 dot3stats_frame_too_longs_high
[0x20];
1314 u8 dot3stats_frame_too_longs_low
[0x20];
1316 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
1318 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
1320 u8 dot3stats_symbol_errors_high
[0x20];
1322 u8 dot3stats_symbol_errors_low
[0x20];
1324 u8 dot3control_in_unknown_opcodes_high
[0x20];
1326 u8 dot3control_in_unknown_opcodes_low
[0x20];
1328 u8 dot3in_pause_frames_high
[0x20];
1330 u8 dot3in_pause_frames_low
[0x20];
1332 u8 dot3out_pause_frames_high
[0x20];
1334 u8 dot3out_pause_frames_low
[0x20];
1336 u8 reserved_0
[0x3c0];
1339 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
1340 u8 ether_stats_drop_events_high
[0x20];
1342 u8 ether_stats_drop_events_low
[0x20];
1344 u8 ether_stats_octets_high
[0x20];
1346 u8 ether_stats_octets_low
[0x20];
1348 u8 ether_stats_pkts_high
[0x20];
1350 u8 ether_stats_pkts_low
[0x20];
1352 u8 ether_stats_broadcast_pkts_high
[0x20];
1354 u8 ether_stats_broadcast_pkts_low
[0x20];
1356 u8 ether_stats_multicast_pkts_high
[0x20];
1358 u8 ether_stats_multicast_pkts_low
[0x20];
1360 u8 ether_stats_crc_align_errors_high
[0x20];
1362 u8 ether_stats_crc_align_errors_low
[0x20];
1364 u8 ether_stats_undersize_pkts_high
[0x20];
1366 u8 ether_stats_undersize_pkts_low
[0x20];
1368 u8 ether_stats_oversize_pkts_high
[0x20];
1370 u8 ether_stats_oversize_pkts_low
[0x20];
1372 u8 ether_stats_fragments_high
[0x20];
1374 u8 ether_stats_fragments_low
[0x20];
1376 u8 ether_stats_jabbers_high
[0x20];
1378 u8 ether_stats_jabbers_low
[0x20];
1380 u8 ether_stats_collisions_high
[0x20];
1382 u8 ether_stats_collisions_low
[0x20];
1384 u8 ether_stats_pkts64octets_high
[0x20];
1386 u8 ether_stats_pkts64octets_low
[0x20];
1388 u8 ether_stats_pkts65to127octets_high
[0x20];
1390 u8 ether_stats_pkts65to127octets_low
[0x20];
1392 u8 ether_stats_pkts128to255octets_high
[0x20];
1394 u8 ether_stats_pkts128to255octets_low
[0x20];
1396 u8 ether_stats_pkts256to511octets_high
[0x20];
1398 u8 ether_stats_pkts256to511octets_low
[0x20];
1400 u8 ether_stats_pkts512to1023octets_high
[0x20];
1402 u8 ether_stats_pkts512to1023octets_low
[0x20];
1404 u8 ether_stats_pkts1024to1518octets_high
[0x20];
1406 u8 ether_stats_pkts1024to1518octets_low
[0x20];
1408 u8 ether_stats_pkts1519to2047octets_high
[0x20];
1410 u8 ether_stats_pkts1519to2047octets_low
[0x20];
1412 u8 ether_stats_pkts2048to4095octets_high
[0x20];
1414 u8 ether_stats_pkts2048to4095octets_low
[0x20];
1416 u8 ether_stats_pkts4096to8191octets_high
[0x20];
1418 u8 ether_stats_pkts4096to8191octets_low
[0x20];
1420 u8 ether_stats_pkts8192to10239octets_high
[0x20];
1422 u8 ether_stats_pkts8192to10239octets_low
[0x20];
1424 u8 reserved_0
[0x280];
1427 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
1428 u8 if_in_octets_high
[0x20];
1430 u8 if_in_octets_low
[0x20];
1432 u8 if_in_ucast_pkts_high
[0x20];
1434 u8 if_in_ucast_pkts_low
[0x20];
1436 u8 if_in_discards_high
[0x20];
1438 u8 if_in_discards_low
[0x20];
1440 u8 if_in_errors_high
[0x20];
1442 u8 if_in_errors_low
[0x20];
1444 u8 if_in_unknown_protos_high
[0x20];
1446 u8 if_in_unknown_protos_low
[0x20];
1448 u8 if_out_octets_high
[0x20];
1450 u8 if_out_octets_low
[0x20];
1452 u8 if_out_ucast_pkts_high
[0x20];
1454 u8 if_out_ucast_pkts_low
[0x20];
1456 u8 if_out_discards_high
[0x20];
1458 u8 if_out_discards_low
[0x20];
1460 u8 if_out_errors_high
[0x20];
1462 u8 if_out_errors_low
[0x20];
1464 u8 if_in_multicast_pkts_high
[0x20];
1466 u8 if_in_multicast_pkts_low
[0x20];
1468 u8 if_in_broadcast_pkts_high
[0x20];
1470 u8 if_in_broadcast_pkts_low
[0x20];
1472 u8 if_out_multicast_pkts_high
[0x20];
1474 u8 if_out_multicast_pkts_low
[0x20];
1476 u8 if_out_broadcast_pkts_high
[0x20];
1478 u8 if_out_broadcast_pkts_low
[0x20];
1480 u8 reserved_0
[0x480];
1483 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
1484 u8 a_frames_transmitted_ok_high
[0x20];
1486 u8 a_frames_transmitted_ok_low
[0x20];
1488 u8 a_frames_received_ok_high
[0x20];
1490 u8 a_frames_received_ok_low
[0x20];
1492 u8 a_frame_check_sequence_errors_high
[0x20];
1494 u8 a_frame_check_sequence_errors_low
[0x20];
1496 u8 a_alignment_errors_high
[0x20];
1498 u8 a_alignment_errors_low
[0x20];
1500 u8 a_octets_transmitted_ok_high
[0x20];
1502 u8 a_octets_transmitted_ok_low
[0x20];
1504 u8 a_octets_received_ok_high
[0x20];
1506 u8 a_octets_received_ok_low
[0x20];
1508 u8 a_multicast_frames_xmitted_ok_high
[0x20];
1510 u8 a_multicast_frames_xmitted_ok_low
[0x20];
1512 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
1514 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
1516 u8 a_multicast_frames_received_ok_high
[0x20];
1518 u8 a_multicast_frames_received_ok_low
[0x20];
1520 u8 a_broadcast_frames_received_ok_high
[0x20];
1522 u8 a_broadcast_frames_received_ok_low
[0x20];
1524 u8 a_in_range_length_errors_high
[0x20];
1526 u8 a_in_range_length_errors_low
[0x20];
1528 u8 a_out_of_range_length_field_high
[0x20];
1530 u8 a_out_of_range_length_field_low
[0x20];
1532 u8 a_frame_too_long_errors_high
[0x20];
1534 u8 a_frame_too_long_errors_low
[0x20];
1536 u8 a_symbol_error_during_carrier_high
[0x20];
1538 u8 a_symbol_error_during_carrier_low
[0x20];
1540 u8 a_mac_control_frames_transmitted_high
[0x20];
1542 u8 a_mac_control_frames_transmitted_low
[0x20];
1544 u8 a_mac_control_frames_received_high
[0x20];
1546 u8 a_mac_control_frames_received_low
[0x20];
1548 u8 a_unsupported_opcodes_received_high
[0x20];
1550 u8 a_unsupported_opcodes_received_low
[0x20];
1552 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
1554 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
1556 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
1558 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
1560 u8 reserved_0
[0x300];
1563 struct mlx5_ifc_cmd_inter_comp_event_bits
{
1564 u8 command_completion_vector
[0x20];
1566 u8 reserved_0
[0xc0];
1569 struct mlx5_ifc_stall_vl_event_bits
{
1570 u8 reserved_0
[0x18];
1575 u8 reserved_2
[0xa0];
1578 struct mlx5_ifc_db_bf_congestion_event_bits
{
1579 u8 event_subtype
[0x8];
1581 u8 congestion_level
[0x8];
1584 u8 reserved_2
[0xa0];
1587 struct mlx5_ifc_gpio_event_bits
{
1588 u8 reserved_0
[0x60];
1590 u8 gpio_event_hi
[0x20];
1592 u8 gpio_event_lo
[0x20];
1594 u8 reserved_1
[0x40];
1597 struct mlx5_ifc_port_state_change_event_bits
{
1598 u8 reserved_0
[0x40];
1601 u8 reserved_1
[0x1c];
1603 u8 reserved_2
[0x80];
1606 struct mlx5_ifc_dropped_packet_logged_bits
{
1607 u8 reserved_0
[0xe0];
1611 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
1612 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
1615 struct mlx5_ifc_cq_error_bits
{
1619 u8 reserved_1
[0x20];
1621 u8 reserved_2
[0x18];
1624 u8 reserved_3
[0x80];
1627 struct mlx5_ifc_rdma_page_fault_event_bits
{
1628 u8 bytes_committed
[0x20];
1632 u8 reserved_0
[0x10];
1633 u8 packet_len
[0x10];
1635 u8 rdma_op_len
[0x20];
1646 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
1647 u8 bytes_committed
[0x20];
1649 u8 reserved_0
[0x10];
1652 u8 reserved_1
[0x10];
1655 u8 reserved_2
[0x60];
1664 struct mlx5_ifc_qp_events_bits
{
1665 u8 reserved_0
[0xa0];
1668 u8 reserved_1
[0x18];
1671 u8 qpn_rqn_sqn
[0x18];
1674 struct mlx5_ifc_dct_events_bits
{
1675 u8 reserved_0
[0xc0];
1678 u8 dct_number
[0x18];
1681 struct mlx5_ifc_comp_event_bits
{
1682 u8 reserved_0
[0xc0];
1689 MLX5_QPC_STATE_RST
= 0x0,
1690 MLX5_QPC_STATE_INIT
= 0x1,
1691 MLX5_QPC_STATE_RTR
= 0x2,
1692 MLX5_QPC_STATE_RTS
= 0x3,
1693 MLX5_QPC_STATE_SQER
= 0x4,
1694 MLX5_QPC_STATE_ERR
= 0x6,
1695 MLX5_QPC_STATE_SQD
= 0x7,
1696 MLX5_QPC_STATE_SUSPENDED
= 0x9,
1700 MLX5_QPC_ST_RC
= 0x0,
1701 MLX5_QPC_ST_UC
= 0x1,
1702 MLX5_QPC_ST_UD
= 0x2,
1703 MLX5_QPC_ST_XRC
= 0x3,
1704 MLX5_QPC_ST_DCI
= 0x5,
1705 MLX5_QPC_ST_QP0
= 0x7,
1706 MLX5_QPC_ST_QP1
= 0x8,
1707 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
1708 MLX5_QPC_ST_REG_UMR
= 0xc,
1712 MLX5_QPC_PM_STATE_ARMED
= 0x0,
1713 MLX5_QPC_PM_STATE_REARM
= 0x1,
1714 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
1715 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
1719 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
1720 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
1724 MLX5_QPC_MTU_256_BYTES
= 0x1,
1725 MLX5_QPC_MTU_512_BYTES
= 0x2,
1726 MLX5_QPC_MTU_1K_BYTES
= 0x3,
1727 MLX5_QPC_MTU_2K_BYTES
= 0x4,
1728 MLX5_QPC_MTU_4K_BYTES
= 0x5,
1729 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
1733 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
1734 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
1735 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
1736 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
1737 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
1738 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
1739 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
1740 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
1744 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
1745 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
1746 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
1750 MLX5_QPC_CS_RES_DISABLE
= 0x0,
1751 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
1752 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
1755 struct mlx5_ifc_qpc_bits
{
1762 u8 end_padding_mode
[0x2];
1765 u8 wq_signature
[0x1];
1766 u8 block_lb_mc
[0x1];
1767 u8 atomic_like_write_en
[0x1];
1768 u8 latency_sensitive
[0x1];
1770 u8 drain_sigerr
[0x1];
1775 u8 log_msg_max
[0x5];
1777 u8 log_rq_size
[0x4];
1778 u8 log_rq_stride
[0x3];
1780 u8 log_sq_size
[0x4];
1785 u8 counter_set_id
[0x8];
1789 u8 user_index
[0x18];
1791 u8 reserved_10
[0x3];
1792 u8 log_page_size
[0x5];
1793 u8 remote_qpn
[0x18];
1795 struct mlx5_ifc_ads_bits primary_address_path
;
1797 struct mlx5_ifc_ads_bits secondary_address_path
;
1799 u8 log_ack_req_freq
[0x4];
1800 u8 reserved_11
[0x4];
1801 u8 log_sra_max
[0x3];
1802 u8 reserved_12
[0x2];
1803 u8 retry_count
[0x3];
1805 u8 reserved_13
[0x1];
1807 u8 cur_rnr_retry
[0x3];
1808 u8 cur_retry_count
[0x3];
1809 u8 reserved_14
[0x5];
1811 u8 reserved_15
[0x20];
1813 u8 reserved_16
[0x8];
1814 u8 next_send_psn
[0x18];
1816 u8 reserved_17
[0x8];
1819 u8 reserved_18
[0x40];
1821 u8 reserved_19
[0x8];
1822 u8 last_acked_psn
[0x18];
1824 u8 reserved_20
[0x8];
1827 u8 reserved_21
[0x8];
1828 u8 log_rra_max
[0x3];
1829 u8 reserved_22
[0x1];
1830 u8 atomic_mode
[0x4];
1834 u8 reserved_23
[0x1];
1835 u8 page_offset
[0x6];
1836 u8 reserved_24
[0x3];
1837 u8 cd_slave_receive
[0x1];
1838 u8 cd_slave_send
[0x1];
1841 u8 reserved_25
[0x3];
1842 u8 min_rnr_nak
[0x5];
1843 u8 next_rcv_psn
[0x18];
1845 u8 reserved_26
[0x8];
1848 u8 reserved_27
[0x8];
1855 u8 reserved_28
[0x5];
1859 u8 reserved_29
[0x8];
1862 u8 hw_sq_wqebb_counter
[0x10];
1863 u8 sw_sq_wqebb_counter
[0x10];
1865 u8 hw_rq_counter
[0x20];
1867 u8 sw_rq_counter
[0x20];
1869 u8 reserved_30
[0x20];
1871 u8 reserved_31
[0xf];
1876 u8 dc_access_key
[0x40];
1878 u8 reserved_32
[0xc0];
1881 struct mlx5_ifc_roce_addr_layout_bits
{
1882 u8 source_l3_address
[16][0x8];
1887 u8 source_mac_47_32
[0x10];
1889 u8 source_mac_31_0
[0x20];
1891 u8 reserved_1
[0x14];
1892 u8 roce_l3_type
[0x4];
1893 u8 roce_version
[0x8];
1895 u8 reserved_2
[0x20];
1898 union mlx5_ifc_hca_cap_union_bits
{
1899 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
1900 struct mlx5_ifc_odp_cap_bits odp_cap
;
1901 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
1902 struct mlx5_ifc_roce_cap_bits roce_cap
;
1903 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
1904 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
1905 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
1906 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
1907 u8 reserved_0
[0x8000];
1911 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
1912 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
1913 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
1916 struct mlx5_ifc_flow_context_bits
{
1917 u8 reserved_0
[0x20];
1924 u8 reserved_2
[0x10];
1928 u8 destination_list_size
[0x18];
1930 u8 reserved_4
[0x160];
1932 struct mlx5_ifc_fte_match_param_bits match_value
;
1934 u8 reserved_5
[0x600];
1936 struct mlx5_ifc_dest_format_struct_bits destination
[0];
1940 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
1941 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
1944 struct mlx5_ifc_xrc_srqc_bits
{
1946 u8 log_xrc_srq_size
[0x4];
1947 u8 reserved_0
[0x18];
1949 u8 wq_signature
[0x1];
1953 u8 basic_cyclic_rcv_wqe
[0x1];
1954 u8 log_rq_stride
[0x3];
1957 u8 page_offset
[0x6];
1961 u8 reserved_3
[0x20];
1963 u8 user_index_equal_xrc_srqn
[0x1];
1965 u8 log_page_size
[0x6];
1966 u8 user_index
[0x18];
1968 u8 reserved_5
[0x20];
1976 u8 reserved_7
[0x40];
1978 u8 db_record_addr_h
[0x20];
1980 u8 db_record_addr_l
[0x1e];
1983 u8 reserved_9
[0x80];
1986 struct mlx5_ifc_traffic_counter_bits
{
1992 struct mlx5_ifc_tisc_bits
{
1995 u8 reserved_1
[0x10];
1997 u8 reserved_2
[0x100];
2000 u8 transport_domain
[0x18];
2002 u8 reserved_4
[0x3c0];
2006 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2007 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2011 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2012 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2016 MLX5_RX_HASH_FN_NONE
= 0x0,
2017 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2018 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2022 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
= 0x1,
2023 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_
= 0x2,
2026 struct mlx5_ifc_tirc_bits
{
2027 u8 reserved_0
[0x20];
2030 u8 reserved_1
[0x1c];
2032 u8 reserved_2
[0x40];
2035 u8 lro_timeout_period_usecs
[0x10];
2036 u8 lro_enable_mask
[0x4];
2037 u8 lro_max_ip_payload_size
[0x8];
2039 u8 reserved_4
[0x40];
2042 u8 inline_rqn
[0x18];
2044 u8 rx_hash_symmetric
[0x1];
2046 u8 tunneled_offload_en
[0x1];
2048 u8 indirect_table
[0x18];
2052 u8 self_lb_block
[0x2];
2053 u8 transport_domain
[0x18];
2055 u8 rx_hash_toeplitz_key
[10][0x20];
2057 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2059 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2061 u8 reserved_9
[0x4c0];
2065 MLX5_SRQC_STATE_GOOD
= 0x0,
2066 MLX5_SRQC_STATE_ERROR
= 0x1,
2069 struct mlx5_ifc_srqc_bits
{
2071 u8 log_srq_size
[0x4];
2072 u8 reserved_0
[0x18];
2074 u8 wq_signature
[0x1];
2079 u8 log_rq_stride
[0x3];
2082 u8 page_offset
[0x6];
2086 u8 reserved_4
[0x20];
2089 u8 log_page_size
[0x6];
2090 u8 reserved_6
[0x18];
2092 u8 reserved_7
[0x20];
2100 u8 reserved_9
[0x40];
2104 u8 reserved_10
[0x80];
2108 MLX5_SQC_STATE_RST
= 0x0,
2109 MLX5_SQC_STATE_RDY
= 0x1,
2110 MLX5_SQC_STATE_ERR
= 0x3,
2113 struct mlx5_ifc_sqc_bits
{
2117 u8 flush_in_error_en
[0x1];
2120 u8 reserved_1
[0x14];
2123 u8 user_index
[0x18];
2128 u8 reserved_4
[0xa0];
2130 u8 tis_lst_sz
[0x10];
2131 u8 reserved_5
[0x10];
2133 u8 reserved_6
[0x40];
2138 struct mlx5_ifc_wq_bits wq
;
2141 struct mlx5_ifc_rqtc_bits
{
2142 u8 reserved_0
[0xa0];
2144 u8 reserved_1
[0x10];
2145 u8 rqt_max_size
[0x10];
2147 u8 reserved_2
[0x10];
2148 u8 rqt_actual_size
[0x10];
2150 u8 reserved_3
[0x6a0];
2152 struct mlx5_ifc_rq_num_bits rq_num
[0];
2156 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
2157 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
2161 MLX5_RQC_STATE_RST
= 0x0,
2162 MLX5_RQC_STATE_RDY
= 0x1,
2163 MLX5_RQC_STATE_ERR
= 0x3,
2166 struct mlx5_ifc_rqc_bits
{
2170 u8 mem_rq_type
[0x4];
2173 u8 flush_in_error_en
[0x1];
2174 u8 reserved_2
[0x12];
2177 u8 user_index
[0x18];
2182 u8 counter_set_id
[0x8];
2183 u8 reserved_5
[0x18];
2188 u8 reserved_7
[0xe0];
2190 struct mlx5_ifc_wq_bits wq
;
2194 MLX5_RMPC_STATE_RDY
= 0x1,
2195 MLX5_RMPC_STATE_ERR
= 0x3,
2198 struct mlx5_ifc_rmpc_bits
{
2201 u8 reserved_1
[0x14];
2203 u8 basic_cyclic_rcv_wqe
[0x1];
2204 u8 reserved_2
[0x1f];
2206 u8 reserved_3
[0x140];
2208 struct mlx5_ifc_wq_bits wq
;
2211 struct mlx5_ifc_nic_vport_context_bits
{
2212 u8 reserved_0
[0x1f];
2215 u8 arm_change_event
[0x1];
2216 u8 reserved_1
[0x1a];
2217 u8 event_on_mtu
[0x1];
2218 u8 event_on_promisc_change
[0x1];
2219 u8 event_on_vlan_change
[0x1];
2220 u8 event_on_mc_address_change
[0x1];
2221 u8 event_on_uc_address_change
[0x1];
2223 u8 reserved_2
[0xf0];
2227 u8 system_image_guid
[0x40];
2231 u8 reserved_3
[0x140];
2232 u8 qkey_violation_counter
[0x10];
2233 u8 reserved_4
[0x430];
2237 u8 promisc_all
[0x1];
2239 u8 allowed_list_type
[0x3];
2241 u8 allowed_list_size
[0xc];
2243 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
2245 u8 reserved_7
[0x20];
2247 u8 current_uc_mac_address
[0][0x40];
2251 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
2252 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
2253 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
2256 struct mlx5_ifc_mkc_bits
{
2260 u8 small_fence_on_rdma_read_response
[0x1];
2267 u8 access_mode
[0x2];
2273 u8 reserved_3
[0x20];
2279 u8 expected_sigerr_count
[0x1];
2284 u8 start_addr
[0x40];
2288 u8 bsf_octword_size
[0x20];
2290 u8 reserved_6
[0x80];
2292 u8 translations_octword_size
[0x20];
2294 u8 reserved_7
[0x1b];
2295 u8 log_page_size
[0x5];
2297 u8 reserved_8
[0x20];
2300 struct mlx5_ifc_pkey_bits
{
2301 u8 reserved_0
[0x10];
2305 struct mlx5_ifc_array128_auto_bits
{
2306 u8 array128_auto
[16][0x8];
2309 struct mlx5_ifc_hca_vport_context_bits
{
2310 u8 field_select
[0x20];
2312 u8 reserved_0
[0xe0];
2314 u8 sm_virt_aware
[0x1];
2317 u8 grh_required
[0x1];
2319 u8 port_physical_state
[0x4];
2320 u8 vport_state_policy
[0x4];
2322 u8 vport_state
[0x4];
2324 u8 reserved_2
[0x20];
2326 u8 system_image_guid
[0x40];
2334 u8 cap_mask1_field_select
[0x20];
2338 u8 cap_mask2_field_select
[0x20];
2340 u8 reserved_3
[0x80];
2344 u8 init_type_reply
[0x4];
2346 u8 subnet_timeout
[0x5];
2352 u8 qkey_violation_counter
[0x10];
2353 u8 pkey_violation_counter
[0x10];
2355 u8 reserved_6
[0xca0];
2358 struct mlx5_ifc_esw_vport_context_bits
{
2360 u8 vport_svlan_strip
[0x1];
2361 u8 vport_cvlan_strip
[0x1];
2362 u8 vport_svlan_insert
[0x1];
2363 u8 vport_cvlan_insert
[0x2];
2364 u8 reserved_1
[0x18];
2366 u8 reserved_2
[0x20];
2375 u8 reserved_3
[0x7a0];
2379 MLX5_EQC_STATUS_OK
= 0x0,
2380 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
2384 MLX5_EQC_ST_ARMED
= 0x9,
2385 MLX5_EQC_ST_FIRED
= 0xa,
2388 struct mlx5_ifc_eqc_bits
{
2397 u8 reserved_3
[0x20];
2399 u8 reserved_4
[0x14];
2400 u8 page_offset
[0x6];
2404 u8 log_eq_size
[0x5];
2407 u8 reserved_7
[0x20];
2409 u8 reserved_8
[0x18];
2413 u8 log_page_size
[0x5];
2414 u8 reserved_10
[0x18];
2416 u8 reserved_11
[0x60];
2418 u8 reserved_12
[0x8];
2419 u8 consumer_counter
[0x18];
2421 u8 reserved_13
[0x8];
2422 u8 producer_counter
[0x18];
2424 u8 reserved_14
[0x80];
2428 MLX5_DCTC_STATE_ACTIVE
= 0x0,
2429 MLX5_DCTC_STATE_DRAINING
= 0x1,
2430 MLX5_DCTC_STATE_DRAINED
= 0x2,
2434 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
2435 MLX5_DCTC_CS_RES_NA
= 0x1,
2436 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
2440 MLX5_DCTC_MTU_256_BYTES
= 0x1,
2441 MLX5_DCTC_MTU_512_BYTES
= 0x2,
2442 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
2443 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
2444 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
2447 struct mlx5_ifc_dctc_bits
{
2450 u8 reserved_1
[0x18];
2453 u8 user_index
[0x18];
2458 u8 counter_set_id
[0x8];
2459 u8 atomic_mode
[0x4];
2463 u8 atomic_like_write_en
[0x1];
2464 u8 latency_sensitive
[0x1];
2472 u8 min_rnr_nak
[0x5];
2482 u8 reserved_10
[0x4];
2483 u8 flow_label
[0x14];
2485 u8 dc_access_key
[0x40];
2487 u8 reserved_11
[0x5];
2490 u8 pkey_index
[0x10];
2492 u8 reserved_12
[0x8];
2493 u8 my_addr_index
[0x8];
2494 u8 reserved_13
[0x8];
2497 u8 dc_access_key_violation_count
[0x20];
2499 u8 reserved_14
[0x14];
2505 u8 reserved_15
[0x40];
2509 MLX5_CQC_STATUS_OK
= 0x0,
2510 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
2511 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
2515 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
2516 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
2520 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
2521 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
2522 MLX5_CQC_ST_FIRED
= 0xa,
2525 struct mlx5_ifc_cqc_bits
{
2531 u8 scqe_break_moderation_en
[0x1];
2535 u8 mini_cqe_res_format
[0x2];
2539 u8 reserved_4
[0x20];
2541 u8 reserved_5
[0x14];
2542 u8 page_offset
[0x6];
2546 u8 log_cq_size
[0x5];
2551 u8 cq_max_count
[0x10];
2553 u8 reserved_9
[0x18];
2556 u8 reserved_10
[0x3];
2557 u8 log_page_size
[0x5];
2558 u8 reserved_11
[0x18];
2560 u8 reserved_12
[0x20];
2562 u8 reserved_13
[0x8];
2563 u8 last_notified_index
[0x18];
2565 u8 reserved_14
[0x8];
2566 u8 last_solicit_index
[0x18];
2568 u8 reserved_15
[0x8];
2569 u8 consumer_counter
[0x18];
2571 u8 reserved_16
[0x8];
2572 u8 producer_counter
[0x18];
2574 u8 reserved_17
[0x40];
2579 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
2580 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
2581 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
2582 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
2583 u8 reserved_0
[0x800];
2586 struct mlx5_ifc_query_adapter_param_block_bits
{
2587 u8 reserved_0
[0xc0];
2590 u8 ieee_vendor_id
[0x18];
2592 u8 reserved_2
[0x10];
2593 u8 vsd_vendor_id
[0x10];
2597 u8 vsd_contd_psid
[16][0x8];
2600 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
2601 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
2602 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
2603 u8 reserved_0
[0x20];
2606 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
2607 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
2608 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
2609 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
2610 u8 reserved_0
[0x20];
2613 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
2614 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
2615 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
2616 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
2617 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
2618 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
2619 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
2620 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
2621 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
2622 u8 reserved_0
[0x7c0];
2625 union mlx5_ifc_event_auto_bits
{
2626 struct mlx5_ifc_comp_event_bits comp_event
;
2627 struct mlx5_ifc_dct_events_bits dct_events
;
2628 struct mlx5_ifc_qp_events_bits qp_events
;
2629 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
2630 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
2631 struct mlx5_ifc_cq_error_bits cq_error
;
2632 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
2633 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
2634 struct mlx5_ifc_gpio_event_bits gpio_event
;
2635 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
2636 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
2637 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
2638 u8 reserved_0
[0xe0];
2641 struct mlx5_ifc_health_buffer_bits
{
2642 u8 reserved_0
[0x100];
2644 u8 assert_existptr
[0x20];
2646 u8 assert_callra
[0x20];
2648 u8 reserved_1
[0x40];
2650 u8 fw_version
[0x20];
2654 u8 reserved_2
[0x20];
2656 u8 irisc_index
[0x8];
2661 struct mlx5_ifc_register_loopback_control_bits
{
2665 u8 reserved_1
[0x10];
2667 u8 reserved_2
[0x60];
2670 struct mlx5_ifc_teardown_hca_out_bits
{
2672 u8 reserved_0
[0x18];
2676 u8 reserved_1
[0x40];
2680 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
2681 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE
= 0x1,
2684 struct mlx5_ifc_teardown_hca_in_bits
{
2686 u8 reserved_0
[0x10];
2688 u8 reserved_1
[0x10];
2691 u8 reserved_2
[0x10];
2694 u8 reserved_3
[0x20];
2697 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
2699 u8 reserved_0
[0x18];
2703 u8 reserved_1
[0x40];
2706 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
2708 u8 reserved_0
[0x10];
2710 u8 reserved_1
[0x10];
2716 u8 reserved_3
[0x20];
2718 u8 opt_param_mask
[0x20];
2720 u8 reserved_4
[0x20];
2722 struct mlx5_ifc_qpc_bits qpc
;
2724 u8 reserved_5
[0x80];
2727 struct mlx5_ifc_sqd2rts_qp_out_bits
{
2729 u8 reserved_0
[0x18];
2733 u8 reserved_1
[0x40];
2736 struct mlx5_ifc_sqd2rts_qp_in_bits
{
2738 u8 reserved_0
[0x10];
2740 u8 reserved_1
[0x10];
2746 u8 reserved_3
[0x20];
2748 u8 opt_param_mask
[0x20];
2750 u8 reserved_4
[0x20];
2752 struct mlx5_ifc_qpc_bits qpc
;
2754 u8 reserved_5
[0x80];
2757 struct mlx5_ifc_set_roce_address_out_bits
{
2759 u8 reserved_0
[0x18];
2763 u8 reserved_1
[0x40];
2766 struct mlx5_ifc_set_roce_address_in_bits
{
2768 u8 reserved_0
[0x10];
2770 u8 reserved_1
[0x10];
2773 u8 roce_address_index
[0x10];
2774 u8 reserved_2
[0x10];
2776 u8 reserved_3
[0x20];
2778 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
2781 struct mlx5_ifc_set_mad_demux_out_bits
{
2783 u8 reserved_0
[0x18];
2787 u8 reserved_1
[0x40];
2791 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
2792 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
2795 struct mlx5_ifc_set_mad_demux_in_bits
{
2797 u8 reserved_0
[0x10];
2799 u8 reserved_1
[0x10];
2802 u8 reserved_2
[0x20];
2806 u8 reserved_4
[0x18];
2809 struct mlx5_ifc_set_l2_table_entry_out_bits
{
2811 u8 reserved_0
[0x18];
2815 u8 reserved_1
[0x40];
2818 struct mlx5_ifc_set_l2_table_entry_in_bits
{
2820 u8 reserved_0
[0x10];
2822 u8 reserved_1
[0x10];
2825 u8 reserved_2
[0x60];
2828 u8 table_index
[0x18];
2830 u8 reserved_4
[0x20];
2832 u8 reserved_5
[0x13];
2836 struct mlx5_ifc_mac_address_layout_bits mac_address
;
2838 u8 reserved_6
[0xc0];
2841 struct mlx5_ifc_set_issi_out_bits
{
2843 u8 reserved_0
[0x18];
2847 u8 reserved_1
[0x40];
2850 struct mlx5_ifc_set_issi_in_bits
{
2852 u8 reserved_0
[0x10];
2854 u8 reserved_1
[0x10];
2857 u8 reserved_2
[0x10];
2858 u8 current_issi
[0x10];
2860 u8 reserved_3
[0x20];
2863 struct mlx5_ifc_set_hca_cap_out_bits
{
2865 u8 reserved_0
[0x18];
2869 u8 reserved_1
[0x40];
2872 struct mlx5_ifc_set_hca_cap_in_bits
{
2874 u8 reserved_0
[0x10];
2876 u8 reserved_1
[0x10];
2879 u8 reserved_2
[0x40];
2881 union mlx5_ifc_hca_cap_union_bits capability
;
2885 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
2886 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
2887 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
2888 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
2891 struct mlx5_ifc_set_fte_out_bits
{
2893 u8 reserved_0
[0x18];
2897 u8 reserved_1
[0x40];
2900 struct mlx5_ifc_set_fte_in_bits
{
2902 u8 reserved_0
[0x10];
2904 u8 reserved_1
[0x10];
2907 u8 reserved_2
[0x40];
2910 u8 reserved_3
[0x18];
2915 u8 reserved_5
[0x18];
2916 u8 modify_enable_mask
[0x8];
2918 u8 reserved_6
[0x20];
2920 u8 flow_index
[0x20];
2922 u8 reserved_7
[0xe0];
2924 struct mlx5_ifc_flow_context_bits flow_context
;
2927 struct mlx5_ifc_rts2rts_qp_out_bits
{
2929 u8 reserved_0
[0x18];
2933 u8 reserved_1
[0x40];
2936 struct mlx5_ifc_rts2rts_qp_in_bits
{
2938 u8 reserved_0
[0x10];
2940 u8 reserved_1
[0x10];
2946 u8 reserved_3
[0x20];
2948 u8 opt_param_mask
[0x20];
2950 u8 reserved_4
[0x20];
2952 struct mlx5_ifc_qpc_bits qpc
;
2954 u8 reserved_5
[0x80];
2957 struct mlx5_ifc_rtr2rts_qp_out_bits
{
2959 u8 reserved_0
[0x18];
2963 u8 reserved_1
[0x40];
2966 struct mlx5_ifc_rtr2rts_qp_in_bits
{
2968 u8 reserved_0
[0x10];
2970 u8 reserved_1
[0x10];
2976 u8 reserved_3
[0x20];
2978 u8 opt_param_mask
[0x20];
2980 u8 reserved_4
[0x20];
2982 struct mlx5_ifc_qpc_bits qpc
;
2984 u8 reserved_5
[0x80];
2987 struct mlx5_ifc_rst2init_qp_out_bits
{
2989 u8 reserved_0
[0x18];
2993 u8 reserved_1
[0x40];
2996 struct mlx5_ifc_rst2init_qp_in_bits
{
2998 u8 reserved_0
[0x10];
3000 u8 reserved_1
[0x10];
3006 u8 reserved_3
[0x20];
3008 u8 opt_param_mask
[0x20];
3010 u8 reserved_4
[0x20];
3012 struct mlx5_ifc_qpc_bits qpc
;
3014 u8 reserved_5
[0x80];
3017 struct mlx5_ifc_query_xrc_srq_out_bits
{
3019 u8 reserved_0
[0x18];
3023 u8 reserved_1
[0x40];
3025 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
3027 u8 reserved_2
[0x600];
3032 struct mlx5_ifc_query_xrc_srq_in_bits
{
3034 u8 reserved_0
[0x10];
3036 u8 reserved_1
[0x10];
3042 u8 reserved_3
[0x20];
3046 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
3047 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
3050 struct mlx5_ifc_query_vport_state_out_bits
{
3052 u8 reserved_0
[0x18];
3056 u8 reserved_1
[0x20];
3058 u8 reserved_2
[0x18];
3059 u8 admin_state
[0x4];
3064 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
= 0x0,
3065 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT
= 0x1,
3068 struct mlx5_ifc_query_vport_state_in_bits
{
3070 u8 reserved_0
[0x10];
3072 u8 reserved_1
[0x10];
3075 u8 other_vport
[0x1];
3077 u8 vport_number
[0x10];
3079 u8 reserved_3
[0x20];
3082 struct mlx5_ifc_query_vport_counter_out_bits
{
3084 u8 reserved_0
[0x18];
3088 u8 reserved_1
[0x40];
3090 struct mlx5_ifc_traffic_counter_bits received_errors
;
3092 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
3094 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
3096 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
3098 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
3100 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
3102 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
3104 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
3106 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
3108 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
3110 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
3112 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
3114 u8 reserved_2
[0xa00];
3118 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
3121 struct mlx5_ifc_query_vport_counter_in_bits
{
3123 u8 reserved_0
[0x10];
3125 u8 reserved_1
[0x10];
3128 u8 other_vport
[0x1];
3130 u8 vport_number
[0x10];
3132 u8 reserved_3
[0x60];
3135 u8 reserved_4
[0x1f];
3137 u8 reserved_5
[0x20];
3140 struct mlx5_ifc_query_tis_out_bits
{
3142 u8 reserved_0
[0x18];
3146 u8 reserved_1
[0x40];
3148 struct mlx5_ifc_tisc_bits tis_context
;
3151 struct mlx5_ifc_query_tis_in_bits
{
3153 u8 reserved_0
[0x10];
3155 u8 reserved_1
[0x10];
3161 u8 reserved_3
[0x20];
3164 struct mlx5_ifc_query_tir_out_bits
{
3166 u8 reserved_0
[0x18];
3170 u8 reserved_1
[0xc0];
3172 struct mlx5_ifc_tirc_bits tir_context
;
3175 struct mlx5_ifc_query_tir_in_bits
{
3177 u8 reserved_0
[0x10];
3179 u8 reserved_1
[0x10];
3185 u8 reserved_3
[0x20];
3188 struct mlx5_ifc_query_srq_out_bits
{
3190 u8 reserved_0
[0x18];
3194 u8 reserved_1
[0x40];
3196 struct mlx5_ifc_srqc_bits srq_context_entry
;
3198 u8 reserved_2
[0x600];
3203 struct mlx5_ifc_query_srq_in_bits
{
3205 u8 reserved_0
[0x10];
3207 u8 reserved_1
[0x10];
3213 u8 reserved_3
[0x20];
3216 struct mlx5_ifc_query_sq_out_bits
{
3218 u8 reserved_0
[0x18];
3222 u8 reserved_1
[0xc0];
3224 struct mlx5_ifc_sqc_bits sq_context
;
3227 struct mlx5_ifc_query_sq_in_bits
{
3229 u8 reserved_0
[0x10];
3231 u8 reserved_1
[0x10];
3237 u8 reserved_3
[0x20];
3240 struct mlx5_ifc_query_special_contexts_out_bits
{
3242 u8 reserved_0
[0x18];
3246 u8 reserved_1
[0x20];
3251 struct mlx5_ifc_query_special_contexts_in_bits
{
3253 u8 reserved_0
[0x10];
3255 u8 reserved_1
[0x10];
3258 u8 reserved_2
[0x40];
3261 struct mlx5_ifc_query_rqt_out_bits
{
3263 u8 reserved_0
[0x18];
3267 u8 reserved_1
[0xc0];
3269 struct mlx5_ifc_rqtc_bits rqt_context
;
3272 struct mlx5_ifc_query_rqt_in_bits
{
3274 u8 reserved_0
[0x10];
3276 u8 reserved_1
[0x10];
3282 u8 reserved_3
[0x20];
3285 struct mlx5_ifc_query_rq_out_bits
{
3287 u8 reserved_0
[0x18];
3291 u8 reserved_1
[0xc0];
3293 struct mlx5_ifc_rqc_bits rq_context
;
3296 struct mlx5_ifc_query_rq_in_bits
{
3298 u8 reserved_0
[0x10];
3300 u8 reserved_1
[0x10];
3306 u8 reserved_3
[0x20];
3309 struct mlx5_ifc_query_roce_address_out_bits
{
3311 u8 reserved_0
[0x18];
3315 u8 reserved_1
[0x40];
3317 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3320 struct mlx5_ifc_query_roce_address_in_bits
{
3322 u8 reserved_0
[0x10];
3324 u8 reserved_1
[0x10];
3327 u8 roce_address_index
[0x10];
3328 u8 reserved_2
[0x10];
3330 u8 reserved_3
[0x20];
3333 struct mlx5_ifc_query_rmp_out_bits
{
3335 u8 reserved_0
[0x18];
3339 u8 reserved_1
[0xc0];
3341 struct mlx5_ifc_rmpc_bits rmp_context
;
3344 struct mlx5_ifc_query_rmp_in_bits
{
3346 u8 reserved_0
[0x10];
3348 u8 reserved_1
[0x10];
3354 u8 reserved_3
[0x20];
3357 struct mlx5_ifc_query_qp_out_bits
{
3359 u8 reserved_0
[0x18];
3363 u8 reserved_1
[0x40];
3365 u8 opt_param_mask
[0x20];
3367 u8 reserved_2
[0x20];
3369 struct mlx5_ifc_qpc_bits qpc
;
3371 u8 reserved_3
[0x80];
3376 struct mlx5_ifc_query_qp_in_bits
{
3378 u8 reserved_0
[0x10];
3380 u8 reserved_1
[0x10];
3386 u8 reserved_3
[0x20];
3389 struct mlx5_ifc_query_q_counter_out_bits
{
3391 u8 reserved_0
[0x18];
3395 u8 reserved_1
[0x40];
3397 u8 rx_write_requests
[0x20];
3399 u8 reserved_2
[0x20];
3401 u8 rx_read_requests
[0x20];
3403 u8 reserved_3
[0x20];
3405 u8 rx_atomic_requests
[0x20];
3407 u8 reserved_4
[0x20];
3409 u8 rx_dct_connect
[0x20];
3411 u8 reserved_5
[0x20];
3413 u8 out_of_buffer
[0x20];
3415 u8 reserved_6
[0x20];
3417 u8 out_of_sequence
[0x20];
3419 u8 reserved_7
[0x620];
3422 struct mlx5_ifc_query_q_counter_in_bits
{
3424 u8 reserved_0
[0x10];
3426 u8 reserved_1
[0x10];
3429 u8 reserved_2
[0x80];
3432 u8 reserved_3
[0x1f];
3434 u8 reserved_4
[0x18];
3435 u8 counter_set_id
[0x8];
3438 struct mlx5_ifc_query_pages_out_bits
{
3440 u8 reserved_0
[0x18];
3444 u8 reserved_1
[0x10];
3445 u8 function_id
[0x10];
3451 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
3452 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
3453 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
3456 struct mlx5_ifc_query_pages_in_bits
{
3458 u8 reserved_0
[0x10];
3460 u8 reserved_1
[0x10];
3463 u8 reserved_2
[0x10];
3464 u8 function_id
[0x10];
3466 u8 reserved_3
[0x20];
3469 struct mlx5_ifc_query_nic_vport_context_out_bits
{
3471 u8 reserved_0
[0x18];
3475 u8 reserved_1
[0x40];
3477 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
3480 struct mlx5_ifc_query_nic_vport_context_in_bits
{
3482 u8 reserved_0
[0x10];
3484 u8 reserved_1
[0x10];
3487 u8 other_vport
[0x1];
3489 u8 vport_number
[0x10];
3492 u8 allowed_list_type
[0x3];
3493 u8 reserved_4
[0x18];
3496 struct mlx5_ifc_query_mkey_out_bits
{
3498 u8 reserved_0
[0x18];
3502 u8 reserved_1
[0x40];
3504 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
3506 u8 reserved_2
[0x600];
3508 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
3510 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
3513 struct mlx5_ifc_query_mkey_in_bits
{
3515 u8 reserved_0
[0x10];
3517 u8 reserved_1
[0x10];
3521 u8 mkey_index
[0x18];
3524 u8 reserved_3
[0x1f];
3527 struct mlx5_ifc_query_mad_demux_out_bits
{
3529 u8 reserved_0
[0x18];
3533 u8 reserved_1
[0x40];
3535 u8 mad_dumux_parameters_block
[0x20];
3538 struct mlx5_ifc_query_mad_demux_in_bits
{
3540 u8 reserved_0
[0x10];
3542 u8 reserved_1
[0x10];
3545 u8 reserved_2
[0x40];
3548 struct mlx5_ifc_query_l2_table_entry_out_bits
{
3550 u8 reserved_0
[0x18];
3554 u8 reserved_1
[0xa0];
3556 u8 reserved_2
[0x13];
3560 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3562 u8 reserved_3
[0xc0];
3565 struct mlx5_ifc_query_l2_table_entry_in_bits
{
3567 u8 reserved_0
[0x10];
3569 u8 reserved_1
[0x10];
3572 u8 reserved_2
[0x60];
3575 u8 table_index
[0x18];
3577 u8 reserved_4
[0x140];
3580 struct mlx5_ifc_query_issi_out_bits
{
3582 u8 reserved_0
[0x18];
3586 u8 reserved_1
[0x10];
3587 u8 current_issi
[0x10];
3589 u8 reserved_2
[0xa0];
3591 u8 supported_issi_reserved
[76][0x8];
3592 u8 supported_issi_dw0
[0x20];
3595 struct mlx5_ifc_query_issi_in_bits
{
3597 u8 reserved_0
[0x10];
3599 u8 reserved_1
[0x10];
3602 u8 reserved_2
[0x40];
3605 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
3607 u8 reserved_0
[0x18];
3611 u8 reserved_1
[0x40];
3613 struct mlx5_ifc_pkey_bits pkey
[0];
3616 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
3618 u8 reserved_0
[0x10];
3620 u8 reserved_1
[0x10];
3623 u8 other_vport
[0x1];
3626 u8 vport_number
[0x10];
3628 u8 reserved_3
[0x10];
3629 u8 pkey_index
[0x10];
3632 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
3634 u8 reserved_0
[0x18];
3638 u8 reserved_1
[0x20];
3641 u8 reserved_2
[0x10];
3643 struct mlx5_ifc_array128_auto_bits gid
[0];
3646 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
3648 u8 reserved_0
[0x10];
3650 u8 reserved_1
[0x10];
3653 u8 other_vport
[0x1];
3656 u8 vport_number
[0x10];
3658 u8 reserved_3
[0x10];
3662 struct mlx5_ifc_query_hca_vport_context_out_bits
{
3664 u8 reserved_0
[0x18];
3668 u8 reserved_1
[0x40];
3670 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
3673 struct mlx5_ifc_query_hca_vport_context_in_bits
{
3675 u8 reserved_0
[0x10];
3677 u8 reserved_1
[0x10];
3680 u8 other_vport
[0x1];
3683 u8 vport_number
[0x10];
3685 u8 reserved_3
[0x20];
3688 struct mlx5_ifc_query_hca_cap_out_bits
{
3690 u8 reserved_0
[0x18];
3694 u8 reserved_1
[0x40];
3696 union mlx5_ifc_hca_cap_union_bits capability
;
3699 struct mlx5_ifc_query_hca_cap_in_bits
{
3701 u8 reserved_0
[0x10];
3703 u8 reserved_1
[0x10];
3706 u8 reserved_2
[0x40];
3709 struct mlx5_ifc_query_flow_table_out_bits
{
3711 u8 reserved_0
[0x18];
3715 u8 reserved_1
[0x80];
3722 u8 reserved_4
[0x120];
3725 struct mlx5_ifc_query_flow_table_in_bits
{
3727 u8 reserved_0
[0x10];
3729 u8 reserved_1
[0x10];
3732 u8 reserved_2
[0x40];
3735 u8 reserved_3
[0x18];
3740 u8 reserved_5
[0x140];
3743 struct mlx5_ifc_query_fte_out_bits
{
3745 u8 reserved_0
[0x18];
3749 u8 reserved_1
[0x1c0];
3751 struct mlx5_ifc_flow_context_bits flow_context
;
3754 struct mlx5_ifc_query_fte_in_bits
{
3756 u8 reserved_0
[0x10];
3758 u8 reserved_1
[0x10];
3761 u8 reserved_2
[0x40];
3764 u8 reserved_3
[0x18];
3769 u8 reserved_5
[0x40];
3771 u8 flow_index
[0x20];
3773 u8 reserved_6
[0xe0];
3777 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
3778 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
3779 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
3782 struct mlx5_ifc_query_flow_group_out_bits
{
3784 u8 reserved_0
[0x18];
3788 u8 reserved_1
[0xa0];
3790 u8 start_flow_index
[0x20];
3792 u8 reserved_2
[0x20];
3794 u8 end_flow_index
[0x20];
3796 u8 reserved_3
[0xa0];
3798 u8 reserved_4
[0x18];
3799 u8 match_criteria_enable
[0x8];
3801 struct mlx5_ifc_fte_match_param_bits match_criteria
;
3803 u8 reserved_5
[0xe00];
3806 struct mlx5_ifc_query_flow_group_in_bits
{
3808 u8 reserved_0
[0x10];
3810 u8 reserved_1
[0x10];
3813 u8 reserved_2
[0x40];
3816 u8 reserved_3
[0x18];
3823 u8 reserved_5
[0x120];
3826 struct mlx5_ifc_query_esw_vport_context_out_bits
{
3828 u8 reserved_0
[0x18];
3832 u8 reserved_1
[0x40];
3834 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
3837 struct mlx5_ifc_query_esw_vport_context_in_bits
{
3839 u8 reserved_0
[0x10];
3841 u8 reserved_1
[0x10];
3844 u8 other_vport
[0x1];
3846 u8 vport_number
[0x10];
3848 u8 reserved_3
[0x20];
3851 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
3853 u8 reserved_0
[0x18];
3857 u8 reserved_1
[0x40];
3860 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
3862 u8 vport_cvlan_insert
[0x1];
3863 u8 vport_svlan_insert
[0x1];
3864 u8 vport_cvlan_strip
[0x1];
3865 u8 vport_svlan_strip
[0x1];
3868 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
3870 u8 reserved_0
[0x10];
3872 u8 reserved_1
[0x10];
3875 u8 other_vport
[0x1];
3877 u8 vport_number
[0x10];
3879 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
3881 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
3884 struct mlx5_ifc_query_eq_out_bits
{
3886 u8 reserved_0
[0x18];
3890 u8 reserved_1
[0x40];
3892 struct mlx5_ifc_eqc_bits eq_context_entry
;
3894 u8 reserved_2
[0x40];
3896 u8 event_bitmask
[0x40];
3898 u8 reserved_3
[0x580];
3903 struct mlx5_ifc_query_eq_in_bits
{
3905 u8 reserved_0
[0x10];
3907 u8 reserved_1
[0x10];
3910 u8 reserved_2
[0x18];
3913 u8 reserved_3
[0x20];
3916 struct mlx5_ifc_query_dct_out_bits
{
3918 u8 reserved_0
[0x18];
3922 u8 reserved_1
[0x40];
3924 struct mlx5_ifc_dctc_bits dct_context_entry
;
3926 u8 reserved_2
[0x180];
3929 struct mlx5_ifc_query_dct_in_bits
{
3931 u8 reserved_0
[0x10];
3933 u8 reserved_1
[0x10];
3939 u8 reserved_3
[0x20];
3942 struct mlx5_ifc_query_cq_out_bits
{
3944 u8 reserved_0
[0x18];
3948 u8 reserved_1
[0x40];
3950 struct mlx5_ifc_cqc_bits cq_context
;
3952 u8 reserved_2
[0x600];
3957 struct mlx5_ifc_query_cq_in_bits
{
3959 u8 reserved_0
[0x10];
3961 u8 reserved_1
[0x10];
3967 u8 reserved_3
[0x20];
3970 struct mlx5_ifc_query_cong_status_out_bits
{
3972 u8 reserved_0
[0x18];
3976 u8 reserved_1
[0x20];
3980 u8 reserved_2
[0x1e];
3983 struct mlx5_ifc_query_cong_status_in_bits
{
3985 u8 reserved_0
[0x10];
3987 u8 reserved_1
[0x10];
3990 u8 reserved_2
[0x18];
3992 u8 cong_protocol
[0x4];
3994 u8 reserved_3
[0x20];
3997 struct mlx5_ifc_query_cong_statistics_out_bits
{
3999 u8 reserved_0
[0x18];
4003 u8 reserved_1
[0x40];
4009 u8 cnp_ignored_high
[0x20];
4011 u8 cnp_ignored_low
[0x20];
4013 u8 cnp_handled_high
[0x20];
4015 u8 cnp_handled_low
[0x20];
4017 u8 reserved_2
[0x100];
4019 u8 time_stamp_high
[0x20];
4021 u8 time_stamp_low
[0x20];
4023 u8 accumulators_period
[0x20];
4025 u8 ecn_marked_roce_packets_high
[0x20];
4027 u8 ecn_marked_roce_packets_low
[0x20];
4029 u8 cnps_sent_high
[0x20];
4031 u8 cnps_sent_low
[0x20];
4033 u8 reserved_3
[0x560];
4036 struct mlx5_ifc_query_cong_statistics_in_bits
{
4038 u8 reserved_0
[0x10];
4040 u8 reserved_1
[0x10];
4044 u8 reserved_2
[0x1f];
4046 u8 reserved_3
[0x20];
4049 struct mlx5_ifc_query_cong_params_out_bits
{
4051 u8 reserved_0
[0x18];
4055 u8 reserved_1
[0x40];
4057 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4060 struct mlx5_ifc_query_cong_params_in_bits
{
4062 u8 reserved_0
[0x10];
4064 u8 reserved_1
[0x10];
4067 u8 reserved_2
[0x1c];
4068 u8 cong_protocol
[0x4];
4070 u8 reserved_3
[0x20];
4073 struct mlx5_ifc_query_adapter_out_bits
{
4075 u8 reserved_0
[0x18];
4079 u8 reserved_1
[0x40];
4081 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
4084 struct mlx5_ifc_query_adapter_in_bits
{
4086 u8 reserved_0
[0x10];
4088 u8 reserved_1
[0x10];
4091 u8 reserved_2
[0x40];
4094 struct mlx5_ifc_qp_2rst_out_bits
{
4096 u8 reserved_0
[0x18];
4100 u8 reserved_1
[0x40];
4103 struct mlx5_ifc_qp_2rst_in_bits
{
4105 u8 reserved_0
[0x10];
4107 u8 reserved_1
[0x10];
4113 u8 reserved_3
[0x20];
4116 struct mlx5_ifc_qp_2err_out_bits
{
4118 u8 reserved_0
[0x18];
4122 u8 reserved_1
[0x40];
4125 struct mlx5_ifc_qp_2err_in_bits
{
4127 u8 reserved_0
[0x10];
4129 u8 reserved_1
[0x10];
4135 u8 reserved_3
[0x20];
4138 struct mlx5_ifc_page_fault_resume_out_bits
{
4140 u8 reserved_0
[0x18];
4144 u8 reserved_1
[0x40];
4147 struct mlx5_ifc_page_fault_resume_in_bits
{
4149 u8 reserved_0
[0x10];
4151 u8 reserved_1
[0x10];
4161 u8 reserved_3
[0x20];
4164 struct mlx5_ifc_nop_out_bits
{
4166 u8 reserved_0
[0x18];
4170 u8 reserved_1
[0x40];
4173 struct mlx5_ifc_nop_in_bits
{
4175 u8 reserved_0
[0x10];
4177 u8 reserved_1
[0x10];
4180 u8 reserved_2
[0x40];
4183 struct mlx5_ifc_modify_vport_state_out_bits
{
4185 u8 reserved_0
[0x18];
4189 u8 reserved_1
[0x40];
4192 struct mlx5_ifc_modify_vport_state_in_bits
{
4194 u8 reserved_0
[0x10];
4196 u8 reserved_1
[0x10];
4199 u8 other_vport
[0x1];
4201 u8 vport_number
[0x10];
4203 u8 reserved_3
[0x18];
4204 u8 admin_state
[0x4];
4208 struct mlx5_ifc_modify_tis_out_bits
{
4210 u8 reserved_0
[0x18];
4214 u8 reserved_1
[0x40];
4217 struct mlx5_ifc_modify_tis_bitmask_bits
{
4218 u8 reserved_0
[0x20];
4220 u8 reserved_1
[0x1f];
4224 struct mlx5_ifc_modify_tis_in_bits
{
4226 u8 reserved_0
[0x10];
4228 u8 reserved_1
[0x10];
4234 u8 reserved_3
[0x20];
4236 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
4238 u8 reserved_4
[0x40];
4240 struct mlx5_ifc_tisc_bits ctx
;
4243 struct mlx5_ifc_modify_tir_bitmask_bits
{
4244 u8 reserved_0
[0x20];
4246 u8 reserved_1
[0x1b];
4252 struct mlx5_ifc_modify_tir_out_bits
{
4254 u8 reserved_0
[0x18];
4258 u8 reserved_1
[0x40];
4261 struct mlx5_ifc_modify_tir_in_bits
{
4263 u8 reserved_0
[0x10];
4265 u8 reserved_1
[0x10];
4271 u8 reserved_3
[0x20];
4273 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
4275 u8 reserved_4
[0x40];
4277 struct mlx5_ifc_tirc_bits ctx
;
4280 struct mlx5_ifc_modify_sq_out_bits
{
4282 u8 reserved_0
[0x18];
4286 u8 reserved_1
[0x40];
4289 struct mlx5_ifc_modify_sq_in_bits
{
4291 u8 reserved_0
[0x10];
4293 u8 reserved_1
[0x10];
4300 u8 reserved_3
[0x20];
4302 u8 modify_bitmask
[0x40];
4304 u8 reserved_4
[0x40];
4306 struct mlx5_ifc_sqc_bits ctx
;
4309 struct mlx5_ifc_modify_rqt_out_bits
{
4311 u8 reserved_0
[0x18];
4315 u8 reserved_1
[0x40];
4318 struct mlx5_ifc_rqt_bitmask_bits
{
4325 struct mlx5_ifc_modify_rqt_in_bits
{
4327 u8 reserved_0
[0x10];
4329 u8 reserved_1
[0x10];
4335 u8 reserved_3
[0x20];
4337 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
4339 u8 reserved_4
[0x40];
4341 struct mlx5_ifc_rqtc_bits ctx
;
4344 struct mlx5_ifc_modify_rq_out_bits
{
4346 u8 reserved_0
[0x18];
4350 u8 reserved_1
[0x40];
4353 struct mlx5_ifc_modify_rq_in_bits
{
4355 u8 reserved_0
[0x10];
4357 u8 reserved_1
[0x10];
4364 u8 reserved_3
[0x20];
4366 u8 modify_bitmask
[0x40];
4368 u8 reserved_4
[0x40];
4370 struct mlx5_ifc_rqc_bits ctx
;
4373 struct mlx5_ifc_modify_rmp_out_bits
{
4375 u8 reserved_0
[0x18];
4379 u8 reserved_1
[0x40];
4382 struct mlx5_ifc_rmp_bitmask_bits
{
4389 struct mlx5_ifc_modify_rmp_in_bits
{
4391 u8 reserved_0
[0x10];
4393 u8 reserved_1
[0x10];
4400 u8 reserved_3
[0x20];
4402 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
4404 u8 reserved_4
[0x40];
4406 struct mlx5_ifc_rmpc_bits ctx
;
4409 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
4411 u8 reserved_0
[0x18];
4415 u8 reserved_1
[0x40];
4418 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
4419 u8 reserved_0
[0x19];
4421 u8 change_event
[0x1];
4423 u8 permanent_address
[0x1];
4424 u8 addresses_list
[0x1];
4429 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
4431 u8 reserved_0
[0x10];
4433 u8 reserved_1
[0x10];
4436 u8 other_vport
[0x1];
4438 u8 vport_number
[0x10];
4440 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
4442 u8 reserved_3
[0x780];
4444 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4447 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
4449 u8 reserved_0
[0x18];
4453 u8 reserved_1
[0x40];
4456 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
4458 u8 reserved_0
[0x10];
4460 u8 reserved_1
[0x10];
4463 u8 other_vport
[0x1];
4466 u8 vport_number
[0x10];
4468 u8 reserved_3
[0x20];
4470 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
4473 struct mlx5_ifc_modify_cq_out_bits
{
4475 u8 reserved_0
[0x18];
4479 u8 reserved_1
[0x40];
4483 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
4484 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
4487 struct mlx5_ifc_modify_cq_in_bits
{
4489 u8 reserved_0
[0x10];
4491 u8 reserved_1
[0x10];
4497 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
4499 struct mlx5_ifc_cqc_bits cq_context
;
4501 u8 reserved_3
[0x600];
4506 struct mlx5_ifc_modify_cong_status_out_bits
{
4508 u8 reserved_0
[0x18];
4512 u8 reserved_1
[0x40];
4515 struct mlx5_ifc_modify_cong_status_in_bits
{
4517 u8 reserved_0
[0x10];
4519 u8 reserved_1
[0x10];
4522 u8 reserved_2
[0x18];
4524 u8 cong_protocol
[0x4];
4528 u8 reserved_3
[0x1e];
4531 struct mlx5_ifc_modify_cong_params_out_bits
{
4533 u8 reserved_0
[0x18];
4537 u8 reserved_1
[0x40];
4540 struct mlx5_ifc_modify_cong_params_in_bits
{
4542 u8 reserved_0
[0x10];
4544 u8 reserved_1
[0x10];
4547 u8 reserved_2
[0x1c];
4548 u8 cong_protocol
[0x4];
4550 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
4552 u8 reserved_3
[0x80];
4554 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4557 struct mlx5_ifc_manage_pages_out_bits
{
4559 u8 reserved_0
[0x18];
4563 u8 output_num_entries
[0x20];
4565 u8 reserved_1
[0x20];
4571 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
4572 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
4573 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
4576 struct mlx5_ifc_manage_pages_in_bits
{
4578 u8 reserved_0
[0x10];
4580 u8 reserved_1
[0x10];
4583 u8 reserved_2
[0x10];
4584 u8 function_id
[0x10];
4586 u8 input_num_entries
[0x20];
4591 struct mlx5_ifc_mad_ifc_out_bits
{
4593 u8 reserved_0
[0x18];
4597 u8 reserved_1
[0x40];
4599 u8 response_mad_packet
[256][0x8];
4602 struct mlx5_ifc_mad_ifc_in_bits
{
4604 u8 reserved_0
[0x10];
4606 u8 reserved_1
[0x10];
4609 u8 remote_lid
[0x10];
4613 u8 reserved_3
[0x20];
4618 struct mlx5_ifc_init_hca_out_bits
{
4620 u8 reserved_0
[0x18];
4624 u8 reserved_1
[0x40];
4627 struct mlx5_ifc_init_hca_in_bits
{
4629 u8 reserved_0
[0x10];
4631 u8 reserved_1
[0x10];
4634 u8 reserved_2
[0x40];
4637 struct mlx5_ifc_init2rtr_qp_out_bits
{
4639 u8 reserved_0
[0x18];
4643 u8 reserved_1
[0x40];
4646 struct mlx5_ifc_init2rtr_qp_in_bits
{
4648 u8 reserved_0
[0x10];
4650 u8 reserved_1
[0x10];
4656 u8 reserved_3
[0x20];
4658 u8 opt_param_mask
[0x20];
4660 u8 reserved_4
[0x20];
4662 struct mlx5_ifc_qpc_bits qpc
;
4664 u8 reserved_5
[0x80];
4667 struct mlx5_ifc_init2init_qp_out_bits
{
4669 u8 reserved_0
[0x18];
4673 u8 reserved_1
[0x40];
4676 struct mlx5_ifc_init2init_qp_in_bits
{
4678 u8 reserved_0
[0x10];
4680 u8 reserved_1
[0x10];
4686 u8 reserved_3
[0x20];
4688 u8 opt_param_mask
[0x20];
4690 u8 reserved_4
[0x20];
4692 struct mlx5_ifc_qpc_bits qpc
;
4694 u8 reserved_5
[0x80];
4697 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
4699 u8 reserved_0
[0x18];
4703 u8 reserved_1
[0x40];
4705 u8 packet_headers_log
[128][0x8];
4707 u8 packet_syndrome
[64][0x8];
4710 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
4712 u8 reserved_0
[0x10];
4714 u8 reserved_1
[0x10];
4717 u8 reserved_2
[0x40];
4720 struct mlx5_ifc_gen_eqe_in_bits
{
4722 u8 reserved_0
[0x10];
4724 u8 reserved_1
[0x10];
4727 u8 reserved_2
[0x18];
4730 u8 reserved_3
[0x20];
4735 struct mlx5_ifc_gen_eq_out_bits
{
4737 u8 reserved_0
[0x18];
4741 u8 reserved_1
[0x40];
4744 struct mlx5_ifc_enable_hca_out_bits
{
4746 u8 reserved_0
[0x18];
4750 u8 reserved_1
[0x20];
4753 struct mlx5_ifc_enable_hca_in_bits
{
4755 u8 reserved_0
[0x10];
4757 u8 reserved_1
[0x10];
4760 u8 reserved_2
[0x10];
4761 u8 function_id
[0x10];
4763 u8 reserved_3
[0x20];
4766 struct mlx5_ifc_drain_dct_out_bits
{
4768 u8 reserved_0
[0x18];
4772 u8 reserved_1
[0x40];
4775 struct mlx5_ifc_drain_dct_in_bits
{
4777 u8 reserved_0
[0x10];
4779 u8 reserved_1
[0x10];
4785 u8 reserved_3
[0x20];
4788 struct mlx5_ifc_disable_hca_out_bits
{
4790 u8 reserved_0
[0x18];
4794 u8 reserved_1
[0x20];
4797 struct mlx5_ifc_disable_hca_in_bits
{
4799 u8 reserved_0
[0x10];
4801 u8 reserved_1
[0x10];
4804 u8 reserved_2
[0x10];
4805 u8 function_id
[0x10];
4807 u8 reserved_3
[0x20];
4810 struct mlx5_ifc_detach_from_mcg_out_bits
{
4812 u8 reserved_0
[0x18];
4816 u8 reserved_1
[0x40];
4819 struct mlx5_ifc_detach_from_mcg_in_bits
{
4821 u8 reserved_0
[0x10];
4823 u8 reserved_1
[0x10];
4829 u8 reserved_3
[0x20];
4831 u8 multicast_gid
[16][0x8];
4834 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
4836 u8 reserved_0
[0x18];
4840 u8 reserved_1
[0x40];
4843 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
4845 u8 reserved_0
[0x10];
4847 u8 reserved_1
[0x10];
4853 u8 reserved_3
[0x20];
4856 struct mlx5_ifc_destroy_tis_out_bits
{
4858 u8 reserved_0
[0x18];
4862 u8 reserved_1
[0x40];
4865 struct mlx5_ifc_destroy_tis_in_bits
{
4867 u8 reserved_0
[0x10];
4869 u8 reserved_1
[0x10];
4875 u8 reserved_3
[0x20];
4878 struct mlx5_ifc_destroy_tir_out_bits
{
4880 u8 reserved_0
[0x18];
4884 u8 reserved_1
[0x40];
4887 struct mlx5_ifc_destroy_tir_in_bits
{
4889 u8 reserved_0
[0x10];
4891 u8 reserved_1
[0x10];
4897 u8 reserved_3
[0x20];
4900 struct mlx5_ifc_destroy_srq_out_bits
{
4902 u8 reserved_0
[0x18];
4906 u8 reserved_1
[0x40];
4909 struct mlx5_ifc_destroy_srq_in_bits
{
4911 u8 reserved_0
[0x10];
4913 u8 reserved_1
[0x10];
4919 u8 reserved_3
[0x20];
4922 struct mlx5_ifc_destroy_sq_out_bits
{
4924 u8 reserved_0
[0x18];
4928 u8 reserved_1
[0x40];
4931 struct mlx5_ifc_destroy_sq_in_bits
{
4933 u8 reserved_0
[0x10];
4935 u8 reserved_1
[0x10];
4941 u8 reserved_3
[0x20];
4944 struct mlx5_ifc_destroy_rqt_out_bits
{
4946 u8 reserved_0
[0x18];
4950 u8 reserved_1
[0x40];
4953 struct mlx5_ifc_destroy_rqt_in_bits
{
4955 u8 reserved_0
[0x10];
4957 u8 reserved_1
[0x10];
4963 u8 reserved_3
[0x20];
4966 struct mlx5_ifc_destroy_rq_out_bits
{
4968 u8 reserved_0
[0x18];
4972 u8 reserved_1
[0x40];
4975 struct mlx5_ifc_destroy_rq_in_bits
{
4977 u8 reserved_0
[0x10];
4979 u8 reserved_1
[0x10];
4985 u8 reserved_3
[0x20];
4988 struct mlx5_ifc_destroy_rmp_out_bits
{
4990 u8 reserved_0
[0x18];
4994 u8 reserved_1
[0x40];
4997 struct mlx5_ifc_destroy_rmp_in_bits
{
4999 u8 reserved_0
[0x10];
5001 u8 reserved_1
[0x10];
5007 u8 reserved_3
[0x20];
5010 struct mlx5_ifc_destroy_qp_out_bits
{
5012 u8 reserved_0
[0x18];
5016 u8 reserved_1
[0x40];
5019 struct mlx5_ifc_destroy_qp_in_bits
{
5021 u8 reserved_0
[0x10];
5023 u8 reserved_1
[0x10];
5029 u8 reserved_3
[0x20];
5032 struct mlx5_ifc_destroy_psv_out_bits
{
5034 u8 reserved_0
[0x18];
5038 u8 reserved_1
[0x40];
5041 struct mlx5_ifc_destroy_psv_in_bits
{
5043 u8 reserved_0
[0x10];
5045 u8 reserved_1
[0x10];
5051 u8 reserved_3
[0x20];
5054 struct mlx5_ifc_destroy_mkey_out_bits
{
5056 u8 reserved_0
[0x18];
5060 u8 reserved_1
[0x40];
5063 struct mlx5_ifc_destroy_mkey_in_bits
{
5065 u8 reserved_0
[0x10];
5067 u8 reserved_1
[0x10];
5071 u8 mkey_index
[0x18];
5073 u8 reserved_3
[0x20];
5076 struct mlx5_ifc_destroy_flow_table_out_bits
{
5078 u8 reserved_0
[0x18];
5082 u8 reserved_1
[0x40];
5085 struct mlx5_ifc_destroy_flow_table_in_bits
{
5087 u8 reserved_0
[0x10];
5089 u8 reserved_1
[0x10];
5092 u8 reserved_2
[0x40];
5095 u8 reserved_3
[0x18];
5100 u8 reserved_5
[0x140];
5103 struct mlx5_ifc_destroy_flow_group_out_bits
{
5105 u8 reserved_0
[0x18];
5109 u8 reserved_1
[0x40];
5112 struct mlx5_ifc_destroy_flow_group_in_bits
{
5114 u8 reserved_0
[0x10];
5116 u8 reserved_1
[0x10];
5119 u8 reserved_2
[0x40];
5122 u8 reserved_3
[0x18];
5129 u8 reserved_5
[0x120];
5132 struct mlx5_ifc_destroy_eq_out_bits
{
5134 u8 reserved_0
[0x18];
5138 u8 reserved_1
[0x40];
5141 struct mlx5_ifc_destroy_eq_in_bits
{
5143 u8 reserved_0
[0x10];
5145 u8 reserved_1
[0x10];
5148 u8 reserved_2
[0x18];
5151 u8 reserved_3
[0x20];
5154 struct mlx5_ifc_destroy_dct_out_bits
{
5156 u8 reserved_0
[0x18];
5160 u8 reserved_1
[0x40];
5163 struct mlx5_ifc_destroy_dct_in_bits
{
5165 u8 reserved_0
[0x10];
5167 u8 reserved_1
[0x10];
5173 u8 reserved_3
[0x20];
5176 struct mlx5_ifc_destroy_cq_out_bits
{
5178 u8 reserved_0
[0x18];
5182 u8 reserved_1
[0x40];
5185 struct mlx5_ifc_destroy_cq_in_bits
{
5187 u8 reserved_0
[0x10];
5189 u8 reserved_1
[0x10];
5195 u8 reserved_3
[0x20];
5198 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
5200 u8 reserved_0
[0x18];
5204 u8 reserved_1
[0x40];
5207 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
5209 u8 reserved_0
[0x10];
5211 u8 reserved_1
[0x10];
5214 u8 reserved_2
[0x20];
5216 u8 reserved_3
[0x10];
5217 u8 vxlan_udp_port
[0x10];
5220 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
5222 u8 reserved_0
[0x18];
5226 u8 reserved_1
[0x40];
5229 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
5231 u8 reserved_0
[0x10];
5233 u8 reserved_1
[0x10];
5236 u8 reserved_2
[0x60];
5239 u8 table_index
[0x18];
5241 u8 reserved_4
[0x140];
5244 struct mlx5_ifc_delete_fte_out_bits
{
5246 u8 reserved_0
[0x18];
5250 u8 reserved_1
[0x40];
5253 struct mlx5_ifc_delete_fte_in_bits
{
5255 u8 reserved_0
[0x10];
5257 u8 reserved_1
[0x10];
5260 u8 reserved_2
[0x40];
5263 u8 reserved_3
[0x18];
5268 u8 reserved_5
[0x40];
5270 u8 flow_index
[0x20];
5272 u8 reserved_6
[0xe0];
5275 struct mlx5_ifc_dealloc_xrcd_out_bits
{
5277 u8 reserved_0
[0x18];
5281 u8 reserved_1
[0x40];
5284 struct mlx5_ifc_dealloc_xrcd_in_bits
{
5286 u8 reserved_0
[0x10];
5288 u8 reserved_1
[0x10];
5294 u8 reserved_3
[0x20];
5297 struct mlx5_ifc_dealloc_uar_out_bits
{
5299 u8 reserved_0
[0x18];
5303 u8 reserved_1
[0x40];
5306 struct mlx5_ifc_dealloc_uar_in_bits
{
5308 u8 reserved_0
[0x10];
5310 u8 reserved_1
[0x10];
5316 u8 reserved_3
[0x20];
5319 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
5321 u8 reserved_0
[0x18];
5325 u8 reserved_1
[0x40];
5328 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
5330 u8 reserved_0
[0x10];
5332 u8 reserved_1
[0x10];
5336 u8 transport_domain
[0x18];
5338 u8 reserved_3
[0x20];
5341 struct mlx5_ifc_dealloc_q_counter_out_bits
{
5343 u8 reserved_0
[0x18];
5347 u8 reserved_1
[0x40];
5350 struct mlx5_ifc_dealloc_q_counter_in_bits
{
5352 u8 reserved_0
[0x10];
5354 u8 reserved_1
[0x10];
5357 u8 reserved_2
[0x18];
5358 u8 counter_set_id
[0x8];
5360 u8 reserved_3
[0x20];
5363 struct mlx5_ifc_dealloc_pd_out_bits
{
5365 u8 reserved_0
[0x18];
5369 u8 reserved_1
[0x40];
5372 struct mlx5_ifc_dealloc_pd_in_bits
{
5374 u8 reserved_0
[0x10];
5376 u8 reserved_1
[0x10];
5382 u8 reserved_3
[0x20];
5385 struct mlx5_ifc_create_xrc_srq_out_bits
{
5387 u8 reserved_0
[0x18];
5394 u8 reserved_2
[0x20];
5397 struct mlx5_ifc_create_xrc_srq_in_bits
{
5399 u8 reserved_0
[0x10];
5401 u8 reserved_1
[0x10];
5404 u8 reserved_2
[0x40];
5406 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
5408 u8 reserved_3
[0x600];
5413 struct mlx5_ifc_create_tis_out_bits
{
5415 u8 reserved_0
[0x18];
5422 u8 reserved_2
[0x20];
5425 struct mlx5_ifc_create_tis_in_bits
{
5427 u8 reserved_0
[0x10];
5429 u8 reserved_1
[0x10];
5432 u8 reserved_2
[0xc0];
5434 struct mlx5_ifc_tisc_bits ctx
;
5437 struct mlx5_ifc_create_tir_out_bits
{
5439 u8 reserved_0
[0x18];
5446 u8 reserved_2
[0x20];
5449 struct mlx5_ifc_create_tir_in_bits
{
5451 u8 reserved_0
[0x10];
5453 u8 reserved_1
[0x10];
5456 u8 reserved_2
[0xc0];
5458 struct mlx5_ifc_tirc_bits ctx
;
5461 struct mlx5_ifc_create_srq_out_bits
{
5463 u8 reserved_0
[0x18];
5470 u8 reserved_2
[0x20];
5473 struct mlx5_ifc_create_srq_in_bits
{
5475 u8 reserved_0
[0x10];
5477 u8 reserved_1
[0x10];
5480 u8 reserved_2
[0x40];
5482 struct mlx5_ifc_srqc_bits srq_context_entry
;
5484 u8 reserved_3
[0x600];
5489 struct mlx5_ifc_create_sq_out_bits
{
5491 u8 reserved_0
[0x18];
5498 u8 reserved_2
[0x20];
5501 struct mlx5_ifc_create_sq_in_bits
{
5503 u8 reserved_0
[0x10];
5505 u8 reserved_1
[0x10];
5508 u8 reserved_2
[0xc0];
5510 struct mlx5_ifc_sqc_bits ctx
;
5513 struct mlx5_ifc_create_rqt_out_bits
{
5515 u8 reserved_0
[0x18];
5522 u8 reserved_2
[0x20];
5525 struct mlx5_ifc_create_rqt_in_bits
{
5527 u8 reserved_0
[0x10];
5529 u8 reserved_1
[0x10];
5532 u8 reserved_2
[0xc0];
5534 struct mlx5_ifc_rqtc_bits rqt_context
;
5537 struct mlx5_ifc_create_rq_out_bits
{
5539 u8 reserved_0
[0x18];
5546 u8 reserved_2
[0x20];
5549 struct mlx5_ifc_create_rq_in_bits
{
5551 u8 reserved_0
[0x10];
5553 u8 reserved_1
[0x10];
5556 u8 reserved_2
[0xc0];
5558 struct mlx5_ifc_rqc_bits ctx
;
5561 struct mlx5_ifc_create_rmp_out_bits
{
5563 u8 reserved_0
[0x18];
5570 u8 reserved_2
[0x20];
5573 struct mlx5_ifc_create_rmp_in_bits
{
5575 u8 reserved_0
[0x10];
5577 u8 reserved_1
[0x10];
5580 u8 reserved_2
[0xc0];
5582 struct mlx5_ifc_rmpc_bits ctx
;
5585 struct mlx5_ifc_create_qp_out_bits
{
5587 u8 reserved_0
[0x18];
5594 u8 reserved_2
[0x20];
5597 struct mlx5_ifc_create_qp_in_bits
{
5599 u8 reserved_0
[0x10];
5601 u8 reserved_1
[0x10];
5604 u8 reserved_2
[0x40];
5606 u8 opt_param_mask
[0x20];
5608 u8 reserved_3
[0x20];
5610 struct mlx5_ifc_qpc_bits qpc
;
5612 u8 reserved_4
[0x80];
5617 struct mlx5_ifc_create_psv_out_bits
{
5619 u8 reserved_0
[0x18];
5623 u8 reserved_1
[0x40];
5626 u8 psv0_index
[0x18];
5629 u8 psv1_index
[0x18];
5632 u8 psv2_index
[0x18];
5635 u8 psv3_index
[0x18];
5638 struct mlx5_ifc_create_psv_in_bits
{
5640 u8 reserved_0
[0x10];
5642 u8 reserved_1
[0x10];
5649 u8 reserved_3
[0x20];
5652 struct mlx5_ifc_create_mkey_out_bits
{
5654 u8 reserved_0
[0x18];
5659 u8 mkey_index
[0x18];
5661 u8 reserved_2
[0x20];
5664 struct mlx5_ifc_create_mkey_in_bits
{
5666 u8 reserved_0
[0x10];
5668 u8 reserved_1
[0x10];
5671 u8 reserved_2
[0x20];
5674 u8 reserved_3
[0x1f];
5676 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
5678 u8 reserved_4
[0x80];
5680 u8 translations_octword_actual_size
[0x20];
5682 u8 reserved_5
[0x560];
5684 u8 klm_pas_mtt
[0][0x20];
5687 struct mlx5_ifc_create_flow_table_out_bits
{
5689 u8 reserved_0
[0x18];
5696 u8 reserved_2
[0x20];
5699 struct mlx5_ifc_create_flow_table_in_bits
{
5701 u8 reserved_0
[0x10];
5703 u8 reserved_1
[0x10];
5706 u8 reserved_2
[0x40];
5709 u8 reserved_3
[0x18];
5711 u8 reserved_4
[0x20];
5714 u8 table_miss_mode
[0x4];
5720 u8 table_miss_id
[0x18];
5722 u8 reserved_8
[0x100];
5725 struct mlx5_ifc_create_flow_group_out_bits
{
5727 u8 reserved_0
[0x18];
5734 u8 reserved_2
[0x20];
5738 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
5739 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
5740 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
5743 struct mlx5_ifc_create_flow_group_in_bits
{
5745 u8 reserved_0
[0x10];
5747 u8 reserved_1
[0x10];
5750 u8 reserved_2
[0x40];
5753 u8 reserved_3
[0x18];
5758 u8 reserved_5
[0x20];
5760 u8 start_flow_index
[0x20];
5762 u8 reserved_6
[0x20];
5764 u8 end_flow_index
[0x20];
5766 u8 reserved_7
[0xa0];
5768 u8 reserved_8
[0x18];
5769 u8 match_criteria_enable
[0x8];
5771 struct mlx5_ifc_fte_match_param_bits match_criteria
;
5773 u8 reserved_9
[0xe00];
5776 struct mlx5_ifc_create_eq_out_bits
{
5778 u8 reserved_0
[0x18];
5782 u8 reserved_1
[0x18];
5785 u8 reserved_2
[0x20];
5788 struct mlx5_ifc_create_eq_in_bits
{
5790 u8 reserved_0
[0x10];
5792 u8 reserved_1
[0x10];
5795 u8 reserved_2
[0x40];
5797 struct mlx5_ifc_eqc_bits eq_context_entry
;
5799 u8 reserved_3
[0x40];
5801 u8 event_bitmask
[0x40];
5803 u8 reserved_4
[0x580];
5808 struct mlx5_ifc_create_dct_out_bits
{
5810 u8 reserved_0
[0x18];
5817 u8 reserved_2
[0x20];
5820 struct mlx5_ifc_create_dct_in_bits
{
5822 u8 reserved_0
[0x10];
5824 u8 reserved_1
[0x10];
5827 u8 reserved_2
[0x40];
5829 struct mlx5_ifc_dctc_bits dct_context_entry
;
5831 u8 reserved_3
[0x180];
5834 struct mlx5_ifc_create_cq_out_bits
{
5836 u8 reserved_0
[0x18];
5843 u8 reserved_2
[0x20];
5846 struct mlx5_ifc_create_cq_in_bits
{
5848 u8 reserved_0
[0x10];
5850 u8 reserved_1
[0x10];
5853 u8 reserved_2
[0x40];
5855 struct mlx5_ifc_cqc_bits cq_context
;
5857 u8 reserved_3
[0x600];
5862 struct mlx5_ifc_config_int_moderation_out_bits
{
5864 u8 reserved_0
[0x18];
5870 u8 int_vector
[0x10];
5872 u8 reserved_2
[0x20];
5876 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
5877 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
5880 struct mlx5_ifc_config_int_moderation_in_bits
{
5882 u8 reserved_0
[0x10];
5884 u8 reserved_1
[0x10];
5889 u8 int_vector
[0x10];
5891 u8 reserved_3
[0x20];
5894 struct mlx5_ifc_attach_to_mcg_out_bits
{
5896 u8 reserved_0
[0x18];
5900 u8 reserved_1
[0x40];
5903 struct mlx5_ifc_attach_to_mcg_in_bits
{
5905 u8 reserved_0
[0x10];
5907 u8 reserved_1
[0x10];
5913 u8 reserved_3
[0x20];
5915 u8 multicast_gid
[16][0x8];
5918 struct mlx5_ifc_arm_xrc_srq_out_bits
{
5920 u8 reserved_0
[0x18];
5924 u8 reserved_1
[0x40];
5928 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
5931 struct mlx5_ifc_arm_xrc_srq_in_bits
{
5933 u8 reserved_0
[0x10];
5935 u8 reserved_1
[0x10];
5941 u8 reserved_3
[0x10];
5945 struct mlx5_ifc_arm_rq_out_bits
{
5947 u8 reserved_0
[0x18];
5951 u8 reserved_1
[0x40];
5955 MLX5_ARM_RQ_IN_OP_MOD_SRQ_
= 0x1,
5958 struct mlx5_ifc_arm_rq_in_bits
{
5960 u8 reserved_0
[0x10];
5962 u8 reserved_1
[0x10];
5966 u8 srq_number
[0x18];
5968 u8 reserved_3
[0x10];
5972 struct mlx5_ifc_arm_dct_out_bits
{
5974 u8 reserved_0
[0x18];
5978 u8 reserved_1
[0x40];
5981 struct mlx5_ifc_arm_dct_in_bits
{
5983 u8 reserved_0
[0x10];
5985 u8 reserved_1
[0x10];
5989 u8 dct_number
[0x18];
5991 u8 reserved_3
[0x20];
5994 struct mlx5_ifc_alloc_xrcd_out_bits
{
5996 u8 reserved_0
[0x18];
6003 u8 reserved_2
[0x20];
6006 struct mlx5_ifc_alloc_xrcd_in_bits
{
6008 u8 reserved_0
[0x10];
6010 u8 reserved_1
[0x10];
6013 u8 reserved_2
[0x40];
6016 struct mlx5_ifc_alloc_uar_out_bits
{
6018 u8 reserved_0
[0x18];
6025 u8 reserved_2
[0x20];
6028 struct mlx5_ifc_alloc_uar_in_bits
{
6030 u8 reserved_0
[0x10];
6032 u8 reserved_1
[0x10];
6035 u8 reserved_2
[0x40];
6038 struct mlx5_ifc_alloc_transport_domain_out_bits
{
6040 u8 reserved_0
[0x18];
6045 u8 transport_domain
[0x18];
6047 u8 reserved_2
[0x20];
6050 struct mlx5_ifc_alloc_transport_domain_in_bits
{
6052 u8 reserved_0
[0x10];
6054 u8 reserved_1
[0x10];
6057 u8 reserved_2
[0x40];
6060 struct mlx5_ifc_alloc_q_counter_out_bits
{
6062 u8 reserved_0
[0x18];
6066 u8 reserved_1
[0x18];
6067 u8 counter_set_id
[0x8];
6069 u8 reserved_2
[0x20];
6072 struct mlx5_ifc_alloc_q_counter_in_bits
{
6074 u8 reserved_0
[0x10];
6076 u8 reserved_1
[0x10];
6079 u8 reserved_2
[0x40];
6082 struct mlx5_ifc_alloc_pd_out_bits
{
6084 u8 reserved_0
[0x18];
6091 u8 reserved_2
[0x20];
6094 struct mlx5_ifc_alloc_pd_in_bits
{
6096 u8 reserved_0
[0x10];
6098 u8 reserved_1
[0x10];
6101 u8 reserved_2
[0x40];
6104 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
6106 u8 reserved_0
[0x18];
6110 u8 reserved_1
[0x40];
6113 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
6115 u8 reserved_0
[0x10];
6117 u8 reserved_1
[0x10];
6120 u8 reserved_2
[0x20];
6122 u8 reserved_3
[0x10];
6123 u8 vxlan_udp_port
[0x10];
6126 struct mlx5_ifc_access_register_out_bits
{
6128 u8 reserved_0
[0x18];
6132 u8 reserved_1
[0x40];
6134 u8 register_data
[0][0x20];
6138 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
6139 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
6142 struct mlx5_ifc_access_register_in_bits
{
6144 u8 reserved_0
[0x10];
6146 u8 reserved_1
[0x10];
6149 u8 reserved_2
[0x10];
6150 u8 register_id
[0x10];
6154 u8 register_data
[0][0x20];
6157 struct mlx5_ifc_sltp_reg_bits
{
6166 u8 reserved_2
[0x20];
6175 u8 ob_preemp_mode
[0x4];
6179 u8 reserved_5
[0x20];
6182 struct mlx5_ifc_slrg_reg_bits
{
6191 u8 time_to_link_up
[0x10];
6193 u8 grade_lane_speed
[0x4];
6195 u8 grade_version
[0x8];
6199 u8 height_grade_type
[0x4];
6200 u8 height_grade
[0x18];
6205 u8 reserved_4
[0x10];
6206 u8 height_sigma
[0x10];
6208 u8 reserved_5
[0x20];
6211 u8 phase_grade_type
[0x4];
6212 u8 phase_grade
[0x18];
6215 u8 phase_eo_pos
[0x8];
6217 u8 phase_eo_neg
[0x8];
6219 u8 ffe_set_tested
[0x10];
6220 u8 test_errors_per_lane
[0x10];
6223 struct mlx5_ifc_pvlc_reg_bits
{
6226 u8 reserved_1
[0x10];
6228 u8 reserved_2
[0x1c];
6231 u8 reserved_3
[0x1c];
6234 u8 reserved_4
[0x1c];
6235 u8 vl_operational
[0x4];
6238 struct mlx5_ifc_pude_reg_bits
{
6242 u8 admin_status
[0x4];
6244 u8 oper_status
[0x4];
6246 u8 reserved_2
[0x60];
6249 struct mlx5_ifc_ptys_reg_bits
{
6255 u8 reserved_2
[0x40];
6257 u8 eth_proto_capability
[0x20];
6259 u8 ib_link_width_capability
[0x10];
6260 u8 ib_proto_capability
[0x10];
6262 u8 reserved_3
[0x20];
6264 u8 eth_proto_admin
[0x20];
6266 u8 ib_link_width_admin
[0x10];
6267 u8 ib_proto_admin
[0x10];
6269 u8 reserved_4
[0x20];
6271 u8 eth_proto_oper
[0x20];
6273 u8 ib_link_width_oper
[0x10];
6274 u8 ib_proto_oper
[0x10];
6276 u8 reserved_5
[0x20];
6278 u8 eth_proto_lp_advertise
[0x20];
6280 u8 reserved_6
[0x60];
6283 struct mlx5_ifc_ptas_reg_bits
{
6284 u8 reserved_0
[0x20];
6286 u8 algorithm_options
[0x10];
6288 u8 repetitions_mode
[0x4];
6289 u8 num_of_repetitions
[0x8];
6291 u8 grade_version
[0x8];
6292 u8 height_grade_type
[0x4];
6293 u8 phase_grade_type
[0x4];
6294 u8 height_grade_weight
[0x8];
6295 u8 phase_grade_weight
[0x8];
6297 u8 gisim_measure_bits
[0x10];
6298 u8 adaptive_tap_measure_bits
[0x10];
6300 u8 ber_bath_high_error_threshold
[0x10];
6301 u8 ber_bath_mid_error_threshold
[0x10];
6303 u8 ber_bath_low_error_threshold
[0x10];
6304 u8 one_ratio_high_threshold
[0x10];
6306 u8 one_ratio_high_mid_threshold
[0x10];
6307 u8 one_ratio_low_mid_threshold
[0x10];
6309 u8 one_ratio_low_threshold
[0x10];
6310 u8 ndeo_error_threshold
[0x10];
6312 u8 mixer_offset_step_size
[0x10];
6314 u8 mix90_phase_for_voltage_bath
[0x8];
6316 u8 mixer_offset_start
[0x10];
6317 u8 mixer_offset_end
[0x10];
6319 u8 reserved_3
[0x15];
6320 u8 ber_test_time
[0xb];
6323 struct mlx5_ifc_pspa_reg_bits
{
6329 u8 reserved_1
[0x20];
6332 struct mlx5_ifc_pqdr_reg_bits
{
6340 u8 reserved_3
[0x20];
6342 u8 reserved_4
[0x10];
6343 u8 min_threshold
[0x10];
6345 u8 reserved_5
[0x10];
6346 u8 max_threshold
[0x10];
6348 u8 reserved_6
[0x10];
6349 u8 mark_probability_denominator
[0x10];
6351 u8 reserved_7
[0x60];
6354 struct mlx5_ifc_ppsc_reg_bits
{
6357 u8 reserved_1
[0x10];
6359 u8 reserved_2
[0x60];
6361 u8 reserved_3
[0x1c];
6364 u8 reserved_4
[0x1c];
6365 u8 wrps_status
[0x4];
6368 u8 up_threshold
[0x8];
6370 u8 down_threshold
[0x8];
6372 u8 reserved_7
[0x20];
6374 u8 reserved_8
[0x1c];
6377 u8 reserved_9
[0x1c];
6378 u8 srps_status
[0x4];
6380 u8 reserved_10
[0x40];
6383 struct mlx5_ifc_pplr_reg_bits
{
6386 u8 reserved_1
[0x10];
6394 struct mlx5_ifc_pplm_reg_bits
{
6397 u8 reserved_1
[0x10];
6399 u8 reserved_2
[0x20];
6401 u8 port_profile_mode
[0x8];
6402 u8 static_port_profile
[0x8];
6403 u8 active_port_profile
[0x8];
6406 u8 retransmission_active
[0x8];
6407 u8 fec_mode_active
[0x18];
6409 u8 reserved_4
[0x20];
6412 struct mlx5_ifc_ppcnt_reg_bits
{
6420 u8 reserved_1
[0x1c];
6423 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
6426 struct mlx5_ifc_ppad_reg_bits
{
6435 u8 reserved_2
[0x40];
6438 struct mlx5_ifc_pmtu_reg_bits
{
6441 u8 reserved_1
[0x10];
6444 u8 reserved_2
[0x10];
6447 u8 reserved_3
[0x10];
6450 u8 reserved_4
[0x10];
6453 struct mlx5_ifc_pmpr_reg_bits
{
6456 u8 reserved_1
[0x10];
6458 u8 reserved_2
[0x18];
6459 u8 attenuation_5g
[0x8];
6461 u8 reserved_3
[0x18];
6462 u8 attenuation_7g
[0x8];
6464 u8 reserved_4
[0x18];
6465 u8 attenuation_12g
[0x8];
6468 struct mlx5_ifc_pmpe_reg_bits
{
6472 u8 module_status
[0x4];
6474 u8 reserved_2
[0x60];
6477 struct mlx5_ifc_pmpc_reg_bits
{
6478 u8 module_state_updated
[32][0x8];
6481 struct mlx5_ifc_pmlpn_reg_bits
{
6483 u8 mlpn_status
[0x4];
6485 u8 reserved_1
[0x10];
6488 u8 reserved_2
[0x1f];
6491 struct mlx5_ifc_pmlp_reg_bits
{
6498 u8 lane0_module_mapping
[0x20];
6500 u8 lane1_module_mapping
[0x20];
6502 u8 lane2_module_mapping
[0x20];
6504 u8 lane3_module_mapping
[0x20];
6506 u8 reserved_2
[0x160];
6509 struct mlx5_ifc_pmaos_reg_bits
{
6513 u8 admin_status
[0x4];
6515 u8 oper_status
[0x4];
6519 u8 reserved_3
[0x1c];
6522 u8 reserved_4
[0x40];
6525 struct mlx5_ifc_plpc_reg_bits
{
6532 u8 reserved_3
[0x10];
6533 u8 lane_speed
[0x10];
6535 u8 reserved_4
[0x17];
6537 u8 fec_mode_policy
[0x8];
6539 u8 retransmission_capability
[0x8];
6540 u8 fec_mode_capability
[0x18];
6542 u8 retransmission_support_admin
[0x8];
6543 u8 fec_mode_support_admin
[0x18];
6545 u8 retransmission_request_admin
[0x8];
6546 u8 fec_mode_request_admin
[0x18];
6548 u8 reserved_5
[0x80];
6551 struct mlx5_ifc_plib_reg_bits
{
6557 u8 reserved_2
[0x60];
6560 struct mlx5_ifc_plbf_reg_bits
{
6566 u8 reserved_2
[0x20];
6569 struct mlx5_ifc_pipg_reg_bits
{
6572 u8 reserved_1
[0x10];
6575 u8 reserved_2
[0x19];
6580 struct mlx5_ifc_pifr_reg_bits
{
6583 u8 reserved_1
[0x10];
6585 u8 reserved_2
[0xe0];
6587 u8 port_filter
[8][0x20];
6589 u8 port_filter_update_en
[8][0x20];
6592 struct mlx5_ifc_pfcc_reg_bits
{
6595 u8 reserved_1
[0x10];
6599 u8 prio_mask_tx
[0x8];
6601 u8 prio_mask_rx
[0x8];
6607 u8 reserved_5
[0x10];
6613 u8 reserved_7
[0x10];
6615 u8 reserved_8
[0x80];
6618 struct mlx5_ifc_pelc_reg_bits
{
6622 u8 reserved_1
[0x10];
6625 u8 op_capability
[0x8];
6631 u8 capability
[0x40];
6637 u8 reserved_2
[0x80];
6640 struct mlx5_ifc_peir_reg_bits
{
6643 u8 reserved_1
[0x10];
6646 u8 error_count
[0x4];
6647 u8 reserved_3
[0x10];
6655 struct mlx5_ifc_pcap_reg_bits
{
6658 u8 reserved_1
[0x10];
6660 u8 port_capability_mask
[4][0x20];
6663 struct mlx5_ifc_paos_reg_bits
{
6667 u8 admin_status
[0x4];
6669 u8 oper_status
[0x4];
6673 u8 reserved_2
[0x1c];
6676 u8 reserved_3
[0x40];
6679 struct mlx5_ifc_pamp_reg_bits
{
6681 u8 opamp_group
[0x8];
6683 u8 opamp_group_type
[0x4];
6685 u8 start_index
[0x10];
6687 u8 num_of_indices
[0xc];
6689 u8 index_data
[18][0x10];
6692 struct mlx5_ifc_lane_2_module_mapping_bits
{
6701 struct mlx5_ifc_bufferx_reg_bits
{
6708 u8 xoff_threshold
[0x10];
6709 u8 xon_threshold
[0x10];
6712 struct mlx5_ifc_set_node_in_bits
{
6713 u8 node_description
[64][0x8];
6716 struct mlx5_ifc_register_power_settings_bits
{
6717 u8 reserved_0
[0x18];
6718 u8 power_settings_level
[0x8];
6720 u8 reserved_1
[0x60];
6723 struct mlx5_ifc_register_host_endianness_bits
{
6725 u8 reserved_0
[0x1f];
6727 u8 reserved_1
[0x60];
6730 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
6731 u8 reserved_0
[0x20];
6735 u8 addressh_63_32
[0x20];
6737 u8 addressl_31_0
[0x20];
6740 struct mlx5_ifc_ud_adrs_vector_bits
{
6745 u8 destination_qp_dct
[0x18];
6747 u8 static_rate
[0x4];
6748 u8 sl_eth_prio
[0x4];
6751 u8 rlid_udp_sport
[0x10];
6753 u8 reserved_1
[0x20];
6755 u8 rmac_47_16
[0x20];
6764 u8 src_addr_index
[0x8];
6765 u8 flow_label
[0x14];
6767 u8 rgid_rip
[16][0x8];
6770 struct mlx5_ifc_pages_req_event_bits
{
6771 u8 reserved_0
[0x10];
6772 u8 function_id
[0x10];
6776 u8 reserved_1
[0xa0];
6779 struct mlx5_ifc_eqe_bits
{
6783 u8 event_sub_type
[0x8];
6785 u8 reserved_2
[0xe0];
6787 union mlx5_ifc_event_auto_bits event_data
;
6789 u8 reserved_3
[0x10];
6796 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
6799 struct mlx5_ifc_cmd_queue_entry_bits
{
6801 u8 reserved_0
[0x18];
6803 u8 input_length
[0x20];
6805 u8 input_mailbox_pointer_63_32
[0x20];
6807 u8 input_mailbox_pointer_31_9
[0x17];
6810 u8 command_input_inline_data
[16][0x8];
6812 u8 command_output_inline_data
[16][0x8];
6814 u8 output_mailbox_pointer_63_32
[0x20];
6816 u8 output_mailbox_pointer_31_9
[0x17];
6819 u8 output_length
[0x20];
6828 struct mlx5_ifc_cmd_out_bits
{
6830 u8 reserved_0
[0x18];
6834 u8 command_output
[0x20];
6837 struct mlx5_ifc_cmd_in_bits
{
6839 u8 reserved_0
[0x10];
6841 u8 reserved_1
[0x10];
6844 u8 command
[0][0x20];
6847 struct mlx5_ifc_cmd_if_box_bits
{
6848 u8 mailbox_data
[512][0x8];
6850 u8 reserved_0
[0x180];
6852 u8 next_pointer_63_32
[0x20];
6854 u8 next_pointer_31_10
[0x16];
6857 u8 block_number
[0x20];
6861 u8 ctrl_signature
[0x8];
6865 struct mlx5_ifc_mtt_bits
{
6866 u8 ptag_63_32
[0x20];
6875 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
6876 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
6877 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
6881 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
6882 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
6883 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
6887 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
6888 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
6889 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
6890 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
6891 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
6892 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
6893 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
6894 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
6895 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
6896 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
6897 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
6900 struct mlx5_ifc_initial_seg_bits
{
6901 u8 fw_rev_minor
[0x10];
6902 u8 fw_rev_major
[0x10];
6904 u8 cmd_interface_rev
[0x10];
6905 u8 fw_rev_subminor
[0x10];
6907 u8 reserved_0
[0x40];
6909 u8 cmdq_phy_addr_63_32
[0x20];
6911 u8 cmdq_phy_addr_31_12
[0x14];
6913 u8 nic_interface
[0x2];
6914 u8 log_cmdq_size
[0x4];
6915 u8 log_cmdq_stride
[0x4];
6917 u8 command_doorbell_vector
[0x20];
6919 u8 reserved_2
[0xf00];
6921 u8 initializing
[0x1];
6923 u8 nic_interface_supported
[0x3];
6924 u8 reserved_4
[0x18];
6926 struct mlx5_ifc_health_buffer_bits health_buffer
;
6928 u8 no_dram_nic_offset
[0x20];
6930 u8 reserved_5
[0x6e40];
6932 u8 reserved_6
[0x1f];
6935 u8 health_syndrome
[0x8];
6936 u8 health_counter
[0x18];
6938 u8 reserved_7
[0x17fc0];
6941 union mlx5_ifc_ports_control_registers_document_bits
{
6942 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
6943 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
6944 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
6945 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
6946 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
6947 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
6948 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
6949 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
6950 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
6951 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
6952 struct mlx5_ifc_paos_reg_bits paos_reg
;
6953 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
6954 struct mlx5_ifc_peir_reg_bits peir_reg
;
6955 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
6956 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
6957 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
6958 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
6959 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
6960 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
6961 struct mlx5_ifc_plib_reg_bits plib_reg
;
6962 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
6963 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
6964 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
6965 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
6966 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
6967 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
6968 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
6969 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
6970 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
6971 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
6972 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
6973 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
6974 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
6975 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
6976 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
6977 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
6978 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
6979 struct mlx5_ifc_pude_reg_bits pude_reg
;
6980 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
6981 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
6982 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
6983 u8 reserved_0
[0x60e0];
6986 union mlx5_ifc_debug_enhancements_document_bits
{
6987 struct mlx5_ifc_health_buffer_bits health_buffer
;
6988 u8 reserved_0
[0x200];
6991 union mlx5_ifc_uplink_pci_interface_document_bits
{
6992 struct mlx5_ifc_initial_seg_bits initial_seg
;
6993 u8 reserved_0
[0x20060];
6996 struct mlx5_ifc_set_flow_table_root_out_bits
{
6998 u8 reserved_0
[0x18];
7002 u8 reserved_1
[0x40];
7005 struct mlx5_ifc_set_flow_table_root_in_bits
{
7007 u8 reserved_0
[0x10];
7009 u8 reserved_1
[0x10];
7012 u8 reserved_2
[0x40];
7015 u8 reserved_3
[0x18];
7020 u8 reserved_5
[0x140];
7024 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= 0x1,
7027 struct mlx5_ifc_modify_flow_table_out_bits
{
7029 u8 reserved_0
[0x18];
7033 u8 reserved_1
[0x40];
7036 struct mlx5_ifc_modify_flow_table_in_bits
{
7038 u8 reserved_0
[0x10];
7040 u8 reserved_1
[0x10];
7043 u8 reserved_2
[0x20];
7045 u8 reserved_3
[0x10];
7046 u8 modify_field_select
[0x10];
7049 u8 reserved_4
[0x18];
7055 u8 table_miss_mode
[0x4];
7056 u8 reserved_7
[0x18];
7059 u8 table_miss_id
[0x18];
7061 u8 reserved_9
[0x100];
7064 #endif /* MLX5_IFC_H */