2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
77 MLX5_CMD_OP_INIT_HCA
= 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
79 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
80 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
81 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
84 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
85 MLX5_CMD_OP_SET_ISSI
= 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
87 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
91 MLX5_CMD_OP_CREATE_EQ
= 0x301,
92 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
93 MLX5_CMD_OP_QUERY_EQ
= 0x303,
94 MLX5_CMD_OP_GEN_EQE
= 0x304,
95 MLX5_CMD_OP_CREATE_CQ
= 0x400,
96 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
97 MLX5_CMD_OP_QUERY_CQ
= 0x402,
98 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
99 MLX5_CMD_OP_CREATE_QP
= 0x500,
100 MLX5_CMD_OP_DESTROY_QP
= 0x501,
101 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
106 MLX5_CMD_OP_2ERR_QP
= 0x507,
107 MLX5_CMD_OP_2RST_QP
= 0x50a,
108 MLX5_CMD_OP_QUERY_QP
= 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
111 MLX5_CMD_OP_CREATE_PSV
= 0x600,
112 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
113 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
115 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
116 MLX5_CMD_OP_ARM_RQ
= 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
121 MLX5_CMD_OP_CREATE_DCT
= 0x710,
122 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
123 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
124 MLX5_CMD_OP_QUERY_DCT
= 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
126 MLX5_CMD_OP_CREATE_XRQ
= 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ
= 0x718,
128 MLX5_CMD_OP_QUERY_XRQ
= 0x719,
129 MLX5_CMD_OP_ARM_XRQ
= 0x71a,
130 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
137 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
142 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
146 MLX5_CMD_OP_SET_RATE_LIMIT
= 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT
= 0x781,
148 MLX5_CMD_OP_ALLOC_PD
= 0x800,
149 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
150 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
153 MLX5_CMD_OP_ACCESS_REG
= 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
155 MLX5_CMD_OP_DETTACH_FROM_MCG
= 0x807,
156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
157 MLX5_CMD_OP_MAD_IFC
= 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
160 MLX5_CMD_OP_NOP
= 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
175 MLX5_CMD_OP_SET_WOL_ROL
= 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL
= 0x831,
177 MLX5_CMD_OP_CREATE_TIR
= 0x900,
178 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
179 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
180 MLX5_CMD_OP_QUERY_TIR
= 0x903,
181 MLX5_CMD_OP_CREATE_SQ
= 0x904,
182 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
183 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
184 MLX5_CMD_OP_QUERY_SQ
= 0x907,
185 MLX5_CMD_OP_CREATE_RQ
= 0x908,
186 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
187 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
188 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
189 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
190 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
191 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
192 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
193 MLX5_CMD_OP_CREATE_TIS
= 0x912,
194 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
195 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
196 MLX5_CMD_OP_QUERY_TIS
= 0x915,
197 MLX5_CMD_OP_CREATE_RQT
= 0x916,
198 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
199 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
200 MLX5_CMD_OP_QUERY_RQT
= 0x919,
201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
202 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
203 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
204 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
205 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
206 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
207 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER
= 0x939,
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER
= 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER
= 0x93b,
214 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c,
218 struct mlx5_ifc_flow_table_fields_supported_bits
{
221 u8 outer_ether_type
[0x1];
222 u8 reserved_at_3
[0x1];
223 u8 outer_first_prio
[0x1];
224 u8 outer_first_cfi
[0x1];
225 u8 outer_first_vid
[0x1];
226 u8 reserved_at_7
[0x1];
227 u8 outer_second_prio
[0x1];
228 u8 outer_second_cfi
[0x1];
229 u8 outer_second_vid
[0x1];
230 u8 reserved_at_b
[0x1];
234 u8 outer_ip_protocol
[0x1];
235 u8 outer_ip_ecn
[0x1];
236 u8 outer_ip_dscp
[0x1];
237 u8 outer_udp_sport
[0x1];
238 u8 outer_udp_dport
[0x1];
239 u8 outer_tcp_sport
[0x1];
240 u8 outer_tcp_dport
[0x1];
241 u8 outer_tcp_flags
[0x1];
242 u8 outer_gre_protocol
[0x1];
243 u8 outer_gre_key
[0x1];
244 u8 outer_vxlan_vni
[0x1];
245 u8 reserved_at_1a
[0x5];
246 u8 source_eswitch_port
[0x1];
250 u8 inner_ether_type
[0x1];
251 u8 reserved_at_23
[0x1];
252 u8 inner_first_prio
[0x1];
253 u8 inner_first_cfi
[0x1];
254 u8 inner_first_vid
[0x1];
255 u8 reserved_at_27
[0x1];
256 u8 inner_second_prio
[0x1];
257 u8 inner_second_cfi
[0x1];
258 u8 inner_second_vid
[0x1];
259 u8 reserved_at_2b
[0x1];
263 u8 inner_ip_protocol
[0x1];
264 u8 inner_ip_ecn
[0x1];
265 u8 inner_ip_dscp
[0x1];
266 u8 inner_udp_sport
[0x1];
267 u8 inner_udp_dport
[0x1];
268 u8 inner_tcp_sport
[0x1];
269 u8 inner_tcp_dport
[0x1];
270 u8 inner_tcp_flags
[0x1];
271 u8 reserved_at_37
[0x9];
273 u8 reserved_at_40
[0x40];
276 struct mlx5_ifc_flow_table_prop_layout_bits
{
278 u8 reserved_at_1
[0x1];
279 u8 flow_counter
[0x1];
280 u8 flow_modify_en
[0x1];
282 u8 identified_miss_table_mode
[0x1];
283 u8 flow_table_modify
[0x1];
284 u8 reserved_at_7
[0x19];
286 u8 reserved_at_20
[0x2];
287 u8 log_max_ft_size
[0x6];
288 u8 reserved_at_28
[0x10];
289 u8 max_ft_level
[0x8];
291 u8 reserved_at_40
[0x20];
293 u8 reserved_at_60
[0x18];
294 u8 log_max_ft_num
[0x8];
296 u8 reserved_at_80
[0x18];
297 u8 log_max_destination
[0x8];
299 u8 reserved_at_a0
[0x18];
300 u8 log_max_flow
[0x8];
302 u8 reserved_at_c0
[0x40];
304 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
306 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
309 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
314 u8 reserved_at_4
[0x1];
316 u8 reserved_at_6
[0x1a];
319 struct mlx5_ifc_ipv4_layout_bits
{
320 u8 reserved_at_0
[0x60];
325 struct mlx5_ifc_ipv6_layout_bits
{
329 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits
{
330 struct mlx5_ifc_ipv6_layout_bits ipv6_layout
;
331 struct mlx5_ifc_ipv4_layout_bits ipv4_layout
;
332 u8 reserved_at_0
[0x80];
335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
352 u8 reserved_at_91
[0x1];
354 u8 reserved_at_93
[0x4];
360 u8 reserved_at_c0
[0x20];
365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
370 struct mlx5_ifc_fte_match_set_misc_bits
{
371 u8 reserved_at_0
[0x8];
374 u8 reserved_at_20
[0x10];
375 u8 source_port
[0x10];
377 u8 outer_second_prio
[0x3];
378 u8 outer_second_cfi
[0x1];
379 u8 outer_second_vid
[0xc];
380 u8 inner_second_prio
[0x3];
381 u8 inner_second_cfi
[0x1];
382 u8 inner_second_vid
[0xc];
384 u8 outer_second_vlan_tag
[0x1];
385 u8 inner_second_vlan_tag
[0x1];
386 u8 reserved_at_62
[0xe];
387 u8 gre_protocol
[0x10];
393 u8 reserved_at_b8
[0x8];
395 u8 reserved_at_c0
[0x20];
397 u8 reserved_at_e0
[0xc];
398 u8 outer_ipv6_flow_label
[0x14];
400 u8 reserved_at_100
[0xc];
401 u8 inner_ipv6_flow_label
[0x14];
403 u8 reserved_at_120
[0xe0];
406 struct mlx5_ifc_cmd_pas_bits
{
410 u8 reserved_at_34
[0xc];
413 struct mlx5_ifc_uint64_bits
{
420 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
421 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
422 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
423 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
424 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
425 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
426 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
427 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
428 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
429 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
432 struct mlx5_ifc_ads_bits
{
435 u8 reserved_at_2
[0xe];
438 u8 reserved_at_20
[0x8];
444 u8 reserved_at_45
[0x3];
445 u8 src_addr_index
[0x8];
446 u8 reserved_at_50
[0x4];
450 u8 reserved_at_60
[0x4];
454 u8 rgid_rip
[16][0x8];
456 u8 reserved_at_100
[0x4];
459 u8 reserved_at_106
[0x1];
474 struct mlx5_ifc_flow_table_nic_cap_bits
{
475 u8 nic_rx_multi_path_tirs
[0x1];
476 u8 reserved_at_1
[0x1ff];
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
480 u8 reserved_at_400
[0x200];
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
486 u8 reserved_at_a00
[0x200];
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
490 u8 reserved_at_e00
[0x7200];
493 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
494 u8 reserved_at_0
[0x200];
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
498 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
502 u8 reserved_at_800
[0x7800];
505 struct mlx5_ifc_e_switch_cap_bits
{
506 u8 vport_svlan_strip
[0x1];
507 u8 vport_cvlan_strip
[0x1];
508 u8 vport_svlan_insert
[0x1];
509 u8 vport_cvlan_insert_if_not_exist
[0x1];
510 u8 vport_cvlan_insert_overwrite
[0x1];
511 u8 reserved_at_5
[0x19];
512 u8 nic_vport_node_guid_modify
[0x1];
513 u8 nic_vport_port_guid_modify
[0x1];
515 u8 reserved_at_20
[0x7e0];
518 struct mlx5_ifc_qos_cap_bits
{
519 u8 packet_pacing
[0x1];
522 u8 packet_pacing_max_rate
[0x20];
523 u8 packet_pacing_min_rate
[0x20];
525 u8 packet_pacing_rate_table_size
[0x10];
526 u8 reserved_3
[0x760];
529 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
533 u8 lro_psh_flag
[0x1];
534 u8 lro_time_stamp
[0x1];
535 u8 reserved_at_5
[0x3];
536 u8 self_lb_en_modifiable
[0x1];
537 u8 reserved_at_9
[0x2];
539 u8 reserved_at_10
[0x2];
540 u8 wqe_inline_mode
[0x2];
541 u8 rss_ind_tbl_cap
[0x4];
544 u8 reserved_at_1a
[0x1];
545 u8 tunnel_lso_const_out_ip_id
[0x1];
546 u8 reserved_at_1c
[0x2];
547 u8 tunnel_statless_gre
[0x1];
548 u8 tunnel_stateless_vxlan
[0x1];
550 u8 reserved_at_20
[0x20];
552 u8 reserved_at_40
[0x10];
553 u8 lro_min_mss_size
[0x10];
555 u8 reserved_at_60
[0x120];
557 u8 lro_timer_supported_periods
[4][0x20];
559 u8 reserved_at_200
[0x600];
562 struct mlx5_ifc_roce_cap_bits
{
564 u8 reserved_at_1
[0x1f];
566 u8 reserved_at_20
[0x60];
568 u8 reserved_at_80
[0xc];
570 u8 reserved_at_90
[0x8];
571 u8 roce_version
[0x8];
573 u8 reserved_at_a0
[0x10];
574 u8 r_roce_dest_udp_port
[0x10];
576 u8 r_roce_max_src_udp_port
[0x10];
577 u8 r_roce_min_src_udp_port
[0x10];
579 u8 reserved_at_e0
[0x10];
580 u8 roce_address_table_size
[0x10];
582 u8 reserved_at_100
[0x700];
586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
588 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
589 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
590 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
591 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
592 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
593 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
594 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
606 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
609 struct mlx5_ifc_atomic_caps_bits
{
610 u8 reserved_at_0
[0x40];
612 u8 atomic_req_8B_endianess_mode
[0x2];
613 u8 reserved_at_42
[0x4];
614 u8 supported_atomic_req_8B_endianess_mode_1
[0x1];
616 u8 reserved_at_47
[0x19];
618 u8 reserved_at_60
[0x20];
620 u8 reserved_at_80
[0x10];
621 u8 atomic_operations
[0x10];
623 u8 reserved_at_a0
[0x10];
624 u8 atomic_size_qp
[0x10];
626 u8 reserved_at_c0
[0x10];
627 u8 atomic_size_dc
[0x10];
629 u8 reserved_at_e0
[0x720];
632 struct mlx5_ifc_odp_cap_bits
{
633 u8 reserved_at_0
[0x40];
636 u8 reserved_at_41
[0x1f];
638 u8 reserved_at_60
[0x20];
640 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
642 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
644 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
646 u8 reserved_at_e0
[0x720];
649 struct mlx5_ifc_calc_op
{
650 u8 reserved_at_0
[0x10];
651 u8 reserved_at_10
[0x9];
652 u8 op_swap_endianness
[0x1];
661 struct mlx5_ifc_vector_calc_cap_bits
{
663 u8 reserved_at_1
[0x1f];
664 u8 reserved_at_20
[0x8];
665 u8 max_vec_count
[0x8];
666 u8 reserved_at_30
[0xd];
667 u8 max_chunk_size
[0x3];
668 struct mlx5_ifc_calc_op calc0
;
669 struct mlx5_ifc_calc_op calc1
;
670 struct mlx5_ifc_calc_op calc2
;
671 struct mlx5_ifc_calc_op calc3
;
673 u8 reserved_at_e0
[0x720];
677 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
678 MLX5_WQ_TYPE_CYCLIC
= 0x1,
679 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
= 0x2,
683 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
684 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
688 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
689 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
690 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
691 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
692 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
696 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
697 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
698 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
699 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
700 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
701 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
705 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
706 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
710 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
711 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
712 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
716 MLX5_CAP_PORT_TYPE_IB
= 0x0,
717 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
720 struct mlx5_ifc_cmd_hca_cap_bits
{
721 u8 reserved_at_0
[0x80];
723 u8 log_max_srq_sz
[0x8];
724 u8 log_max_qp_sz
[0x8];
725 u8 reserved_at_90
[0xb];
728 u8 reserved_at_a0
[0xb];
730 u8 reserved_at_b0
[0x10];
732 u8 reserved_at_c0
[0x8];
733 u8 log_max_cq_sz
[0x8];
734 u8 reserved_at_d0
[0xb];
737 u8 log_max_eq_sz
[0x8];
738 u8 reserved_at_e8
[0x2];
739 u8 log_max_mkey
[0x6];
740 u8 reserved_at_f0
[0xc];
743 u8 max_indirection
[0x8];
744 u8 reserved_at_108
[0x1];
745 u8 log_max_mrw_sz
[0x7];
746 u8 reserved_at_110
[0x2];
747 u8 log_max_bsf_list_size
[0x6];
748 u8 reserved_at_118
[0x2];
749 u8 log_max_klm_list_size
[0x6];
751 u8 reserved_at_120
[0xa];
752 u8 log_max_ra_req_dc
[0x6];
753 u8 reserved_at_130
[0xa];
754 u8 log_max_ra_res_dc
[0x6];
756 u8 reserved_at_140
[0xa];
757 u8 log_max_ra_req_qp
[0x6];
758 u8 reserved_at_150
[0xa];
759 u8 log_max_ra_res_qp
[0x6];
762 u8 cc_query_allowed
[0x1];
763 u8 cc_modify_allowed
[0x1];
764 u8 reserved_at_163
[0xd];
765 u8 gid_table_size
[0x10];
767 u8 out_of_seq_cnt
[0x1];
768 u8 vport_counters
[0x1];
769 u8 retransmission_q_counters
[0x1];
770 u8 reserved_at_183
[0x3];
772 u8 pkey_table_size
[0x10];
774 u8 vport_group_manager
[0x1];
775 u8 vhca_group_manager
[0x1];
778 u8 reserved_at_1a4
[0x1];
780 u8 nic_flow_table
[0x1];
781 u8 eswitch_flow_table
[0x1];
782 u8 early_vf_enable
[0x1];
783 u8 reserved_at_1a9
[0x2];
784 u8 local_ca_ack_delay
[0x5];
785 u8 reserved_at_1af
[0x2];
787 u8 reserved_at_1b2
[0x1];
788 u8 disable_link_up
[0x1];
793 u8 reserved_at_1c0
[0x3];
795 u8 reserved_at_1c8
[0x4];
797 u8 reserved_at_1d0
[0x1];
799 u8 reserved_at_1d2
[0x4];
802 u8 reserved_at_1d8
[0x1];
811 u8 stat_rate_support
[0x10];
812 u8 reserved_at_1f0
[0xc];
815 u8 compact_address_vector
[0x1];
817 u8 reserved_at_201
[0x2];
818 u8 ipoib_basic_offloads
[0x1];
819 u8 reserved_at_205
[0xa];
820 u8 drain_sigerr
[0x1];
821 u8 cmdif_checksum
[0x2];
823 u8 reserved_at_213
[0x1];
824 u8 wq_signature
[0x1];
825 u8 sctr_data_cqe
[0x1];
826 u8 reserved_at_216
[0x1];
832 u8 eth_net_offloads
[0x1];
835 u8 reserved_at_21f
[0x1];
839 u8 cq_moderation
[0x1];
840 u8 reserved_at_223
[0x3];
844 u8 reserved_at_229
[0x1];
845 u8 scqe_break_moderation
[0x1];
846 u8 cq_period_start_from_cqe
[0x1];
848 u8 reserved_at_22d
[0x1];
851 u8 umr_ptr_rlky
[0x1];
853 u8 reserved_at_232
[0x4];
856 u8 set_deth_sqpn
[0x1];
857 u8 reserved_at_239
[0x3];
863 u8 reserved_at_240
[0xa];
865 u8 reserved_at_250
[0x8];
869 u8 reserved_at_261
[0x1];
870 u8 pad_tx_eth_packet
[0x1];
871 u8 reserved_at_263
[0x8];
872 u8 log_bf_reg_size
[0x5];
873 u8 reserved_at_270
[0x10];
875 u8 reserved_at_280
[0x10];
876 u8 max_wqe_sz_sq
[0x10];
878 u8 reserved_at_2a0
[0x10];
879 u8 max_wqe_sz_rq
[0x10];
881 u8 reserved_at_2c0
[0x10];
882 u8 max_wqe_sz_sq_dc
[0x10];
884 u8 reserved_at_2e0
[0x7];
887 u8 reserved_at_300
[0x18];
890 u8 reserved_at_320
[0x3];
891 u8 log_max_transport_domain
[0x5];
892 u8 reserved_at_328
[0x3];
894 u8 reserved_at_330
[0xb];
895 u8 log_max_xrcd
[0x5];
897 u8 reserved_at_340
[0x8];
898 u8 log_max_flow_counter_bulk
[0x8];
899 u8 max_flow_counter
[0x10];
902 u8 reserved_at_360
[0x3];
904 u8 reserved_at_368
[0x3];
906 u8 reserved_at_370
[0x3];
908 u8 reserved_at_378
[0x3];
911 u8 basic_cyclic_rcv_wqe
[0x1];
912 u8 reserved_at_381
[0x2];
914 u8 reserved_at_388
[0x3];
916 u8 reserved_at_390
[0x3];
917 u8 log_max_rqt_size
[0x5];
918 u8 reserved_at_398
[0x3];
919 u8 log_max_tis_per_sq
[0x5];
921 u8 reserved_at_3a0
[0x3];
922 u8 log_max_stride_sz_rq
[0x5];
923 u8 reserved_at_3a8
[0x3];
924 u8 log_min_stride_sz_rq
[0x5];
925 u8 reserved_at_3b0
[0x3];
926 u8 log_max_stride_sz_sq
[0x5];
927 u8 reserved_at_3b8
[0x3];
928 u8 log_min_stride_sz_sq
[0x5];
930 u8 reserved_at_3c0
[0x1b];
931 u8 log_max_wq_sz
[0x5];
933 u8 nic_vport_change_event
[0x1];
934 u8 reserved_at_3e1
[0xa];
935 u8 log_max_vlan_list
[0x5];
936 u8 reserved_at_3f0
[0x3];
937 u8 log_max_current_mc_list
[0x5];
938 u8 reserved_at_3f8
[0x3];
939 u8 log_max_current_uc_list
[0x5];
941 u8 reserved_at_400
[0x80];
943 u8 reserved_at_480
[0x3];
944 u8 log_max_l2_table
[0x5];
945 u8 reserved_at_488
[0x8];
946 u8 log_uar_page_sz
[0x10];
948 u8 reserved_at_4a0
[0x20];
949 u8 device_frequency_mhz
[0x20];
950 u8 device_frequency_khz
[0x20];
952 u8 reserved_at_500
[0x80];
954 u8 reserved_at_580
[0x3f];
955 u8 cqe_compression
[0x1];
957 u8 cqe_compression_timeout
[0x10];
958 u8 cqe_compression_max_num
[0x10];
960 u8 reserved_at_5e0
[0x10];
961 u8 tag_matching
[0x1];
962 u8 rndv_offload_rc
[0x1];
963 u8 rndv_offload_dc
[0x1];
964 u8 log_tag_matching_list_sz
[0x5];
965 u8 reserved_at_5e8
[0x3];
968 u8 reserved_at_5f0
[0x200];
971 enum mlx5_flow_destination_type
{
972 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
973 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
974 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
976 MLX5_FLOW_DESTINATION_TYPE_COUNTER
= 0x100,
979 struct mlx5_ifc_dest_format_struct_bits
{
980 u8 destination_type
[0x8];
981 u8 destination_id
[0x18];
983 u8 reserved_at_20
[0x20];
986 struct mlx5_ifc_flow_counter_list_bits
{
988 u8 num_of_counters
[0xf];
989 u8 flow_counter_id
[0x10];
991 u8 reserved_at_20
[0x20];
994 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits
{
995 struct mlx5_ifc_dest_format_struct_bits dest_format_struct
;
996 struct mlx5_ifc_flow_counter_list_bits flow_counter_list
;
997 u8 reserved_at_0
[0x40];
1000 struct mlx5_ifc_fte_match_param_bits
{
1001 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
1003 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
1005 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
1007 u8 reserved_at_600
[0xa00];
1011 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
1012 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
1013 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
1014 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
1015 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
1018 struct mlx5_ifc_rx_hash_field_select_bits
{
1019 u8 l3_prot_type
[0x1];
1020 u8 l4_prot_type
[0x1];
1021 u8 selected_fields
[0x1e];
1025 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
1026 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
1030 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
1031 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
1034 struct mlx5_ifc_wq_bits
{
1036 u8 wq_signature
[0x1];
1037 u8 end_padding_mode
[0x2];
1039 u8 reserved_at_8
[0x18];
1041 u8 hds_skip_first_sge
[0x1];
1042 u8 log2_hds_buf_size
[0x3];
1043 u8 reserved_at_24
[0x7];
1044 u8 page_offset
[0x5];
1047 u8 reserved_at_40
[0x8];
1050 u8 reserved_at_60
[0x8];
1055 u8 hw_counter
[0x20];
1057 u8 sw_counter
[0x20];
1059 u8 reserved_at_100
[0xc];
1060 u8 log_wq_stride
[0x4];
1061 u8 reserved_at_110
[0x3];
1062 u8 log_wq_pg_sz
[0x5];
1063 u8 reserved_at_118
[0x3];
1066 u8 reserved_at_120
[0x15];
1067 u8 log_wqe_num_of_strides
[0x3];
1068 u8 two_byte_shift_en
[0x1];
1069 u8 reserved_at_139
[0x4];
1070 u8 log_wqe_stride_size
[0x3];
1072 u8 reserved_at_140
[0x4c0];
1074 struct mlx5_ifc_cmd_pas_bits pas
[0];
1077 struct mlx5_ifc_rq_num_bits
{
1078 u8 reserved_at_0
[0x8];
1082 struct mlx5_ifc_mac_address_layout_bits
{
1083 u8 reserved_at_0
[0x10];
1084 u8 mac_addr_47_32
[0x10];
1086 u8 mac_addr_31_0
[0x20];
1089 struct mlx5_ifc_vlan_layout_bits
{
1090 u8 reserved_at_0
[0x14];
1093 u8 reserved_at_20
[0x20];
1096 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
1097 u8 reserved_at_0
[0xa0];
1099 u8 min_time_between_cnps
[0x20];
1101 u8 reserved_at_c0
[0x12];
1103 u8 reserved_at_d8
[0x5];
1104 u8 cnp_802p_prio
[0x3];
1106 u8 reserved_at_e0
[0x720];
1109 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
1110 u8 reserved_at_0
[0x60];
1112 u8 reserved_at_60
[0x4];
1113 u8 clamp_tgt_rate
[0x1];
1114 u8 reserved_at_65
[0x3];
1115 u8 clamp_tgt_rate_after_time_inc
[0x1];
1116 u8 reserved_at_69
[0x17];
1118 u8 reserved_at_80
[0x20];
1120 u8 rpg_time_reset
[0x20];
1122 u8 rpg_byte_reset
[0x20];
1124 u8 rpg_threshold
[0x20];
1126 u8 rpg_max_rate
[0x20];
1128 u8 rpg_ai_rate
[0x20];
1130 u8 rpg_hai_rate
[0x20];
1134 u8 rpg_min_dec_fac
[0x20];
1136 u8 rpg_min_rate
[0x20];
1138 u8 reserved_at_1c0
[0xe0];
1140 u8 rate_to_set_on_first_cnp
[0x20];
1144 u8 dce_tcp_rtt
[0x20];
1146 u8 rate_reduce_monitor_period
[0x20];
1148 u8 reserved_at_320
[0x20];
1150 u8 initial_alpha_value
[0x20];
1152 u8 reserved_at_360
[0x4a0];
1155 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1156 u8 reserved_at_0
[0x80];
1158 u8 rppp_max_rps
[0x20];
1160 u8 rpg_time_reset
[0x20];
1162 u8 rpg_byte_reset
[0x20];
1164 u8 rpg_threshold
[0x20];
1166 u8 rpg_max_rate
[0x20];
1168 u8 rpg_ai_rate
[0x20];
1170 u8 rpg_hai_rate
[0x20];
1174 u8 rpg_min_dec_fac
[0x20];
1176 u8 rpg_min_rate
[0x20];
1178 u8 reserved_at_1c0
[0x640];
1182 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1183 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1184 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1187 struct mlx5_ifc_resize_field_select_bits
{
1188 u8 resize_field_select
[0x20];
1192 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1193 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1194 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1195 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1198 struct mlx5_ifc_modify_field_select_bits
{
1199 u8 modify_field_select
[0x20];
1202 struct mlx5_ifc_field_select_r_roce_np_bits
{
1203 u8 field_select_r_roce_np
[0x20];
1206 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1207 u8 field_select_r_roce_rp
[0x20];
1211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1216 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1217 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1218 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1223 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1224 u8 field_select_8021qaurp
[0x20];
1227 struct mlx5_ifc_phys_layer_cntrs_bits
{
1228 u8 time_since_last_clear_high
[0x20];
1230 u8 time_since_last_clear_low
[0x20];
1232 u8 symbol_errors_high
[0x20];
1234 u8 symbol_errors_low
[0x20];
1236 u8 sync_headers_errors_high
[0x20];
1238 u8 sync_headers_errors_low
[0x20];
1240 u8 edpl_bip_errors_lane0_high
[0x20];
1242 u8 edpl_bip_errors_lane0_low
[0x20];
1244 u8 edpl_bip_errors_lane1_high
[0x20];
1246 u8 edpl_bip_errors_lane1_low
[0x20];
1248 u8 edpl_bip_errors_lane2_high
[0x20];
1250 u8 edpl_bip_errors_lane2_low
[0x20];
1252 u8 edpl_bip_errors_lane3_high
[0x20];
1254 u8 edpl_bip_errors_lane3_low
[0x20];
1256 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1258 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1260 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1262 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1264 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1266 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1268 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1270 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1272 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1274 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1276 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1278 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1280 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1282 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1284 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1286 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1288 u8 rs_fec_corrected_blocks_high
[0x20];
1290 u8 rs_fec_corrected_blocks_low
[0x20];
1292 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1294 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1296 u8 rs_fec_no_errors_blocks_high
[0x20];
1298 u8 rs_fec_no_errors_blocks_low
[0x20];
1300 u8 rs_fec_single_error_blocks_high
[0x20];
1302 u8 rs_fec_single_error_blocks_low
[0x20];
1304 u8 rs_fec_corrected_symbols_total_high
[0x20];
1306 u8 rs_fec_corrected_symbols_total_low
[0x20];
1308 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1310 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1312 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1314 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1316 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1318 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1320 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1322 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1324 u8 link_down_events
[0x20];
1326 u8 successful_recovery_events
[0x20];
1328 u8 reserved_at_640
[0x180];
1331 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits
{
1332 u8 symbol_error_counter
[0x10];
1334 u8 link_error_recovery_counter
[0x8];
1336 u8 link_downed_counter
[0x8];
1338 u8 port_rcv_errors
[0x10];
1340 u8 port_rcv_remote_physical_errors
[0x10];
1342 u8 port_rcv_switch_relay_errors
[0x10];
1344 u8 port_xmit_discards
[0x10];
1346 u8 port_xmit_constraint_errors
[0x8];
1348 u8 port_rcv_constraint_errors
[0x8];
1350 u8 reserved_at_70
[0x8];
1352 u8 link_overrun_errors
[0x8];
1354 u8 reserved_at_80
[0x10];
1356 u8 vl_15_dropped
[0x10];
1358 u8 reserved_at_a0
[0xa0];
1361 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits
{
1362 u8 transmit_queue_high
[0x20];
1364 u8 transmit_queue_low
[0x20];
1366 u8 reserved_at_40
[0x780];
1369 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1370 u8 rx_octets_high
[0x20];
1372 u8 rx_octets_low
[0x20];
1374 u8 reserved_at_40
[0xc0];
1376 u8 rx_frames_high
[0x20];
1378 u8 rx_frames_low
[0x20];
1380 u8 tx_octets_high
[0x20];
1382 u8 tx_octets_low
[0x20];
1384 u8 reserved_at_180
[0xc0];
1386 u8 tx_frames_high
[0x20];
1388 u8 tx_frames_low
[0x20];
1390 u8 rx_pause_high
[0x20];
1392 u8 rx_pause_low
[0x20];
1394 u8 rx_pause_duration_high
[0x20];
1396 u8 rx_pause_duration_low
[0x20];
1398 u8 tx_pause_high
[0x20];
1400 u8 tx_pause_low
[0x20];
1402 u8 tx_pause_duration_high
[0x20];
1404 u8 tx_pause_duration_low
[0x20];
1406 u8 rx_pause_transition_high
[0x20];
1408 u8 rx_pause_transition_low
[0x20];
1410 u8 reserved_at_3c0
[0x400];
1413 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
1414 u8 port_transmit_wait_high
[0x20];
1416 u8 port_transmit_wait_low
[0x20];
1418 u8 reserved_at_40
[0x780];
1421 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
1422 u8 dot3stats_alignment_errors_high
[0x20];
1424 u8 dot3stats_alignment_errors_low
[0x20];
1426 u8 dot3stats_fcs_errors_high
[0x20];
1428 u8 dot3stats_fcs_errors_low
[0x20];
1430 u8 dot3stats_single_collision_frames_high
[0x20];
1432 u8 dot3stats_single_collision_frames_low
[0x20];
1434 u8 dot3stats_multiple_collision_frames_high
[0x20];
1436 u8 dot3stats_multiple_collision_frames_low
[0x20];
1438 u8 dot3stats_sqe_test_errors_high
[0x20];
1440 u8 dot3stats_sqe_test_errors_low
[0x20];
1442 u8 dot3stats_deferred_transmissions_high
[0x20];
1444 u8 dot3stats_deferred_transmissions_low
[0x20];
1446 u8 dot3stats_late_collisions_high
[0x20];
1448 u8 dot3stats_late_collisions_low
[0x20];
1450 u8 dot3stats_excessive_collisions_high
[0x20];
1452 u8 dot3stats_excessive_collisions_low
[0x20];
1454 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
1456 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
1458 u8 dot3stats_carrier_sense_errors_high
[0x20];
1460 u8 dot3stats_carrier_sense_errors_low
[0x20];
1462 u8 dot3stats_frame_too_longs_high
[0x20];
1464 u8 dot3stats_frame_too_longs_low
[0x20];
1466 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
1468 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
1470 u8 dot3stats_symbol_errors_high
[0x20];
1472 u8 dot3stats_symbol_errors_low
[0x20];
1474 u8 dot3control_in_unknown_opcodes_high
[0x20];
1476 u8 dot3control_in_unknown_opcodes_low
[0x20];
1478 u8 dot3in_pause_frames_high
[0x20];
1480 u8 dot3in_pause_frames_low
[0x20];
1482 u8 dot3out_pause_frames_high
[0x20];
1484 u8 dot3out_pause_frames_low
[0x20];
1486 u8 reserved_at_400
[0x3c0];
1489 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
1490 u8 ether_stats_drop_events_high
[0x20];
1492 u8 ether_stats_drop_events_low
[0x20];
1494 u8 ether_stats_octets_high
[0x20];
1496 u8 ether_stats_octets_low
[0x20];
1498 u8 ether_stats_pkts_high
[0x20];
1500 u8 ether_stats_pkts_low
[0x20];
1502 u8 ether_stats_broadcast_pkts_high
[0x20];
1504 u8 ether_stats_broadcast_pkts_low
[0x20];
1506 u8 ether_stats_multicast_pkts_high
[0x20];
1508 u8 ether_stats_multicast_pkts_low
[0x20];
1510 u8 ether_stats_crc_align_errors_high
[0x20];
1512 u8 ether_stats_crc_align_errors_low
[0x20];
1514 u8 ether_stats_undersize_pkts_high
[0x20];
1516 u8 ether_stats_undersize_pkts_low
[0x20];
1518 u8 ether_stats_oversize_pkts_high
[0x20];
1520 u8 ether_stats_oversize_pkts_low
[0x20];
1522 u8 ether_stats_fragments_high
[0x20];
1524 u8 ether_stats_fragments_low
[0x20];
1526 u8 ether_stats_jabbers_high
[0x20];
1528 u8 ether_stats_jabbers_low
[0x20];
1530 u8 ether_stats_collisions_high
[0x20];
1532 u8 ether_stats_collisions_low
[0x20];
1534 u8 ether_stats_pkts64octets_high
[0x20];
1536 u8 ether_stats_pkts64octets_low
[0x20];
1538 u8 ether_stats_pkts65to127octets_high
[0x20];
1540 u8 ether_stats_pkts65to127octets_low
[0x20];
1542 u8 ether_stats_pkts128to255octets_high
[0x20];
1544 u8 ether_stats_pkts128to255octets_low
[0x20];
1546 u8 ether_stats_pkts256to511octets_high
[0x20];
1548 u8 ether_stats_pkts256to511octets_low
[0x20];
1550 u8 ether_stats_pkts512to1023octets_high
[0x20];
1552 u8 ether_stats_pkts512to1023octets_low
[0x20];
1554 u8 ether_stats_pkts1024to1518octets_high
[0x20];
1556 u8 ether_stats_pkts1024to1518octets_low
[0x20];
1558 u8 ether_stats_pkts1519to2047octets_high
[0x20];
1560 u8 ether_stats_pkts1519to2047octets_low
[0x20];
1562 u8 ether_stats_pkts2048to4095octets_high
[0x20];
1564 u8 ether_stats_pkts2048to4095octets_low
[0x20];
1566 u8 ether_stats_pkts4096to8191octets_high
[0x20];
1568 u8 ether_stats_pkts4096to8191octets_low
[0x20];
1570 u8 ether_stats_pkts8192to10239octets_high
[0x20];
1572 u8 ether_stats_pkts8192to10239octets_low
[0x20];
1574 u8 reserved_at_540
[0x280];
1577 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
1578 u8 if_in_octets_high
[0x20];
1580 u8 if_in_octets_low
[0x20];
1582 u8 if_in_ucast_pkts_high
[0x20];
1584 u8 if_in_ucast_pkts_low
[0x20];
1586 u8 if_in_discards_high
[0x20];
1588 u8 if_in_discards_low
[0x20];
1590 u8 if_in_errors_high
[0x20];
1592 u8 if_in_errors_low
[0x20];
1594 u8 if_in_unknown_protos_high
[0x20];
1596 u8 if_in_unknown_protos_low
[0x20];
1598 u8 if_out_octets_high
[0x20];
1600 u8 if_out_octets_low
[0x20];
1602 u8 if_out_ucast_pkts_high
[0x20];
1604 u8 if_out_ucast_pkts_low
[0x20];
1606 u8 if_out_discards_high
[0x20];
1608 u8 if_out_discards_low
[0x20];
1610 u8 if_out_errors_high
[0x20];
1612 u8 if_out_errors_low
[0x20];
1614 u8 if_in_multicast_pkts_high
[0x20];
1616 u8 if_in_multicast_pkts_low
[0x20];
1618 u8 if_in_broadcast_pkts_high
[0x20];
1620 u8 if_in_broadcast_pkts_low
[0x20];
1622 u8 if_out_multicast_pkts_high
[0x20];
1624 u8 if_out_multicast_pkts_low
[0x20];
1626 u8 if_out_broadcast_pkts_high
[0x20];
1628 u8 if_out_broadcast_pkts_low
[0x20];
1630 u8 reserved_at_340
[0x480];
1633 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
1634 u8 a_frames_transmitted_ok_high
[0x20];
1636 u8 a_frames_transmitted_ok_low
[0x20];
1638 u8 a_frames_received_ok_high
[0x20];
1640 u8 a_frames_received_ok_low
[0x20];
1642 u8 a_frame_check_sequence_errors_high
[0x20];
1644 u8 a_frame_check_sequence_errors_low
[0x20];
1646 u8 a_alignment_errors_high
[0x20];
1648 u8 a_alignment_errors_low
[0x20];
1650 u8 a_octets_transmitted_ok_high
[0x20];
1652 u8 a_octets_transmitted_ok_low
[0x20];
1654 u8 a_octets_received_ok_high
[0x20];
1656 u8 a_octets_received_ok_low
[0x20];
1658 u8 a_multicast_frames_xmitted_ok_high
[0x20];
1660 u8 a_multicast_frames_xmitted_ok_low
[0x20];
1662 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
1664 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
1666 u8 a_multicast_frames_received_ok_high
[0x20];
1668 u8 a_multicast_frames_received_ok_low
[0x20];
1670 u8 a_broadcast_frames_received_ok_high
[0x20];
1672 u8 a_broadcast_frames_received_ok_low
[0x20];
1674 u8 a_in_range_length_errors_high
[0x20];
1676 u8 a_in_range_length_errors_low
[0x20];
1678 u8 a_out_of_range_length_field_high
[0x20];
1680 u8 a_out_of_range_length_field_low
[0x20];
1682 u8 a_frame_too_long_errors_high
[0x20];
1684 u8 a_frame_too_long_errors_low
[0x20];
1686 u8 a_symbol_error_during_carrier_high
[0x20];
1688 u8 a_symbol_error_during_carrier_low
[0x20];
1690 u8 a_mac_control_frames_transmitted_high
[0x20];
1692 u8 a_mac_control_frames_transmitted_low
[0x20];
1694 u8 a_mac_control_frames_received_high
[0x20];
1696 u8 a_mac_control_frames_received_low
[0x20];
1698 u8 a_unsupported_opcodes_received_high
[0x20];
1700 u8 a_unsupported_opcodes_received_low
[0x20];
1702 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
1704 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
1706 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
1708 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
1710 u8 reserved_at_4c0
[0x300];
1713 struct mlx5_ifc_cmd_inter_comp_event_bits
{
1714 u8 command_completion_vector
[0x20];
1716 u8 reserved_at_20
[0xc0];
1719 struct mlx5_ifc_stall_vl_event_bits
{
1720 u8 reserved_at_0
[0x18];
1722 u8 reserved_at_19
[0x3];
1725 u8 reserved_at_20
[0xa0];
1728 struct mlx5_ifc_db_bf_congestion_event_bits
{
1729 u8 event_subtype
[0x8];
1730 u8 reserved_at_8
[0x8];
1731 u8 congestion_level
[0x8];
1732 u8 reserved_at_18
[0x8];
1734 u8 reserved_at_20
[0xa0];
1737 struct mlx5_ifc_gpio_event_bits
{
1738 u8 reserved_at_0
[0x60];
1740 u8 gpio_event_hi
[0x20];
1742 u8 gpio_event_lo
[0x20];
1744 u8 reserved_at_a0
[0x40];
1747 struct mlx5_ifc_port_state_change_event_bits
{
1748 u8 reserved_at_0
[0x40];
1751 u8 reserved_at_44
[0x1c];
1753 u8 reserved_at_60
[0x80];
1756 struct mlx5_ifc_dropped_packet_logged_bits
{
1757 u8 reserved_at_0
[0xe0];
1761 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
1762 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
1765 struct mlx5_ifc_cq_error_bits
{
1766 u8 reserved_at_0
[0x8];
1769 u8 reserved_at_20
[0x20];
1771 u8 reserved_at_40
[0x18];
1774 u8 reserved_at_60
[0x80];
1777 struct mlx5_ifc_rdma_page_fault_event_bits
{
1778 u8 bytes_committed
[0x20];
1782 u8 reserved_at_40
[0x10];
1783 u8 packet_len
[0x10];
1785 u8 rdma_op_len
[0x20];
1789 u8 reserved_at_c0
[0x5];
1796 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
1797 u8 bytes_committed
[0x20];
1799 u8 reserved_at_20
[0x10];
1802 u8 reserved_at_40
[0x10];
1805 u8 reserved_at_60
[0x60];
1807 u8 reserved_at_c0
[0x5];
1814 struct mlx5_ifc_qp_events_bits
{
1815 u8 reserved_at_0
[0xa0];
1818 u8 reserved_at_a8
[0x18];
1820 u8 reserved_at_c0
[0x8];
1821 u8 qpn_rqn_sqn
[0x18];
1824 struct mlx5_ifc_dct_events_bits
{
1825 u8 reserved_at_0
[0xc0];
1827 u8 reserved_at_c0
[0x8];
1828 u8 dct_number
[0x18];
1831 struct mlx5_ifc_comp_event_bits
{
1832 u8 reserved_at_0
[0xc0];
1834 u8 reserved_at_c0
[0x8];
1839 MLX5_QPC_STATE_RST
= 0x0,
1840 MLX5_QPC_STATE_INIT
= 0x1,
1841 MLX5_QPC_STATE_RTR
= 0x2,
1842 MLX5_QPC_STATE_RTS
= 0x3,
1843 MLX5_QPC_STATE_SQER
= 0x4,
1844 MLX5_QPC_STATE_ERR
= 0x6,
1845 MLX5_QPC_STATE_SQD
= 0x7,
1846 MLX5_QPC_STATE_SUSPENDED
= 0x9,
1850 MLX5_QPC_ST_RC
= 0x0,
1851 MLX5_QPC_ST_UC
= 0x1,
1852 MLX5_QPC_ST_UD
= 0x2,
1853 MLX5_QPC_ST_XRC
= 0x3,
1854 MLX5_QPC_ST_DCI
= 0x5,
1855 MLX5_QPC_ST_QP0
= 0x7,
1856 MLX5_QPC_ST_QP1
= 0x8,
1857 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
1858 MLX5_QPC_ST_REG_UMR
= 0xc,
1862 MLX5_QPC_PM_STATE_ARMED
= 0x0,
1863 MLX5_QPC_PM_STATE_REARM
= 0x1,
1864 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
1865 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
1869 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
1870 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
1874 MLX5_QPC_MTU_256_BYTES
= 0x1,
1875 MLX5_QPC_MTU_512_BYTES
= 0x2,
1876 MLX5_QPC_MTU_1K_BYTES
= 0x3,
1877 MLX5_QPC_MTU_2K_BYTES
= 0x4,
1878 MLX5_QPC_MTU_4K_BYTES
= 0x5,
1879 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
1883 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
1884 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
1885 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
1886 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
1887 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
1888 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
1889 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
1890 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
1894 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
1895 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
1896 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
1900 MLX5_QPC_CS_RES_DISABLE
= 0x0,
1901 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
1902 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
1905 struct mlx5_ifc_qpc_bits
{
1907 u8 reserved_at_4
[0x4];
1909 u8 reserved_at_10
[0x3];
1911 u8 reserved_at_15
[0x7];
1912 u8 end_padding_mode
[0x2];
1913 u8 reserved_at_1e
[0x2];
1915 u8 wq_signature
[0x1];
1916 u8 block_lb_mc
[0x1];
1917 u8 atomic_like_write_en
[0x1];
1918 u8 latency_sensitive
[0x1];
1919 u8 reserved_at_24
[0x1];
1920 u8 drain_sigerr
[0x1];
1921 u8 reserved_at_26
[0x2];
1925 u8 log_msg_max
[0x5];
1926 u8 reserved_at_48
[0x1];
1927 u8 log_rq_size
[0x4];
1928 u8 log_rq_stride
[0x3];
1930 u8 log_sq_size
[0x4];
1931 u8 reserved_at_55
[0x6];
1933 u8 ulp_stateless_offload_mode
[0x4];
1935 u8 counter_set_id
[0x8];
1938 u8 reserved_at_80
[0x8];
1939 u8 user_index
[0x18];
1941 u8 reserved_at_a0
[0x3];
1942 u8 log_page_size
[0x5];
1943 u8 remote_qpn
[0x18];
1945 struct mlx5_ifc_ads_bits primary_address_path
;
1947 struct mlx5_ifc_ads_bits secondary_address_path
;
1949 u8 log_ack_req_freq
[0x4];
1950 u8 reserved_at_384
[0x4];
1951 u8 log_sra_max
[0x3];
1952 u8 reserved_at_38b
[0x2];
1953 u8 retry_count
[0x3];
1955 u8 reserved_at_393
[0x1];
1957 u8 cur_rnr_retry
[0x3];
1958 u8 cur_retry_count
[0x3];
1959 u8 reserved_at_39b
[0x5];
1961 u8 reserved_at_3a0
[0x20];
1963 u8 reserved_at_3c0
[0x8];
1964 u8 next_send_psn
[0x18];
1966 u8 reserved_at_3e0
[0x8];
1969 u8 reserved_at_400
[0x40];
1971 u8 reserved_at_440
[0x8];
1972 u8 last_acked_psn
[0x18];
1974 u8 reserved_at_460
[0x8];
1977 u8 reserved_at_480
[0x8];
1978 u8 log_rra_max
[0x3];
1979 u8 reserved_at_48b
[0x1];
1980 u8 atomic_mode
[0x4];
1984 u8 reserved_at_493
[0x1];
1985 u8 page_offset
[0x6];
1986 u8 reserved_at_49a
[0x3];
1987 u8 cd_slave_receive
[0x1];
1988 u8 cd_slave_send
[0x1];
1991 u8 reserved_at_4a0
[0x3];
1992 u8 min_rnr_nak
[0x5];
1993 u8 next_rcv_psn
[0x18];
1995 u8 reserved_at_4c0
[0x8];
1998 u8 reserved_at_4e0
[0x8];
2005 u8 reserved_at_560
[0x5];
2007 u8 srqn_rmpn_xrqn
[0x18];
2009 u8 reserved_at_580
[0x8];
2012 u8 hw_sq_wqebb_counter
[0x10];
2013 u8 sw_sq_wqebb_counter
[0x10];
2015 u8 hw_rq_counter
[0x20];
2017 u8 sw_rq_counter
[0x20];
2019 u8 reserved_at_600
[0x20];
2021 u8 reserved_at_620
[0xf];
2026 u8 dc_access_key
[0x40];
2028 u8 reserved_at_680
[0xc0];
2031 struct mlx5_ifc_roce_addr_layout_bits
{
2032 u8 source_l3_address
[16][0x8];
2034 u8 reserved_at_80
[0x3];
2037 u8 source_mac_47_32
[0x10];
2039 u8 source_mac_31_0
[0x20];
2041 u8 reserved_at_c0
[0x14];
2042 u8 roce_l3_type
[0x4];
2043 u8 roce_version
[0x8];
2045 u8 reserved_at_e0
[0x20];
2048 union mlx5_ifc_hca_cap_union_bits
{
2049 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
2050 struct mlx5_ifc_odp_cap_bits odp_cap
;
2051 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
2052 struct mlx5_ifc_roce_cap_bits roce_cap
;
2053 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
2054 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
2055 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
2056 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
2057 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap
;
2058 struct mlx5_ifc_qos_cap_bits qos_cap
;
2059 u8 reserved_at_0
[0x8000];
2063 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
2064 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
2065 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
2066 MLX5_FLOW_CONTEXT_ACTION_COUNT
= 0x8,
2069 struct mlx5_ifc_flow_context_bits
{
2070 u8 reserved_at_0
[0x20];
2074 u8 reserved_at_40
[0x8];
2077 u8 reserved_at_60
[0x10];
2080 u8 reserved_at_80
[0x8];
2081 u8 destination_list_size
[0x18];
2083 u8 reserved_at_a0
[0x8];
2084 u8 flow_counter_list_size
[0x18];
2086 u8 reserved_at_c0
[0x140];
2088 struct mlx5_ifc_fte_match_param_bits match_value
;
2090 u8 reserved_at_1200
[0x600];
2092 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination
[0];
2096 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
2097 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
2100 struct mlx5_ifc_xrc_srqc_bits
{
2102 u8 log_xrc_srq_size
[0x4];
2103 u8 reserved_at_8
[0x18];
2105 u8 wq_signature
[0x1];
2107 u8 reserved_at_22
[0x1];
2109 u8 basic_cyclic_rcv_wqe
[0x1];
2110 u8 log_rq_stride
[0x3];
2113 u8 page_offset
[0x6];
2114 u8 reserved_at_46
[0x2];
2117 u8 reserved_at_60
[0x20];
2119 u8 user_index_equal_xrc_srqn
[0x1];
2120 u8 reserved_at_81
[0x1];
2121 u8 log_page_size
[0x6];
2122 u8 user_index
[0x18];
2124 u8 reserved_at_a0
[0x20];
2126 u8 reserved_at_c0
[0x8];
2132 u8 reserved_at_100
[0x40];
2134 u8 db_record_addr_h
[0x20];
2136 u8 db_record_addr_l
[0x1e];
2137 u8 reserved_at_17e
[0x2];
2139 u8 reserved_at_180
[0x80];
2142 struct mlx5_ifc_traffic_counter_bits
{
2148 struct mlx5_ifc_tisc_bits
{
2149 u8 reserved_at_0
[0xc];
2151 u8 reserved_at_10
[0x10];
2153 u8 reserved_at_20
[0x100];
2155 u8 reserved_at_120
[0x8];
2156 u8 transport_domain
[0x18];
2158 u8 reserved_at_140
[0x3c0];
2162 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2163 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2167 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2168 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2172 MLX5_RX_HASH_FN_NONE
= 0x0,
2173 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2174 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2178 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
= 0x1,
2179 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_
= 0x2,
2182 struct mlx5_ifc_tirc_bits
{
2183 u8 reserved_at_0
[0x20];
2186 u8 reserved_at_24
[0x1c];
2188 u8 reserved_at_40
[0x40];
2190 u8 reserved_at_80
[0x4];
2191 u8 lro_timeout_period_usecs
[0x10];
2192 u8 lro_enable_mask
[0x4];
2193 u8 lro_max_ip_payload_size
[0x8];
2195 u8 reserved_at_a0
[0x40];
2197 u8 reserved_at_e0
[0x8];
2198 u8 inline_rqn
[0x18];
2200 u8 rx_hash_symmetric
[0x1];
2201 u8 reserved_at_101
[0x1];
2202 u8 tunneled_offload_en
[0x1];
2203 u8 reserved_at_103
[0x5];
2204 u8 indirect_table
[0x18];
2207 u8 reserved_at_124
[0x2];
2208 u8 self_lb_block
[0x2];
2209 u8 transport_domain
[0x18];
2211 u8 rx_hash_toeplitz_key
[10][0x20];
2213 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2215 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2217 u8 reserved_at_2c0
[0x4c0];
2221 MLX5_SRQC_STATE_GOOD
= 0x0,
2222 MLX5_SRQC_STATE_ERROR
= 0x1,
2225 struct mlx5_ifc_srqc_bits
{
2227 u8 log_srq_size
[0x4];
2228 u8 reserved_at_8
[0x18];
2230 u8 wq_signature
[0x1];
2232 u8 reserved_at_22
[0x1];
2234 u8 reserved_at_24
[0x1];
2235 u8 log_rq_stride
[0x3];
2238 u8 page_offset
[0x6];
2239 u8 reserved_at_46
[0x2];
2242 u8 reserved_at_60
[0x20];
2244 u8 reserved_at_80
[0x2];
2245 u8 log_page_size
[0x6];
2246 u8 reserved_at_88
[0x18];
2248 u8 reserved_at_a0
[0x20];
2250 u8 reserved_at_c0
[0x8];
2256 u8 reserved_at_100
[0x40];
2260 u8 reserved_at_180
[0x80];
2264 MLX5_SQC_STATE_RST
= 0x0,
2265 MLX5_SQC_STATE_RDY
= 0x1,
2266 MLX5_SQC_STATE_ERR
= 0x3,
2269 struct mlx5_ifc_sqc_bits
{
2273 u8 flush_in_error_en
[0x1];
2274 u8 reserved_at_4
[0x1];
2275 u8 min_wqe_inline_mode
[0x3];
2278 u8 reserved_at_d
[0x13];
2280 u8 reserved_at_20
[0x8];
2281 u8 user_index
[0x18];
2283 u8 reserved_at_40
[0x8];
2286 u8 reserved_at_60
[0x90];
2288 u8 packet_pacing_rate_limit_index
[0x10];
2289 u8 tis_lst_sz
[0x10];
2290 u8 reserved_at_110
[0x10];
2292 u8 reserved_at_120
[0x40];
2294 u8 reserved_at_160
[0x8];
2297 struct mlx5_ifc_wq_bits wq
;
2300 struct mlx5_ifc_rqtc_bits
{
2301 u8 reserved_at_0
[0xa0];
2303 u8 reserved_at_a0
[0x10];
2304 u8 rqt_max_size
[0x10];
2306 u8 reserved_at_c0
[0x10];
2307 u8 rqt_actual_size
[0x10];
2309 u8 reserved_at_e0
[0x6a0];
2311 struct mlx5_ifc_rq_num_bits rq_num
[0];
2315 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
2316 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
2320 MLX5_RQC_STATE_RST
= 0x0,
2321 MLX5_RQC_STATE_RDY
= 0x1,
2322 MLX5_RQC_STATE_ERR
= 0x3,
2325 struct mlx5_ifc_rqc_bits
{
2327 u8 reserved_at_1
[0x1];
2328 u8 scatter_fcs
[0x1];
2330 u8 mem_rq_type
[0x4];
2332 u8 reserved_at_c
[0x1];
2333 u8 flush_in_error_en
[0x1];
2334 u8 reserved_at_e
[0x12];
2336 u8 reserved_at_20
[0x8];
2337 u8 user_index
[0x18];
2339 u8 reserved_at_40
[0x8];
2342 u8 counter_set_id
[0x8];
2343 u8 reserved_at_68
[0x18];
2345 u8 reserved_at_80
[0x8];
2348 u8 reserved_at_a0
[0xe0];
2350 struct mlx5_ifc_wq_bits wq
;
2354 MLX5_RMPC_STATE_RDY
= 0x1,
2355 MLX5_RMPC_STATE_ERR
= 0x3,
2358 struct mlx5_ifc_rmpc_bits
{
2359 u8 reserved_at_0
[0x8];
2361 u8 reserved_at_c
[0x14];
2363 u8 basic_cyclic_rcv_wqe
[0x1];
2364 u8 reserved_at_21
[0x1f];
2366 u8 reserved_at_40
[0x140];
2368 struct mlx5_ifc_wq_bits wq
;
2371 struct mlx5_ifc_nic_vport_context_bits
{
2372 u8 reserved_at_0
[0x5];
2373 u8 min_wqe_inline_mode
[0x3];
2374 u8 reserved_at_8
[0x17];
2377 u8 arm_change_event
[0x1];
2378 u8 reserved_at_21
[0x1a];
2379 u8 event_on_mtu
[0x1];
2380 u8 event_on_promisc_change
[0x1];
2381 u8 event_on_vlan_change
[0x1];
2382 u8 event_on_mc_address_change
[0x1];
2383 u8 event_on_uc_address_change
[0x1];
2385 u8 reserved_at_40
[0xf0];
2389 u8 system_image_guid
[0x40];
2393 u8 reserved_at_200
[0x140];
2394 u8 qkey_violation_counter
[0x10];
2395 u8 reserved_at_350
[0x430];
2399 u8 promisc_all
[0x1];
2400 u8 reserved_at_783
[0x2];
2401 u8 allowed_list_type
[0x3];
2402 u8 reserved_at_788
[0xc];
2403 u8 allowed_list_size
[0xc];
2405 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
2407 u8 reserved_at_7e0
[0x20];
2409 u8 current_uc_mac_address
[0][0x40];
2413 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
2414 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
2415 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
2418 struct mlx5_ifc_mkc_bits
{
2419 u8 reserved_at_0
[0x1];
2421 u8 reserved_at_2
[0xd];
2422 u8 small_fence_on_rdma_read_response
[0x1];
2429 u8 access_mode
[0x2];
2430 u8 reserved_at_18
[0x8];
2435 u8 reserved_at_40
[0x20];
2440 u8 reserved_at_63
[0x2];
2441 u8 expected_sigerr_count
[0x1];
2442 u8 reserved_at_66
[0x1];
2446 u8 start_addr
[0x40];
2450 u8 bsf_octword_size
[0x20];
2452 u8 reserved_at_120
[0x80];
2454 u8 translations_octword_size
[0x20];
2456 u8 reserved_at_1c0
[0x1b];
2457 u8 log_page_size
[0x5];
2459 u8 reserved_at_1e0
[0x20];
2462 struct mlx5_ifc_pkey_bits
{
2463 u8 reserved_at_0
[0x10];
2467 struct mlx5_ifc_array128_auto_bits
{
2468 u8 array128_auto
[16][0x8];
2471 struct mlx5_ifc_hca_vport_context_bits
{
2472 u8 field_select
[0x20];
2474 u8 reserved_at_20
[0xe0];
2476 u8 sm_virt_aware
[0x1];
2479 u8 grh_required
[0x1];
2480 u8 reserved_at_104
[0xc];
2481 u8 port_physical_state
[0x4];
2482 u8 vport_state_policy
[0x4];
2484 u8 vport_state
[0x4];
2486 u8 reserved_at_120
[0x20];
2488 u8 system_image_guid
[0x40];
2496 u8 cap_mask1_field_select
[0x20];
2500 u8 cap_mask2_field_select
[0x20];
2502 u8 reserved_at_280
[0x80];
2505 u8 reserved_at_310
[0x4];
2506 u8 init_type_reply
[0x4];
2508 u8 subnet_timeout
[0x5];
2512 u8 reserved_at_334
[0xc];
2514 u8 qkey_violation_counter
[0x10];
2515 u8 pkey_violation_counter
[0x10];
2517 u8 reserved_at_360
[0xca0];
2520 struct mlx5_ifc_esw_vport_context_bits
{
2521 u8 reserved_at_0
[0x3];
2522 u8 vport_svlan_strip
[0x1];
2523 u8 vport_cvlan_strip
[0x1];
2524 u8 vport_svlan_insert
[0x1];
2525 u8 vport_cvlan_insert
[0x2];
2526 u8 reserved_at_8
[0x18];
2528 u8 reserved_at_20
[0x20];
2537 u8 reserved_at_60
[0x7a0];
2541 MLX5_EQC_STATUS_OK
= 0x0,
2542 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
2546 MLX5_EQC_ST_ARMED
= 0x9,
2547 MLX5_EQC_ST_FIRED
= 0xa,
2550 struct mlx5_ifc_eqc_bits
{
2552 u8 reserved_at_4
[0x9];
2555 u8 reserved_at_f
[0x5];
2557 u8 reserved_at_18
[0x8];
2559 u8 reserved_at_20
[0x20];
2561 u8 reserved_at_40
[0x14];
2562 u8 page_offset
[0x6];
2563 u8 reserved_at_5a
[0x6];
2565 u8 reserved_at_60
[0x3];
2566 u8 log_eq_size
[0x5];
2569 u8 reserved_at_80
[0x20];
2571 u8 reserved_at_a0
[0x18];
2574 u8 reserved_at_c0
[0x3];
2575 u8 log_page_size
[0x5];
2576 u8 reserved_at_c8
[0x18];
2578 u8 reserved_at_e0
[0x60];
2580 u8 reserved_at_140
[0x8];
2581 u8 consumer_counter
[0x18];
2583 u8 reserved_at_160
[0x8];
2584 u8 producer_counter
[0x18];
2586 u8 reserved_at_180
[0x80];
2590 MLX5_DCTC_STATE_ACTIVE
= 0x0,
2591 MLX5_DCTC_STATE_DRAINING
= 0x1,
2592 MLX5_DCTC_STATE_DRAINED
= 0x2,
2596 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
2597 MLX5_DCTC_CS_RES_NA
= 0x1,
2598 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
2602 MLX5_DCTC_MTU_256_BYTES
= 0x1,
2603 MLX5_DCTC_MTU_512_BYTES
= 0x2,
2604 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
2605 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
2606 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
2609 struct mlx5_ifc_dctc_bits
{
2610 u8 reserved_at_0
[0x4];
2612 u8 reserved_at_8
[0x18];
2614 u8 reserved_at_20
[0x8];
2615 u8 user_index
[0x18];
2617 u8 reserved_at_40
[0x8];
2620 u8 counter_set_id
[0x8];
2621 u8 atomic_mode
[0x4];
2625 u8 atomic_like_write_en
[0x1];
2626 u8 latency_sensitive
[0x1];
2629 u8 reserved_at_73
[0xd];
2631 u8 reserved_at_80
[0x8];
2633 u8 reserved_at_90
[0x3];
2634 u8 min_rnr_nak
[0x5];
2635 u8 reserved_at_98
[0x8];
2637 u8 reserved_at_a0
[0x8];
2640 u8 reserved_at_c0
[0x8];
2644 u8 reserved_at_e8
[0x4];
2645 u8 flow_label
[0x14];
2647 u8 dc_access_key
[0x40];
2649 u8 reserved_at_140
[0x5];
2652 u8 pkey_index
[0x10];
2654 u8 reserved_at_160
[0x8];
2655 u8 my_addr_index
[0x8];
2656 u8 reserved_at_170
[0x8];
2659 u8 dc_access_key_violation_count
[0x20];
2661 u8 reserved_at_1a0
[0x14];
2667 u8 reserved_at_1c0
[0x40];
2671 MLX5_CQC_STATUS_OK
= 0x0,
2672 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
2673 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
2677 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
2678 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
2682 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
2683 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
2684 MLX5_CQC_ST_FIRED
= 0xa,
2688 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
= 0x0,
2689 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
= 0x1,
2690 MLX5_CQ_PERIOD_NUM_MODES
2693 struct mlx5_ifc_cqc_bits
{
2695 u8 reserved_at_4
[0x4];
2698 u8 reserved_at_c
[0x1];
2699 u8 scqe_break_moderation_en
[0x1];
2701 u8 cq_period_mode
[0x2];
2702 u8 cqe_comp_en
[0x1];
2703 u8 mini_cqe_res_format
[0x2];
2705 u8 reserved_at_18
[0x8];
2707 u8 reserved_at_20
[0x20];
2709 u8 reserved_at_40
[0x14];
2710 u8 page_offset
[0x6];
2711 u8 reserved_at_5a
[0x6];
2713 u8 reserved_at_60
[0x3];
2714 u8 log_cq_size
[0x5];
2717 u8 reserved_at_80
[0x4];
2719 u8 cq_max_count
[0x10];
2721 u8 reserved_at_a0
[0x18];
2724 u8 reserved_at_c0
[0x3];
2725 u8 log_page_size
[0x5];
2726 u8 reserved_at_c8
[0x18];
2728 u8 reserved_at_e0
[0x20];
2730 u8 reserved_at_100
[0x8];
2731 u8 last_notified_index
[0x18];
2733 u8 reserved_at_120
[0x8];
2734 u8 last_solicit_index
[0x18];
2736 u8 reserved_at_140
[0x8];
2737 u8 consumer_counter
[0x18];
2739 u8 reserved_at_160
[0x8];
2740 u8 producer_counter
[0x18];
2742 u8 reserved_at_180
[0x40];
2747 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
2748 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
2749 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
2750 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
2751 u8 reserved_at_0
[0x800];
2754 struct mlx5_ifc_query_adapter_param_block_bits
{
2755 u8 reserved_at_0
[0xc0];
2757 u8 reserved_at_c0
[0x8];
2758 u8 ieee_vendor_id
[0x18];
2760 u8 reserved_at_e0
[0x10];
2761 u8 vsd_vendor_id
[0x10];
2765 u8 vsd_contd_psid
[16][0x8];
2769 MLX5_XRQC_STATE_GOOD
= 0x0,
2770 MLX5_XRQC_STATE_ERROR
= 0x1,
2774 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY
= 0x0,
2775 MLX5_XRQC_TOPOLOGY_TAG_MATCHING
= 0x1,
2779 MLX5_XRQC_OFFLOAD_RNDV
= 0x1,
2782 struct mlx5_ifc_tag_matching_topology_context_bits
{
2783 u8 log_matching_list_sz
[0x4];
2784 u8 reserved_at_4
[0xc];
2785 u8 append_next_index
[0x10];
2787 u8 sw_phase_cnt
[0x10];
2788 u8 hw_phase_cnt
[0x10];
2790 u8 reserved_at_40
[0x40];
2793 struct mlx5_ifc_xrqc_bits
{
2796 u8 reserved_at_5
[0xf];
2798 u8 reserved_at_18
[0x4];
2801 u8 reserved_at_20
[0x8];
2802 u8 user_index
[0x18];
2804 u8 reserved_at_40
[0x8];
2807 u8 reserved_at_60
[0xa0];
2809 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context
;
2811 u8 reserved_at_180
[0x180];
2813 struct mlx5_ifc_wq_bits wq
;
2816 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
2817 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
2818 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
2819 u8 reserved_at_0
[0x20];
2822 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
2823 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
2824 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
2825 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
2826 u8 reserved_at_0
[0x20];
2829 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
2830 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
2831 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
2832 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
2833 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
2834 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
2835 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
2836 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
2837 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
2838 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
2839 u8 reserved_at_0
[0x7c0];
2842 union mlx5_ifc_event_auto_bits
{
2843 struct mlx5_ifc_comp_event_bits comp_event
;
2844 struct mlx5_ifc_dct_events_bits dct_events
;
2845 struct mlx5_ifc_qp_events_bits qp_events
;
2846 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
2847 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
2848 struct mlx5_ifc_cq_error_bits cq_error
;
2849 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
2850 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
2851 struct mlx5_ifc_gpio_event_bits gpio_event
;
2852 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
2853 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
2854 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
2855 u8 reserved_at_0
[0xe0];
2858 struct mlx5_ifc_health_buffer_bits
{
2859 u8 reserved_at_0
[0x100];
2861 u8 assert_existptr
[0x20];
2863 u8 assert_callra
[0x20];
2865 u8 reserved_at_140
[0x40];
2867 u8 fw_version
[0x20];
2871 u8 reserved_at_1c0
[0x20];
2873 u8 irisc_index
[0x8];
2878 struct mlx5_ifc_register_loopback_control_bits
{
2880 u8 reserved_at_1
[0x7];
2882 u8 reserved_at_10
[0x10];
2884 u8 reserved_at_20
[0x60];
2887 struct mlx5_ifc_teardown_hca_out_bits
{
2889 u8 reserved_at_8
[0x18];
2893 u8 reserved_at_40
[0x40];
2897 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
2898 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE
= 0x1,
2901 struct mlx5_ifc_teardown_hca_in_bits
{
2903 u8 reserved_at_10
[0x10];
2905 u8 reserved_at_20
[0x10];
2908 u8 reserved_at_40
[0x10];
2911 u8 reserved_at_60
[0x20];
2914 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
2916 u8 reserved_at_8
[0x18];
2920 u8 reserved_at_40
[0x40];
2923 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
2925 u8 reserved_at_10
[0x10];
2927 u8 reserved_at_20
[0x10];
2930 u8 reserved_at_40
[0x8];
2933 u8 reserved_at_60
[0x20];
2935 u8 opt_param_mask
[0x20];
2937 u8 reserved_at_a0
[0x20];
2939 struct mlx5_ifc_qpc_bits qpc
;
2941 u8 reserved_at_800
[0x80];
2944 struct mlx5_ifc_sqd2rts_qp_out_bits
{
2946 u8 reserved_at_8
[0x18];
2950 u8 reserved_at_40
[0x40];
2953 struct mlx5_ifc_sqd2rts_qp_in_bits
{
2955 u8 reserved_at_10
[0x10];
2957 u8 reserved_at_20
[0x10];
2960 u8 reserved_at_40
[0x8];
2963 u8 reserved_at_60
[0x20];
2965 u8 opt_param_mask
[0x20];
2967 u8 reserved_at_a0
[0x20];
2969 struct mlx5_ifc_qpc_bits qpc
;
2971 u8 reserved_at_800
[0x80];
2974 struct mlx5_ifc_set_roce_address_out_bits
{
2976 u8 reserved_at_8
[0x18];
2980 u8 reserved_at_40
[0x40];
2983 struct mlx5_ifc_set_roce_address_in_bits
{
2985 u8 reserved_at_10
[0x10];
2987 u8 reserved_at_20
[0x10];
2990 u8 roce_address_index
[0x10];
2991 u8 reserved_at_50
[0x10];
2993 u8 reserved_at_60
[0x20];
2995 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
2998 struct mlx5_ifc_set_mad_demux_out_bits
{
3000 u8 reserved_at_8
[0x18];
3004 u8 reserved_at_40
[0x40];
3008 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
3009 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
3012 struct mlx5_ifc_set_mad_demux_in_bits
{
3014 u8 reserved_at_10
[0x10];
3016 u8 reserved_at_20
[0x10];
3019 u8 reserved_at_40
[0x20];
3021 u8 reserved_at_60
[0x6];
3023 u8 reserved_at_68
[0x18];
3026 struct mlx5_ifc_set_l2_table_entry_out_bits
{
3028 u8 reserved_at_8
[0x18];
3032 u8 reserved_at_40
[0x40];
3035 struct mlx5_ifc_set_l2_table_entry_in_bits
{
3037 u8 reserved_at_10
[0x10];
3039 u8 reserved_at_20
[0x10];
3042 u8 reserved_at_40
[0x60];
3044 u8 reserved_at_a0
[0x8];
3045 u8 table_index
[0x18];
3047 u8 reserved_at_c0
[0x20];
3049 u8 reserved_at_e0
[0x13];
3053 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3055 u8 reserved_at_140
[0xc0];
3058 struct mlx5_ifc_set_issi_out_bits
{
3060 u8 reserved_at_8
[0x18];
3064 u8 reserved_at_40
[0x40];
3067 struct mlx5_ifc_set_issi_in_bits
{
3069 u8 reserved_at_10
[0x10];
3071 u8 reserved_at_20
[0x10];
3074 u8 reserved_at_40
[0x10];
3075 u8 current_issi
[0x10];
3077 u8 reserved_at_60
[0x20];
3080 struct mlx5_ifc_set_hca_cap_out_bits
{
3082 u8 reserved_at_8
[0x18];
3086 u8 reserved_at_40
[0x40];
3089 struct mlx5_ifc_set_hca_cap_in_bits
{
3091 u8 reserved_at_10
[0x10];
3093 u8 reserved_at_20
[0x10];
3096 u8 reserved_at_40
[0x40];
3098 union mlx5_ifc_hca_cap_union_bits capability
;
3102 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
3103 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
3104 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
3105 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
3108 struct mlx5_ifc_set_fte_out_bits
{
3110 u8 reserved_at_8
[0x18];
3114 u8 reserved_at_40
[0x40];
3117 struct mlx5_ifc_set_fte_in_bits
{
3119 u8 reserved_at_10
[0x10];
3121 u8 reserved_at_20
[0x10];
3124 u8 other_vport
[0x1];
3125 u8 reserved_at_41
[0xf];
3126 u8 vport_number
[0x10];
3128 u8 reserved_at_60
[0x20];
3131 u8 reserved_at_88
[0x18];
3133 u8 reserved_at_a0
[0x8];
3136 u8 reserved_at_c0
[0x18];
3137 u8 modify_enable_mask
[0x8];
3139 u8 reserved_at_e0
[0x20];
3141 u8 flow_index
[0x20];
3143 u8 reserved_at_120
[0xe0];
3145 struct mlx5_ifc_flow_context_bits flow_context
;
3148 struct mlx5_ifc_rts2rts_qp_out_bits
{
3150 u8 reserved_at_8
[0x18];
3154 u8 reserved_at_40
[0x40];
3157 struct mlx5_ifc_rts2rts_qp_in_bits
{
3159 u8 reserved_at_10
[0x10];
3161 u8 reserved_at_20
[0x10];
3164 u8 reserved_at_40
[0x8];
3167 u8 reserved_at_60
[0x20];
3169 u8 opt_param_mask
[0x20];
3171 u8 reserved_at_a0
[0x20];
3173 struct mlx5_ifc_qpc_bits qpc
;
3175 u8 reserved_at_800
[0x80];
3178 struct mlx5_ifc_rtr2rts_qp_out_bits
{
3180 u8 reserved_at_8
[0x18];
3184 u8 reserved_at_40
[0x40];
3187 struct mlx5_ifc_rtr2rts_qp_in_bits
{
3189 u8 reserved_at_10
[0x10];
3191 u8 reserved_at_20
[0x10];
3194 u8 reserved_at_40
[0x8];
3197 u8 reserved_at_60
[0x20];
3199 u8 opt_param_mask
[0x20];
3201 u8 reserved_at_a0
[0x20];
3203 struct mlx5_ifc_qpc_bits qpc
;
3205 u8 reserved_at_800
[0x80];
3208 struct mlx5_ifc_rst2init_qp_out_bits
{
3210 u8 reserved_at_8
[0x18];
3214 u8 reserved_at_40
[0x40];
3217 struct mlx5_ifc_rst2init_qp_in_bits
{
3219 u8 reserved_at_10
[0x10];
3221 u8 reserved_at_20
[0x10];
3224 u8 reserved_at_40
[0x8];
3227 u8 reserved_at_60
[0x20];
3229 u8 opt_param_mask
[0x20];
3231 u8 reserved_at_a0
[0x20];
3233 struct mlx5_ifc_qpc_bits qpc
;
3235 u8 reserved_at_800
[0x80];
3238 struct mlx5_ifc_query_xrq_out_bits
{
3240 u8 reserved_at_8
[0x18];
3244 u8 reserved_at_40
[0x40];
3246 struct mlx5_ifc_xrqc_bits xrq_context
;
3249 struct mlx5_ifc_query_xrq_in_bits
{
3251 u8 reserved_at_10
[0x10];
3253 u8 reserved_at_20
[0x10];
3256 u8 reserved_at_40
[0x8];
3259 u8 reserved_at_60
[0x20];
3262 struct mlx5_ifc_query_xrc_srq_out_bits
{
3264 u8 reserved_at_8
[0x18];
3268 u8 reserved_at_40
[0x40];
3270 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
3272 u8 reserved_at_280
[0x600];
3277 struct mlx5_ifc_query_xrc_srq_in_bits
{
3279 u8 reserved_at_10
[0x10];
3281 u8 reserved_at_20
[0x10];
3284 u8 reserved_at_40
[0x8];
3287 u8 reserved_at_60
[0x20];
3291 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
3292 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
3295 struct mlx5_ifc_query_vport_state_out_bits
{
3297 u8 reserved_at_8
[0x18];
3301 u8 reserved_at_40
[0x20];
3303 u8 reserved_at_60
[0x18];
3304 u8 admin_state
[0x4];
3309 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
= 0x0,
3310 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT
= 0x1,
3313 struct mlx5_ifc_query_vport_state_in_bits
{
3315 u8 reserved_at_10
[0x10];
3317 u8 reserved_at_20
[0x10];
3320 u8 other_vport
[0x1];
3321 u8 reserved_at_41
[0xf];
3322 u8 vport_number
[0x10];
3324 u8 reserved_at_60
[0x20];
3327 struct mlx5_ifc_query_vport_counter_out_bits
{
3329 u8 reserved_at_8
[0x18];
3333 u8 reserved_at_40
[0x40];
3335 struct mlx5_ifc_traffic_counter_bits received_errors
;
3337 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
3339 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
3341 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
3343 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
3345 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
3347 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
3349 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
3351 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
3353 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
3355 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
3357 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
3359 u8 reserved_at_680
[0xa00];
3363 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
3366 struct mlx5_ifc_query_vport_counter_in_bits
{
3368 u8 reserved_at_10
[0x10];
3370 u8 reserved_at_20
[0x10];
3373 u8 other_vport
[0x1];
3374 u8 reserved_at_41
[0xb];
3376 u8 vport_number
[0x10];
3378 u8 reserved_at_60
[0x60];
3381 u8 reserved_at_c1
[0x1f];
3383 u8 reserved_at_e0
[0x20];
3386 struct mlx5_ifc_query_tis_out_bits
{
3388 u8 reserved_at_8
[0x18];
3392 u8 reserved_at_40
[0x40];
3394 struct mlx5_ifc_tisc_bits tis_context
;
3397 struct mlx5_ifc_query_tis_in_bits
{
3399 u8 reserved_at_10
[0x10];
3401 u8 reserved_at_20
[0x10];
3404 u8 reserved_at_40
[0x8];
3407 u8 reserved_at_60
[0x20];
3410 struct mlx5_ifc_query_tir_out_bits
{
3412 u8 reserved_at_8
[0x18];
3416 u8 reserved_at_40
[0xc0];
3418 struct mlx5_ifc_tirc_bits tir_context
;
3421 struct mlx5_ifc_query_tir_in_bits
{
3423 u8 reserved_at_10
[0x10];
3425 u8 reserved_at_20
[0x10];
3428 u8 reserved_at_40
[0x8];
3431 u8 reserved_at_60
[0x20];
3434 struct mlx5_ifc_query_srq_out_bits
{
3436 u8 reserved_at_8
[0x18];
3440 u8 reserved_at_40
[0x40];
3442 struct mlx5_ifc_srqc_bits srq_context_entry
;
3444 u8 reserved_at_280
[0x600];
3449 struct mlx5_ifc_query_srq_in_bits
{
3451 u8 reserved_at_10
[0x10];
3453 u8 reserved_at_20
[0x10];
3456 u8 reserved_at_40
[0x8];
3459 u8 reserved_at_60
[0x20];
3462 struct mlx5_ifc_query_sq_out_bits
{
3464 u8 reserved_at_8
[0x18];
3468 u8 reserved_at_40
[0xc0];
3470 struct mlx5_ifc_sqc_bits sq_context
;
3473 struct mlx5_ifc_query_sq_in_bits
{
3475 u8 reserved_at_10
[0x10];
3477 u8 reserved_at_20
[0x10];
3480 u8 reserved_at_40
[0x8];
3483 u8 reserved_at_60
[0x20];
3486 struct mlx5_ifc_query_special_contexts_out_bits
{
3488 u8 reserved_at_8
[0x18];
3492 u8 reserved_at_40
[0x20];
3497 struct mlx5_ifc_query_special_contexts_in_bits
{
3499 u8 reserved_at_10
[0x10];
3501 u8 reserved_at_20
[0x10];
3504 u8 reserved_at_40
[0x40];
3507 struct mlx5_ifc_query_rqt_out_bits
{
3509 u8 reserved_at_8
[0x18];
3513 u8 reserved_at_40
[0xc0];
3515 struct mlx5_ifc_rqtc_bits rqt_context
;
3518 struct mlx5_ifc_query_rqt_in_bits
{
3520 u8 reserved_at_10
[0x10];
3522 u8 reserved_at_20
[0x10];
3525 u8 reserved_at_40
[0x8];
3528 u8 reserved_at_60
[0x20];
3531 struct mlx5_ifc_query_rq_out_bits
{
3533 u8 reserved_at_8
[0x18];
3537 u8 reserved_at_40
[0xc0];
3539 struct mlx5_ifc_rqc_bits rq_context
;
3542 struct mlx5_ifc_query_rq_in_bits
{
3544 u8 reserved_at_10
[0x10];
3546 u8 reserved_at_20
[0x10];
3549 u8 reserved_at_40
[0x8];
3552 u8 reserved_at_60
[0x20];
3555 struct mlx5_ifc_query_roce_address_out_bits
{
3557 u8 reserved_at_8
[0x18];
3561 u8 reserved_at_40
[0x40];
3563 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3566 struct mlx5_ifc_query_roce_address_in_bits
{
3568 u8 reserved_at_10
[0x10];
3570 u8 reserved_at_20
[0x10];
3573 u8 roce_address_index
[0x10];
3574 u8 reserved_at_50
[0x10];
3576 u8 reserved_at_60
[0x20];
3579 struct mlx5_ifc_query_rmp_out_bits
{
3581 u8 reserved_at_8
[0x18];
3585 u8 reserved_at_40
[0xc0];
3587 struct mlx5_ifc_rmpc_bits rmp_context
;
3590 struct mlx5_ifc_query_rmp_in_bits
{
3592 u8 reserved_at_10
[0x10];
3594 u8 reserved_at_20
[0x10];
3597 u8 reserved_at_40
[0x8];
3600 u8 reserved_at_60
[0x20];
3603 struct mlx5_ifc_query_qp_out_bits
{
3605 u8 reserved_at_8
[0x18];
3609 u8 reserved_at_40
[0x40];
3611 u8 opt_param_mask
[0x20];
3613 u8 reserved_at_a0
[0x20];
3615 struct mlx5_ifc_qpc_bits qpc
;
3617 u8 reserved_at_800
[0x80];
3622 struct mlx5_ifc_query_qp_in_bits
{
3624 u8 reserved_at_10
[0x10];
3626 u8 reserved_at_20
[0x10];
3629 u8 reserved_at_40
[0x8];
3632 u8 reserved_at_60
[0x20];
3635 struct mlx5_ifc_query_q_counter_out_bits
{
3637 u8 reserved_at_8
[0x18];
3641 u8 reserved_at_40
[0x40];
3643 u8 rx_write_requests
[0x20];
3645 u8 reserved_at_a0
[0x20];
3647 u8 rx_read_requests
[0x20];
3649 u8 reserved_at_e0
[0x20];
3651 u8 rx_atomic_requests
[0x20];
3653 u8 reserved_at_120
[0x20];
3655 u8 rx_dct_connect
[0x20];
3657 u8 reserved_at_160
[0x20];
3659 u8 out_of_buffer
[0x20];
3661 u8 reserved_at_1a0
[0x20];
3663 u8 out_of_sequence
[0x20];
3665 u8 reserved_at_1e0
[0x20];
3667 u8 duplicate_request
[0x20];
3669 u8 reserved_at_220
[0x20];
3671 u8 rnr_nak_retry_err
[0x20];
3673 u8 reserved_at_260
[0x20];
3675 u8 packet_seq_err
[0x20];
3677 u8 reserved_at_2a0
[0x20];
3679 u8 implied_nak_seq_err
[0x20];
3681 u8 reserved_at_2e0
[0x20];
3683 u8 local_ack_timeout_err
[0x20];
3685 u8 reserved_at_320
[0x4e0];
3688 struct mlx5_ifc_query_q_counter_in_bits
{
3690 u8 reserved_at_10
[0x10];
3692 u8 reserved_at_20
[0x10];
3695 u8 reserved_at_40
[0x80];
3698 u8 reserved_at_c1
[0x1f];
3700 u8 reserved_at_e0
[0x18];
3701 u8 counter_set_id
[0x8];
3704 struct mlx5_ifc_query_pages_out_bits
{
3706 u8 reserved_at_8
[0x18];
3710 u8 reserved_at_40
[0x10];
3711 u8 function_id
[0x10];
3717 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
3718 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
3719 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
3722 struct mlx5_ifc_query_pages_in_bits
{
3724 u8 reserved_at_10
[0x10];
3726 u8 reserved_at_20
[0x10];
3729 u8 reserved_at_40
[0x10];
3730 u8 function_id
[0x10];
3732 u8 reserved_at_60
[0x20];
3735 struct mlx5_ifc_query_nic_vport_context_out_bits
{
3737 u8 reserved_at_8
[0x18];
3741 u8 reserved_at_40
[0x40];
3743 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
3746 struct mlx5_ifc_query_nic_vport_context_in_bits
{
3748 u8 reserved_at_10
[0x10];
3750 u8 reserved_at_20
[0x10];
3753 u8 other_vport
[0x1];
3754 u8 reserved_at_41
[0xf];
3755 u8 vport_number
[0x10];
3757 u8 reserved_at_60
[0x5];
3758 u8 allowed_list_type
[0x3];
3759 u8 reserved_at_68
[0x18];
3762 struct mlx5_ifc_query_mkey_out_bits
{
3764 u8 reserved_at_8
[0x18];
3768 u8 reserved_at_40
[0x40];
3770 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
3772 u8 reserved_at_280
[0x600];
3774 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
3776 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
3779 struct mlx5_ifc_query_mkey_in_bits
{
3781 u8 reserved_at_10
[0x10];
3783 u8 reserved_at_20
[0x10];
3786 u8 reserved_at_40
[0x8];
3787 u8 mkey_index
[0x18];
3790 u8 reserved_at_61
[0x1f];
3793 struct mlx5_ifc_query_mad_demux_out_bits
{
3795 u8 reserved_at_8
[0x18];
3799 u8 reserved_at_40
[0x40];
3801 u8 mad_dumux_parameters_block
[0x20];
3804 struct mlx5_ifc_query_mad_demux_in_bits
{
3806 u8 reserved_at_10
[0x10];
3808 u8 reserved_at_20
[0x10];
3811 u8 reserved_at_40
[0x40];
3814 struct mlx5_ifc_query_l2_table_entry_out_bits
{
3816 u8 reserved_at_8
[0x18];
3820 u8 reserved_at_40
[0xa0];
3822 u8 reserved_at_e0
[0x13];
3826 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3828 u8 reserved_at_140
[0xc0];
3831 struct mlx5_ifc_query_l2_table_entry_in_bits
{
3833 u8 reserved_at_10
[0x10];
3835 u8 reserved_at_20
[0x10];
3838 u8 reserved_at_40
[0x60];
3840 u8 reserved_at_a0
[0x8];
3841 u8 table_index
[0x18];
3843 u8 reserved_at_c0
[0x140];
3846 struct mlx5_ifc_query_issi_out_bits
{
3848 u8 reserved_at_8
[0x18];
3852 u8 reserved_at_40
[0x10];
3853 u8 current_issi
[0x10];
3855 u8 reserved_at_60
[0xa0];
3857 u8 reserved_at_100
[76][0x8];
3858 u8 supported_issi_dw0
[0x20];
3861 struct mlx5_ifc_query_issi_in_bits
{
3863 u8 reserved_at_10
[0x10];
3865 u8 reserved_at_20
[0x10];
3868 u8 reserved_at_40
[0x40];
3871 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
3873 u8 reserved_at_8
[0x18];
3877 u8 reserved_at_40
[0x40];
3879 struct mlx5_ifc_pkey_bits pkey
[0];
3882 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
3884 u8 reserved_at_10
[0x10];
3886 u8 reserved_at_20
[0x10];
3889 u8 other_vport
[0x1];
3890 u8 reserved_at_41
[0xb];
3892 u8 vport_number
[0x10];
3894 u8 reserved_at_60
[0x10];
3895 u8 pkey_index
[0x10];
3899 MLX5_HCA_VPORT_SEL_PORT_GUID
= 1 << 0,
3900 MLX5_HCA_VPORT_SEL_NODE_GUID
= 1 << 1,
3901 MLX5_HCA_VPORT_SEL_STATE_POLICY
= 1 << 2,
3904 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
3906 u8 reserved_at_8
[0x18];
3910 u8 reserved_at_40
[0x20];
3913 u8 reserved_at_70
[0x10];
3915 struct mlx5_ifc_array128_auto_bits gid
[0];
3918 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
3920 u8 reserved_at_10
[0x10];
3922 u8 reserved_at_20
[0x10];
3925 u8 other_vport
[0x1];
3926 u8 reserved_at_41
[0xb];
3928 u8 vport_number
[0x10];
3930 u8 reserved_at_60
[0x10];
3934 struct mlx5_ifc_query_hca_vport_context_out_bits
{
3936 u8 reserved_at_8
[0x18];
3940 u8 reserved_at_40
[0x40];
3942 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
3945 struct mlx5_ifc_query_hca_vport_context_in_bits
{
3947 u8 reserved_at_10
[0x10];
3949 u8 reserved_at_20
[0x10];
3952 u8 other_vport
[0x1];
3953 u8 reserved_at_41
[0xb];
3955 u8 vport_number
[0x10];
3957 u8 reserved_at_60
[0x20];
3960 struct mlx5_ifc_query_hca_cap_out_bits
{
3962 u8 reserved_at_8
[0x18];
3966 u8 reserved_at_40
[0x40];
3968 union mlx5_ifc_hca_cap_union_bits capability
;
3971 struct mlx5_ifc_query_hca_cap_in_bits
{
3973 u8 reserved_at_10
[0x10];
3975 u8 reserved_at_20
[0x10];
3978 u8 reserved_at_40
[0x40];
3981 struct mlx5_ifc_query_flow_table_out_bits
{
3983 u8 reserved_at_8
[0x18];
3987 u8 reserved_at_40
[0x80];
3989 u8 reserved_at_c0
[0x8];
3991 u8 reserved_at_d0
[0x8];
3994 u8 reserved_at_e0
[0x120];
3997 struct mlx5_ifc_query_flow_table_in_bits
{
3999 u8 reserved_at_10
[0x10];
4001 u8 reserved_at_20
[0x10];
4004 u8 reserved_at_40
[0x40];
4007 u8 reserved_at_88
[0x18];
4009 u8 reserved_at_a0
[0x8];
4012 u8 reserved_at_c0
[0x140];
4015 struct mlx5_ifc_query_fte_out_bits
{
4017 u8 reserved_at_8
[0x18];
4021 u8 reserved_at_40
[0x1c0];
4023 struct mlx5_ifc_flow_context_bits flow_context
;
4026 struct mlx5_ifc_query_fte_in_bits
{
4028 u8 reserved_at_10
[0x10];
4030 u8 reserved_at_20
[0x10];
4033 u8 reserved_at_40
[0x40];
4036 u8 reserved_at_88
[0x18];
4038 u8 reserved_at_a0
[0x8];
4041 u8 reserved_at_c0
[0x40];
4043 u8 flow_index
[0x20];
4045 u8 reserved_at_120
[0xe0];
4049 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
4050 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
4051 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
4054 struct mlx5_ifc_query_flow_group_out_bits
{
4056 u8 reserved_at_8
[0x18];
4060 u8 reserved_at_40
[0xa0];
4062 u8 start_flow_index
[0x20];
4064 u8 reserved_at_100
[0x20];
4066 u8 end_flow_index
[0x20];
4068 u8 reserved_at_140
[0xa0];
4070 u8 reserved_at_1e0
[0x18];
4071 u8 match_criteria_enable
[0x8];
4073 struct mlx5_ifc_fte_match_param_bits match_criteria
;
4075 u8 reserved_at_1200
[0xe00];
4078 struct mlx5_ifc_query_flow_group_in_bits
{
4080 u8 reserved_at_10
[0x10];
4082 u8 reserved_at_20
[0x10];
4085 u8 reserved_at_40
[0x40];
4088 u8 reserved_at_88
[0x18];
4090 u8 reserved_at_a0
[0x8];
4095 u8 reserved_at_e0
[0x120];
4098 struct mlx5_ifc_query_flow_counter_out_bits
{
4100 u8 reserved_at_8
[0x18];
4104 u8 reserved_at_40
[0x40];
4106 struct mlx5_ifc_traffic_counter_bits flow_statistics
[0];
4109 struct mlx5_ifc_query_flow_counter_in_bits
{
4111 u8 reserved_at_10
[0x10];
4113 u8 reserved_at_20
[0x10];
4116 u8 reserved_at_40
[0x80];
4119 u8 reserved_at_c1
[0xf];
4120 u8 num_of_counters
[0x10];
4122 u8 reserved_at_e0
[0x10];
4123 u8 flow_counter_id
[0x10];
4126 struct mlx5_ifc_query_esw_vport_context_out_bits
{
4128 u8 reserved_at_8
[0x18];
4132 u8 reserved_at_40
[0x40];
4134 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4137 struct mlx5_ifc_query_esw_vport_context_in_bits
{
4139 u8 reserved_at_10
[0x10];
4141 u8 reserved_at_20
[0x10];
4144 u8 other_vport
[0x1];
4145 u8 reserved_at_41
[0xf];
4146 u8 vport_number
[0x10];
4148 u8 reserved_at_60
[0x20];
4151 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
4153 u8 reserved_at_8
[0x18];
4157 u8 reserved_at_40
[0x40];
4160 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
4161 u8 reserved_at_0
[0x1c];
4162 u8 vport_cvlan_insert
[0x1];
4163 u8 vport_svlan_insert
[0x1];
4164 u8 vport_cvlan_strip
[0x1];
4165 u8 vport_svlan_strip
[0x1];
4168 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
4170 u8 reserved_at_10
[0x10];
4172 u8 reserved_at_20
[0x10];
4175 u8 other_vport
[0x1];
4176 u8 reserved_at_41
[0xf];
4177 u8 vport_number
[0x10];
4179 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
4181 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4184 struct mlx5_ifc_query_eq_out_bits
{
4186 u8 reserved_at_8
[0x18];
4190 u8 reserved_at_40
[0x40];
4192 struct mlx5_ifc_eqc_bits eq_context_entry
;
4194 u8 reserved_at_280
[0x40];
4196 u8 event_bitmask
[0x40];
4198 u8 reserved_at_300
[0x580];
4203 struct mlx5_ifc_query_eq_in_bits
{
4205 u8 reserved_at_10
[0x10];
4207 u8 reserved_at_20
[0x10];
4210 u8 reserved_at_40
[0x18];
4213 u8 reserved_at_60
[0x20];
4216 struct mlx5_ifc_query_dct_out_bits
{
4218 u8 reserved_at_8
[0x18];
4222 u8 reserved_at_40
[0x40];
4224 struct mlx5_ifc_dctc_bits dct_context_entry
;
4226 u8 reserved_at_280
[0x180];
4229 struct mlx5_ifc_query_dct_in_bits
{
4231 u8 reserved_at_10
[0x10];
4233 u8 reserved_at_20
[0x10];
4236 u8 reserved_at_40
[0x8];
4239 u8 reserved_at_60
[0x20];
4242 struct mlx5_ifc_query_cq_out_bits
{
4244 u8 reserved_at_8
[0x18];
4248 u8 reserved_at_40
[0x40];
4250 struct mlx5_ifc_cqc_bits cq_context
;
4252 u8 reserved_at_280
[0x600];
4257 struct mlx5_ifc_query_cq_in_bits
{
4259 u8 reserved_at_10
[0x10];
4261 u8 reserved_at_20
[0x10];
4264 u8 reserved_at_40
[0x8];
4267 u8 reserved_at_60
[0x20];
4270 struct mlx5_ifc_query_cong_status_out_bits
{
4272 u8 reserved_at_8
[0x18];
4276 u8 reserved_at_40
[0x20];
4280 u8 reserved_at_62
[0x1e];
4283 struct mlx5_ifc_query_cong_status_in_bits
{
4285 u8 reserved_at_10
[0x10];
4287 u8 reserved_at_20
[0x10];
4290 u8 reserved_at_40
[0x18];
4292 u8 cong_protocol
[0x4];
4294 u8 reserved_at_60
[0x20];
4297 struct mlx5_ifc_query_cong_statistics_out_bits
{
4299 u8 reserved_at_8
[0x18];
4303 u8 reserved_at_40
[0x40];
4309 u8 cnp_ignored_high
[0x20];
4311 u8 cnp_ignored_low
[0x20];
4313 u8 cnp_handled_high
[0x20];
4315 u8 cnp_handled_low
[0x20];
4317 u8 reserved_at_140
[0x100];
4319 u8 time_stamp_high
[0x20];
4321 u8 time_stamp_low
[0x20];
4323 u8 accumulators_period
[0x20];
4325 u8 ecn_marked_roce_packets_high
[0x20];
4327 u8 ecn_marked_roce_packets_low
[0x20];
4329 u8 cnps_sent_high
[0x20];
4331 u8 cnps_sent_low
[0x20];
4333 u8 reserved_at_320
[0x560];
4336 struct mlx5_ifc_query_cong_statistics_in_bits
{
4338 u8 reserved_at_10
[0x10];
4340 u8 reserved_at_20
[0x10];
4344 u8 reserved_at_41
[0x1f];
4346 u8 reserved_at_60
[0x20];
4349 struct mlx5_ifc_query_cong_params_out_bits
{
4351 u8 reserved_at_8
[0x18];
4355 u8 reserved_at_40
[0x40];
4357 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4360 struct mlx5_ifc_query_cong_params_in_bits
{
4362 u8 reserved_at_10
[0x10];
4364 u8 reserved_at_20
[0x10];
4367 u8 reserved_at_40
[0x1c];
4368 u8 cong_protocol
[0x4];
4370 u8 reserved_at_60
[0x20];
4373 struct mlx5_ifc_query_adapter_out_bits
{
4375 u8 reserved_at_8
[0x18];
4379 u8 reserved_at_40
[0x40];
4381 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
4384 struct mlx5_ifc_query_adapter_in_bits
{
4386 u8 reserved_at_10
[0x10];
4388 u8 reserved_at_20
[0x10];
4391 u8 reserved_at_40
[0x40];
4394 struct mlx5_ifc_qp_2rst_out_bits
{
4396 u8 reserved_at_8
[0x18];
4400 u8 reserved_at_40
[0x40];
4403 struct mlx5_ifc_qp_2rst_in_bits
{
4405 u8 reserved_at_10
[0x10];
4407 u8 reserved_at_20
[0x10];
4410 u8 reserved_at_40
[0x8];
4413 u8 reserved_at_60
[0x20];
4416 struct mlx5_ifc_qp_2err_out_bits
{
4418 u8 reserved_at_8
[0x18];
4422 u8 reserved_at_40
[0x40];
4425 struct mlx5_ifc_qp_2err_in_bits
{
4427 u8 reserved_at_10
[0x10];
4429 u8 reserved_at_20
[0x10];
4432 u8 reserved_at_40
[0x8];
4435 u8 reserved_at_60
[0x20];
4438 struct mlx5_ifc_page_fault_resume_out_bits
{
4440 u8 reserved_at_8
[0x18];
4444 u8 reserved_at_40
[0x40];
4447 struct mlx5_ifc_page_fault_resume_in_bits
{
4449 u8 reserved_at_10
[0x10];
4451 u8 reserved_at_20
[0x10];
4455 u8 reserved_at_41
[0x4];
4461 u8 reserved_at_60
[0x20];
4464 struct mlx5_ifc_nop_out_bits
{
4466 u8 reserved_at_8
[0x18];
4470 u8 reserved_at_40
[0x40];
4473 struct mlx5_ifc_nop_in_bits
{
4475 u8 reserved_at_10
[0x10];
4477 u8 reserved_at_20
[0x10];
4480 u8 reserved_at_40
[0x40];
4483 struct mlx5_ifc_modify_vport_state_out_bits
{
4485 u8 reserved_at_8
[0x18];
4489 u8 reserved_at_40
[0x40];
4492 struct mlx5_ifc_modify_vport_state_in_bits
{
4494 u8 reserved_at_10
[0x10];
4496 u8 reserved_at_20
[0x10];
4499 u8 other_vport
[0x1];
4500 u8 reserved_at_41
[0xf];
4501 u8 vport_number
[0x10];
4503 u8 reserved_at_60
[0x18];
4504 u8 admin_state
[0x4];
4505 u8 reserved_at_7c
[0x4];
4508 struct mlx5_ifc_modify_tis_out_bits
{
4510 u8 reserved_at_8
[0x18];
4514 u8 reserved_at_40
[0x40];
4517 struct mlx5_ifc_modify_tis_bitmask_bits
{
4518 u8 reserved_at_0
[0x20];
4520 u8 reserved_at_20
[0x1f];
4524 struct mlx5_ifc_modify_tis_in_bits
{
4526 u8 reserved_at_10
[0x10];
4528 u8 reserved_at_20
[0x10];
4531 u8 reserved_at_40
[0x8];
4534 u8 reserved_at_60
[0x20];
4536 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
4538 u8 reserved_at_c0
[0x40];
4540 struct mlx5_ifc_tisc_bits ctx
;
4543 struct mlx5_ifc_modify_tir_bitmask_bits
{
4544 u8 reserved_at_0
[0x20];
4546 u8 reserved_at_20
[0x1b];
4548 u8 reserved_at_3c
[0x1];
4550 u8 reserved_at_3e
[0x1];
4554 struct mlx5_ifc_modify_tir_out_bits
{
4556 u8 reserved_at_8
[0x18];
4560 u8 reserved_at_40
[0x40];
4563 struct mlx5_ifc_modify_tir_in_bits
{
4565 u8 reserved_at_10
[0x10];
4567 u8 reserved_at_20
[0x10];
4570 u8 reserved_at_40
[0x8];
4573 u8 reserved_at_60
[0x20];
4575 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
4577 u8 reserved_at_c0
[0x40];
4579 struct mlx5_ifc_tirc_bits ctx
;
4582 struct mlx5_ifc_modify_sq_out_bits
{
4584 u8 reserved_at_8
[0x18];
4588 u8 reserved_at_40
[0x40];
4591 struct mlx5_ifc_modify_sq_in_bits
{
4593 u8 reserved_at_10
[0x10];
4595 u8 reserved_at_20
[0x10];
4599 u8 reserved_at_44
[0x4];
4602 u8 reserved_at_60
[0x20];
4604 u8 modify_bitmask
[0x40];
4606 u8 reserved_at_c0
[0x40];
4608 struct mlx5_ifc_sqc_bits ctx
;
4611 struct mlx5_ifc_modify_rqt_out_bits
{
4613 u8 reserved_at_8
[0x18];
4617 u8 reserved_at_40
[0x40];
4620 struct mlx5_ifc_rqt_bitmask_bits
{
4621 u8 reserved_at_0
[0x20];
4623 u8 reserved_at_20
[0x1f];
4627 struct mlx5_ifc_modify_rqt_in_bits
{
4629 u8 reserved_at_10
[0x10];
4631 u8 reserved_at_20
[0x10];
4634 u8 reserved_at_40
[0x8];
4637 u8 reserved_at_60
[0x20];
4639 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
4641 u8 reserved_at_c0
[0x40];
4643 struct mlx5_ifc_rqtc_bits ctx
;
4646 struct mlx5_ifc_modify_rq_out_bits
{
4648 u8 reserved_at_8
[0x18];
4652 u8 reserved_at_40
[0x40];
4655 struct mlx5_ifc_modify_rq_in_bits
{
4657 u8 reserved_at_10
[0x10];
4659 u8 reserved_at_20
[0x10];
4663 u8 reserved_at_44
[0x4];
4666 u8 reserved_at_60
[0x20];
4668 u8 modify_bitmask
[0x40];
4670 u8 reserved_at_c0
[0x40];
4672 struct mlx5_ifc_rqc_bits ctx
;
4675 struct mlx5_ifc_modify_rmp_out_bits
{
4677 u8 reserved_at_8
[0x18];
4681 u8 reserved_at_40
[0x40];
4684 struct mlx5_ifc_rmp_bitmask_bits
{
4685 u8 reserved_at_0
[0x20];
4687 u8 reserved_at_20
[0x1f];
4691 struct mlx5_ifc_modify_rmp_in_bits
{
4693 u8 reserved_at_10
[0x10];
4695 u8 reserved_at_20
[0x10];
4699 u8 reserved_at_44
[0x4];
4702 u8 reserved_at_60
[0x20];
4704 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
4706 u8 reserved_at_c0
[0x40];
4708 struct mlx5_ifc_rmpc_bits ctx
;
4711 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
4713 u8 reserved_at_8
[0x18];
4717 u8 reserved_at_40
[0x40];
4720 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
4721 u8 reserved_at_0
[0x16];
4724 u8 reserved_at_18
[0x1];
4726 u8 change_event
[0x1];
4728 u8 permanent_address
[0x1];
4729 u8 addresses_list
[0x1];
4731 u8 reserved_at_1f
[0x1];
4734 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
4736 u8 reserved_at_10
[0x10];
4738 u8 reserved_at_20
[0x10];
4741 u8 other_vport
[0x1];
4742 u8 reserved_at_41
[0xf];
4743 u8 vport_number
[0x10];
4745 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
4747 u8 reserved_at_80
[0x780];
4749 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4752 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
4754 u8 reserved_at_8
[0x18];
4758 u8 reserved_at_40
[0x40];
4761 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
4763 u8 reserved_at_10
[0x10];
4765 u8 reserved_at_20
[0x10];
4768 u8 other_vport
[0x1];
4769 u8 reserved_at_41
[0xb];
4771 u8 vport_number
[0x10];
4773 u8 reserved_at_60
[0x20];
4775 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
4778 struct mlx5_ifc_modify_cq_out_bits
{
4780 u8 reserved_at_8
[0x18];
4784 u8 reserved_at_40
[0x40];
4788 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
4789 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
4792 struct mlx5_ifc_modify_cq_in_bits
{
4794 u8 reserved_at_10
[0x10];
4796 u8 reserved_at_20
[0x10];
4799 u8 reserved_at_40
[0x8];
4802 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
4804 struct mlx5_ifc_cqc_bits cq_context
;
4806 u8 reserved_at_280
[0x600];
4811 struct mlx5_ifc_modify_cong_status_out_bits
{
4813 u8 reserved_at_8
[0x18];
4817 u8 reserved_at_40
[0x40];
4820 struct mlx5_ifc_modify_cong_status_in_bits
{
4822 u8 reserved_at_10
[0x10];
4824 u8 reserved_at_20
[0x10];
4827 u8 reserved_at_40
[0x18];
4829 u8 cong_protocol
[0x4];
4833 u8 reserved_at_62
[0x1e];
4836 struct mlx5_ifc_modify_cong_params_out_bits
{
4838 u8 reserved_at_8
[0x18];
4842 u8 reserved_at_40
[0x40];
4845 struct mlx5_ifc_modify_cong_params_in_bits
{
4847 u8 reserved_at_10
[0x10];
4849 u8 reserved_at_20
[0x10];
4852 u8 reserved_at_40
[0x1c];
4853 u8 cong_protocol
[0x4];
4855 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
4857 u8 reserved_at_80
[0x80];
4859 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4862 struct mlx5_ifc_manage_pages_out_bits
{
4864 u8 reserved_at_8
[0x18];
4868 u8 output_num_entries
[0x20];
4870 u8 reserved_at_60
[0x20];
4876 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
4877 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
4878 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
4881 struct mlx5_ifc_manage_pages_in_bits
{
4883 u8 reserved_at_10
[0x10];
4885 u8 reserved_at_20
[0x10];
4888 u8 reserved_at_40
[0x10];
4889 u8 function_id
[0x10];
4891 u8 input_num_entries
[0x20];
4896 struct mlx5_ifc_mad_ifc_out_bits
{
4898 u8 reserved_at_8
[0x18];
4902 u8 reserved_at_40
[0x40];
4904 u8 response_mad_packet
[256][0x8];
4907 struct mlx5_ifc_mad_ifc_in_bits
{
4909 u8 reserved_at_10
[0x10];
4911 u8 reserved_at_20
[0x10];
4914 u8 remote_lid
[0x10];
4915 u8 reserved_at_50
[0x8];
4918 u8 reserved_at_60
[0x20];
4923 struct mlx5_ifc_init_hca_out_bits
{
4925 u8 reserved_at_8
[0x18];
4929 u8 reserved_at_40
[0x40];
4932 struct mlx5_ifc_init_hca_in_bits
{
4934 u8 reserved_at_10
[0x10];
4936 u8 reserved_at_20
[0x10];
4939 u8 reserved_at_40
[0x40];
4942 struct mlx5_ifc_init2rtr_qp_out_bits
{
4944 u8 reserved_at_8
[0x18];
4948 u8 reserved_at_40
[0x40];
4951 struct mlx5_ifc_init2rtr_qp_in_bits
{
4953 u8 reserved_at_10
[0x10];
4955 u8 reserved_at_20
[0x10];
4958 u8 reserved_at_40
[0x8];
4961 u8 reserved_at_60
[0x20];
4963 u8 opt_param_mask
[0x20];
4965 u8 reserved_at_a0
[0x20];
4967 struct mlx5_ifc_qpc_bits qpc
;
4969 u8 reserved_at_800
[0x80];
4972 struct mlx5_ifc_init2init_qp_out_bits
{
4974 u8 reserved_at_8
[0x18];
4978 u8 reserved_at_40
[0x40];
4981 struct mlx5_ifc_init2init_qp_in_bits
{
4983 u8 reserved_at_10
[0x10];
4985 u8 reserved_at_20
[0x10];
4988 u8 reserved_at_40
[0x8];
4991 u8 reserved_at_60
[0x20];
4993 u8 opt_param_mask
[0x20];
4995 u8 reserved_at_a0
[0x20];
4997 struct mlx5_ifc_qpc_bits qpc
;
4999 u8 reserved_at_800
[0x80];
5002 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
5004 u8 reserved_at_8
[0x18];
5008 u8 reserved_at_40
[0x40];
5010 u8 packet_headers_log
[128][0x8];
5012 u8 packet_syndrome
[64][0x8];
5015 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
5017 u8 reserved_at_10
[0x10];
5019 u8 reserved_at_20
[0x10];
5022 u8 reserved_at_40
[0x40];
5025 struct mlx5_ifc_gen_eqe_in_bits
{
5027 u8 reserved_at_10
[0x10];
5029 u8 reserved_at_20
[0x10];
5032 u8 reserved_at_40
[0x18];
5035 u8 reserved_at_60
[0x20];
5040 struct mlx5_ifc_gen_eq_out_bits
{
5042 u8 reserved_at_8
[0x18];
5046 u8 reserved_at_40
[0x40];
5049 struct mlx5_ifc_enable_hca_out_bits
{
5051 u8 reserved_at_8
[0x18];
5055 u8 reserved_at_40
[0x20];
5058 struct mlx5_ifc_enable_hca_in_bits
{
5060 u8 reserved_at_10
[0x10];
5062 u8 reserved_at_20
[0x10];
5065 u8 reserved_at_40
[0x10];
5066 u8 function_id
[0x10];
5068 u8 reserved_at_60
[0x20];
5071 struct mlx5_ifc_drain_dct_out_bits
{
5073 u8 reserved_at_8
[0x18];
5077 u8 reserved_at_40
[0x40];
5080 struct mlx5_ifc_drain_dct_in_bits
{
5082 u8 reserved_at_10
[0x10];
5084 u8 reserved_at_20
[0x10];
5087 u8 reserved_at_40
[0x8];
5090 u8 reserved_at_60
[0x20];
5093 struct mlx5_ifc_disable_hca_out_bits
{
5095 u8 reserved_at_8
[0x18];
5099 u8 reserved_at_40
[0x20];
5102 struct mlx5_ifc_disable_hca_in_bits
{
5104 u8 reserved_at_10
[0x10];
5106 u8 reserved_at_20
[0x10];
5109 u8 reserved_at_40
[0x10];
5110 u8 function_id
[0x10];
5112 u8 reserved_at_60
[0x20];
5115 struct mlx5_ifc_detach_from_mcg_out_bits
{
5117 u8 reserved_at_8
[0x18];
5121 u8 reserved_at_40
[0x40];
5124 struct mlx5_ifc_detach_from_mcg_in_bits
{
5126 u8 reserved_at_10
[0x10];
5128 u8 reserved_at_20
[0x10];
5131 u8 reserved_at_40
[0x8];
5134 u8 reserved_at_60
[0x20];
5136 u8 multicast_gid
[16][0x8];
5139 struct mlx5_ifc_destroy_xrq_out_bits
{
5141 u8 reserved_at_8
[0x18];
5145 u8 reserved_at_40
[0x40];
5148 struct mlx5_ifc_destroy_xrq_in_bits
{
5150 u8 reserved_at_10
[0x10];
5152 u8 reserved_at_20
[0x10];
5155 u8 reserved_at_40
[0x8];
5158 u8 reserved_at_60
[0x20];
5161 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
5163 u8 reserved_at_8
[0x18];
5167 u8 reserved_at_40
[0x40];
5170 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
5172 u8 reserved_at_10
[0x10];
5174 u8 reserved_at_20
[0x10];
5177 u8 reserved_at_40
[0x8];
5180 u8 reserved_at_60
[0x20];
5183 struct mlx5_ifc_destroy_tis_out_bits
{
5185 u8 reserved_at_8
[0x18];
5189 u8 reserved_at_40
[0x40];
5192 struct mlx5_ifc_destroy_tis_in_bits
{
5194 u8 reserved_at_10
[0x10];
5196 u8 reserved_at_20
[0x10];
5199 u8 reserved_at_40
[0x8];
5202 u8 reserved_at_60
[0x20];
5205 struct mlx5_ifc_destroy_tir_out_bits
{
5207 u8 reserved_at_8
[0x18];
5211 u8 reserved_at_40
[0x40];
5214 struct mlx5_ifc_destroy_tir_in_bits
{
5216 u8 reserved_at_10
[0x10];
5218 u8 reserved_at_20
[0x10];
5221 u8 reserved_at_40
[0x8];
5224 u8 reserved_at_60
[0x20];
5227 struct mlx5_ifc_destroy_srq_out_bits
{
5229 u8 reserved_at_8
[0x18];
5233 u8 reserved_at_40
[0x40];
5236 struct mlx5_ifc_destroy_srq_in_bits
{
5238 u8 reserved_at_10
[0x10];
5240 u8 reserved_at_20
[0x10];
5243 u8 reserved_at_40
[0x8];
5246 u8 reserved_at_60
[0x20];
5249 struct mlx5_ifc_destroy_sq_out_bits
{
5251 u8 reserved_at_8
[0x18];
5255 u8 reserved_at_40
[0x40];
5258 struct mlx5_ifc_destroy_sq_in_bits
{
5260 u8 reserved_at_10
[0x10];
5262 u8 reserved_at_20
[0x10];
5265 u8 reserved_at_40
[0x8];
5268 u8 reserved_at_60
[0x20];
5271 struct mlx5_ifc_destroy_rqt_out_bits
{
5273 u8 reserved_at_8
[0x18];
5277 u8 reserved_at_40
[0x40];
5280 struct mlx5_ifc_destroy_rqt_in_bits
{
5282 u8 reserved_at_10
[0x10];
5284 u8 reserved_at_20
[0x10];
5287 u8 reserved_at_40
[0x8];
5290 u8 reserved_at_60
[0x20];
5293 struct mlx5_ifc_destroy_rq_out_bits
{
5295 u8 reserved_at_8
[0x18];
5299 u8 reserved_at_40
[0x40];
5302 struct mlx5_ifc_destroy_rq_in_bits
{
5304 u8 reserved_at_10
[0x10];
5306 u8 reserved_at_20
[0x10];
5309 u8 reserved_at_40
[0x8];
5312 u8 reserved_at_60
[0x20];
5315 struct mlx5_ifc_destroy_rmp_out_bits
{
5317 u8 reserved_at_8
[0x18];
5321 u8 reserved_at_40
[0x40];
5324 struct mlx5_ifc_destroy_rmp_in_bits
{
5326 u8 reserved_at_10
[0x10];
5328 u8 reserved_at_20
[0x10];
5331 u8 reserved_at_40
[0x8];
5334 u8 reserved_at_60
[0x20];
5337 struct mlx5_ifc_destroy_qp_out_bits
{
5339 u8 reserved_at_8
[0x18];
5343 u8 reserved_at_40
[0x40];
5346 struct mlx5_ifc_destroy_qp_in_bits
{
5348 u8 reserved_at_10
[0x10];
5350 u8 reserved_at_20
[0x10];
5353 u8 reserved_at_40
[0x8];
5356 u8 reserved_at_60
[0x20];
5359 struct mlx5_ifc_destroy_psv_out_bits
{
5361 u8 reserved_at_8
[0x18];
5365 u8 reserved_at_40
[0x40];
5368 struct mlx5_ifc_destroy_psv_in_bits
{
5370 u8 reserved_at_10
[0x10];
5372 u8 reserved_at_20
[0x10];
5375 u8 reserved_at_40
[0x8];
5378 u8 reserved_at_60
[0x20];
5381 struct mlx5_ifc_destroy_mkey_out_bits
{
5383 u8 reserved_at_8
[0x18];
5387 u8 reserved_at_40
[0x40];
5390 struct mlx5_ifc_destroy_mkey_in_bits
{
5392 u8 reserved_at_10
[0x10];
5394 u8 reserved_at_20
[0x10];
5397 u8 reserved_at_40
[0x8];
5398 u8 mkey_index
[0x18];
5400 u8 reserved_at_60
[0x20];
5403 struct mlx5_ifc_destroy_flow_table_out_bits
{
5405 u8 reserved_at_8
[0x18];
5409 u8 reserved_at_40
[0x40];
5412 struct mlx5_ifc_destroy_flow_table_in_bits
{
5414 u8 reserved_at_10
[0x10];
5416 u8 reserved_at_20
[0x10];
5419 u8 other_vport
[0x1];
5420 u8 reserved_at_41
[0xf];
5421 u8 vport_number
[0x10];
5423 u8 reserved_at_60
[0x20];
5426 u8 reserved_at_88
[0x18];
5428 u8 reserved_at_a0
[0x8];
5431 u8 reserved_at_c0
[0x140];
5434 struct mlx5_ifc_destroy_flow_group_out_bits
{
5436 u8 reserved_at_8
[0x18];
5440 u8 reserved_at_40
[0x40];
5443 struct mlx5_ifc_destroy_flow_group_in_bits
{
5445 u8 reserved_at_10
[0x10];
5447 u8 reserved_at_20
[0x10];
5450 u8 other_vport
[0x1];
5451 u8 reserved_at_41
[0xf];
5452 u8 vport_number
[0x10];
5454 u8 reserved_at_60
[0x20];
5457 u8 reserved_at_88
[0x18];
5459 u8 reserved_at_a0
[0x8];
5464 u8 reserved_at_e0
[0x120];
5467 struct mlx5_ifc_destroy_eq_out_bits
{
5469 u8 reserved_at_8
[0x18];
5473 u8 reserved_at_40
[0x40];
5476 struct mlx5_ifc_destroy_eq_in_bits
{
5478 u8 reserved_at_10
[0x10];
5480 u8 reserved_at_20
[0x10];
5483 u8 reserved_at_40
[0x18];
5486 u8 reserved_at_60
[0x20];
5489 struct mlx5_ifc_destroy_dct_out_bits
{
5491 u8 reserved_at_8
[0x18];
5495 u8 reserved_at_40
[0x40];
5498 struct mlx5_ifc_destroy_dct_in_bits
{
5500 u8 reserved_at_10
[0x10];
5502 u8 reserved_at_20
[0x10];
5505 u8 reserved_at_40
[0x8];
5508 u8 reserved_at_60
[0x20];
5511 struct mlx5_ifc_destroy_cq_out_bits
{
5513 u8 reserved_at_8
[0x18];
5517 u8 reserved_at_40
[0x40];
5520 struct mlx5_ifc_destroy_cq_in_bits
{
5522 u8 reserved_at_10
[0x10];
5524 u8 reserved_at_20
[0x10];
5527 u8 reserved_at_40
[0x8];
5530 u8 reserved_at_60
[0x20];
5533 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
5535 u8 reserved_at_8
[0x18];
5539 u8 reserved_at_40
[0x40];
5542 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
5544 u8 reserved_at_10
[0x10];
5546 u8 reserved_at_20
[0x10];
5549 u8 reserved_at_40
[0x20];
5551 u8 reserved_at_60
[0x10];
5552 u8 vxlan_udp_port
[0x10];
5555 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
5557 u8 reserved_at_8
[0x18];
5561 u8 reserved_at_40
[0x40];
5564 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
5566 u8 reserved_at_10
[0x10];
5568 u8 reserved_at_20
[0x10];
5571 u8 reserved_at_40
[0x60];
5573 u8 reserved_at_a0
[0x8];
5574 u8 table_index
[0x18];
5576 u8 reserved_at_c0
[0x140];
5579 struct mlx5_ifc_delete_fte_out_bits
{
5581 u8 reserved_at_8
[0x18];
5585 u8 reserved_at_40
[0x40];
5588 struct mlx5_ifc_delete_fte_in_bits
{
5590 u8 reserved_at_10
[0x10];
5592 u8 reserved_at_20
[0x10];
5595 u8 other_vport
[0x1];
5596 u8 reserved_at_41
[0xf];
5597 u8 vport_number
[0x10];
5599 u8 reserved_at_60
[0x20];
5602 u8 reserved_at_88
[0x18];
5604 u8 reserved_at_a0
[0x8];
5607 u8 reserved_at_c0
[0x40];
5609 u8 flow_index
[0x20];
5611 u8 reserved_at_120
[0xe0];
5614 struct mlx5_ifc_dealloc_xrcd_out_bits
{
5616 u8 reserved_at_8
[0x18];
5620 u8 reserved_at_40
[0x40];
5623 struct mlx5_ifc_dealloc_xrcd_in_bits
{
5625 u8 reserved_at_10
[0x10];
5627 u8 reserved_at_20
[0x10];
5630 u8 reserved_at_40
[0x8];
5633 u8 reserved_at_60
[0x20];
5636 struct mlx5_ifc_dealloc_uar_out_bits
{
5638 u8 reserved_at_8
[0x18];
5642 u8 reserved_at_40
[0x40];
5645 struct mlx5_ifc_dealloc_uar_in_bits
{
5647 u8 reserved_at_10
[0x10];
5649 u8 reserved_at_20
[0x10];
5652 u8 reserved_at_40
[0x8];
5655 u8 reserved_at_60
[0x20];
5658 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
5660 u8 reserved_at_8
[0x18];
5664 u8 reserved_at_40
[0x40];
5667 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
5669 u8 reserved_at_10
[0x10];
5671 u8 reserved_at_20
[0x10];
5674 u8 reserved_at_40
[0x8];
5675 u8 transport_domain
[0x18];
5677 u8 reserved_at_60
[0x20];
5680 struct mlx5_ifc_dealloc_q_counter_out_bits
{
5682 u8 reserved_at_8
[0x18];
5686 u8 reserved_at_40
[0x40];
5689 struct mlx5_ifc_dealloc_q_counter_in_bits
{
5691 u8 reserved_at_10
[0x10];
5693 u8 reserved_at_20
[0x10];
5696 u8 reserved_at_40
[0x18];
5697 u8 counter_set_id
[0x8];
5699 u8 reserved_at_60
[0x20];
5702 struct mlx5_ifc_dealloc_pd_out_bits
{
5704 u8 reserved_at_8
[0x18];
5708 u8 reserved_at_40
[0x40];
5711 struct mlx5_ifc_dealloc_pd_in_bits
{
5713 u8 reserved_at_10
[0x10];
5715 u8 reserved_at_20
[0x10];
5718 u8 reserved_at_40
[0x8];
5721 u8 reserved_at_60
[0x20];
5724 struct mlx5_ifc_dealloc_flow_counter_out_bits
{
5726 u8 reserved_at_8
[0x18];
5730 u8 reserved_at_40
[0x40];
5733 struct mlx5_ifc_dealloc_flow_counter_in_bits
{
5735 u8 reserved_at_10
[0x10];
5737 u8 reserved_at_20
[0x10];
5740 u8 reserved_at_40
[0x10];
5741 u8 flow_counter_id
[0x10];
5743 u8 reserved_at_60
[0x20];
5746 struct mlx5_ifc_create_xrq_out_bits
{
5748 u8 reserved_at_8
[0x18];
5752 u8 reserved_at_40
[0x8];
5755 u8 reserved_at_60
[0x20];
5758 struct mlx5_ifc_create_xrq_in_bits
{
5760 u8 reserved_at_10
[0x10];
5762 u8 reserved_at_20
[0x10];
5765 u8 reserved_at_40
[0x40];
5767 struct mlx5_ifc_xrqc_bits xrq_context
;
5770 struct mlx5_ifc_create_xrc_srq_out_bits
{
5772 u8 reserved_at_8
[0x18];
5776 u8 reserved_at_40
[0x8];
5779 u8 reserved_at_60
[0x20];
5782 struct mlx5_ifc_create_xrc_srq_in_bits
{
5784 u8 reserved_at_10
[0x10];
5786 u8 reserved_at_20
[0x10];
5789 u8 reserved_at_40
[0x40];
5791 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
5793 u8 reserved_at_280
[0x600];
5798 struct mlx5_ifc_create_tis_out_bits
{
5800 u8 reserved_at_8
[0x18];
5804 u8 reserved_at_40
[0x8];
5807 u8 reserved_at_60
[0x20];
5810 struct mlx5_ifc_create_tis_in_bits
{
5812 u8 reserved_at_10
[0x10];
5814 u8 reserved_at_20
[0x10];
5817 u8 reserved_at_40
[0xc0];
5819 struct mlx5_ifc_tisc_bits ctx
;
5822 struct mlx5_ifc_create_tir_out_bits
{
5824 u8 reserved_at_8
[0x18];
5828 u8 reserved_at_40
[0x8];
5831 u8 reserved_at_60
[0x20];
5834 struct mlx5_ifc_create_tir_in_bits
{
5836 u8 reserved_at_10
[0x10];
5838 u8 reserved_at_20
[0x10];
5841 u8 reserved_at_40
[0xc0];
5843 struct mlx5_ifc_tirc_bits ctx
;
5846 struct mlx5_ifc_create_srq_out_bits
{
5848 u8 reserved_at_8
[0x18];
5852 u8 reserved_at_40
[0x8];
5855 u8 reserved_at_60
[0x20];
5858 struct mlx5_ifc_create_srq_in_bits
{
5860 u8 reserved_at_10
[0x10];
5862 u8 reserved_at_20
[0x10];
5865 u8 reserved_at_40
[0x40];
5867 struct mlx5_ifc_srqc_bits srq_context_entry
;
5869 u8 reserved_at_280
[0x600];
5874 struct mlx5_ifc_create_sq_out_bits
{
5876 u8 reserved_at_8
[0x18];
5880 u8 reserved_at_40
[0x8];
5883 u8 reserved_at_60
[0x20];
5886 struct mlx5_ifc_create_sq_in_bits
{
5888 u8 reserved_at_10
[0x10];
5890 u8 reserved_at_20
[0x10];
5893 u8 reserved_at_40
[0xc0];
5895 struct mlx5_ifc_sqc_bits ctx
;
5898 struct mlx5_ifc_create_rqt_out_bits
{
5900 u8 reserved_at_8
[0x18];
5904 u8 reserved_at_40
[0x8];
5907 u8 reserved_at_60
[0x20];
5910 struct mlx5_ifc_create_rqt_in_bits
{
5912 u8 reserved_at_10
[0x10];
5914 u8 reserved_at_20
[0x10];
5917 u8 reserved_at_40
[0xc0];
5919 struct mlx5_ifc_rqtc_bits rqt_context
;
5922 struct mlx5_ifc_create_rq_out_bits
{
5924 u8 reserved_at_8
[0x18];
5928 u8 reserved_at_40
[0x8];
5931 u8 reserved_at_60
[0x20];
5934 struct mlx5_ifc_create_rq_in_bits
{
5936 u8 reserved_at_10
[0x10];
5938 u8 reserved_at_20
[0x10];
5941 u8 reserved_at_40
[0xc0];
5943 struct mlx5_ifc_rqc_bits ctx
;
5946 struct mlx5_ifc_create_rmp_out_bits
{
5948 u8 reserved_at_8
[0x18];
5952 u8 reserved_at_40
[0x8];
5955 u8 reserved_at_60
[0x20];
5958 struct mlx5_ifc_create_rmp_in_bits
{
5960 u8 reserved_at_10
[0x10];
5962 u8 reserved_at_20
[0x10];
5965 u8 reserved_at_40
[0xc0];
5967 struct mlx5_ifc_rmpc_bits ctx
;
5970 struct mlx5_ifc_create_qp_out_bits
{
5972 u8 reserved_at_8
[0x18];
5976 u8 reserved_at_40
[0x8];
5979 u8 reserved_at_60
[0x20];
5982 struct mlx5_ifc_create_qp_in_bits
{
5984 u8 reserved_at_10
[0x10];
5986 u8 reserved_at_20
[0x10];
5989 u8 reserved_at_40
[0x40];
5991 u8 opt_param_mask
[0x20];
5993 u8 reserved_at_a0
[0x20];
5995 struct mlx5_ifc_qpc_bits qpc
;
5997 u8 reserved_at_800
[0x80];
6002 struct mlx5_ifc_create_psv_out_bits
{
6004 u8 reserved_at_8
[0x18];
6008 u8 reserved_at_40
[0x40];
6010 u8 reserved_at_80
[0x8];
6011 u8 psv0_index
[0x18];
6013 u8 reserved_at_a0
[0x8];
6014 u8 psv1_index
[0x18];
6016 u8 reserved_at_c0
[0x8];
6017 u8 psv2_index
[0x18];
6019 u8 reserved_at_e0
[0x8];
6020 u8 psv3_index
[0x18];
6023 struct mlx5_ifc_create_psv_in_bits
{
6025 u8 reserved_at_10
[0x10];
6027 u8 reserved_at_20
[0x10];
6031 u8 reserved_at_44
[0x4];
6034 u8 reserved_at_60
[0x20];
6037 struct mlx5_ifc_create_mkey_out_bits
{
6039 u8 reserved_at_8
[0x18];
6043 u8 reserved_at_40
[0x8];
6044 u8 mkey_index
[0x18];
6046 u8 reserved_at_60
[0x20];
6049 struct mlx5_ifc_create_mkey_in_bits
{
6051 u8 reserved_at_10
[0x10];
6053 u8 reserved_at_20
[0x10];
6056 u8 reserved_at_40
[0x20];
6059 u8 reserved_at_61
[0x1f];
6061 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
6063 u8 reserved_at_280
[0x80];
6065 u8 translations_octword_actual_size
[0x20];
6067 u8 reserved_at_320
[0x560];
6069 u8 klm_pas_mtt
[0][0x20];
6072 struct mlx5_ifc_create_flow_table_out_bits
{
6074 u8 reserved_at_8
[0x18];
6078 u8 reserved_at_40
[0x8];
6081 u8 reserved_at_60
[0x20];
6084 struct mlx5_ifc_create_flow_table_in_bits
{
6086 u8 reserved_at_10
[0x10];
6088 u8 reserved_at_20
[0x10];
6091 u8 other_vport
[0x1];
6092 u8 reserved_at_41
[0xf];
6093 u8 vport_number
[0x10];
6095 u8 reserved_at_60
[0x20];
6098 u8 reserved_at_88
[0x18];
6100 u8 reserved_at_a0
[0x20];
6102 u8 reserved_at_c0
[0x4];
6103 u8 table_miss_mode
[0x4];
6105 u8 reserved_at_d0
[0x8];
6108 u8 reserved_at_e0
[0x8];
6109 u8 table_miss_id
[0x18];
6111 u8 reserved_at_100
[0x100];
6114 struct mlx5_ifc_create_flow_group_out_bits
{
6116 u8 reserved_at_8
[0x18];
6120 u8 reserved_at_40
[0x8];
6123 u8 reserved_at_60
[0x20];
6127 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
6128 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
6129 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
6132 struct mlx5_ifc_create_flow_group_in_bits
{
6134 u8 reserved_at_10
[0x10];
6136 u8 reserved_at_20
[0x10];
6139 u8 other_vport
[0x1];
6140 u8 reserved_at_41
[0xf];
6141 u8 vport_number
[0x10];
6143 u8 reserved_at_60
[0x20];
6146 u8 reserved_at_88
[0x18];
6148 u8 reserved_at_a0
[0x8];
6151 u8 reserved_at_c0
[0x20];
6153 u8 start_flow_index
[0x20];
6155 u8 reserved_at_100
[0x20];
6157 u8 end_flow_index
[0x20];
6159 u8 reserved_at_140
[0xa0];
6161 u8 reserved_at_1e0
[0x18];
6162 u8 match_criteria_enable
[0x8];
6164 struct mlx5_ifc_fte_match_param_bits match_criteria
;
6166 u8 reserved_at_1200
[0xe00];
6169 struct mlx5_ifc_create_eq_out_bits
{
6171 u8 reserved_at_8
[0x18];
6175 u8 reserved_at_40
[0x18];
6178 u8 reserved_at_60
[0x20];
6181 struct mlx5_ifc_create_eq_in_bits
{
6183 u8 reserved_at_10
[0x10];
6185 u8 reserved_at_20
[0x10];
6188 u8 reserved_at_40
[0x40];
6190 struct mlx5_ifc_eqc_bits eq_context_entry
;
6192 u8 reserved_at_280
[0x40];
6194 u8 event_bitmask
[0x40];
6196 u8 reserved_at_300
[0x580];
6201 struct mlx5_ifc_create_dct_out_bits
{
6203 u8 reserved_at_8
[0x18];
6207 u8 reserved_at_40
[0x8];
6210 u8 reserved_at_60
[0x20];
6213 struct mlx5_ifc_create_dct_in_bits
{
6215 u8 reserved_at_10
[0x10];
6217 u8 reserved_at_20
[0x10];
6220 u8 reserved_at_40
[0x40];
6222 struct mlx5_ifc_dctc_bits dct_context_entry
;
6224 u8 reserved_at_280
[0x180];
6227 struct mlx5_ifc_create_cq_out_bits
{
6229 u8 reserved_at_8
[0x18];
6233 u8 reserved_at_40
[0x8];
6236 u8 reserved_at_60
[0x20];
6239 struct mlx5_ifc_create_cq_in_bits
{
6241 u8 reserved_at_10
[0x10];
6243 u8 reserved_at_20
[0x10];
6246 u8 reserved_at_40
[0x40];
6248 struct mlx5_ifc_cqc_bits cq_context
;
6250 u8 reserved_at_280
[0x600];
6255 struct mlx5_ifc_config_int_moderation_out_bits
{
6257 u8 reserved_at_8
[0x18];
6261 u8 reserved_at_40
[0x4];
6263 u8 int_vector
[0x10];
6265 u8 reserved_at_60
[0x20];
6269 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
6270 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
6273 struct mlx5_ifc_config_int_moderation_in_bits
{
6275 u8 reserved_at_10
[0x10];
6277 u8 reserved_at_20
[0x10];
6280 u8 reserved_at_40
[0x4];
6282 u8 int_vector
[0x10];
6284 u8 reserved_at_60
[0x20];
6287 struct mlx5_ifc_attach_to_mcg_out_bits
{
6289 u8 reserved_at_8
[0x18];
6293 u8 reserved_at_40
[0x40];
6296 struct mlx5_ifc_attach_to_mcg_in_bits
{
6298 u8 reserved_at_10
[0x10];
6300 u8 reserved_at_20
[0x10];
6303 u8 reserved_at_40
[0x8];
6306 u8 reserved_at_60
[0x20];
6308 u8 multicast_gid
[16][0x8];
6311 struct mlx5_ifc_arm_xrq_out_bits
{
6313 u8 reserved_at_8
[0x18];
6317 u8 reserved_at_40
[0x40];
6320 struct mlx5_ifc_arm_xrq_in_bits
{
6322 u8 reserved_at_10
[0x10];
6324 u8 reserved_at_20
[0x10];
6327 u8 reserved_at_40
[0x8];
6330 u8 reserved_at_60
[0x10];
6334 struct mlx5_ifc_arm_xrc_srq_out_bits
{
6336 u8 reserved_at_8
[0x18];
6340 u8 reserved_at_40
[0x40];
6344 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
6347 struct mlx5_ifc_arm_xrc_srq_in_bits
{
6349 u8 reserved_at_10
[0x10];
6351 u8 reserved_at_20
[0x10];
6354 u8 reserved_at_40
[0x8];
6357 u8 reserved_at_60
[0x10];
6361 struct mlx5_ifc_arm_rq_out_bits
{
6363 u8 reserved_at_8
[0x18];
6367 u8 reserved_at_40
[0x40];
6371 MLX5_ARM_RQ_IN_OP_MOD_SRQ
= 0x1,
6372 MLX5_ARM_RQ_IN_OP_MOD_XRQ
= 0x2,
6375 struct mlx5_ifc_arm_rq_in_bits
{
6377 u8 reserved_at_10
[0x10];
6379 u8 reserved_at_20
[0x10];
6382 u8 reserved_at_40
[0x8];
6383 u8 srq_number
[0x18];
6385 u8 reserved_at_60
[0x10];
6389 struct mlx5_ifc_arm_dct_out_bits
{
6391 u8 reserved_at_8
[0x18];
6395 u8 reserved_at_40
[0x40];
6398 struct mlx5_ifc_arm_dct_in_bits
{
6400 u8 reserved_at_10
[0x10];
6402 u8 reserved_at_20
[0x10];
6405 u8 reserved_at_40
[0x8];
6406 u8 dct_number
[0x18];
6408 u8 reserved_at_60
[0x20];
6411 struct mlx5_ifc_alloc_xrcd_out_bits
{
6413 u8 reserved_at_8
[0x18];
6417 u8 reserved_at_40
[0x8];
6420 u8 reserved_at_60
[0x20];
6423 struct mlx5_ifc_alloc_xrcd_in_bits
{
6425 u8 reserved_at_10
[0x10];
6427 u8 reserved_at_20
[0x10];
6430 u8 reserved_at_40
[0x40];
6433 struct mlx5_ifc_alloc_uar_out_bits
{
6435 u8 reserved_at_8
[0x18];
6439 u8 reserved_at_40
[0x8];
6442 u8 reserved_at_60
[0x20];
6445 struct mlx5_ifc_alloc_uar_in_bits
{
6447 u8 reserved_at_10
[0x10];
6449 u8 reserved_at_20
[0x10];
6452 u8 reserved_at_40
[0x40];
6455 struct mlx5_ifc_alloc_transport_domain_out_bits
{
6457 u8 reserved_at_8
[0x18];
6461 u8 reserved_at_40
[0x8];
6462 u8 transport_domain
[0x18];
6464 u8 reserved_at_60
[0x20];
6467 struct mlx5_ifc_alloc_transport_domain_in_bits
{
6469 u8 reserved_at_10
[0x10];
6471 u8 reserved_at_20
[0x10];
6474 u8 reserved_at_40
[0x40];
6477 struct mlx5_ifc_alloc_q_counter_out_bits
{
6479 u8 reserved_at_8
[0x18];
6483 u8 reserved_at_40
[0x18];
6484 u8 counter_set_id
[0x8];
6486 u8 reserved_at_60
[0x20];
6489 struct mlx5_ifc_alloc_q_counter_in_bits
{
6491 u8 reserved_at_10
[0x10];
6493 u8 reserved_at_20
[0x10];
6496 u8 reserved_at_40
[0x40];
6499 struct mlx5_ifc_alloc_pd_out_bits
{
6501 u8 reserved_at_8
[0x18];
6505 u8 reserved_at_40
[0x8];
6508 u8 reserved_at_60
[0x20];
6511 struct mlx5_ifc_alloc_pd_in_bits
{
6513 u8 reserved_at_10
[0x10];
6515 u8 reserved_at_20
[0x10];
6518 u8 reserved_at_40
[0x40];
6521 struct mlx5_ifc_alloc_flow_counter_out_bits
{
6523 u8 reserved_at_8
[0x18];
6527 u8 reserved_at_40
[0x10];
6528 u8 flow_counter_id
[0x10];
6530 u8 reserved_at_60
[0x20];
6533 struct mlx5_ifc_alloc_flow_counter_in_bits
{
6535 u8 reserved_at_10
[0x10];
6537 u8 reserved_at_20
[0x10];
6540 u8 reserved_at_40
[0x40];
6543 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
6545 u8 reserved_at_8
[0x18];
6549 u8 reserved_at_40
[0x40];
6552 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
6554 u8 reserved_at_10
[0x10];
6556 u8 reserved_at_20
[0x10];
6559 u8 reserved_at_40
[0x20];
6561 u8 reserved_at_60
[0x10];
6562 u8 vxlan_udp_port
[0x10];
6565 struct mlx5_ifc_set_rate_limit_out_bits
{
6567 u8 reserved_at_8
[0x18];
6571 u8 reserved_at_40
[0x40];
6574 struct mlx5_ifc_set_rate_limit_in_bits
{
6576 u8 reserved_at_10
[0x10];
6578 u8 reserved_at_20
[0x10];
6581 u8 reserved_at_40
[0x10];
6582 u8 rate_limit_index
[0x10];
6584 u8 reserved_at_60
[0x20];
6586 u8 rate_limit
[0x20];
6589 struct mlx5_ifc_access_register_out_bits
{
6591 u8 reserved_at_8
[0x18];
6595 u8 reserved_at_40
[0x40];
6597 u8 register_data
[0][0x20];
6601 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
6602 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
6605 struct mlx5_ifc_access_register_in_bits
{
6607 u8 reserved_at_10
[0x10];
6609 u8 reserved_at_20
[0x10];
6612 u8 reserved_at_40
[0x10];
6613 u8 register_id
[0x10];
6617 u8 register_data
[0][0x20];
6620 struct mlx5_ifc_sltp_reg_bits
{
6625 u8 reserved_at_12
[0x2];
6627 u8 reserved_at_18
[0x8];
6629 u8 reserved_at_20
[0x20];
6631 u8 reserved_at_40
[0x7];
6637 u8 reserved_at_60
[0xc];
6638 u8 ob_preemp_mode
[0x4];
6642 u8 reserved_at_80
[0x20];
6645 struct mlx5_ifc_slrg_reg_bits
{
6650 u8 reserved_at_12
[0x2];
6652 u8 reserved_at_18
[0x8];
6654 u8 time_to_link_up
[0x10];
6655 u8 reserved_at_30
[0xc];
6656 u8 grade_lane_speed
[0x4];
6658 u8 grade_version
[0x8];
6661 u8 reserved_at_60
[0x4];
6662 u8 height_grade_type
[0x4];
6663 u8 height_grade
[0x18];
6668 u8 reserved_at_a0
[0x10];
6669 u8 height_sigma
[0x10];
6671 u8 reserved_at_c0
[0x20];
6673 u8 reserved_at_e0
[0x4];
6674 u8 phase_grade_type
[0x4];
6675 u8 phase_grade
[0x18];
6677 u8 reserved_at_100
[0x8];
6678 u8 phase_eo_pos
[0x8];
6679 u8 reserved_at_110
[0x8];
6680 u8 phase_eo_neg
[0x8];
6682 u8 ffe_set_tested
[0x10];
6683 u8 test_errors_per_lane
[0x10];
6686 struct mlx5_ifc_pvlc_reg_bits
{
6687 u8 reserved_at_0
[0x8];
6689 u8 reserved_at_10
[0x10];
6691 u8 reserved_at_20
[0x1c];
6694 u8 reserved_at_40
[0x1c];
6697 u8 reserved_at_60
[0x1c];
6698 u8 vl_operational
[0x4];
6701 struct mlx5_ifc_pude_reg_bits
{
6704 u8 reserved_at_10
[0x4];
6705 u8 admin_status
[0x4];
6706 u8 reserved_at_18
[0x4];
6707 u8 oper_status
[0x4];
6709 u8 reserved_at_20
[0x60];
6712 struct mlx5_ifc_ptys_reg_bits
{
6713 u8 an_disable_cap
[0x1];
6714 u8 an_disable_admin
[0x1];
6715 u8 reserved_at_2
[0x6];
6717 u8 reserved_at_10
[0xd];
6721 u8 reserved_at_24
[0x3c];
6723 u8 eth_proto_capability
[0x20];
6725 u8 ib_link_width_capability
[0x10];
6726 u8 ib_proto_capability
[0x10];
6728 u8 reserved_at_a0
[0x20];
6730 u8 eth_proto_admin
[0x20];
6732 u8 ib_link_width_admin
[0x10];
6733 u8 ib_proto_admin
[0x10];
6735 u8 reserved_at_100
[0x20];
6737 u8 eth_proto_oper
[0x20];
6739 u8 ib_link_width_oper
[0x10];
6740 u8 ib_proto_oper
[0x10];
6742 u8 reserved_at_160
[0x20];
6744 u8 eth_proto_lp_advertise
[0x20];
6746 u8 reserved_at_1a0
[0x60];
6749 struct mlx5_ifc_mlcr_reg_bits
{
6750 u8 reserved_at_0
[0x8];
6752 u8 reserved_at_10
[0x20];
6754 u8 beacon_duration
[0x10];
6755 u8 reserved_at_40
[0x10];
6757 u8 beacon_remain
[0x10];
6760 struct mlx5_ifc_ptas_reg_bits
{
6761 u8 reserved_at_0
[0x20];
6763 u8 algorithm_options
[0x10];
6764 u8 reserved_at_30
[0x4];
6765 u8 repetitions_mode
[0x4];
6766 u8 num_of_repetitions
[0x8];
6768 u8 grade_version
[0x8];
6769 u8 height_grade_type
[0x4];
6770 u8 phase_grade_type
[0x4];
6771 u8 height_grade_weight
[0x8];
6772 u8 phase_grade_weight
[0x8];
6774 u8 gisim_measure_bits
[0x10];
6775 u8 adaptive_tap_measure_bits
[0x10];
6777 u8 ber_bath_high_error_threshold
[0x10];
6778 u8 ber_bath_mid_error_threshold
[0x10];
6780 u8 ber_bath_low_error_threshold
[0x10];
6781 u8 one_ratio_high_threshold
[0x10];
6783 u8 one_ratio_high_mid_threshold
[0x10];
6784 u8 one_ratio_low_mid_threshold
[0x10];
6786 u8 one_ratio_low_threshold
[0x10];
6787 u8 ndeo_error_threshold
[0x10];
6789 u8 mixer_offset_step_size
[0x10];
6790 u8 reserved_at_110
[0x8];
6791 u8 mix90_phase_for_voltage_bath
[0x8];
6793 u8 mixer_offset_start
[0x10];
6794 u8 mixer_offset_end
[0x10];
6796 u8 reserved_at_140
[0x15];
6797 u8 ber_test_time
[0xb];
6800 struct mlx5_ifc_pspa_reg_bits
{
6804 u8 reserved_at_18
[0x8];
6806 u8 reserved_at_20
[0x20];
6809 struct mlx5_ifc_pqdr_reg_bits
{
6810 u8 reserved_at_0
[0x8];
6812 u8 reserved_at_10
[0x5];
6814 u8 reserved_at_18
[0x6];
6817 u8 reserved_at_20
[0x20];
6819 u8 reserved_at_40
[0x10];
6820 u8 min_threshold
[0x10];
6822 u8 reserved_at_60
[0x10];
6823 u8 max_threshold
[0x10];
6825 u8 reserved_at_80
[0x10];
6826 u8 mark_probability_denominator
[0x10];
6828 u8 reserved_at_a0
[0x60];
6831 struct mlx5_ifc_ppsc_reg_bits
{
6832 u8 reserved_at_0
[0x8];
6834 u8 reserved_at_10
[0x10];
6836 u8 reserved_at_20
[0x60];
6838 u8 reserved_at_80
[0x1c];
6841 u8 reserved_at_a0
[0x1c];
6842 u8 wrps_status
[0x4];
6844 u8 reserved_at_c0
[0x8];
6845 u8 up_threshold
[0x8];
6846 u8 reserved_at_d0
[0x8];
6847 u8 down_threshold
[0x8];
6849 u8 reserved_at_e0
[0x20];
6851 u8 reserved_at_100
[0x1c];
6854 u8 reserved_at_120
[0x1c];
6855 u8 srps_status
[0x4];
6857 u8 reserved_at_140
[0x40];
6860 struct mlx5_ifc_pplr_reg_bits
{
6861 u8 reserved_at_0
[0x8];
6863 u8 reserved_at_10
[0x10];
6865 u8 reserved_at_20
[0x8];
6867 u8 reserved_at_30
[0x8];
6871 struct mlx5_ifc_pplm_reg_bits
{
6872 u8 reserved_at_0
[0x8];
6874 u8 reserved_at_10
[0x10];
6876 u8 reserved_at_20
[0x20];
6878 u8 port_profile_mode
[0x8];
6879 u8 static_port_profile
[0x8];
6880 u8 active_port_profile
[0x8];
6881 u8 reserved_at_58
[0x8];
6883 u8 retransmission_active
[0x8];
6884 u8 fec_mode_active
[0x18];
6886 u8 reserved_at_80
[0x20];
6889 struct mlx5_ifc_ppcnt_reg_bits
{
6893 u8 reserved_at_12
[0x8];
6897 u8 reserved_at_21
[0x1c];
6900 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
6903 struct mlx5_ifc_ppad_reg_bits
{
6904 u8 reserved_at_0
[0x3];
6906 u8 reserved_at_4
[0x4];
6912 u8 reserved_at_40
[0x40];
6915 struct mlx5_ifc_pmtu_reg_bits
{
6916 u8 reserved_at_0
[0x8];
6918 u8 reserved_at_10
[0x10];
6921 u8 reserved_at_30
[0x10];
6924 u8 reserved_at_50
[0x10];
6927 u8 reserved_at_70
[0x10];
6930 struct mlx5_ifc_pmpr_reg_bits
{
6931 u8 reserved_at_0
[0x8];
6933 u8 reserved_at_10
[0x10];
6935 u8 reserved_at_20
[0x18];
6936 u8 attenuation_5g
[0x8];
6938 u8 reserved_at_40
[0x18];
6939 u8 attenuation_7g
[0x8];
6941 u8 reserved_at_60
[0x18];
6942 u8 attenuation_12g
[0x8];
6945 struct mlx5_ifc_pmpe_reg_bits
{
6946 u8 reserved_at_0
[0x8];
6948 u8 reserved_at_10
[0xc];
6949 u8 module_status
[0x4];
6951 u8 reserved_at_20
[0x60];
6954 struct mlx5_ifc_pmpc_reg_bits
{
6955 u8 module_state_updated
[32][0x8];
6958 struct mlx5_ifc_pmlpn_reg_bits
{
6959 u8 reserved_at_0
[0x4];
6960 u8 mlpn_status
[0x4];
6962 u8 reserved_at_10
[0x10];
6965 u8 reserved_at_21
[0x1f];
6968 struct mlx5_ifc_pmlp_reg_bits
{
6970 u8 reserved_at_1
[0x7];
6972 u8 reserved_at_10
[0x8];
6975 u8 lane0_module_mapping
[0x20];
6977 u8 lane1_module_mapping
[0x20];
6979 u8 lane2_module_mapping
[0x20];
6981 u8 lane3_module_mapping
[0x20];
6983 u8 reserved_at_a0
[0x160];
6986 struct mlx5_ifc_pmaos_reg_bits
{
6987 u8 reserved_at_0
[0x8];
6989 u8 reserved_at_10
[0x4];
6990 u8 admin_status
[0x4];
6991 u8 reserved_at_18
[0x4];
6992 u8 oper_status
[0x4];
6996 u8 reserved_at_22
[0x1c];
6999 u8 reserved_at_40
[0x40];
7002 struct mlx5_ifc_plpc_reg_bits
{
7003 u8 reserved_at_0
[0x4];
7005 u8 reserved_at_10
[0x4];
7007 u8 reserved_at_18
[0x8];
7009 u8 reserved_at_20
[0x10];
7010 u8 lane_speed
[0x10];
7012 u8 reserved_at_40
[0x17];
7014 u8 fec_mode_policy
[0x8];
7016 u8 retransmission_capability
[0x8];
7017 u8 fec_mode_capability
[0x18];
7019 u8 retransmission_support_admin
[0x8];
7020 u8 fec_mode_support_admin
[0x18];
7022 u8 retransmission_request_admin
[0x8];
7023 u8 fec_mode_request_admin
[0x18];
7025 u8 reserved_at_c0
[0x80];
7028 struct mlx5_ifc_plib_reg_bits
{
7029 u8 reserved_at_0
[0x8];
7031 u8 reserved_at_10
[0x8];
7034 u8 reserved_at_20
[0x60];
7037 struct mlx5_ifc_plbf_reg_bits
{
7038 u8 reserved_at_0
[0x8];
7040 u8 reserved_at_10
[0xd];
7043 u8 reserved_at_20
[0x20];
7046 struct mlx5_ifc_pipg_reg_bits
{
7047 u8 reserved_at_0
[0x8];
7049 u8 reserved_at_10
[0x10];
7052 u8 reserved_at_21
[0x19];
7054 u8 reserved_at_3e
[0x2];
7057 struct mlx5_ifc_pifr_reg_bits
{
7058 u8 reserved_at_0
[0x8];
7060 u8 reserved_at_10
[0x10];
7062 u8 reserved_at_20
[0xe0];
7064 u8 port_filter
[8][0x20];
7066 u8 port_filter_update_en
[8][0x20];
7069 struct mlx5_ifc_pfcc_reg_bits
{
7070 u8 reserved_at_0
[0x8];
7072 u8 reserved_at_10
[0x10];
7075 u8 reserved_at_24
[0x4];
7076 u8 prio_mask_tx
[0x8];
7077 u8 reserved_at_30
[0x8];
7078 u8 prio_mask_rx
[0x8];
7082 u8 reserved_at_42
[0x6];
7084 u8 reserved_at_50
[0x10];
7088 u8 reserved_at_62
[0x6];
7090 u8 reserved_at_70
[0x10];
7092 u8 reserved_at_80
[0x80];
7095 struct mlx5_ifc_pelc_reg_bits
{
7097 u8 reserved_at_4
[0x4];
7099 u8 reserved_at_10
[0x10];
7102 u8 op_capability
[0x8];
7108 u8 capability
[0x40];
7114 u8 reserved_at_140
[0x80];
7117 struct mlx5_ifc_peir_reg_bits
{
7118 u8 reserved_at_0
[0x8];
7120 u8 reserved_at_10
[0x10];
7122 u8 reserved_at_20
[0xc];
7123 u8 error_count
[0x4];
7124 u8 reserved_at_30
[0x10];
7126 u8 reserved_at_40
[0xc];
7128 u8 reserved_at_50
[0x8];
7132 struct mlx5_ifc_pcap_reg_bits
{
7133 u8 reserved_at_0
[0x8];
7135 u8 reserved_at_10
[0x10];
7137 u8 port_capability_mask
[4][0x20];
7140 struct mlx5_ifc_paos_reg_bits
{
7143 u8 reserved_at_10
[0x4];
7144 u8 admin_status
[0x4];
7145 u8 reserved_at_18
[0x4];
7146 u8 oper_status
[0x4];
7150 u8 reserved_at_22
[0x1c];
7153 u8 reserved_at_40
[0x40];
7156 struct mlx5_ifc_pamp_reg_bits
{
7157 u8 reserved_at_0
[0x8];
7158 u8 opamp_group
[0x8];
7159 u8 reserved_at_10
[0xc];
7160 u8 opamp_group_type
[0x4];
7162 u8 start_index
[0x10];
7163 u8 reserved_at_30
[0x4];
7164 u8 num_of_indices
[0xc];
7166 u8 index_data
[18][0x10];
7169 struct mlx5_ifc_pcmr_reg_bits
{
7170 u8 reserved_at_0
[0x8];
7172 u8 reserved_at_10
[0x2e];
7174 u8 reserved_at_3f
[0x1f];
7176 u8 reserved_at_5f
[0x1];
7179 struct mlx5_ifc_lane_2_module_mapping_bits
{
7180 u8 reserved_at_0
[0x6];
7182 u8 reserved_at_8
[0x6];
7184 u8 reserved_at_10
[0x8];
7188 struct mlx5_ifc_bufferx_reg_bits
{
7189 u8 reserved_at_0
[0x6];
7192 u8 reserved_at_8
[0xc];
7195 u8 xoff_threshold
[0x10];
7196 u8 xon_threshold
[0x10];
7199 struct mlx5_ifc_set_node_in_bits
{
7200 u8 node_description
[64][0x8];
7203 struct mlx5_ifc_register_power_settings_bits
{
7204 u8 reserved_at_0
[0x18];
7205 u8 power_settings_level
[0x8];
7207 u8 reserved_at_20
[0x60];
7210 struct mlx5_ifc_register_host_endianness_bits
{
7212 u8 reserved_at_1
[0x1f];
7214 u8 reserved_at_20
[0x60];
7217 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
7218 u8 reserved_at_0
[0x20];
7222 u8 addressh_63_32
[0x20];
7224 u8 addressl_31_0
[0x20];
7227 struct mlx5_ifc_ud_adrs_vector_bits
{
7231 u8 reserved_at_41
[0x7];
7232 u8 destination_qp_dct
[0x18];
7234 u8 static_rate
[0x4];
7235 u8 sl_eth_prio
[0x4];
7238 u8 rlid_udp_sport
[0x10];
7240 u8 reserved_at_80
[0x20];
7242 u8 rmac_47_16
[0x20];
7248 u8 reserved_at_e0
[0x1];
7250 u8 reserved_at_e2
[0x2];
7251 u8 src_addr_index
[0x8];
7252 u8 flow_label
[0x14];
7254 u8 rgid_rip
[16][0x8];
7257 struct mlx5_ifc_pages_req_event_bits
{
7258 u8 reserved_at_0
[0x10];
7259 u8 function_id
[0x10];
7263 u8 reserved_at_40
[0xa0];
7266 struct mlx5_ifc_eqe_bits
{
7267 u8 reserved_at_0
[0x8];
7269 u8 reserved_at_10
[0x8];
7270 u8 event_sub_type
[0x8];
7272 u8 reserved_at_20
[0xe0];
7274 union mlx5_ifc_event_auto_bits event_data
;
7276 u8 reserved_at_1e0
[0x10];
7278 u8 reserved_at_1f8
[0x7];
7283 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
7286 struct mlx5_ifc_cmd_queue_entry_bits
{
7288 u8 reserved_at_8
[0x18];
7290 u8 input_length
[0x20];
7292 u8 input_mailbox_pointer_63_32
[0x20];
7294 u8 input_mailbox_pointer_31_9
[0x17];
7295 u8 reserved_at_77
[0x9];
7297 u8 command_input_inline_data
[16][0x8];
7299 u8 command_output_inline_data
[16][0x8];
7301 u8 output_mailbox_pointer_63_32
[0x20];
7303 u8 output_mailbox_pointer_31_9
[0x17];
7304 u8 reserved_at_1b7
[0x9];
7306 u8 output_length
[0x20];
7310 u8 reserved_at_1f0
[0x8];
7315 struct mlx5_ifc_cmd_out_bits
{
7317 u8 reserved_at_8
[0x18];
7321 u8 command_output
[0x20];
7324 struct mlx5_ifc_cmd_in_bits
{
7326 u8 reserved_at_10
[0x10];
7328 u8 reserved_at_20
[0x10];
7331 u8 command
[0][0x20];
7334 struct mlx5_ifc_cmd_if_box_bits
{
7335 u8 mailbox_data
[512][0x8];
7337 u8 reserved_at_1000
[0x180];
7339 u8 next_pointer_63_32
[0x20];
7341 u8 next_pointer_31_10
[0x16];
7342 u8 reserved_at_11b6
[0xa];
7344 u8 block_number
[0x20];
7346 u8 reserved_at_11e0
[0x8];
7348 u8 ctrl_signature
[0x8];
7352 struct mlx5_ifc_mtt_bits
{
7353 u8 ptag_63_32
[0x20];
7356 u8 reserved_at_38
[0x6];
7361 struct mlx5_ifc_query_wol_rol_out_bits
{
7363 u8 reserved_at_8
[0x18];
7367 u8 reserved_at_40
[0x10];
7371 u8 reserved_at_60
[0x20];
7374 struct mlx5_ifc_query_wol_rol_in_bits
{
7376 u8 reserved_at_10
[0x10];
7378 u8 reserved_at_20
[0x10];
7381 u8 reserved_at_40
[0x40];
7384 struct mlx5_ifc_set_wol_rol_out_bits
{
7386 u8 reserved_at_8
[0x18];
7390 u8 reserved_at_40
[0x40];
7393 struct mlx5_ifc_set_wol_rol_in_bits
{
7395 u8 reserved_at_10
[0x10];
7397 u8 reserved_at_20
[0x10];
7400 u8 rol_mode_valid
[0x1];
7401 u8 wol_mode_valid
[0x1];
7402 u8 reserved_at_42
[0xe];
7406 u8 reserved_at_60
[0x20];
7410 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
7411 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
7412 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
7416 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
7417 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
7418 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
7422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
7423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
7424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
7425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
7426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
7427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
7428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
7429 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
7430 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
7431 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
7432 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
7435 struct mlx5_ifc_initial_seg_bits
{
7436 u8 fw_rev_minor
[0x10];
7437 u8 fw_rev_major
[0x10];
7439 u8 cmd_interface_rev
[0x10];
7440 u8 fw_rev_subminor
[0x10];
7442 u8 reserved_at_40
[0x40];
7444 u8 cmdq_phy_addr_63_32
[0x20];
7446 u8 cmdq_phy_addr_31_12
[0x14];
7447 u8 reserved_at_b4
[0x2];
7448 u8 nic_interface
[0x2];
7449 u8 log_cmdq_size
[0x4];
7450 u8 log_cmdq_stride
[0x4];
7452 u8 command_doorbell_vector
[0x20];
7454 u8 reserved_at_e0
[0xf00];
7456 u8 initializing
[0x1];
7457 u8 reserved_at_fe1
[0x4];
7458 u8 nic_interface_supported
[0x3];
7459 u8 reserved_at_fe8
[0x18];
7461 struct mlx5_ifc_health_buffer_bits health_buffer
;
7463 u8 no_dram_nic_offset
[0x20];
7465 u8 reserved_at_1220
[0x6e40];
7467 u8 reserved_at_8060
[0x1f];
7470 u8 health_syndrome
[0x8];
7471 u8 health_counter
[0x18];
7473 u8 reserved_at_80a0
[0x17fc0];
7476 union mlx5_ifc_ports_control_registers_document_bits
{
7477 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
7478 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
7479 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
7480 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
7481 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
7482 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
7483 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
7484 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
7485 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
7486 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
7487 struct mlx5_ifc_paos_reg_bits paos_reg
;
7488 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
7489 struct mlx5_ifc_peir_reg_bits peir_reg
;
7490 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
7491 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
7492 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
7493 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
7494 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
7495 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
7496 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
7497 struct mlx5_ifc_plib_reg_bits plib_reg
;
7498 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
7499 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
7500 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
7501 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
7502 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
7503 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
7504 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
7505 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
7506 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
7507 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
7508 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
7509 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
7510 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
7511 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
7512 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
7513 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
7514 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
7515 struct mlx5_ifc_mlcr_reg_bits mlcr_reg
;
7516 struct mlx5_ifc_pude_reg_bits pude_reg
;
7517 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
7518 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
7519 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
7520 u8 reserved_at_0
[0x60e0];
7523 union mlx5_ifc_debug_enhancements_document_bits
{
7524 struct mlx5_ifc_health_buffer_bits health_buffer
;
7525 u8 reserved_at_0
[0x200];
7528 union mlx5_ifc_uplink_pci_interface_document_bits
{
7529 struct mlx5_ifc_initial_seg_bits initial_seg
;
7530 u8 reserved_at_0
[0x20060];
7533 struct mlx5_ifc_set_flow_table_root_out_bits
{
7535 u8 reserved_at_8
[0x18];
7539 u8 reserved_at_40
[0x40];
7542 struct mlx5_ifc_set_flow_table_root_in_bits
{
7544 u8 reserved_at_10
[0x10];
7546 u8 reserved_at_20
[0x10];
7549 u8 other_vport
[0x1];
7550 u8 reserved_at_41
[0xf];
7551 u8 vport_number
[0x10];
7553 u8 reserved_at_60
[0x20];
7556 u8 reserved_at_88
[0x18];
7558 u8 reserved_at_a0
[0x8];
7561 u8 reserved_at_c0
[0x140];
7565 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= 0x1,
7568 struct mlx5_ifc_modify_flow_table_out_bits
{
7570 u8 reserved_at_8
[0x18];
7574 u8 reserved_at_40
[0x40];
7577 struct mlx5_ifc_modify_flow_table_in_bits
{
7579 u8 reserved_at_10
[0x10];
7581 u8 reserved_at_20
[0x10];
7584 u8 other_vport
[0x1];
7585 u8 reserved_at_41
[0xf];
7586 u8 vport_number
[0x10];
7588 u8 reserved_at_60
[0x10];
7589 u8 modify_field_select
[0x10];
7592 u8 reserved_at_88
[0x18];
7594 u8 reserved_at_a0
[0x8];
7597 u8 reserved_at_c0
[0x4];
7598 u8 table_miss_mode
[0x4];
7599 u8 reserved_at_c8
[0x18];
7601 u8 reserved_at_e0
[0x8];
7602 u8 table_miss_id
[0x18];
7604 u8 reserved_at_100
[0x100];
7607 struct mlx5_ifc_ets_tcn_config_reg_bits
{
7611 u8 reserved_at_3
[0x9];
7613 u8 reserved_at_10
[0x9];
7614 u8 bw_allocation
[0x7];
7616 u8 reserved_at_20
[0xc];
7617 u8 max_bw_units
[0x4];
7618 u8 reserved_at_30
[0x8];
7619 u8 max_bw_value
[0x8];
7622 struct mlx5_ifc_ets_global_config_reg_bits
{
7623 u8 reserved_at_0
[0x2];
7625 u8 reserved_at_3
[0x1d];
7627 u8 reserved_at_20
[0xc];
7628 u8 max_bw_units
[0x4];
7629 u8 reserved_at_30
[0x8];
7630 u8 max_bw_value
[0x8];
7633 struct mlx5_ifc_qetc_reg_bits
{
7634 u8 reserved_at_0
[0x8];
7635 u8 port_number
[0x8];
7636 u8 reserved_at_10
[0x30];
7638 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration
[0x8];
7639 struct mlx5_ifc_ets_global_config_reg_bits global_configuration
;
7642 struct mlx5_ifc_qtct_reg_bits
{
7643 u8 reserved_at_0
[0x8];
7644 u8 port_number
[0x8];
7645 u8 reserved_at_10
[0xd];
7648 u8 reserved_at_20
[0x1d];
7652 struct mlx5_ifc_mcia_reg_bits
{
7654 u8 reserved_at_1
[0x7];
7656 u8 reserved_at_10
[0x8];
7659 u8 i2c_device_address
[0x8];
7660 u8 page_number
[0x8];
7661 u8 device_address
[0x10];
7663 u8 reserved_at_40
[0x10];
7666 u8 reserved_at_60
[0x20];
7682 struct mlx5_ifc_dcbx_param_bits
{
7683 u8 dcbx_cee_cap
[0x1];
7684 u8 dcbx_ieee_cap
[0x1];
7685 u8 dcbx_standby_cap
[0x1];
7686 u8 reserved_at_0
[0x5];
7687 u8 port_number
[0x8];
7688 u8 reserved_at_10
[0xa];
7689 u8 max_application_table_size
[6];
7690 u8 reserved_at_20
[0x15];
7691 u8 version_oper
[0x3];
7692 u8 reserved_at_38
[5];
7693 u8 version_admin
[0x3];
7694 u8 willing_admin
[0x1];
7695 u8 reserved_at_41
[0x3];
7696 u8 pfc_cap_oper
[0x4];
7697 u8 reserved_at_48
[0x4];
7698 u8 pfc_cap_admin
[0x4];
7699 u8 reserved_at_50
[0x4];
7700 u8 num_of_tc_oper
[0x4];
7701 u8 reserved_at_58
[0x4];
7702 u8 num_of_tc_admin
[0x4];
7703 u8 remote_willing
[0x1];
7704 u8 reserved_at_61
[3];
7705 u8 remote_pfc_cap
[4];
7706 u8 reserved_at_68
[0x14];
7707 u8 remote_num_of_tc
[0x4];
7708 u8 reserved_at_80
[0x18];
7710 u8 reserved_at_a0
[0x160];
7712 #endif /* MLX5_IFC_H */