2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 #define MLX5_QPN_BITS 24
54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
57 MLX5_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
58 MLX5_QP_OPTPAR_RRE
= 1 << 1,
59 MLX5_QP_OPTPAR_RAE
= 1 << 2,
60 MLX5_QP_OPTPAR_RWE
= 1 << 3,
61 MLX5_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
62 MLX5_QP_OPTPAR_Q_KEY
= 1 << 5,
63 MLX5_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
65 MLX5_QP_OPTPAR_SRA_MAX
= 1 << 8,
66 MLX5_QP_OPTPAR_RRA_MAX
= 1 << 9,
67 MLX5_QP_OPTPAR_PM_STATE
= 1 << 10,
68 MLX5_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
69 MLX5_QP_OPTPAR_RNR_RETRY
= 1 << 13,
70 MLX5_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
71 MLX5_QP_OPTPAR_PRI_PORT
= 1 << 16,
72 MLX5_QP_OPTPAR_SRQN
= 1 << 18,
73 MLX5_QP_OPTPAR_CQN_RCV
= 1 << 19,
74 MLX5_QP_OPTPAR_DC_HS
= 1 << 20,
75 MLX5_QP_OPTPAR_DC_KEY
= 1 << 21,
79 MLX5_QP_STATE_RST
= 0,
80 MLX5_QP_STATE_INIT
= 1,
81 MLX5_QP_STATE_RTR
= 2,
82 MLX5_QP_STATE_RTS
= 3,
83 MLX5_QP_STATE_SQER
= 4,
84 MLX5_QP_STATE_SQD
= 5,
85 MLX5_QP_STATE_ERR
= 6,
86 MLX5_QP_STATE_SQ_DRAINING
= 7,
87 MLX5_QP_STATE_SUSPENDED
= 9,
100 MLX5_QP_ST_QP1
= 0x8,
101 MLX5_QP_ST_RAW_ETHERTYPE
= 0x9,
102 MLX5_QP_ST_RAW_IPV6
= 0xa,
103 MLX5_QP_ST_SNIFFER
= 0xb,
104 MLX5_QP_ST_SYNC_UMR
= 0xe,
105 MLX5_QP_ST_PTP_1588
= 0xd,
106 MLX5_QP_ST_REG_UMR
= 0xc,
111 MLX5_QP_PM_MIGRATED
= 0x3,
112 MLX5_QP_PM_ARMED
= 0x0,
113 MLX5_QP_PM_REARM
= 0x1
117 MLX5_NON_ZERO_RQ
= 0 << 24,
118 MLX5_SRQ_RQ
= 1 << 24,
119 MLX5_CRQ_RQ
= 2 << 24,
120 MLX5_ZERO_LEN_RQ
= 3 << 24
125 MLX5_QP_BIT_SRE
= 1 << 15,
126 MLX5_QP_BIT_SWE
= 1 << 14,
127 MLX5_QP_BIT_SAE
= 1 << 13,
129 MLX5_QP_BIT_RRE
= 1 << 15,
130 MLX5_QP_BIT_RWE
= 1 << 14,
131 MLX5_QP_BIT_RAE
= 1 << 13,
132 MLX5_QP_BIT_RIC
= 1 << 4,
136 MLX5_WQE_CTRL_CQ_UPDATE
= 2 << 2,
137 MLX5_WQE_CTRL_SOLICITED
= 1 << 1,
141 MLX5_SEND_WQE_BB
= 64,
145 MLX5_WQE_FMR_PERM_LOCAL_READ
= 1 << 27,
146 MLX5_WQE_FMR_PERM_LOCAL_WRITE
= 1 << 28,
147 MLX5_WQE_FMR_PERM_REMOTE_READ
= 1 << 29,
148 MLX5_WQE_FMR_PERM_REMOTE_WRITE
= 1 << 30,
149 MLX5_WQE_FMR_PERM_ATOMIC
= 1 << 31
153 MLX5_FENCE_MODE_NONE
= 0 << 5,
154 MLX5_FENCE_MODE_INITIATOR_SMALL
= 1 << 5,
155 MLX5_FENCE_MODE_STRONG_ORDERING
= 3 << 5,
156 MLX5_FENCE_MODE_SMALL_AND_FENCE
= 4 << 5,
160 MLX5_QP_LAT_SENSITIVE
= 1 << 28,
161 MLX5_QP_BLOCK_MCAST
= 1 << 30,
162 MLX5_QP_ENABLE_SIG
= 1 << 31,
171 MLX5_FLAGS_INLINE
= 1<<7,
172 MLX5_FLAGS_CHECK_FREE
= 1<<5,
175 struct mlx5_wqe_fmr_seg
{
186 struct mlx5_wqe_ctrl_seg
{
187 __be32 opmod_idx_opcode
;
195 #define MLX5_WQE_CTRL_DS_MASK 0x3f
196 #define MLX5_WQE_DS_UNITS 16
198 struct mlx5_wqe_xrc_seg
{
203 struct mlx5_wqe_masked_atomic_seg
{
206 __be64 swap_add_mask
;
229 struct mlx5_wqe_datagram_seg
{
233 struct mlx5_wqe_raddr_seg
{
239 struct mlx5_wqe_atomic_seg
{
244 struct mlx5_wqe_data_seg
{
250 struct mlx5_wqe_umr_ctrl_seg
{
253 __be16 klm_octowords
;
254 __be16 bsf_octowords
;
259 struct mlx5_seg_set_psv
{
263 __be32 transient_sig
;
267 struct mlx5_seg_get_psv
{
275 struct mlx5_seg_check_psv
{
277 __be16 err_coalescing_op
;
281 __be16 xport_err_mask
;
289 struct mlx5_rwqe_sig
{
295 struct mlx5_wqe_signature_seg
{
301 struct mlx5_wqe_inline_seg
{
310 struct mlx5_bsf_inl
{
317 u8 dif_inc_ref_guard_check
;
318 __be16 dif_app_bitmask_check
;
322 struct mlx5_bsf_basic
{
334 __be32 raw_data_size
;
338 struct mlx5_bsf_ext
{
339 __be32 t_init_gen_pro_size
;
340 __be32 rsvd_epi_size
;
344 struct mlx5_bsf_inl w_inl
;
345 struct mlx5_bsf_inl m_inl
;
354 struct mlx5_stride_block_entry
{
361 struct mlx5_stride_block_ctrl_seg
{
362 __be32 bcount_per_cycle
;
369 enum mlx5_pagefault_flags
{
370 MLX5_PFAULT_REQUESTOR
= 1 << 0,
371 MLX5_PFAULT_WRITE
= 1 << 1,
372 MLX5_PFAULT_RDMA
= 1 << 2,
375 /* Contains the details of a pagefault. */
376 struct mlx5_pagefault
{
379 enum mlx5_pagefault_flags flags
;
381 /* Initiator or send message responder pagefault details. */
383 /* Received packet size, only valid for responders. */
386 * WQE index. Refers to either the send queue or
387 * receive queue, according to event_subtype.
391 /* RDMA responder pagefault details */
395 * Received packet size, minimal size page fault
396 * resolution required for forward progress.
405 struct mlx5_core_qp
{
406 struct mlx5_core_rsc_common common
; /* must be first */
407 void (*event
) (struct mlx5_core_qp
*, int);
408 void (*pfault_handler
)(struct mlx5_core_qp
*, struct mlx5_pagefault
*);
410 struct mlx5_rsc_debug
*dbg
;
414 struct mlx5_qp_path
{
426 __be32 tclass_flowlabel
;
434 struct mlx5_qp_context
{
440 __be32 qp_counter_set_usr_page
;
442 __be32 log_pg_sz_remote_qpn
;
443 struct mlx5_qp_path pri_path
;
444 struct mlx5_qp_path alt_path
;
447 __be32 next_send_psn
;
450 __be32 last_acked_psn
;
453 __be32 rnr_nextrecvpsn
;
460 __be16 hw_sq_wqe_counter
;
461 __be16 sw_sq_wqe_counter
;
462 __be16 hw_rcyclic_byte_counter
;
463 __be16 hw_rq_counter
;
464 __be16 sw_rcyclic_byte_counter
;
465 __be16 sw_rq_counter
;
470 __be64 dc_access_key
;
474 struct mlx5_create_qp_mbox_in
{
475 struct mlx5_inbox_hdr hdr
;
478 __be32 opt_param_mask
;
480 struct mlx5_qp_context ctx
;
485 struct mlx5_create_qp_mbox_out
{
486 struct mlx5_outbox_hdr hdr
;
491 struct mlx5_destroy_qp_mbox_in
{
492 struct mlx5_inbox_hdr hdr
;
497 struct mlx5_destroy_qp_mbox_out
{
498 struct mlx5_outbox_hdr hdr
;
502 struct mlx5_modify_qp_mbox_in
{
503 struct mlx5_inbox_hdr hdr
;
508 struct mlx5_qp_context ctx
;
511 struct mlx5_modify_qp_mbox_out
{
512 struct mlx5_outbox_hdr hdr
;
516 struct mlx5_query_qp_mbox_in
{
517 struct mlx5_inbox_hdr hdr
;
522 struct mlx5_query_qp_mbox_out
{
523 struct mlx5_outbox_hdr hdr
;
527 struct mlx5_qp_context ctx
;
532 struct mlx5_conf_sqp_mbox_in
{
533 struct mlx5_inbox_hdr hdr
;
539 struct mlx5_conf_sqp_mbox_out
{
540 struct mlx5_outbox_hdr hdr
;
544 struct mlx5_alloc_xrcd_mbox_in
{
545 struct mlx5_inbox_hdr hdr
;
549 struct mlx5_alloc_xrcd_mbox_out
{
550 struct mlx5_outbox_hdr hdr
;
555 struct mlx5_dealloc_xrcd_mbox_in
{
556 struct mlx5_inbox_hdr hdr
;
561 struct mlx5_dealloc_xrcd_mbox_out
{
562 struct mlx5_outbox_hdr hdr
;
566 static inline struct mlx5_core_qp
*__mlx5_qp_lookup(struct mlx5_core_dev
*dev
, u32 qpn
)
568 return radix_tree_lookup(&dev
->priv
.qp_table
.tree
, qpn
);
571 static inline struct mlx5_core_mr
*__mlx5_mr_lookup(struct mlx5_core_dev
*dev
, u32 key
)
573 return radix_tree_lookup(&dev
->priv
.mr_table
.tree
, key
);
576 struct mlx5_page_fault_resume_mbox_in
{
577 struct mlx5_inbox_hdr hdr
;
582 struct mlx5_page_fault_resume_mbox_out
{
583 struct mlx5_outbox_hdr hdr
;
587 int mlx5_core_create_qp(struct mlx5_core_dev
*dev
,
588 struct mlx5_core_qp
*qp
,
589 struct mlx5_create_qp_mbox_in
*in
,
591 int mlx5_core_qp_modify(struct mlx5_core_dev
*dev
, enum mlx5_qp_state cur_state
,
592 enum mlx5_qp_state new_state
,
593 struct mlx5_modify_qp_mbox_in
*in
, int sqd_event
,
594 struct mlx5_core_qp
*qp
);
595 int mlx5_core_destroy_qp(struct mlx5_core_dev
*dev
,
596 struct mlx5_core_qp
*qp
);
597 int mlx5_core_qp_query(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
,
598 struct mlx5_query_qp_mbox_out
*out
, int outlen
);
600 int mlx5_core_xrcd_alloc(struct mlx5_core_dev
*dev
, u32
*xrcdn
);
601 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev
*dev
, u32 xrcdn
);
602 void mlx5_init_qp_table(struct mlx5_core_dev
*dev
);
603 void mlx5_cleanup_qp_table(struct mlx5_core_dev
*dev
);
604 int mlx5_debug_qp_add(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
);
605 void mlx5_debug_qp_remove(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
);
606 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
607 int mlx5_core_page_fault_resume(struct mlx5_core_dev
*dev
, u32 qpn
,
608 u8 context
, int error
);
611 static inline const char *mlx5_qp_type_str(int type
)
614 case MLX5_QP_ST_RC
: return "RC";
615 case MLX5_QP_ST_UC
: return "C";
616 case MLX5_QP_ST_UD
: return "UD";
617 case MLX5_QP_ST_XRC
: return "XRC";
618 case MLX5_QP_ST_MLX
: return "MLX";
619 case MLX5_QP_ST_QP0
: return "QP0";
620 case MLX5_QP_ST_QP1
: return "QP1";
621 case MLX5_QP_ST_RAW_ETHERTYPE
: return "RAW_ETHERTYPE";
622 case MLX5_QP_ST_RAW_IPV6
: return "RAW_IPV6";
623 case MLX5_QP_ST_SNIFFER
: return "SNIFFER";
624 case MLX5_QP_ST_SYNC_UMR
: return "SYNC_UMR";
625 case MLX5_QP_ST_PTP_1588
: return "PTP_1588";
626 case MLX5_QP_ST_REG_UMR
: return "REG_UMR";
627 default: return "Invalid transport type";
631 static inline const char *mlx5_qp_state_str(int state
)
634 case MLX5_QP_STATE_RST
:
636 case MLX5_QP_STATE_INIT
:
638 case MLX5_QP_STATE_RTR
:
640 case MLX5_QP_STATE_RTS
:
642 case MLX5_QP_STATE_SQER
:
644 case MLX5_QP_STATE_SQD
:
646 case MLX5_QP_STATE_ERR
:
648 case MLX5_QP_STATE_SQ_DRAINING
:
649 return "SQ_DRAINING";
650 case MLX5_QP_STATE_SUSPENDED
:
652 default: return "Invalid QP state";
656 #endif /* MLX5_QP_H */