2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #ifndef LINUX_MMC_DW_MMC_H
15 #define LINUX_MMC_DW_MMC_H
17 #include <linux/scatterlist.h>
19 #define MAX_MCI_SLOTS 2
31 EVENT_CMD_COMPLETE
= 0,
41 * struct dw_mci - MMC controller state shared between all slots
42 * @lock: Spinlock protecting the queue and associated data.
43 * @regs: Pointer to MMIO registers.
44 * @sg: Scatterlist entry currently being processed by PIO code, if any.
45 * @sg_miter: PIO mapping scatterlist iterator.
46 * @cur_slot: The slot which is currently using the controller.
47 * @mrq: The request currently being processed on @cur_slot,
48 * or NULL if the controller is idle.
49 * @cmd: The command currently being sent to the card, or NULL.
50 * @data: The data currently being transferred, or NULL if no data
51 * transfer is in progress.
52 * @use_dma: Whether DMA channel is initialized or not.
53 * @using_dma: Whether DMA is in use for the current transfer.
54 * @sg_dma: Bus address of DMA buffer.
55 * @sg_cpu: Virtual address of DMA buffer.
56 * @dma_ops: Pointer to platform-specific DMA callbacks.
57 * @cmd_status: Snapshot of SR taken upon completion of the current
58 * command. Only valid when EVENT_CMD_COMPLETE is pending.
59 * @data_status: Snapshot of SR taken upon completion of the current
60 * data transfer. Only valid when EVENT_DATA_COMPLETE or
61 * EVENT_DATA_ERROR is pending.
62 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
64 * @dir_status: Direction of current transfer.
65 * @tasklet: Tasklet running the request state machine.
66 * @card_tasklet: Tasklet handling card detect.
67 * @pending_events: Bitmask of events flagged by the interrupt handler
68 * to be processed by the tasklet.
69 * @completed_events: Bitmask of events which the state machine has
71 * @state: Tasklet state.
72 * @queue: List of slots waiting for access to the controller.
73 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
74 * rate and timeout calculations.
75 * @current_speed: Configured rate of the controller.
76 * @num_slots: Number of slots available.
77 * @verid: Denote Version ID.
78 * @data_offset: Set the offset of DATA register according to VERID.
79 * @dev: Device associated with the MMC controller.
80 * @pdata: Platform data associated with the MMC controller.
81 * @drv_data: Driver specific data for identified variant of the controller
82 * @priv: Implementation defined private data.
83 * @biu_clk: Pointer to bus interface unit clock instance.
84 * @ciu_clk: Pointer to card interface unit clock instance.
85 * @slot: Slots sharing this MMC controller.
86 * @fifo_depth: depth of FIFO.
87 * @data_shift: log2 of FIFO item size.
88 * @part_buf_start: Start index in part_buf.
89 * @part_buf_count: Bytes of partial data in part_buf.
90 * @part_buf: Simple buffer for partial fifo reads/writes.
91 * @push_data: Pointer to FIFO push function.
92 * @pull_data: Pointer to FIFO pull function.
93 * @quirks: Set of quirks that apply to specific versions of the IP.
94 * @irq_flags: The flags to be passed to request_irq.
95 * @irq: The irq value to be passed to request_irq.
100 * @lock is a softirq-safe spinlock protecting @queue as well as
101 * @cur_slot, @mrq and @state. These must always be updated
102 * at the same time while holding @lock.
104 * The @mrq field of struct dw_mci_slot is also protected by @lock,
105 * and must always be written at the same time as the slot is added to
108 * @pending_events and @completed_events are accessed using atomic bit
109 * operations, so they don't need any locking.
111 * None of the fields touched by the interrupt handler need any
112 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
113 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
114 * interrupts must be disabled and @data_status updated with a
115 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
116 * CMDRDY interrupt must be disabled and @cmd_status updated with a
117 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
118 * bytes_xfered field of @data must be written. This is ensured by
125 struct scatterlist
*sg
;
126 struct sg_mapping_iter sg_miter
;
128 struct dw_mci_slot
*cur_slot
;
129 struct mmc_request
*mrq
;
130 struct mmc_command
*cmd
;
131 struct mmc_data
*data
;
132 struct workqueue_struct
*card_workqueue
;
134 /* DMA interface members*/
140 struct dw_mci_dma_ops
*dma_ops
;
141 #ifdef CONFIG_MMC_DW_IDMAC
142 unsigned int ring_size
;
144 struct dw_mci_dma_data
*dma_data
;
150 struct tasklet_struct tasklet
;
151 struct work_struct card_work
;
152 unsigned long pending_events
;
153 unsigned long completed_events
;
154 enum dw_mci_state state
;
155 struct list_head queue
;
164 struct dw_mci_board
*pdata
;
165 struct dw_mci_drv_data
*drv_data
;
169 struct dw_mci_slot
*slot
[MAX_MCI_SLOTS
];
171 /* FIFO push and pull */
181 void (*push_data
)(struct dw_mci
*host
, void *buf
, int cnt
);
182 void (*pull_data
)(struct dw_mci
*host
, void *buf
, int cnt
);
184 /* Workaround flags */
187 struct regulator
*vmmc
; /* Power regulator */
188 unsigned long irq_flags
; /* IRQ flags */
192 /* DMA ops for Internal/External DMAC interface */
193 struct dw_mci_dma_ops
{
195 int (*init
)(struct dw_mci
*host
);
196 void (*start
)(struct dw_mci
*host
, unsigned int sg_len
);
197 void (*complete
)(struct dw_mci
*host
);
198 void (*stop
)(struct dw_mci
*host
);
199 void (*cleanup
)(struct dw_mci
*host
);
200 void (*exit
)(struct dw_mci
*host
);
203 /* IP Quirks/flags. */
204 /* DTO fix for command transmission with IDMAC configured */
205 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
206 /* delay needed between retries on some 2.11a implementations */
207 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
208 /* High Speed Capable - Supports HS cards (up to 50MHz) */
209 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
210 /* Unreliable card detection */
211 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
212 /* Write Protect detection not available */
213 #define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
217 struct block_settings
{
218 unsigned short max_segs
; /* see blk_queue_max_segments */
219 unsigned int max_blk_size
; /* maximum size of one mmc block */
220 unsigned int max_blk_count
; /* maximum number of blocks in one req*/
221 unsigned int max_req_size
; /* maximum number of bytes in one req*/
222 unsigned int max_seg_size
; /* see blk_queue_max_segment_size */
225 /* Board platform data */
226 struct dw_mci_board
{
229 u32 quirks
; /* Workaround / Quirk flags */
230 unsigned int bus_hz
; /* Bus speed */
232 unsigned int caps
; /* Capabilities */
233 unsigned int caps2
; /* More capabilities */
235 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
236 * but note that this may not be reliable after a bootloader has used
239 unsigned int fifo_depth
;
241 /* delay in mS before detecting cards after interrupt */
244 int (*init
)(u32 slot_id
, irq_handler_t
, void *);
245 int (*get_ro
)(u32 slot_id
);
246 int (*get_cd
)(u32 slot_id
);
247 int (*get_ocr
)(u32 slot_id
);
248 int (*get_bus_wd
)(u32 slot_id
);
250 * Enable power to selected slot and set voltage to desired level.
251 * Voltage levels are specified using MMC_VDD_xxx defines defined
252 * in linux/mmc/host.h file.
254 void (*setpower
)(u32 slot_id
, u32 volt
);
255 void (*exit
)(u32 slot_id
);
256 void (*select_slot
)(u32 slot_id
);
258 struct dw_mci_dma_ops
*dma_ops
;
259 struct dma_pdata
*data
;
260 struct block_settings
*blk_settings
;
263 #endif /* LINUX_MMC_DW_MMC_H */
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