include/linux/mmc/dw_mmc.h

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef LINUX_MMC_DW_MMC_H
  15 #define LINUX_MMC_DW_MMC_H
  16
  17 #include <linux/scatterlist.h>
  18 #include <linux/mmc/core.h>
  19 #include <linux/dmaengine.h>
  20
  21 #define MAX_MCI_SLOTS   2
  22
  23 enum dw_mci_state {
  24         STATE_IDLE = 0,
  25         STATE_SENDING_CMD,
  26         STATE_SENDING_DATA,
  27         STATE_DATA_BUSY,
  28         STATE_SENDING_STOP,
  29         STATE_DATA_ERROR,
  30         STATE_SENDING_CMD11,
  31         STATE_WAITING_CMD11_DONE,
  32 };
  33
  34 enum {
  35         EVENT_CMD_COMPLETE = 0,
  36         EVENT_XFER_COMPLETE,
  37         EVENT_DATA_COMPLETE,
  38         EVENT_DATA_ERROR,
  39         EVENT_XFER_ERROR
  40 };
  41
  42 struct mmc_data;
  43
  44 enum {
  45         TRANS_MODE_PIO = 0,
  46         TRANS_MODE_IDMAC,
  47         TRANS_MODE_EDMAC
  48 };
  49
  50 struct dw_mci_dma_slave {
  51         struct dma_chan *ch;
  52         enum dma_transfer_direction direction;
  53 };
  54
  55 /**
  56  * struct dw_mci - MMC controller state shared between all slots
  57  * @lock: Spinlock protecting the queue and associated data.
  58  * @irq_lock: Spinlock protecting the INTMASK setting.
  59  * @regs: Pointer to MMIO registers.
  60  * @fifo_reg: Pointer to MMIO registers for data FIFO
  61  * @sg: Scatterlist entry currently being processed by PIO code, if any.
  62  * @sg_miter: PIO mapping scatterlist iterator.
  63  * @cur_slot: The slot which is currently using the controller.
  64  * @mrq: The request currently being processed on @cur_slot,
  65  *      or NULL if the controller is idle.
  66  * @cmd: The command currently being sent to the card, or NULL.
  67  * @data: The data currently being transferred, or NULL if no data
  68  *      transfer is in progress.
  69  * @stop_abort: The command currently prepared for stoping transfer.
  70  * @prev_blksz: The former transfer blksz record.
  71  * @timing: Record of current ios timing.
  72  * @use_dma: Whether DMA channel is initialized or not.
  73  * @using_dma: Whether DMA is in use for the current transfer.
  74  * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
  75  * @sg_dma: Bus address of DMA buffer.
  76  * @sg_cpu: Virtual address of DMA buffer.
  77  * @dma_ops: Pointer to platform-specific DMA callbacks.
  78  * @cmd_status: Snapshot of SR taken upon completion of the current
  79  * @ring_size: Buffer size for idma descriptors.
  80  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
  81  * @dms: structure of slave-dma private data.
  82  * @phy_regs: physical address of controller's register map
  83  * @data_status: Snapshot of SR taken upon completion of the current
  84  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
  85  *      EVENT_DATA_ERROR is pending.
  86  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  87  *      to be sent.
  88  * @dir_status: Direction of current transfer.
  89  * @tasklet: Tasklet running the request state machine.
  90  * @pending_events: Bitmask of events flagged by the interrupt handler
  91  *      to be processed by the tasklet.
  92  * @completed_events: Bitmask of events which the state machine has
  93  *      processed.
  94  * @state: Tasklet state.
  95  * @queue: List of slots waiting for access to the controller.
  96  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  97  *      rate and timeout calculations.
  98  * @current_speed: Configured rate of the controller.
  99  * @num_slots: Number of slots available.
 100  * @fifoth_val: The value of FIFOTH register.
 101  * @verid: Denote Version ID.
 102  * @dev: Device associated with the MMC controller.
 103  * @pdata: Platform data associated with the MMC controller.
 104  * @drv_data: Driver specific data for identified variant of the controller
 105  * @priv: Implementation defined private data.
 106  * @biu_clk: Pointer to bus interface unit clock instance.
 107  * @ciu_clk: Pointer to card interface unit clock instance.
 108  * @slot: Slots sharing this MMC controller.
 109  * @fifo_depth: depth of FIFO.
 110  * @data_shift: log2 of FIFO item size.
 111  * @part_buf_start: Start index in part_buf.
 112  * @part_buf_count: Bytes of partial data in part_buf.
 113  * @part_buf: Simple buffer for partial fifo reads/writes.
 114  * @push_data: Pointer to FIFO push function.
 115  * @pull_data: Pointer to FIFO pull function.
 116  * @quirks: Set of quirks that apply to specific versions of the IP.
 117  * @vqmmc_enabled: Status of vqmmc, should be true or false.
 118  * @irq_flags: The flags to be passed to request_irq.
 119  * @irq: The irq value to be passed to request_irq.
 120  * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
 121  * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
 122  * @dto_timer: Timer for broken data transfer over scheme.
 123  *
 124  * Locking
 125  * =======
 126  *
 127  * @lock is a softirq-safe spinlock protecting @queue as well as
 128  * @cur_slot, @mrq and @state. These must always be updated
 129  * at the same time while holding @lock.
 130  *
 131  * @irq_lock is an irq-safe spinlock protecting the INTMASK register
 132  * to allow the interrupt handler to modify it directly.  Held for only long
 133  * enough to read-modify-write INTMASK and no other locks are grabbed when
 134  * holding this one.
 135  *
 136  * The @mrq field of struct dw_mci_slot is also protected by @lock,
 137  * and must always be written at the same time as the slot is added to
 138  * @queue.
 139  *
 140  * @pending_events and @completed_events are accessed using atomic bit
 141  * operations, so they don't need any locking.
 142  *
 143  * None of the fields touched by the interrupt handler need any
 144  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 145  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 146  * interrupts must be disabled and @data_status updated with a
 147  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 148  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 149  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 150  * bytes_xfered field of @data must be written. This is ensured by
 151  * using barriers.
 152  */
 153 struct dw_mci {
 154         spinlock_t              lock;
 155         spinlock_t              irq_lock;
 156         void __iomem            *regs;
 157         void __iomem            *fifo_reg;
 158
 159         struct scatterlist      *sg;
 160         struct sg_mapping_iter  sg_miter;
 161
 162         struct dw_mci_slot      *cur_slot;
 163         struct mmc_request      *mrq;
 164         struct mmc_command      *cmd;
 165         struct mmc_data         *data;
 166         struct mmc_command      stop_abort;
 167         unsigned int            prev_blksz;
 168         unsigned char           timing;
 169
 170         /* DMA interface members*/
 171         int                     use_dma;
 172         int                     using_dma;
 173         int                     dma_64bit_address;
 174
 175         dma_addr_t              sg_dma;
 176         void                    *sg_cpu;
 177         const struct dw_mci_dma_ops     *dma_ops;
 178         /* For idmac */
 179         unsigned int            ring_size;
 180
 181         /* For edmac */
 182         struct dw_mci_dma_slave *dms;
 183         /* Registers's physical base address */
 184         resource_size_t         phy_regs;
 185
 186         u32                     cmd_status;
 187         u32                     data_status;
 188         u32                     stop_cmdr;
 189         u32                     dir_status;
 190         struct tasklet_struct   tasklet;
 191         unsigned long           pending_events;
 192         unsigned long           completed_events;
 193         enum dw_mci_state       state;
 194         struct list_head        queue;
 195
 196         u32                     bus_hz;
 197         u32                     current_speed;
 198         u32                     num_slots;
 199         u32                     fifoth_val;
 200         u16                     verid;
 201         struct device           *dev;
 202         struct dw_mci_board     *pdata;
 203         const struct dw_mci_drv_data    *drv_data;
 204         void                    *priv;
 205         struct clk              *biu_clk;
 206         struct clk              *ciu_clk;
 207         struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
 208
 209         /* FIFO push and pull */
 210         int                     fifo_depth;
 211         int                     data_shift;
 212         u8                      part_buf_start;
 213         u8                      part_buf_count;
 214         union {
 215                 u16             part_buf16;
 216                 u32             part_buf32;
 217                 u64             part_buf;
 218         };
 219         void (*push_data)(struct dw_mci *host, void *buf, int cnt);
 220         void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
 221
 222         /* Workaround flags */
 223         u32                     quirks;
 224
 225         bool                    vqmmc_enabled;
 226         unsigned long           irq_flags; /* IRQ flags */
 227         int                     irq;
 228
 229         int                     sdio_id0;
 230
 231         struct timer_list       cmd11_timer;
 232         struct timer_list       dto_timer;
 233 };
 234
 235 /* DMA ops for Internal/External DMAC interface */
 236 struct dw_mci_dma_ops {
 237         /* DMA Ops */
 238         int (*init)(struct dw_mci *host);
 239         int (*start)(struct dw_mci *host, unsigned int sg_len);
 240         void (*complete)(void *host);
 241         void (*stop)(struct dw_mci *host);
 242         void (*cleanup)(struct dw_mci *host);
 243         void (*exit)(struct dw_mci *host);
 244 };
 245
 246 /* IP Quirks/flags. */
 247 /* Timer for broken data transfer over scheme */
 248 #define DW_MCI_QUIRK_BROKEN_DTO                 BIT(0)
 249
 250 struct dma_pdata;
 251
 252 /* Board platform data */
 253 struct dw_mci_board {
 254         u32 num_slots;
 255
 256         u32 quirks; /* Workaround / Quirk flags */
 257         unsigned int bus_hz; /* Clock speed at the cclk_in pad */
 258
 259         u32 caps;       /* Capabilities */
 260         u32 caps2;      /* More capabilities */
 261         u32 pm_caps;    /* PM capabilities */
 262         /*
 263          * Override fifo depth. If 0, autodetect it from the FIFOTH register,
 264          * but note that this may not be reliable after a bootloader has used
 265          * it.
 266          */
 267         unsigned int fifo_depth;
 268
 269         /* delay in mS before detecting cards after interrupt */
 270         u32 detect_delay_ms;
 271
 272         struct dw_mci_dma_ops *dma_ops;
 273         struct dma_pdata *data;
 274 };
 275
 276 #endif /* LINUX_MMC_DW_MMC_H */