include/linux/mmc/sh_mmcif.h

   1 /*
   2  * include/linux/mmc/sh_mmcif.h
   3  *
   4  * platform data for eMMC driver
   5  *
   6  * Copyright (C) 2010 Renesas Solutions Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  *
  12  */
  13
  14 #ifndef __SH_MMCIF_H__
  15 #define __SH_MMCIF_H__
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19
  20 /*
  21  * MMCIF : CE_CLK_CTRL [19:16]
  22  * 1000 : Peripheral clock / 512
  23  * 0111 : Peripheral clock / 256
  24  * 0110 : Peripheral clock / 128
  25  * 0101 : Peripheral clock / 64
  26  * 0100 : Peripheral clock / 32
  27  * 0011 : Peripheral clock / 16
  28  * 0010 : Peripheral clock / 8
  29  * 0001 : Peripheral clock / 4
  30  * 0000 : Peripheral clock / 2
  31  * 1111 : Peripheral clock (sup_pclk set '1')
  32  */
  33
  34 struct sh_mmcif_plat_data {
  35         void (*set_pwr)(struct platform_device *pdev, int state);
  36         void (*down_pwr)(struct platform_device *pdev);
  37         int (*get_cd)(struct platform_device *pdef);
  38         u8      sup_pclk;       /* 1 :SH7757, 0: SH7724/SH7372 */
  39         unsigned long caps;
  40         u32     ocr;
  41 };
  42
  43 #define MMCIF_CE_CMD_SET        0x00000000
  44 #define MMCIF_CE_ARG            0x00000008
  45 #define MMCIF_CE_ARG_CMD12      0x0000000C
  46 #define MMCIF_CE_CMD_CTRL       0x00000010
  47 #define MMCIF_CE_BLOCK_SET      0x00000014
  48 #define MMCIF_CE_CLK_CTRL       0x00000018
  49 #define MMCIF_CE_BUF_ACC        0x0000001C
  50 #define MMCIF_CE_RESP3          0x00000020
  51 #define MMCIF_CE_RESP2          0x00000024
  52 #define MMCIF_CE_RESP1          0x00000028
  53 #define MMCIF_CE_RESP0          0x0000002C
  54 #define MMCIF_CE_RESP_CMD12     0x00000030
  55 #define MMCIF_CE_DATA           0x00000034
  56 #define MMCIF_CE_INT            0x00000040
  57 #define MMCIF_CE_INT_MASK       0x00000044
  58 #define MMCIF_CE_HOST_STS1      0x00000048
  59 #define MMCIF_CE_HOST_STS2      0x0000004C
  60 #define MMCIF_CE_VERSION        0x0000007C
  61
  62 extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
  63 {
  64         return readl(addr + reg);
  65 }
  66
  67 extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
  68 {
  69         writel(val, addr + reg);
  70 }
  71
  72 #define SH_MMCIF_BBS 512 /* boot block size */
  73
  74 extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
  75                                           unsigned long cmd, unsigned long arg)
  76 {
  77         sh_mmcif_writel(base, MMCIF_CE_INT, 0);
  78         sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
  79         sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
  80 }
  81
  82 extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
  83 {
  84         unsigned long tmp;
  85         int cnt;
  86
  87         for (cnt = 0; cnt < 1000000; cnt++) {
  88                 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
  89                 if (tmp & mask) {
  90                         sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
  91                         return 0;
  92                 }
  93         }
  94
  95         return -1;
  96 }
  97
  98 extern inline int sh_mmcif_boot_cmd(void __iomem *base,
  99                                     unsigned long cmd, unsigned long arg)
 100 {
 101         sh_mmcif_boot_cmd_send(base, cmd, arg);
 102         return sh_mmcif_boot_cmd_poll(base, 0x00010000);
 103 }
 104
 105 extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
 106                                                unsigned int block_nr,
 107                                                unsigned long *buf)
 108 {
 109         int k;
 110
 111         /* CMD13 - Status */
 112         sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
 113
 114         if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
 115                 return -1;
 116
 117         /* CMD17 - Read */
 118         sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
 119         if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
 120                 return -1;
 121
 122         for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
 123                 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
 124
 125         return 0;
 126 }
 127
 128 extern inline int sh_mmcif_boot_do_read(void __iomem *base,
 129                                         unsigned long first_block,
 130                                         unsigned long nr_blocks,
 131                                         void *buf)
 132 {
 133         unsigned long k;
 134         int ret = 0;
 135
 136         /* CMD16 - Set the block size */
 137         sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
 138
 139         for (k = 0; !ret && k < nr_blocks; k++)
 140                 ret = sh_mmcif_boot_do_read_single(base, first_block + k,
 141                                                    buf + (k * SH_MMCIF_BBS));
 142
 143         return ret;
 144 }
 145
 146 extern inline void sh_mmcif_boot_init(void __iomem *base)
 147 {
 148         unsigned long tmp;
 149
 150         /* reset */
 151         tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
 152         sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
 153         sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
 154
 155         /* byte swap */
 156         sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
 157
 158         /* Set block size in MMCIF hardware */
 159         sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
 160
 161         /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
 162         sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
 163
 164         /* CMD0 */
 165         sh_mmcif_boot_cmd(base, 0x00000040, 0);
 166
 167         /* CMD1 - Get OCR */
 168         do {
 169                 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
 170         } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
 171                  != 0x80000000);
 172
 173         /* CMD2 - Get CID */
 174         sh_mmcif_boot_cmd(base, 0x02806040, 0);
 175
 176         /* CMD3 - Set card relative address */
 177         sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
 178 }
 179
 180 extern inline void sh_mmcif_boot_slurp(void __iomem *base,
 181                                        unsigned char *buf,
 182                                        unsigned long no_bytes)
 183 {
 184         unsigned long tmp;
 185
 186         /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
 187         sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
 188
 189         /* CMD9 - Get CSD */
 190         sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
 191
 192         /* CMD7 - Select the card */
 193         sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
 194
 195         tmp = no_bytes / SH_MMCIF_BBS;
 196         tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
 197
 198         sh_mmcif_boot_do_read(base, 512, tmp, buf);
 199 }
 200
 201 #endif /* __SH_MMCIF_H__ */