include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31 /*
  32  * Separate phases of nand_scan(), allowing board driver to intervene
  33  * and override command or ECC setup according to flash type.
  34  */
  35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                            struct nand_flash_dev *table);
  37 extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39 /* Free resources held by the NAND device */
  40 extern void nand_release(struct mtd_info *mtd);
  41
  42 /* Internal helper for board drivers which need to override command function */
  43 extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45 /* locks all blocks present in the device */
  46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48 /* unlocks specified locked blocks */
  49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51 /* The maximum number of NAND chips in an array */
  52 #define NAND_MAX_CHIPS          8
  53
  54 /*
  55  * This constant declares the max. oobsize / page, which
  56  * is supported now. If you add a chip with bigger oobsize/page
  57  * adjust this accordingly.
  58  */
  59 #define NAND_MAX_OOBSIZE        640
  60 #define NAND_MAX_PAGESIZE       8192
  61
  62 /*
  63  * Constants for hardware specific CLE/ALE/NCE function
  64  *
  65  * These are bits which can be or'ed to set/clear multiple
  66  * bits in one go.
  67  */
  68 /* Select the chip by setting nCE to low */
  69 #define NAND_NCE                0x01
  70 /* Select the command latch by setting CLE to high */
  71 #define NAND_CLE                0x02
  72 /* Select the address latch by setting ALE to high */
  73 #define NAND_ALE                0x04
  74
  75 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77 #define NAND_CTRL_CHANGE        0x80
  78
  79 /*
  80  * Standard NAND flash commands
  81  */
  82 #define NAND_CMD_READ0          0
  83 #define NAND_CMD_READ1          1
  84 #define NAND_CMD_RNDOUT         5
  85 #define NAND_CMD_PAGEPROG       0x10
  86 #define NAND_CMD_READOOB        0x50
  87 #define NAND_CMD_ERASE1         0x60
  88 #define NAND_CMD_STATUS         0x70
  89 #define NAND_CMD_STATUS_MULTI   0x71
  90 #define NAND_CMD_SEQIN          0x80
  91 #define NAND_CMD_RNDIN          0x85
  92 #define NAND_CMD_READID         0x90
  93 #define NAND_CMD_ERASE2         0xd0
  94 #define NAND_CMD_PARAM          0xec
  95 #define NAND_CMD_GET_FEATURES   0xee
  96 #define NAND_CMD_SET_FEATURES   0xef
  97 #define NAND_CMD_RESET          0xff
  98
  99 #define NAND_CMD_LOCK           0x2a
 100 #define NAND_CMD_UNLOCK1        0x23
 101 #define NAND_CMD_UNLOCK2        0x24
 102
 103 /* Extended commands for large page devices */
 104 #define NAND_CMD_READSTART      0x30
 105 #define NAND_CMD_RNDOUTSTART    0xE0
 106 #define NAND_CMD_CACHEDPROG     0x15
 107
 108 /* Extended commands for AG-AND device */
 109 /*
 110  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 111  *       there is no way to distinguish that from NAND_CMD_READ0
 112  *       until the remaining sequence of commands has been completed
 113  *       so add a high order bit and mask it off in the command.
 114  */
 115 #define NAND_CMD_DEPLETE1       0x100
 116 #define NAND_CMD_DEPLETE2       0x38
 117 #define NAND_CMD_STATUS_MULTI   0x71
 118 #define NAND_CMD_STATUS_ERROR   0x72
 119 /* multi-bank error status (banks 0-3) */
 120 #define NAND_CMD_STATUS_ERROR0  0x73
 121 #define NAND_CMD_STATUS_ERROR1  0x74
 122 #define NAND_CMD_STATUS_ERROR2  0x75
 123 #define NAND_CMD_STATUS_ERROR3  0x76
 124 #define NAND_CMD_STATUS_RESET   0x7f
 125 #define NAND_CMD_STATUS_CLEAR   0xff
 126
 127 #define NAND_CMD_NONE           -1
 128
 129 /* Status bits */
 130 #define NAND_STATUS_FAIL        0x01
 131 #define NAND_STATUS_FAIL_N1     0x02
 132 #define NAND_STATUS_TRUE_READY  0x20
 133 #define NAND_STATUS_READY       0x40
 134 #define NAND_STATUS_WP          0x80
 135
 136 /*
 137  * Constants for ECC_MODES
 138  */
 139 typedef enum {
 140         NAND_ECC_NONE,
 141         NAND_ECC_SOFT,
 142         NAND_ECC_HW,
 143         NAND_ECC_HW_SYNDROME,
 144         NAND_ECC_HW_OOB_FIRST,
 145         NAND_ECC_SOFT_BCH,
 146 } nand_ecc_modes_t;
 147
 148 /*
 149  * Constants for Hardware ECC
 150  */
 151 /* Reset Hardware ECC for read */
 152 #define NAND_ECC_READ           0
 153 /* Reset Hardware ECC for write */
 154 #define NAND_ECC_WRITE          1
 155 /* Enable Hardware ECC before syndrome is read back from flash */
 156 #define NAND_ECC_READSYN        2
 157
 158 /* Bit mask for flags passed to do_nand_read_ecc */
 159 #define NAND_GET_DEVICE         0x80
 160
 161
 162 /*
 163  * Option constants for bizarre disfunctionality and real
 164  * features.
 165  */
 166 /* Buswidth is 16 bit */
 167 #define NAND_BUSWIDTH_16        0x00000002
 168 /* Device supports partial programming without padding */
 169 #define NAND_NO_PADDING         0x00000004
 170 /* Chip has cache program function */
 171 #define NAND_CACHEPRG           0x00000008
 172 /* Chip has copy back function */
 173 #define NAND_COPYBACK           0x00000010
 174 /*
 175  * AND Chip which has 4 banks and a confusing page / block
 176  * assignment. See Renesas datasheet for further information.
 177  */
 178 #define NAND_IS_AND             0x00000020
 179 /*
 180  * Chip has a array of 4 pages which can be read without
 181  * additional ready /busy waits.
 182  */
 183 #define NAND_4PAGE_ARRAY        0x00000040
 184 /*
 185  * Chip requires that BBT is periodically rewritten to prevent
 186  * bits from adjacent blocks from 'leaking' in altering data.
 187  * This happens with the Renesas AG-AND chips, possibly others.
 188  */
 189 #define BBT_AUTO_REFRESH        0x00000080
 190 /* Chip does not allow subpage writes */
 191 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 192
 193 /* Device is one of 'new' xD cards that expose fake nand command set */
 194 #define NAND_BROKEN_XD          0x00000400
 195
 196 /* Device behaves just like nand, but is readonly */
 197 #define NAND_ROM                0x00000800
 198
 199 /* Device supports subpage reads */
 200 #define NAND_SUBPAGE_READ       0x00001000
 201
 202 /* Options valid for Samsung large page devices */
 203 #define NAND_SAMSUNG_LP_OPTIONS \
 204         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 205
 206 /* Macros to identify the above */
 207 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 208 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 209 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 210 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 211
 212 /* Non chip related options */
 213 /* This option skips the bbt scan during initialization. */
 214 #define NAND_SKIP_BBTSCAN       0x00010000
 215 /*
 216  * This option is defined if the board driver allocates its own buffers
 217  * (e.g. because it needs them DMA-coherent).
 218  */
 219 #define NAND_OWN_BUFFERS        0x00020000
 220 /* Chip may not exist, so silence any errors in scan */
 221 #define NAND_SCAN_SILENT_NODEV  0x00040000
 222
 223 /* Options set by nand scan */
 224 /* Nand scan has allocated controller struct */
 225 #define NAND_CONTROLLER_ALLOC   0x80000000
 226
 227 /* Cell info constants */
 228 #define NAND_CI_CHIPNR_MSK      0x03
 229 #define NAND_CI_CELLTYPE_MSK    0x0C
 230
 231 /* Keep gcc happy */
 232 struct nand_chip;
 233
 234 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 235 #define ONFI_TIMING_MODE_0              (1 << 0)
 236 #define ONFI_TIMING_MODE_1              (1 << 1)
 237 #define ONFI_TIMING_MODE_2              (1 << 2)
 238 #define ONFI_TIMING_MODE_3              (1 << 3)
 239 #define ONFI_TIMING_MODE_4              (1 << 4)
 240 #define ONFI_TIMING_MODE_5              (1 << 5)
 241 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 242
 243 /* ONFI feature address */
 244 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 245
 246 /* ONFI subfeature parameters length */
 247 #define ONFI_SUBFEATURE_PARAM_LEN       4
 248
 249 struct nand_onfi_params {
 250         /* rev info and features block */
 251         /* 'O' 'N' 'F' 'I'  */
 252         u8 sig[4];
 253         __le16 revision;
 254         __le16 features;
 255         __le16 opt_cmd;
 256         u8 reserved[22];
 257
 258         /* manufacturer information block */
 259         char manufacturer[12];
 260         char model[20];
 261         u8 jedec_id;
 262         __le16 date_code;
 263         u8 reserved2[13];
 264
 265         /* memory organization block */
 266         __le32 byte_per_page;
 267         __le16 spare_bytes_per_page;
 268         __le32 data_bytes_per_ppage;
 269         __le16 spare_bytes_per_ppage;
 270         __le32 pages_per_block;
 271         __le32 blocks_per_lun;
 272         u8 lun_count;
 273         u8 addr_cycles;
 274         u8 bits_per_cell;
 275         __le16 bb_per_lun;
 276         __le16 block_endurance;
 277         u8 guaranteed_good_blocks;
 278         __le16 guaranteed_block_endurance;
 279         u8 programs_per_page;
 280         u8 ppage_attr;
 281         u8 ecc_bits;
 282         u8 interleaved_bits;
 283         u8 interleaved_ops;
 284         u8 reserved3[13];
 285
 286         /* electrical parameter block */
 287         u8 io_pin_capacitance_max;
 288         __le16 async_timing_mode;
 289         __le16 program_cache_timing_mode;
 290         __le16 t_prog;
 291         __le16 t_bers;
 292         __le16 t_r;
 293         __le16 t_ccs;
 294         __le16 src_sync_timing_mode;
 295         __le16 src_ssync_features;
 296         __le16 clk_pin_capacitance_typ;
 297         __le16 io_pin_capacitance_typ;
 298         __le16 input_pin_capacitance_typ;
 299         u8 input_pin_capacitance_max;
 300         u8 driver_strenght_support;
 301         __le16 t_int_r;
 302         __le16 t_ald;
 303         u8 reserved4[7];
 304
 305         /* vendor */
 306         u8 reserved5[90];
 307
 308         __le16 crc;
 309 } __attribute__((packed));
 310
 311 #define ONFI_CRC_BASE   0x4F4E
 312
 313 /**
 314  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 315  * @lock:               protection lock
 316  * @active:             the mtd device which holds the controller currently
 317  * @wq:                 wait queue to sleep on if a NAND operation is in
 318  *                      progress used instead of the per chip wait queue
 319  *                      when a hw controller is available.
 320  */
 321 struct nand_hw_control {
 322         spinlock_t lock;
 323         struct nand_chip *active;
 324         wait_queue_head_t wq;
 325 };
 326
 327 /**
 328  * struct nand_ecc_ctrl - Control structure for ECC
 329  * @mode:       ECC mode
 330  * @steps:      number of ECC steps per page
 331  * @size:       data bytes per ECC step
 332  * @bytes:      ECC bytes per step
 333  * @strength:   max number of correctible bits per ECC step
 334  * @total:      total number of ECC bytes per page
 335  * @prepad:     padding information for syndrome based ECC generators
 336  * @postpad:    padding information for syndrome based ECC generators
 337  * @layout:     ECC layout control struct pointer
 338  * @priv:       pointer to private ECC control data
 339  * @hwctl:      function to control hardware ECC generator. Must only
 340  *              be provided if an hardware ECC is available
 341  * @calculate:  function for ECC calculation or readback from ECC hardware
 342  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 343  * @read_page_raw:      function to read a raw page without ECC
 344  * @write_page_raw:     function to write a raw page without ECC
 345  * @read_page:  function to read a page according to the ECC generator
 346  *              requirements; returns maximum number of bitflips corrected in
 347  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 348  * @read_subpage:       function to read parts of the page covered by ECC;
 349  *                      returns same as read_page()
 350  * @write_page: function to write a page according to the ECC generator
 351  *              requirements.
 352  * @write_oob_raw:      function to write chip OOB data without ECC
 353  * @read_oob_raw:       function to read chip OOB data without ECC
 354  * @read_oob:   function to read chip OOB data
 355  * @write_oob:  function to write chip OOB data
 356  */
 357 struct nand_ecc_ctrl {
 358         nand_ecc_modes_t mode;
 359         int steps;
 360         int size;
 361         int bytes;
 362         int total;
 363         int strength;
 364         int prepad;
 365         int postpad;
 366         struct nand_ecclayout   *layout;
 367         void *priv;
 368         void (*hwctl)(struct mtd_info *mtd, int mode);
 369         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 370                         uint8_t *ecc_code);
 371         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 372                         uint8_t *calc_ecc);
 373         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 374                         uint8_t *buf, int oob_required, int page);
 375         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 376                         const uint8_t *buf, int oob_required);
 377         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 378                         uint8_t *buf, int oob_required, int page);
 379         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 380                         uint32_t offs, uint32_t len, uint8_t *buf);
 381         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 382                         const uint8_t *buf, int oob_required);
 383         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 384                         int page);
 385         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 386                         int page);
 387         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 388         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 389                         int page);
 390 };
 391
 392 /**
 393  * struct nand_buffers - buffer structure for read/write
 394  * @ecccalc:    buffer for calculated ECC
 395  * @ecccode:    buffer for ECC read from flash
 396  * @databuf:    buffer for data - dynamically sized
 397  *
 398  * Do not change the order of buffers. databuf and oobrbuf must be in
 399  * consecutive order.
 400  */
 401 struct nand_buffers {
 402         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 403         uint8_t ecccode[NAND_MAX_OOBSIZE];
 404         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 405 };
 406
 407 /**
 408  * struct nand_chip - NAND Private Flash Chip Data
 409  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 410  *                      flash device
 411  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 412  *                      flash device.
 413  * @read_byte:          [REPLACEABLE] read one byte from the chip
 414  * @read_word:          [REPLACEABLE] read one word from the chip
 415  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 416  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 417  * @select_chip:        [REPLACEABLE] select chip nr
 418  * @block_bad:          [REPLACEABLE] check, if the block is bad
 419  * @block_markbad:      [REPLACEABLE] mark the block bad
 420  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 421  *                      ALE/CLE/nCE. Also used to write command and address
 422  * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 423  *                      mtd->oobsize, mtd->writesize and so on.
 424  *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 425  *                      Return with the bus width.
 426  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 427  *                      device ready/busy line. If set to NULL no access to
 428  *                      ready/busy is available and the ready/busy information
 429  *                      is read from the chip status register.
 430  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 431  *                      commands to the chip.
 432  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 433  *                      ready.
 434  * @ecc:                [BOARDSPECIFIC] ECC control structure
 435  * @buffers:            buffer structure for read/write
 436  * @hwcontrol:          platform-specific hardware control structure
 437  * @erase_cmd:          [INTERN] erase command write function, selectable due
 438  *                      to AND support.
 439  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 440  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 441  *                      data from array to read regs (tR).
 442  * @state:              [INTERN] the current state of the NAND device
 443  * @oob_poi:            "poison value buffer," used for laying out OOB data
 444  *                      before writing
 445  * @page_shift:         [INTERN] number of address bits in a page (column
 446  *                      address bits).
 447  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 448  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 449  * @chip_shift:         [INTERN] number of address bits in one chip
 450  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 451  *                      be set to inform nand_scan about special functionality.
 452  *                      See the defines for further explanation.
 453  * @bbt_options:        [INTERN] bad block specific options. All options used
 454  *                      here must come from bbm.h. By default, these options
 455  *                      will be copied to the appropriate nand_bbt_descr's.
 456  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 457  *                      area.
 458  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 459  *                      bad block marker position; i.e., BBM == 11110111b is
 460  *                      not bad when badblockbits == 7
 461  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 462  * @numchips:           [INTERN] number of physical chips
 463  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 464  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 465  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 466  *                      data_buf.
 467  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 468  *                      currently in data_buf.
 469  * @subpagesize:        [INTERN] holds the subpagesize
 470  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 471  *                      non 0 if ONFI supported.
 472  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 473  *                      supported, 0 otherwise.
 474  * @onfi_set_features   [REPLACEABLE] set the features for ONFI nand
 475  * @onfi_get_features   [REPLACEABLE] get the features for ONFI nand
 476  * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
 477  * @bbt:                [INTERN] bad block table pointer
 478  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 479  *                      lookup.
 480  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 481  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 482  *                      bad block scan.
 483  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 484  *                      structure which is shared among multiple independent
 485  *                      devices.
 486  * @priv:               [OPTIONAL] pointer to private chip data
 487  * @errstat:            [OPTIONAL] hardware specific function to perform
 488  *                      additional error status checks (determine if errors are
 489  *                      correctable).
 490  * @write_page:         [REPLACEABLE] High-level page write function
 491  */
 492
 493 struct nand_chip {
 494         void __iomem *IO_ADDR_R;
 495         void __iomem *IO_ADDR_W;
 496
 497         uint8_t (*read_byte)(struct mtd_info *mtd);
 498         u16 (*read_word)(struct mtd_info *mtd);
 499         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 500         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 501         void (*select_chip)(struct mtd_info *mtd, int chip);
 502         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 503         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 504         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 505         int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 506                         u8 *id_data);
 507         int (*dev_ready)(struct mtd_info *mtd);
 508         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 509                         int page_addr);
 510         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 511         void (*erase_cmd)(struct mtd_info *mtd, int page);
 512         int (*scan_bbt)(struct mtd_info *mtd);
 513         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 514                         int status, int page);
 515         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 516                         const uint8_t *buf, int oob_required, int page,
 517                         int cached, int raw);
 518         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 519                         int feature_addr, uint8_t *subfeature_para);
 520         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 521                         int feature_addr, uint8_t *subfeature_para);
 522
 523         int chip_delay;
 524         unsigned int options;
 525         unsigned int bbt_options;
 526
 527         int page_shift;
 528         int phys_erase_shift;
 529         int bbt_erase_shift;
 530         int chip_shift;
 531         int numchips;
 532         uint64_t chipsize;
 533         int pagemask;
 534         int pagebuf;
 535         unsigned int pagebuf_bitflips;
 536         int subpagesize;
 537         uint8_t cellinfo;
 538         int badblockpos;
 539         int badblockbits;
 540
 541         int onfi_version;
 542         struct nand_onfi_params onfi_params;
 543
 544         flstate_t state;
 545
 546         uint8_t *oob_poi;
 547         struct nand_hw_control *controller;
 548         struct nand_ecclayout *ecclayout;
 549
 550         struct nand_ecc_ctrl ecc;
 551         struct nand_buffers *buffers;
 552         struct nand_hw_control hwcontrol;
 553
 554         uint8_t *bbt;
 555         struct nand_bbt_descr *bbt_td;
 556         struct nand_bbt_descr *bbt_md;
 557
 558         struct nand_bbt_descr *badblock_pattern;
 559
 560         void *priv;
 561 };
 562
 563 /*
 564  * NAND Flash Manufacturer ID Codes
 565  */
 566 #define NAND_MFR_TOSHIBA        0x98
 567 #define NAND_MFR_SAMSUNG        0xec
 568 #define NAND_MFR_FUJITSU        0x04
 569 #define NAND_MFR_NATIONAL       0x8f
 570 #define NAND_MFR_RENESAS        0x07
 571 #define NAND_MFR_STMICRO        0x20
 572 #define NAND_MFR_HYNIX          0xad
 573 #define NAND_MFR_MICRON         0x2c
 574 #define NAND_MFR_AMD            0x01
 575 #define NAND_MFR_MACRONIX       0xc2
 576 #define NAND_MFR_EON            0x92
 577
 578 /**
 579  * struct nand_flash_dev - NAND Flash Device ID Structure
 580  * @name:       Identify the device type
 581  * @id:         device ID code
 582  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 583  *              If the pagesize is 0, then the real pagesize
 584  *              and the eraseize are determined from the
 585  *              extended id bytes in the chip
 586  * @erasesize:  Size of an erase block in the flash device.
 587  * @chipsize:   Total chipsize in Mega Bytes
 588  * @options:    Bitfield to store chip relevant options
 589  */
 590 struct nand_flash_dev {
 591         char *name;
 592         int id;
 593         unsigned long pagesize;
 594         unsigned long chipsize;
 595         unsigned long erasesize;
 596         unsigned long options;
 597 };
 598
 599 /**
 600  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 601  * @name:       Manufacturer name
 602  * @id:         manufacturer ID code of device.
 603 */
 604 struct nand_manufacturers {
 605         int id;
 606         char *name;
 607 };
 608
 609 extern struct nand_flash_dev nand_flash_ids[];
 610 extern struct nand_manufacturers nand_manuf_ids[];
 611
 612 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 613 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 614 extern int nand_default_bbt(struct mtd_info *mtd);
 615 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 616 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 617                            int allowbbt);
 618 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 619                         size_t *retlen, uint8_t *buf);
 620
 621 /**
 622  * struct platform_nand_chip - chip level device structure
 623  * @nr_chips:           max. number of chips to scan for
 624  * @chip_offset:        chip number offset
 625  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 626  * @partitions:         mtd partition list
 627  * @chip_delay:         R/B delay value in us
 628  * @options:            Option flags, e.g. 16bit buswidth
 629  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 630  * @ecclayout:          ECC layout info structure
 631  * @part_probe_types:   NULL-terminated array of probe types
 632  */
 633 struct platform_nand_chip {
 634         int nr_chips;
 635         int chip_offset;
 636         int nr_partitions;
 637         struct mtd_partition *partitions;
 638         struct nand_ecclayout *ecclayout;
 639         int chip_delay;
 640         unsigned int options;
 641         unsigned int bbt_options;
 642         const char **part_probe_types;
 643 };
 644
 645 /* Keep gcc happy */
 646 struct platform_device;
 647
 648 /**
 649  * struct platform_nand_ctrl - controller level device structure
 650  * @probe:              platform specific function to probe/setup hardware
 651  * @remove:             platform specific function to remove/teardown hardware
 652  * @hwcontrol:          platform specific hardware control structure
 653  * @dev_ready:          platform specific function to read ready/busy pin
 654  * @select_chip:        platform specific chip select function
 655  * @cmd_ctrl:           platform specific function for controlling
 656  *                      ALE/CLE/nCE. Also used to write command and address
 657  * @write_buf:          platform specific function for write buffer
 658  * @read_buf:           platform specific function for read buffer
 659  * @read_byte:          platform specific function to read one byte from chip
 660  * @priv:               private data to transport driver specific settings
 661  *
 662  * All fields are optional and depend on the hardware driver requirements
 663  */
 664 struct platform_nand_ctrl {
 665         int (*probe)(struct platform_device *pdev);
 666         void (*remove)(struct platform_device *pdev);
 667         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 668         int (*dev_ready)(struct mtd_info *mtd);
 669         void (*select_chip)(struct mtd_info *mtd, int chip);
 670         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 671         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 672         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 673         unsigned char (*read_byte)(struct mtd_info *mtd);
 674         void *priv;
 675 };
 676
 677 /**
 678  * struct platform_nand_data - container structure for platform-specific data
 679  * @chip:               chip level chip structure
 680  * @ctrl:               controller level device structure
 681  */
 682 struct platform_nand_data {
 683         struct platform_nand_chip chip;
 684         struct platform_nand_ctrl ctrl;
 685 };
 686
 687 /* Some helpers to access the data structures */
 688 static inline
 689 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 690 {
 691         struct nand_chip *chip = mtd->priv;
 692
 693         return chip->priv;
 694 }
 695
 696 /* return the supported asynchronous timing mode. */
 697 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 698 {
 699         if (!chip->onfi_version)
 700                 return ONFI_TIMING_MODE_UNKNOWN;
 701         return le16_to_cpu(chip->onfi_params.async_timing_mode);
 702 }
 703
 704 /* return the supported synchronous timing mode. */
 705 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 706 {
 707         if (!chip->onfi_version)
 708                 return ONFI_TIMING_MODE_UNKNOWN;
 709         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 710 }
 711
 712 #endif /* __LINUX_MTD_NAND_H */