2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev
;
29 /* Scan and identify a NAND device */
30 extern int nand_scan(struct mtd_info
*mtd
, int max_chips
);
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
35 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
,
36 struct nand_flash_dev
*table
);
37 extern int nand_scan_tail(struct mtd_info
*mtd
);
39 /* Free resources held by the NAND device */
40 extern void nand_release(struct mtd_info
*mtd
);
42 /* Internal helper for board drivers which need to override command function */
43 extern void nand_wait_ready(struct mtd_info
*mtd
);
45 /* locks all blocks present in the device */
46 extern int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
48 /* unlocks specified locked blocks */
49 extern int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
51 /* The maximum number of NAND chips in an array */
52 #define NAND_MAX_CHIPS 8
55 * This constant declares the max. oobsize / page, which
56 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
59 #define NAND_MAX_OOBSIZE 576
60 #define NAND_MAX_PAGESIZE 8192
63 * Constants for hardware specific CLE/ALE/NCE function
65 * These are bits which can be or'ed to set/clear multiple
68 /* Select the chip by setting nCE to low */
70 /* Select the command latch by setting CLE to high */
72 /* Select the address latch by setting ALE to high */
75 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77 #define NAND_CTRL_CHANGE 0x80
80 * Standard NAND flash commands
82 #define NAND_CMD_READ0 0
83 #define NAND_CMD_READ1 1
84 #define NAND_CMD_RNDOUT 5
85 #define NAND_CMD_PAGEPROG 0x10
86 #define NAND_CMD_READOOB 0x50
87 #define NAND_CMD_ERASE1 0x60
88 #define NAND_CMD_STATUS 0x70
89 #define NAND_CMD_STATUS_MULTI 0x71
90 #define NAND_CMD_SEQIN 0x80
91 #define NAND_CMD_RNDIN 0x85
92 #define NAND_CMD_READID 0x90
93 #define NAND_CMD_ERASE2 0xd0
94 #define NAND_CMD_PARAM 0xec
95 #define NAND_CMD_RESET 0xff
97 #define NAND_CMD_LOCK 0x2a
98 #define NAND_CMD_UNLOCK1 0x23
99 #define NAND_CMD_UNLOCK2 0x24
101 /* Extended commands for large page devices */
102 #define NAND_CMD_READSTART 0x30
103 #define NAND_CMD_RNDOUTSTART 0xE0
104 #define NAND_CMD_CACHEDPROG 0x15
106 /* Extended commands for AG-AND device */
108 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
109 * there is no way to distinguish that from NAND_CMD_READ0
110 * until the remaining sequence of commands has been completed
111 * so add a high order bit and mask it off in the command.
113 #define NAND_CMD_DEPLETE1 0x100
114 #define NAND_CMD_DEPLETE2 0x38
115 #define NAND_CMD_STATUS_MULTI 0x71
116 #define NAND_CMD_STATUS_ERROR 0x72
117 /* multi-bank error status (banks 0-3) */
118 #define NAND_CMD_STATUS_ERROR0 0x73
119 #define NAND_CMD_STATUS_ERROR1 0x74
120 #define NAND_CMD_STATUS_ERROR2 0x75
121 #define NAND_CMD_STATUS_ERROR3 0x76
122 #define NAND_CMD_STATUS_RESET 0x7f
123 #define NAND_CMD_STATUS_CLEAR 0xff
125 #define NAND_CMD_NONE -1
128 #define NAND_STATUS_FAIL 0x01
129 #define NAND_STATUS_FAIL_N1 0x02
130 #define NAND_STATUS_TRUE_READY 0x20
131 #define NAND_STATUS_READY 0x40
132 #define NAND_STATUS_WP 0x80
135 * Constants for ECC_MODES
141 NAND_ECC_HW_SYNDROME
,
142 NAND_ECC_HW_OOB_FIRST
,
147 * Constants for Hardware ECC
149 /* Reset Hardware ECC for read */
150 #define NAND_ECC_READ 0
151 /* Reset Hardware ECC for write */
152 #define NAND_ECC_WRITE 1
153 /* Enable Hardware ECC before syndrome is read back from flash */
154 #define NAND_ECC_READSYN 2
156 /* Bit mask for flags passed to do_nand_read_ecc */
157 #define NAND_GET_DEVICE 0x80
161 * Option constants for bizarre disfunctionality and real
164 /* Buswidth is 16 bit */
165 #define NAND_BUSWIDTH_16 0x00000002
166 /* Device supports partial programming without padding */
167 #define NAND_NO_PADDING 0x00000004
168 /* Chip has cache program function */
169 #define NAND_CACHEPRG 0x00000008
170 /* Chip has copy back function */
171 #define NAND_COPYBACK 0x00000010
173 * AND Chip which has 4 banks and a confusing page / block
174 * assignment. See Renesas datasheet for further information.
176 #define NAND_IS_AND 0x00000020
178 * Chip has a array of 4 pages which can be read without
179 * additional ready /busy waits.
181 #define NAND_4PAGE_ARRAY 0x00000040
183 * Chip requires that BBT is periodically rewritten to prevent
184 * bits from adjacent blocks from 'leaking' in altering data.
185 * This happens with the Renesas AG-AND chips, possibly others.
187 #define BBT_AUTO_REFRESH 0x00000080
188 /* Chip does not allow subpage writes */
189 #define NAND_NO_SUBPAGE_WRITE 0x00000200
191 /* Device is one of 'new' xD cards that expose fake nand command set */
192 #define NAND_BROKEN_XD 0x00000400
194 /* Device behaves just like nand, but is readonly */
195 #define NAND_ROM 0x00000800
197 /* Options valid for Samsung large page devices */
198 #define NAND_SAMSUNG_LP_OPTIONS \
199 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
201 /* Macros to identify the above */
202 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
203 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
204 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
205 /* Large page NAND with SOFT_ECC should support subpage reads */
206 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
207 && (chip->page_shift > 9))
209 /* Mask to zero out the chip options, which come from the id table */
210 #define NAND_CHIPOPTIONS_MSK 0x0000ffff
212 /* Non chip related options */
213 /* This option skips the bbt scan during initialization. */
214 #define NAND_SKIP_BBTSCAN 0x00010000
216 * This option is defined if the board driver allocates its own buffers
217 * (e.g. because it needs them DMA-coherent).
219 #define NAND_OWN_BUFFERS 0x00020000
220 /* Chip may not exist, so silence any errors in scan */
221 #define NAND_SCAN_SILENT_NODEV 0x00040000
223 /* Options set by nand scan */
224 /* Nand scan has allocated controller struct */
225 #define NAND_CONTROLLER_ALLOC 0x80000000
227 /* Cell info constants */
228 #define NAND_CI_CHIPNR_MSK 0x03
229 #define NAND_CI_CELLTYPE_MSK 0x0C
234 struct nand_onfi_params
{
235 /* rev info and features block */
236 /* 'O' 'N' 'F' 'I' */
243 /* manufacturer information block */
244 char manufacturer
[12];
250 /* memory organization block */
251 __le32 byte_per_page
;
252 __le16 spare_bytes_per_page
;
253 __le32 data_bytes_per_ppage
;
254 __le16 spare_bytes_per_ppage
;
255 __le32 pages_per_block
;
256 __le32 blocks_per_lun
;
261 __le16 block_endurance
;
262 u8 guaranteed_good_blocks
;
263 __le16 guaranteed_block_endurance
;
264 u8 programs_per_page
;
271 /* electrical parameter block */
272 u8 io_pin_capacitance_max
;
273 __le16 async_timing_mode
;
274 __le16 program_cache_timing_mode
;
279 __le16 src_sync_timing_mode
;
280 __le16 src_ssync_features
;
281 __le16 clk_pin_capacitance_typ
;
282 __le16 io_pin_capacitance_typ
;
283 __le16 input_pin_capacitance_typ
;
284 u8 input_pin_capacitance_max
;
285 u8 driver_strenght_support
;
294 } __attribute__((packed
));
296 #define ONFI_CRC_BASE 0x4F4E
299 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
300 * @lock: protection lock
301 * @active: the mtd device which holds the controller currently
302 * @wq: wait queue to sleep on if a NAND operation is in
303 * progress used instead of the per chip wait queue
304 * when a hw controller is available.
306 struct nand_hw_control
{
308 struct nand_chip
*active
;
309 wait_queue_head_t wq
;
313 * struct nand_ecc_ctrl - Control structure for ECC
315 * @steps: number of ECC steps per page
316 * @size: data bytes per ECC step
317 * @bytes: ECC bytes per step
318 * @strength: max number of correctible bits per ECC step
319 * @total: total number of ECC bytes per page
320 * @prepad: padding information for syndrome based ECC generators
321 * @postpad: padding information for syndrome based ECC generators
322 * @layout: ECC layout control struct pointer
323 * @priv: pointer to private ECC control data
324 * @hwctl: function to control hardware ECC generator. Must only
325 * be provided if an hardware ECC is available
326 * @calculate: function for ECC calculation or readback from ECC hardware
327 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
328 * @read_page_raw: function to read a raw page without ECC
329 * @write_page_raw: function to write a raw page without ECC
330 * @read_page: function to read a page according to the ECC generator
332 * @read_subpage: function to read parts of the page covered by ECC.
333 * @write_page: function to write a page according to the ECC generator
335 * @write_oob_raw: function to write chip OOB data without ECC
336 * @read_oob_raw: function to read chip OOB data without ECC
337 * @read_oob: function to read chip OOB data
338 * @write_oob: function to write chip OOB data
340 struct nand_ecc_ctrl
{
341 nand_ecc_modes_t mode
;
349 struct nand_ecclayout
*layout
;
351 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
352 int (*calculate
)(struct mtd_info
*mtd
, const uint8_t *dat
,
354 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
, uint8_t *read_ecc
,
356 int (*read_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
357 uint8_t *buf
, int oob_required
, int page
);
358 int (*write_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
359 const uint8_t *buf
, int oob_required
);
360 int (*read_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
361 uint8_t *buf
, int oob_required
, int page
);
362 int (*read_subpage
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
363 uint32_t offs
, uint32_t len
, uint8_t *buf
);
364 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
365 const uint8_t *buf
, int oob_required
);
366 int (*write_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
368 int (*read_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
370 int (*read_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
371 int (*write_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
376 * struct nand_buffers - buffer structure for read/write
377 * @ecccalc: buffer for calculated ECC
378 * @ecccode: buffer for ECC read from flash
379 * @databuf: buffer for data - dynamically sized
381 * Do not change the order of buffers. databuf and oobrbuf must be in
384 struct nand_buffers
{
385 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
386 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
387 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
391 * struct nand_chip - NAND Private Flash Chip Data
392 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
394 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
396 * @read_byte: [REPLACEABLE] read one byte from the chip
397 * @read_word: [REPLACEABLE] read one word from the chip
398 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
399 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
400 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip
402 * @select_chip: [REPLACEABLE] select chip nr
403 * @block_bad: [REPLACEABLE] check, if the block is bad
404 * @block_markbad: [REPLACEABLE] mark the block bad
405 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
406 * ALE/CLE/nCE. Also used to write command and address
407 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
408 * mtd->oobsize, mtd->writesize and so on.
409 * @id_data contains the 8 bytes values of NAND_CMD_READID.
410 * Return with the bus width.
411 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
412 * device ready/busy line. If set to NULL no access to
413 * ready/busy is available and the ready/busy information
414 * is read from the chip status register.
415 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
416 * commands to the chip.
417 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
419 * @ecc: [BOARDSPECIFIC] ECC control structure
420 * @buffers: buffer structure for read/write
421 * @hwcontrol: platform-specific hardware control structure
422 * @erase_cmd: [INTERN] erase command write function, selectable due
424 * @scan_bbt: [REPLACEABLE] function to scan bad block table
425 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
426 * data from array to read regs (tR).
427 * @state: [INTERN] the current state of the NAND device
428 * @oob_poi: "poison value buffer," used for laying out OOB data
430 * @page_shift: [INTERN] number of address bits in a page (column
432 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
433 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
434 * @chip_shift: [INTERN] number of address bits in one chip
435 * @options: [BOARDSPECIFIC] various chip options. They can partly
436 * be set to inform nand_scan about special functionality.
437 * See the defines for further explanation.
438 * @bbt_options: [INTERN] bad block specific options. All options used
439 * here must come from bbm.h. By default, these options
440 * will be copied to the appropriate nand_bbt_descr's.
441 * @badblockpos: [INTERN] position of the bad block marker in the oob
443 * @badblockbits: [INTERN] minimum number of set bits in a good block's
444 * bad block marker position; i.e., BBM == 11110111b is
445 * not bad when badblockbits == 7
446 * @cellinfo: [INTERN] MLC/multichip data from chip ident
447 * @numchips: [INTERN] number of physical chips
448 * @chipsize: [INTERN] the size of one chip for multichip arrays
449 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
450 * @pagebuf: [INTERN] holds the pagenumber which is currently in
452 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
453 * currently in data_buf.
454 * @subpagesize: [INTERN] holds the subpagesize
455 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
456 * non 0 if ONFI supported.
457 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
458 * supported, 0 otherwise.
459 * @ecclayout: [REPLACEABLE] the default ECC placement scheme
460 * @bbt: [INTERN] bad block table pointer
461 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
463 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
464 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
466 * @controller: [REPLACEABLE] a pointer to a hardware controller
467 * structure which is shared among multiple independent
469 * @priv: [OPTIONAL] pointer to private chip data
470 * @errstat: [OPTIONAL] hardware specific function to perform
471 * additional error status checks (determine if errors are
473 * @write_page: [REPLACEABLE] High-level page write function
477 void __iomem
*IO_ADDR_R
;
478 void __iomem
*IO_ADDR_W
;
480 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
481 u16 (*read_word
)(struct mtd_info
*mtd
);
482 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
483 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
484 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
485 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
486 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
487 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
488 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
489 int (*init_size
)(struct mtd_info
*mtd
, struct nand_chip
*this,
491 int (*dev_ready
)(struct mtd_info
*mtd
);
492 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
,
494 int(*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
495 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
496 int (*scan_bbt
)(struct mtd_info
*mtd
);
497 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
,
498 int status
, int page
);
499 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
500 const uint8_t *buf
, int oob_required
, int page
,
501 int cached
, int raw
);
504 unsigned int options
;
505 unsigned int bbt_options
;
508 int phys_erase_shift
;
515 unsigned int pagebuf_bitflips
;
522 struct nand_onfi_params onfi_params
;
527 struct nand_hw_control
*controller
;
528 struct nand_ecclayout
*ecclayout
;
530 struct nand_ecc_ctrl ecc
;
531 struct nand_buffers
*buffers
;
532 struct nand_hw_control hwcontrol
;
535 struct nand_bbt_descr
*bbt_td
;
536 struct nand_bbt_descr
*bbt_md
;
538 struct nand_bbt_descr
*badblock_pattern
;
544 * NAND Flash Manufacturer ID Codes
546 #define NAND_MFR_TOSHIBA 0x98
547 #define NAND_MFR_SAMSUNG 0xec
548 #define NAND_MFR_FUJITSU 0x04
549 #define NAND_MFR_NATIONAL 0x8f
550 #define NAND_MFR_RENESAS 0x07
551 #define NAND_MFR_STMICRO 0x20
552 #define NAND_MFR_HYNIX 0xad
553 #define NAND_MFR_MICRON 0x2c
554 #define NAND_MFR_AMD 0x01
555 #define NAND_MFR_MACRONIX 0xc2
556 #define NAND_MFR_EON 0x92
559 * struct nand_flash_dev - NAND Flash Device ID Structure
560 * @name: Identify the device type
561 * @id: device ID code
562 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
563 * If the pagesize is 0, then the real pagesize
564 * and the eraseize are determined from the
565 * extended id bytes in the chip
566 * @erasesize: Size of an erase block in the flash device.
567 * @chipsize: Total chipsize in Mega Bytes
568 * @options: Bitfield to store chip relevant options
570 struct nand_flash_dev
{
573 unsigned long pagesize
;
574 unsigned long chipsize
;
575 unsigned long erasesize
;
576 unsigned long options
;
580 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
581 * @name: Manufacturer name
582 * @id: manufacturer ID code of device.
584 struct nand_manufacturers
{
589 extern struct nand_flash_dev nand_flash_ids
[];
590 extern struct nand_manufacturers nand_manuf_ids
[];
592 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
593 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
594 extern int nand_default_bbt(struct mtd_info
*mtd
);
595 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
596 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
598 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
599 size_t *retlen
, uint8_t *buf
);
602 * struct platform_nand_chip - chip level device structure
603 * @nr_chips: max. number of chips to scan for
604 * @chip_offset: chip number offset
605 * @nr_partitions: number of partitions pointed to by partitions (or zero)
606 * @partitions: mtd partition list
607 * @chip_delay: R/B delay value in us
608 * @options: Option flags, e.g. 16bit buswidth
609 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
610 * @ecclayout: ECC layout info structure
611 * @part_probe_types: NULL-terminated array of probe types
613 struct platform_nand_chip
{
617 struct mtd_partition
*partitions
;
618 struct nand_ecclayout
*ecclayout
;
620 unsigned int options
;
621 unsigned int bbt_options
;
622 const char **part_probe_types
;
626 struct platform_device
;
629 * struct platform_nand_ctrl - controller level device structure
630 * @probe: platform specific function to probe/setup hardware
631 * @remove: platform specific function to remove/teardown hardware
632 * @hwcontrol: platform specific hardware control structure
633 * @dev_ready: platform specific function to read ready/busy pin
634 * @select_chip: platform specific chip select function
635 * @cmd_ctrl: platform specific function for controlling
636 * ALE/CLE/nCE. Also used to write command and address
637 * @write_buf: platform specific function for write buffer
638 * @read_buf: platform specific function for read buffer
639 * @priv: private data to transport driver specific settings
641 * All fields are optional and depend on the hardware driver requirements
643 struct platform_nand_ctrl
{
644 int (*probe
)(struct platform_device
*pdev
);
645 void (*remove
)(struct platform_device
*pdev
);
646 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
647 int (*dev_ready
)(struct mtd_info
*mtd
);
648 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
649 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
650 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
651 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
652 unsigned char (*read_byte
)(struct mtd_info
*mtd
);
657 * struct platform_nand_data - container structure for platform-specific data
658 * @chip: chip level chip structure
659 * @ctrl: controller level device structure
661 struct platform_nand_data
{
662 struct platform_nand_chip chip
;
663 struct platform_nand_ctrl ctrl
;
666 /* Some helpers to access the data structures */
668 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
670 struct nand_chip
*chip
= mtd
->priv
;
675 #endif /* __LINUX_MTD_NAND_H */