include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31 /*
  32  * Separate phases of nand_scan(), allowing board driver to intervene
  33  * and override command or ECC setup according to flash type.
  34  */
  35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                            struct nand_flash_dev *table);
  37 extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39 /* Free resources held by the NAND device */
  40 extern void nand_release(struct mtd_info *mtd);
  41
  42 /* Internal helper for board drivers which need to override command function */
  43 extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45 /* locks all blocks present in the device */
  46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48 /* unlocks specified locked blocks */
  49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51 /* The maximum number of NAND chips in an array */
  52 #define NAND_MAX_CHIPS          8
  53
  54 /*
  55  * This constant declares the max. oobsize / page, which
  56  * is supported now. If you add a chip with bigger oobsize/page
  57  * adjust this accordingly.
  58  */
  59 #define NAND_MAX_OOBSIZE        744
  60 #define NAND_MAX_PAGESIZE       8192
  61
  62 /*
  63  * Constants for hardware specific CLE/ALE/NCE function
  64  *
  65  * These are bits which can be or'ed to set/clear multiple
  66  * bits in one go.
  67  */
  68 /* Select the chip by setting nCE to low */
  69 #define NAND_NCE                0x01
  70 /* Select the command latch by setting CLE to high */
  71 #define NAND_CLE                0x02
  72 /* Select the address latch by setting ALE to high */
  73 #define NAND_ALE                0x04
  74
  75 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77 #define NAND_CTRL_CHANGE        0x80
  78
  79 /*
  80  * Standard NAND flash commands
  81  */
  82 #define NAND_CMD_READ0          0
  83 #define NAND_CMD_READ1          1
  84 #define NAND_CMD_RNDOUT         5
  85 #define NAND_CMD_PAGEPROG       0x10
  86 #define NAND_CMD_READOOB        0x50
  87 #define NAND_CMD_ERASE1         0x60
  88 #define NAND_CMD_STATUS         0x70
  89 #define NAND_CMD_SEQIN          0x80
  90 #define NAND_CMD_RNDIN          0x85
  91 #define NAND_CMD_READID         0x90
  92 #define NAND_CMD_ERASE2         0xd0
  93 #define NAND_CMD_PARAM          0xec
  94 #define NAND_CMD_GET_FEATURES   0xee
  95 #define NAND_CMD_SET_FEATURES   0xef
  96 #define NAND_CMD_RESET          0xff
  97
  98 #define NAND_CMD_LOCK           0x2a
  99 #define NAND_CMD_UNLOCK1        0x23
 100 #define NAND_CMD_UNLOCK2        0x24
 101
 102 /* Extended commands for large page devices */
 103 #define NAND_CMD_READSTART      0x30
 104 #define NAND_CMD_RNDOUTSTART    0xE0
 105 #define NAND_CMD_CACHEDPROG     0x15
 106
 107 #define NAND_CMD_NONE           -1
 108
 109 /* Status bits */
 110 #define NAND_STATUS_FAIL        0x01
 111 #define NAND_STATUS_FAIL_N1     0x02
 112 #define NAND_STATUS_TRUE_READY  0x20
 113 #define NAND_STATUS_READY       0x40
 114 #define NAND_STATUS_WP          0x80
 115
 116 /*
 117  * Constants for ECC_MODES
 118  */
 119 typedef enum {
 120         NAND_ECC_NONE,
 121         NAND_ECC_SOFT,
 122         NAND_ECC_HW,
 123         NAND_ECC_HW_SYNDROME,
 124         NAND_ECC_HW_OOB_FIRST,
 125         NAND_ECC_SOFT_BCH,
 126 } nand_ecc_modes_t;
 127
 128 /*
 129  * Constants for Hardware ECC
 130  */
 131 /* Reset Hardware ECC for read */
 132 #define NAND_ECC_READ           0
 133 /* Reset Hardware ECC for write */
 134 #define NAND_ECC_WRITE          1
 135 /* Enable Hardware ECC before syndrome is read back from flash */
 136 #define NAND_ECC_READSYN        2
 137
 138 /* Bit mask for flags passed to do_nand_read_ecc */
 139 #define NAND_GET_DEVICE         0x80
 140
 141
 142 /*
 143  * Option constants for bizarre disfunctionality and real
 144  * features.
 145  */
 146 /* Buswidth is 16 bit */
 147 #define NAND_BUSWIDTH_16        0x00000002
 148 /* Chip has cache program function */
 149 #define NAND_CACHEPRG           0x00000008
 150 /*
 151  * Chip requires ready check on read (for auto-incremented sequential read).
 152  * True only for small page devices; large page devices do not support
 153  * autoincrement.
 154  */
 155 #define NAND_NEED_READRDY       0x00000100
 156
 157 /* Chip does not allow subpage writes */
 158 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 159
 160 /* Device is one of 'new' xD cards that expose fake nand command set */
 161 #define NAND_BROKEN_XD          0x00000400
 162
 163 /* Device behaves just like nand, but is readonly */
 164 #define NAND_ROM                0x00000800
 165
 166 /* Device supports subpage reads */
 167 #define NAND_SUBPAGE_READ       0x00001000
 168
 169 /* Options valid for Samsung large page devices */
 170 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 171
 172 /* Macros to identify the above */
 173 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 174 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 175
 176 /* Non chip related options */
 177 /* This option skips the bbt scan during initialization. */
 178 #define NAND_SKIP_BBTSCAN       0x00010000
 179 /*
 180  * This option is defined if the board driver allocates its own buffers
 181  * (e.g. because it needs them DMA-coherent).
 182  */
 183 #define NAND_OWN_BUFFERS        0x00020000
 184 /* Chip may not exist, so silence any errors in scan */
 185 #define NAND_SCAN_SILENT_NODEV  0x00040000
 186 /*
 187  * Autodetect nand buswidth with readid/onfi.
 188  * This suppose the driver will configure the hardware in 8 bits mode
 189  * when calling nand_scan_ident, and update its configuration
 190  * before calling nand_scan_tail.
 191  */
 192 #define NAND_BUSWIDTH_AUTO      0x00080000
 193
 194 /* Options set by nand scan */
 195 /* Nand scan has allocated controller struct */
 196 #define NAND_CONTROLLER_ALLOC   0x80000000
 197
 198 /* Cell info constants */
 199 #define NAND_CI_CHIPNR_MSK      0x03
 200 #define NAND_CI_CELLTYPE_MSK    0x0C
 201
 202 /* Keep gcc happy */
 203 struct nand_chip;
 204
 205 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 206 #define ONFI_TIMING_MODE_0              (1 << 0)
 207 #define ONFI_TIMING_MODE_1              (1 << 1)
 208 #define ONFI_TIMING_MODE_2              (1 << 2)
 209 #define ONFI_TIMING_MODE_3              (1 << 3)
 210 #define ONFI_TIMING_MODE_4              (1 << 4)
 211 #define ONFI_TIMING_MODE_5              (1 << 5)
 212 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 213
 214 /* ONFI feature address */
 215 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 216
 217 /* ONFI subfeature parameters length */
 218 #define ONFI_SUBFEATURE_PARAM_LEN       4
 219
 220 /* ONFI optional commands SET/GET FEATURES supported? */
 221 #define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
 222
 223 struct nand_onfi_params {
 224         /* rev info and features block */
 225         /* 'O' 'N' 'F' 'I'  */
 226         u8 sig[4];
 227         __le16 revision;
 228         __le16 features;
 229         __le16 opt_cmd;
 230         u8 reserved[22];
 231
 232         /* manufacturer information block */
 233         char manufacturer[12];
 234         char model[20];
 235         u8 jedec_id;
 236         __le16 date_code;
 237         u8 reserved2[13];
 238
 239         /* memory organization block */
 240         __le32 byte_per_page;
 241         __le16 spare_bytes_per_page;
 242         __le32 data_bytes_per_ppage;
 243         __le16 spare_bytes_per_ppage;
 244         __le32 pages_per_block;
 245         __le32 blocks_per_lun;
 246         u8 lun_count;
 247         u8 addr_cycles;
 248         u8 bits_per_cell;
 249         __le16 bb_per_lun;
 250         __le16 block_endurance;
 251         u8 guaranteed_good_blocks;
 252         __le16 guaranteed_block_endurance;
 253         u8 programs_per_page;
 254         u8 ppage_attr;
 255         u8 ecc_bits;
 256         u8 interleaved_bits;
 257         u8 interleaved_ops;
 258         u8 reserved3[13];
 259
 260         /* electrical parameter block */
 261         u8 io_pin_capacitance_max;
 262         __le16 async_timing_mode;
 263         __le16 program_cache_timing_mode;
 264         __le16 t_prog;
 265         __le16 t_bers;
 266         __le16 t_r;
 267         __le16 t_ccs;
 268         __le16 src_sync_timing_mode;
 269         __le16 src_ssync_features;
 270         __le16 clk_pin_capacitance_typ;
 271         __le16 io_pin_capacitance_typ;
 272         __le16 input_pin_capacitance_typ;
 273         u8 input_pin_capacitance_max;
 274         u8 driver_strenght_support;
 275         __le16 t_int_r;
 276         __le16 t_ald;
 277         u8 reserved4[7];
 278
 279         /* vendor */
 280         u8 reserved5[90];
 281
 282         __le16 crc;
 283 } __attribute__((packed));
 284
 285 #define ONFI_CRC_BASE   0x4F4E
 286
 287 /**
 288  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 289  * @lock:               protection lock
 290  * @active:             the mtd device which holds the controller currently
 291  * @wq:                 wait queue to sleep on if a NAND operation is in
 292  *                      progress used instead of the per chip wait queue
 293  *                      when a hw controller is available.
 294  */
 295 struct nand_hw_control {
 296         spinlock_t lock;
 297         struct nand_chip *active;
 298         wait_queue_head_t wq;
 299 };
 300
 301 /**
 302  * struct nand_ecc_ctrl - Control structure for ECC
 303  * @mode:       ECC mode
 304  * @steps:      number of ECC steps per page
 305  * @size:       data bytes per ECC step
 306  * @bytes:      ECC bytes per step
 307  * @strength:   max number of correctible bits per ECC step
 308  * @total:      total number of ECC bytes per page
 309  * @prepad:     padding information for syndrome based ECC generators
 310  * @postpad:    padding information for syndrome based ECC generators
 311  * @layout:     ECC layout control struct pointer
 312  * @priv:       pointer to private ECC control data
 313  * @hwctl:      function to control hardware ECC generator. Must only
 314  *              be provided if an hardware ECC is available
 315  * @calculate:  function for ECC calculation or readback from ECC hardware
 316  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 317  * @read_page_raw:      function to read a raw page without ECC
 318  * @write_page_raw:     function to write a raw page without ECC
 319  * @read_page:  function to read a page according to the ECC generator
 320  *              requirements; returns maximum number of bitflips corrected in
 321  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 322  * @read_subpage:       function to read parts of the page covered by ECC;
 323  *                      returns same as read_page()
 324  * @write_subpage:      function to write parts of the page covered by ECC.
 325  * @write_page: function to write a page according to the ECC generator
 326  *              requirements.
 327  * @write_oob_raw:      function to write chip OOB data without ECC
 328  * @read_oob_raw:       function to read chip OOB data without ECC
 329  * @read_oob:   function to read chip OOB data
 330  * @write_oob:  function to write chip OOB data
 331  */
 332 struct nand_ecc_ctrl {
 333         nand_ecc_modes_t mode;
 334         int steps;
 335         int size;
 336         int bytes;
 337         int total;
 338         int strength;
 339         int prepad;
 340         int postpad;
 341         struct nand_ecclayout   *layout;
 342         void *priv;
 343         void (*hwctl)(struct mtd_info *mtd, int mode);
 344         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 345                         uint8_t *ecc_code);
 346         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 347                         uint8_t *calc_ecc);
 348         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 349                         uint8_t *buf, int oob_required, int page);
 350         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 351                         const uint8_t *buf, int oob_required);
 352         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 353                         uint8_t *buf, int oob_required, int page);
 354         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 355                         uint32_t offs, uint32_t len, uint8_t *buf);
 356         int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 357                         uint32_t offset, uint32_t data_len,
 358                         const uint8_t *data_buf, int oob_required);
 359         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 360                         const uint8_t *buf, int oob_required);
 361         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 362                         int page);
 363         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 364                         int page);
 365         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 366         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 367                         int page);
 368 };
 369
 370 /**
 371  * struct nand_buffers - buffer structure for read/write
 372  * @ecccalc:    buffer for calculated ECC
 373  * @ecccode:    buffer for ECC read from flash
 374  * @databuf:    buffer for data - dynamically sized
 375  *
 376  * Do not change the order of buffers. databuf and oobrbuf must be in
 377  * consecutive order.
 378  */
 379 struct nand_buffers {
 380         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 381         uint8_t ecccode[NAND_MAX_OOBSIZE];
 382         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 383 };
 384
 385 /**
 386  * struct nand_chip - NAND Private Flash Chip Data
 387  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 388  *                      flash device
 389  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 390  *                      flash device.
 391  * @read_byte:          [REPLACEABLE] read one byte from the chip
 392  * @read_word:          [REPLACEABLE] read one word from the chip
 393  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 394  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 395  * @select_chip:        [REPLACEABLE] select chip nr
 396  * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
 397  * @block_markbad:      [REPLACEABLE] mark a block bad
 398  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 399  *                      ALE/CLE/nCE. Also used to write command and address
 400  * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 401  *                      mtd->oobsize, mtd->writesize and so on.
 402  *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 403  *                      Return with the bus width.
 404  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 405  *                      device ready/busy line. If set to NULL no access to
 406  *                      ready/busy is available and the ready/busy information
 407  *                      is read from the chip status register.
 408  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 409  *                      commands to the chip.
 410  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 411  *                      ready.
 412  * @ecc:                [BOARDSPECIFIC] ECC control structure
 413  * @buffers:            buffer structure for read/write
 414  * @hwcontrol:          platform-specific hardware control structure
 415  * @erase_cmd:          [INTERN] erase command write function, selectable due
 416  *                      to AND support.
 417  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 418  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 419  *                      data from array to read regs (tR).
 420  * @state:              [INTERN] the current state of the NAND device
 421  * @oob_poi:            "poison value buffer," used for laying out OOB data
 422  *                      before writing
 423  * @page_shift:         [INTERN] number of address bits in a page (column
 424  *                      address bits).
 425  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 426  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 427  * @chip_shift:         [INTERN] number of address bits in one chip
 428  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 429  *                      be set to inform nand_scan about special functionality.
 430  *                      See the defines for further explanation.
 431  * @bbt_options:        [INTERN] bad block specific options. All options used
 432  *                      here must come from bbm.h. By default, these options
 433  *                      will be copied to the appropriate nand_bbt_descr's.
 434  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 435  *                      area.
 436  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 437  *                      bad block marker position; i.e., BBM == 11110111b is
 438  *                      not bad when badblockbits == 7
 439  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 440  * @numchips:           [INTERN] number of physical chips
 441  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 442  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 443  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 444  *                      data_buf.
 445  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 446  *                      currently in data_buf.
 447  * @subpagesize:        [INTERN] holds the subpagesize
 448  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 449  *                      non 0 if ONFI supported.
 450  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 451  *                      supported, 0 otherwise.
 452  * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 453  * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 454  * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
 455  * @bbt:                [INTERN] bad block table pointer
 456  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 457  *                      lookup.
 458  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 459  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 460  *                      bad block scan.
 461  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 462  *                      structure which is shared among multiple independent
 463  *                      devices.
 464  * @priv:               [OPTIONAL] pointer to private chip data
 465  * @errstat:            [OPTIONAL] hardware specific function to perform
 466  *                      additional error status checks (determine if errors are
 467  *                      correctable).
 468  * @write_page:         [REPLACEABLE] High-level page write function
 469  */
 470
 471 struct nand_chip {
 472         void __iomem *IO_ADDR_R;
 473         void __iomem *IO_ADDR_W;
 474
 475         uint8_t (*read_byte)(struct mtd_info *mtd);
 476         u16 (*read_word)(struct mtd_info *mtd);
 477         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 478         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 479         void (*select_chip)(struct mtd_info *mtd, int chip);
 480         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 481         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 482         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 483         int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 484                         u8 *id_data);
 485         int (*dev_ready)(struct mtd_info *mtd);
 486         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 487                         int page_addr);
 488         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 489         void (*erase_cmd)(struct mtd_info *mtd, int page);
 490         int (*scan_bbt)(struct mtd_info *mtd);
 491         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 492                         int status, int page);
 493         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 494                         uint32_t offset, int data_len, const uint8_t *buf,
 495                         int oob_required, int page, int cached, int raw);
 496         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 497                         int feature_addr, uint8_t *subfeature_para);
 498         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 499                         int feature_addr, uint8_t *subfeature_para);
 500
 501         int chip_delay;
 502         unsigned int options;
 503         unsigned int bbt_options;
 504
 505         int page_shift;
 506         int phys_erase_shift;
 507         int bbt_erase_shift;
 508         int chip_shift;
 509         int numchips;
 510         uint64_t chipsize;
 511         int pagemask;
 512         int pagebuf;
 513         unsigned int pagebuf_bitflips;
 514         int subpagesize;
 515         uint8_t cellinfo;
 516         int badblockpos;
 517         int badblockbits;
 518
 519         int onfi_version;
 520         struct nand_onfi_params onfi_params;
 521
 522         flstate_t state;
 523
 524         uint8_t *oob_poi;
 525         struct nand_hw_control *controller;
 526         struct nand_ecclayout *ecclayout;
 527
 528         struct nand_ecc_ctrl ecc;
 529         struct nand_buffers *buffers;
 530         struct nand_hw_control hwcontrol;
 531
 532         uint8_t *bbt;
 533         struct nand_bbt_descr *bbt_td;
 534         struct nand_bbt_descr *bbt_md;
 535
 536         struct nand_bbt_descr *badblock_pattern;
 537
 538         void *priv;
 539 };
 540
 541 /*
 542  * NAND Flash Manufacturer ID Codes
 543  */
 544 #define NAND_MFR_TOSHIBA        0x98
 545 #define NAND_MFR_SAMSUNG        0xec
 546 #define NAND_MFR_FUJITSU        0x04
 547 #define NAND_MFR_NATIONAL       0x8f
 548 #define NAND_MFR_RENESAS        0x07
 549 #define NAND_MFR_STMICRO        0x20
 550 #define NAND_MFR_HYNIX          0xad
 551 #define NAND_MFR_MICRON         0x2c
 552 #define NAND_MFR_AMD            0x01
 553 #define NAND_MFR_MACRONIX       0xc2
 554 #define NAND_MFR_EON            0x92
 555
 556 /* The maximum expected count of bytes in the NAND ID sequence */
 557 #define NAND_MAX_ID_LEN 8
 558
 559 /*
 560  * A helper for defining older NAND chips where the second ID byte fully
 561  * defined the chip, including the geometry (chip size, eraseblock size, page
 562  * size). All these chips have 512 bytes NAND page size.
 563  */
 564 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 565         { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 566           .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 567
 568 /*
 569  * A helper for defining newer chips which report their page size and
 570  * eraseblock size via the extended ID bytes.
 571  *
 572  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
 573  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
 574  * device ID now only represented a particular total chip size (and voltage,
 575  * buswidth), and the page size, eraseblock size, and OOB size could vary while
 576  * using the same device ID.
 577  */
 578 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 579         { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 580           .options = (opts) }
 581
 582 /**
 583  * struct nand_flash_dev - NAND Flash Device ID Structure
 584  * @name: a human-readable name of the NAND chip
 585  * @dev_id: the device ID (the second byte of the full chip ID array)
 586  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
 587  *          memory address as @id[0])
 588  * @dev_id: device ID part of the full chip ID array (refers the same memory
 589  *          address as @id[1])
 590  * @id: full device ID array
 591  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
 592  *            well as the eraseblock size) is determined from the extended NAND
 593  *            chip ID array)
 594  * @chipsize: total chip size in MiB
 595  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
 596  * @options: stores various chip bit options
 597  * @id_len: The valid length of the @id.
 598  * @oobsize: OOB size
 599  */
 600 struct nand_flash_dev {
 601         char *name;
 602         union {
 603                 struct {
 604                         uint8_t mfr_id;
 605                         uint8_t dev_id;
 606                 };
 607                 uint8_t id[NAND_MAX_ID_LEN];
 608         };
 609         unsigned int pagesize;
 610         unsigned int chipsize;
 611         unsigned int erasesize;
 612         unsigned int options;
 613         uint16_t id_len;
 614         uint16_t oobsize;
 615 };
 616
 617 /**
 618  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 619  * @name:       Manufacturer name
 620  * @id:         manufacturer ID code of device.
 621 */
 622 struct nand_manufacturers {
 623         int id;
 624         char *name;
 625 };
 626
 627 extern struct nand_flash_dev nand_flash_ids[];
 628 extern struct nand_manufacturers nand_manuf_ids[];
 629
 630 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 631 extern int nand_default_bbt(struct mtd_info *mtd);
 632 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 633 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 634 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 635                            int allowbbt);
 636 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 637                         size_t *retlen, uint8_t *buf);
 638
 639 /**
 640  * struct platform_nand_chip - chip level device structure
 641  * @nr_chips:           max. number of chips to scan for
 642  * @chip_offset:        chip number offset
 643  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 644  * @partitions:         mtd partition list
 645  * @chip_delay:         R/B delay value in us
 646  * @options:            Option flags, e.g. 16bit buswidth
 647  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 648  * @ecclayout:          ECC layout info structure
 649  * @part_probe_types:   NULL-terminated array of probe types
 650  */
 651 struct platform_nand_chip {
 652         int nr_chips;
 653         int chip_offset;
 654         int nr_partitions;
 655         struct mtd_partition *partitions;
 656         struct nand_ecclayout *ecclayout;
 657         int chip_delay;
 658         unsigned int options;
 659         unsigned int bbt_options;
 660         const char **part_probe_types;
 661 };
 662
 663 /* Keep gcc happy */
 664 struct platform_device;
 665
 666 /**
 667  * struct platform_nand_ctrl - controller level device structure
 668  * @probe:              platform specific function to probe/setup hardware
 669  * @remove:             platform specific function to remove/teardown hardware
 670  * @hwcontrol:          platform specific hardware control structure
 671  * @dev_ready:          platform specific function to read ready/busy pin
 672  * @select_chip:        platform specific chip select function
 673  * @cmd_ctrl:           platform specific function for controlling
 674  *                      ALE/CLE/nCE. Also used to write command and address
 675  * @write_buf:          platform specific function for write buffer
 676  * @read_buf:           platform specific function for read buffer
 677  * @read_byte:          platform specific function to read one byte from chip
 678  * @priv:               private data to transport driver specific settings
 679  *
 680  * All fields are optional and depend on the hardware driver requirements
 681  */
 682 struct platform_nand_ctrl {
 683         int (*probe)(struct platform_device *pdev);
 684         void (*remove)(struct platform_device *pdev);
 685         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 686         int (*dev_ready)(struct mtd_info *mtd);
 687         void (*select_chip)(struct mtd_info *mtd, int chip);
 688         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 689         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 690         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 691         unsigned char (*read_byte)(struct mtd_info *mtd);
 692         void *priv;
 693 };
 694
 695 /**
 696  * struct platform_nand_data - container structure for platform-specific data
 697  * @chip:               chip level chip structure
 698  * @ctrl:               controller level device structure
 699  */
 700 struct platform_nand_data {
 701         struct platform_nand_chip chip;
 702         struct platform_nand_ctrl ctrl;
 703 };
 704
 705 /* Some helpers to access the data structures */
 706 static inline
 707 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 708 {
 709         struct nand_chip *chip = mtd->priv;
 710
 711         return chip->priv;
 712 }
 713
 714 /* return the supported asynchronous timing mode. */
 715 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 716 {
 717         if (!chip->onfi_version)
 718                 return ONFI_TIMING_MODE_UNKNOWN;
 719         return le16_to_cpu(chip->onfi_params.async_timing_mode);
 720 }
 721
 722 /* return the supported synchronous timing mode. */
 723 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 724 {
 725         if (!chip->onfi_version)
 726                 return ONFI_TIMING_MODE_UNKNOWN;
 727         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 728 }
 729
 730 #endif /* __LINUX_MTD_NAND_H */