2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 /* Scan and identify a NAND device */
29 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
30 /* Separate phases of nand_scan(), allowing board driver to intervene
31 * and override command or ECC setup according to flash type */
32 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
);
33 extern int nand_scan_tail(struct mtd_info
*mtd
);
35 /* Free resources held by the NAND device */
36 extern void nand_release (struct mtd_info
*mtd
);
38 /* Internal helper for board drivers which need to override command function */
39 extern void nand_wait_ready(struct mtd_info
*mtd
);
41 /* locks all blockes present in the device */
42 extern int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
44 /* unlocks specified locked blockes */
45 extern int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
47 /* The maximum number of NAND chips in an array */
48 #define NAND_MAX_CHIPS 8
50 /* This constant declares the max. oobsize / page, which
51 * is supported now. If you add a chip with bigger oobsize/page
52 * adjust this accordingly.
54 #define NAND_MAX_OOBSIZE 128
55 #define NAND_MAX_PAGESIZE 4096
58 * Constants for hardware specific CLE/ALE/NCE function
60 * These are bits which can be or'ed to set/clear multiple
63 /* Select the chip by setting nCE to low */
65 /* Select the command latch by setting CLE to high */
67 /* Select the address latch by setting ALE to high */
70 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
71 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
72 #define NAND_CTRL_CHANGE 0x80
75 * Standard NAND flash commands
77 #define NAND_CMD_READ0 0
78 #define NAND_CMD_READ1 1
79 #define NAND_CMD_RNDOUT 5
80 #define NAND_CMD_PAGEPROG 0x10
81 #define NAND_CMD_READOOB 0x50
82 #define NAND_CMD_ERASE1 0x60
83 #define NAND_CMD_STATUS 0x70
84 #define NAND_CMD_STATUS_MULTI 0x71
85 #define NAND_CMD_SEQIN 0x80
86 #define NAND_CMD_RNDIN 0x85
87 #define NAND_CMD_READID 0x90
88 #define NAND_CMD_ERASE2 0xd0
89 #define NAND_CMD_RESET 0xff
91 #define NAND_CMD_LOCK 0x2a
92 #define NAND_CMD_UNLOCK1 0x23
93 #define NAND_CMD_UNLOCK2 0x24
95 /* Extended commands for large page devices */
96 #define NAND_CMD_READSTART 0x30
97 #define NAND_CMD_RNDOUTSTART 0xE0
98 #define NAND_CMD_CACHEDPROG 0x15
100 /* Extended commands for AG-AND device */
102 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
103 * there is no way to distinguish that from NAND_CMD_READ0
104 * until the remaining sequence of commands has been completed
105 * so add a high order bit and mask it off in the command.
107 #define NAND_CMD_DEPLETE1 0x100
108 #define NAND_CMD_DEPLETE2 0x38
109 #define NAND_CMD_STATUS_MULTI 0x71
110 #define NAND_CMD_STATUS_ERROR 0x72
111 /* multi-bank error status (banks 0-3) */
112 #define NAND_CMD_STATUS_ERROR0 0x73
113 #define NAND_CMD_STATUS_ERROR1 0x74
114 #define NAND_CMD_STATUS_ERROR2 0x75
115 #define NAND_CMD_STATUS_ERROR3 0x76
116 #define NAND_CMD_STATUS_RESET 0x7f
117 #define NAND_CMD_STATUS_CLEAR 0xff
119 #define NAND_CMD_NONE -1
122 #define NAND_STATUS_FAIL 0x01
123 #define NAND_STATUS_FAIL_N1 0x02
124 #define NAND_STATUS_TRUE_READY 0x20
125 #define NAND_STATUS_READY 0x40
126 #define NAND_STATUS_WP 0x80
129 * Constants for ECC_MODES
135 NAND_ECC_HW_SYNDROME
,
136 NAND_ECC_HW_OOB_FIRST
,
140 * Constants for Hardware ECC
142 /* Reset Hardware ECC for read */
143 #define NAND_ECC_READ 0
144 /* Reset Hardware ECC for write */
145 #define NAND_ECC_WRITE 1
146 /* Enable Hardware ECC before syndrom is read back from flash */
147 #define NAND_ECC_READSYN 2
149 /* Bit mask for flags passed to do_nand_read_ecc */
150 #define NAND_GET_DEVICE 0x80
153 /* Option constants for bizarre disfunctionality and real
156 /* Chip can not auto increment pages */
157 #define NAND_NO_AUTOINCR 0x00000001
158 /* Buswitdh is 16 bit */
159 #define NAND_BUSWIDTH_16 0x00000002
160 /* Device supports partial programming without padding */
161 #define NAND_NO_PADDING 0x00000004
162 /* Chip has cache program function */
163 #define NAND_CACHEPRG 0x00000008
164 /* Chip has copy back function */
165 #define NAND_COPYBACK 0x00000010
166 /* AND Chip which has 4 banks and a confusing page / block
167 * assignment. See Renesas datasheet for further information */
168 #define NAND_IS_AND 0x00000020
169 /* Chip has a array of 4 pages which can be read without
170 * additional ready /busy waits */
171 #define NAND_4PAGE_ARRAY 0x00000040
172 /* Chip requires that BBT is periodically rewritten to prevent
173 * bits from adjacent blocks from 'leaking' in altering data.
174 * This happens with the Renesas AG-AND chips, possibly others. */
175 #define BBT_AUTO_REFRESH 0x00000080
176 /* Chip does not require ready check on read. True
177 * for all large page devices, as they do not support
179 #define NAND_NO_READRDY 0x00000100
180 /* Chip does not allow subpage writes */
181 #define NAND_NO_SUBPAGE_WRITE 0x00000200
183 /* Options valid for Samsung large page devices */
184 #define NAND_SAMSUNG_LP_OPTIONS \
185 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
187 /* Macros to identify the above */
188 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
189 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
190 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
191 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
192 /* Large page NAND with SOFT_ECC should support subpage reads */
193 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
194 && (chip->page_shift > 9))
196 /* Mask to zero out the chip options, which come from the id table */
197 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
199 /* Non chip related options */
200 /* Use a flash based bad block table. This option is passed to the
201 * default bad block table function. */
202 #define NAND_USE_FLASH_BBT 0x00010000
203 /* This option skips the bbt scan during initialization. */
204 #define NAND_SKIP_BBTSCAN 0x00020000
205 /* This option is defined if the board driver allocates its own buffers
206 (e.g. because it needs them DMA-coherent */
207 #define NAND_OWN_BUFFERS 0x00040000
208 /* Chip may not exist, so silence any errors in scan */
209 #define NAND_SCAN_SILENT_NODEV 0x00080000
211 /* Options set by nand scan */
212 /* Nand scan has allocated controller struct */
213 #define NAND_CONTROLLER_ALLOC 0x80000000
215 /* Cell info constants */
216 #define NAND_CI_CHIPNR_MSK 0x03
217 #define NAND_CI_CELLTYPE_MSK 0x0C
223 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
224 * @lock: protection lock
225 * @active: the mtd device which holds the controller currently
226 * @wq: wait queue to sleep on if a NAND operation is in progress
227 * used instead of the per chip wait queue when a hw controller is available
229 struct nand_hw_control
{
231 struct nand_chip
*active
;
232 wait_queue_head_t wq
;
236 * struct nand_ecc_ctrl - Control structure for ecc
238 * @steps: number of ecc steps per page
239 * @size: data bytes per ecc step
240 * @bytes: ecc bytes per step
241 * @total: total number of ecc bytes per page
242 * @prepad: padding information for syndrome based ecc generators
243 * @postpad: padding information for syndrome based ecc generators
244 * @layout: ECC layout control struct pointer
245 * @hwctl: function to control hardware ecc generator. Must only
246 * be provided if an hardware ECC is available
247 * @calculate: function for ecc calculation or readback from ecc hardware
248 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
249 * @read_page_raw: function to read a raw page without ECC
250 * @write_page_raw: function to write a raw page without ECC
251 * @read_page: function to read a page according to the ecc generator requirements
252 * @read_subpage: function to read parts of the page covered by ECC.
253 * @write_page: function to write a page according to the ecc generator requirements
254 * @read_oob: function to read chip OOB data
255 * @write_oob: function to write chip OOB data
257 struct nand_ecc_ctrl
{
258 nand_ecc_modes_t mode
;
265 struct nand_ecclayout
*layout
;
266 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
267 int (*calculate
)(struct mtd_info
*mtd
,
270 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
273 int (*read_page_raw
)(struct mtd_info
*mtd
,
274 struct nand_chip
*chip
,
275 uint8_t *buf
, int page
);
276 void (*write_page_raw
)(struct mtd_info
*mtd
,
277 struct nand_chip
*chip
,
279 int (*read_page
)(struct mtd_info
*mtd
,
280 struct nand_chip
*chip
,
281 uint8_t *buf
, int page
);
282 int (*read_subpage
)(struct mtd_info
*mtd
,
283 struct nand_chip
*chip
,
284 uint32_t offs
, uint32_t len
,
286 void (*write_page
)(struct mtd_info
*mtd
,
287 struct nand_chip
*chip
,
289 int (*read_oob
)(struct mtd_info
*mtd
,
290 struct nand_chip
*chip
,
293 int (*write_oob
)(struct mtd_info
*mtd
,
294 struct nand_chip
*chip
,
299 * struct nand_buffers - buffer structure for read/write
300 * @ecccalc: buffer for calculated ecc
301 * @ecccode: buffer for ecc read from flash
302 * @databuf: buffer for data - dynamically sized
304 * Do not change the order of buffers. databuf and oobrbuf must be in
307 struct nand_buffers
{
308 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
309 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
310 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
314 * struct nand_chip - NAND Private Flash Chip Data
315 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
316 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
317 * @read_byte: [REPLACEABLE] read one byte from the chip
318 * @read_word: [REPLACEABLE] read one word from the chip
319 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
320 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
321 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
322 * @select_chip: [REPLACEABLE] select chip nr
323 * @block_bad: [REPLACEABLE] check, if the block is bad
324 * @block_markbad: [REPLACEABLE] mark the block bad
325 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
326 * ALE/CLE/nCE. Also used to write command and address
327 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
328 * If set to NULL no access to ready/busy is available and the ready/busy information
329 * is read from the chip status register
330 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
331 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
332 * @ecc: [BOARDSPECIFIC] ecc control ctructure
333 * @buffers: buffer structure for read/write
334 * @hwcontrol: platform-specific hardware control structure
335 * @ops: oob operation operands
336 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
337 * @scan_bbt: [REPLACEABLE] function to scan bad block table
338 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
339 * @state: [INTERN] the current state of the NAND device
340 * @oob_poi: poison value buffer
341 * @page_shift: [INTERN] number of address bits in a page (column address bits)
342 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
343 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
344 * @chip_shift: [INTERN] number of address bits in one chip
345 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
346 * special functionality. See the defines for further explanation
347 * @badblockpos: [INTERN] position of the bad block marker in the oob area
348 * @cellinfo: [INTERN] MLC/multichip data from chip ident
349 * @numchips: [INTERN] number of physical chips
350 * @chipsize: [INTERN] the size of one chip for multichip arrays
351 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
352 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
353 * @subpagesize: [INTERN] holds the subpagesize
354 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
355 * @bbt: [INTERN] bad block table pointer
356 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
357 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
358 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
359 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
360 * which is shared among multiple independend devices
361 * @priv: [OPTIONAL] pointer to private chip date
362 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
363 * (determine if errors are correctable)
364 * @write_page: [REPLACEABLE] High-level page write function
368 void __iomem
*IO_ADDR_R
;
369 void __iomem
*IO_ADDR_W
;
371 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
372 u16 (*read_word
)(struct mtd_info
*mtd
);
373 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
374 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
375 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
376 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
377 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
378 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
379 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
381 int (*dev_ready
)(struct mtd_info
*mtd
);
382 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
383 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
384 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
385 int (*scan_bbt
)(struct mtd_info
*mtd
);
386 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
387 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
388 const uint8_t *buf
, int page
, int cached
, int raw
);
391 unsigned int options
;
394 int phys_erase_shift
;
408 struct nand_hw_control
*controller
;
409 struct nand_ecclayout
*ecclayout
;
411 struct nand_ecc_ctrl ecc
;
412 struct nand_buffers
*buffers
;
413 struct nand_hw_control hwcontrol
;
415 struct mtd_oob_ops ops
;
418 struct nand_bbt_descr
*bbt_td
;
419 struct nand_bbt_descr
*bbt_md
;
421 struct nand_bbt_descr
*badblock_pattern
;
427 * NAND Flash Manufacturer ID Codes
429 #define NAND_MFR_TOSHIBA 0x98
430 #define NAND_MFR_SAMSUNG 0xec
431 #define NAND_MFR_FUJITSU 0x04
432 #define NAND_MFR_NATIONAL 0x8f
433 #define NAND_MFR_RENESAS 0x07
434 #define NAND_MFR_STMICRO 0x20
435 #define NAND_MFR_HYNIX 0xad
436 #define NAND_MFR_MICRON 0x2c
437 #define NAND_MFR_AMD 0x01
440 * struct nand_flash_dev - NAND Flash Device ID Structure
441 * @name: Identify the device type
442 * @id: device ID code
443 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
444 * If the pagesize is 0, then the real pagesize
445 * and the eraseize are determined from the
446 * extended id bytes in the chip
447 * @erasesize: Size of an erase block in the flash device.
448 * @chipsize: Total chipsize in Mega Bytes
449 * @options: Bitfield to store chip relevant options
451 struct nand_flash_dev
{
454 unsigned long pagesize
;
455 unsigned long chipsize
;
456 unsigned long erasesize
;
457 unsigned long options
;
461 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
462 * @name: Manufacturer name
463 * @id: manufacturer ID code of device.
465 struct nand_manufacturers
{
470 extern struct nand_flash_dev nand_flash_ids
[];
471 extern struct nand_manufacturers nand_manuf_ids
[];
473 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
474 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
475 extern int nand_default_bbt(struct mtd_info
*mtd
);
476 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
477 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
479 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
480 size_t * retlen
, uint8_t * buf
);
483 * struct platform_nand_chip - chip level device structure
484 * @nr_chips: max. number of chips to scan for
485 * @chip_offset: chip number offset
486 * @nr_partitions: number of partitions pointed to by partitions (or zero)
487 * @partitions: mtd partition list
488 * @chip_delay: R/B delay value in us
489 * @options: Option flags, e.g. 16bit buswidth
490 * @ecclayout: ecc layout info structure
491 * @part_probe_types: NULL-terminated array of probe types
492 * @set_parts: platform specific function to set partitions
493 * @priv: hardware controller specific settings
495 struct platform_nand_chip
{
499 struct mtd_partition
*partitions
;
500 struct nand_ecclayout
*ecclayout
;
502 unsigned int options
;
503 const char **part_probe_types
;
504 void (*set_parts
)(uint64_t size
,
505 struct platform_nand_chip
*chip
);
510 struct platform_device
;
513 * struct platform_nand_ctrl - controller level device structure
514 * @probe: platform specific function to probe/setup hardware
515 * @remove: platform specific function to remove/teardown hardware
516 * @hwcontrol: platform specific hardware control structure
517 * @dev_ready: platform specific function to read ready/busy pin
518 * @select_chip: platform specific chip select function
519 * @cmd_ctrl: platform specific function for controlling
520 * ALE/CLE/nCE. Also used to write command and address
521 * @write_buf: platform specific function for write buffer
522 * @read_buf: platform specific function for read buffer
523 * @priv: private data to transport driver specific settings
525 * All fields are optional and depend on the hardware driver requirements
527 struct platform_nand_ctrl
{
528 int (*probe
)(struct platform_device
*pdev
);
529 void (*remove
)(struct platform_device
*pdev
);
530 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
531 int (*dev_ready
)(struct mtd_info
*mtd
);
532 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
533 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
535 void (*write_buf
)(struct mtd_info
*mtd
,
536 const uint8_t *buf
, int len
);
537 void (*read_buf
)(struct mtd_info
*mtd
,
538 uint8_t *buf
, int len
);
543 * struct platform_nand_data - container structure for platform-specific data
544 * @chip: chip level chip structure
545 * @ctrl: controller level device structure
547 struct platform_nand_data
{
548 struct platform_nand_chip chip
;
549 struct platform_nand_ctrl ctrl
;
552 /* Some helpers to access the data structures */
554 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
556 struct nand_chip
*chip
= mtd
->priv
;
561 #endif /* __LINUX_MTD_NAND_H */