include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/bbm.h>
  25
  26 struct mtd_info;
  27 /* Scan and identify a NAND device */
  28 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  29 /* Separate phases of nand_scan(), allowing board driver to intervene
  30  * and override command or ECC setup according to flash type */
  31 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
  32 extern int nand_scan_tail(struct mtd_info *mtd);
  33
  34 /* Free resources held by the NAND device */
  35 extern void nand_release (struct mtd_info *mtd);
  36
  37 /* Internal helper for board drivers which need to override command function */
  38 extern void nand_wait_ready(struct mtd_info *mtd);
  39
  40 /* The maximum number of NAND chips in an array */
  41 #define NAND_MAX_CHIPS          8
  42
  43 /* This constant declares the max. oobsize / page, which
  44  * is supported now. If you add a chip with bigger oobsize/page
  45  * adjust this accordingly.
  46  */
  47 #define NAND_MAX_OOBSIZE        128
  48 #define NAND_MAX_PAGESIZE       4096
  49
  50 /*
  51  * Constants for hardware specific CLE/ALE/NCE function
  52  *
  53  * These are bits which can be or'ed to set/clear multiple
  54  * bits in one go.
  55  */
  56 /* Select the chip by setting nCE to low */
  57 #define NAND_NCE                0x01
  58 /* Select the command latch by setting CLE to high */
  59 #define NAND_CLE                0x02
  60 /* Select the address latch by setting ALE to high */
  61 #define NAND_ALE                0x04
  62
  63 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  64 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  65 #define NAND_CTRL_CHANGE        0x80
  66
  67 /*
  68  * Standard NAND flash commands
  69  */
  70 #define NAND_CMD_READ0          0
  71 #define NAND_CMD_READ1          1
  72 #define NAND_CMD_RNDOUT         5
  73 #define NAND_CMD_PAGEPROG       0x10
  74 #define NAND_CMD_READOOB        0x50
  75 #define NAND_CMD_ERASE1         0x60
  76 #define NAND_CMD_STATUS         0x70
  77 #define NAND_CMD_STATUS_MULTI   0x71
  78 #define NAND_CMD_SEQIN          0x80
  79 #define NAND_CMD_RNDIN          0x85
  80 #define NAND_CMD_READID         0x90
  81 #define NAND_CMD_ERASE2         0xd0
  82 #define NAND_CMD_RESET          0xff
  83
  84 /* Extended commands for large page devices */
  85 #define NAND_CMD_READSTART      0x30
  86 #define NAND_CMD_RNDOUTSTART    0xE0
  87 #define NAND_CMD_CACHEDPROG     0x15
  88
  89 /* Extended commands for AG-AND device */
  90 /*
  91  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  92  *       there is no way to distinguish that from NAND_CMD_READ0
  93  *       until the remaining sequence of commands has been completed
  94  *       so add a high order bit and mask it off in the command.
  95  */
  96 #define NAND_CMD_DEPLETE1       0x100
  97 #define NAND_CMD_DEPLETE2       0x38
  98 #define NAND_CMD_STATUS_MULTI   0x71
  99 #define NAND_CMD_STATUS_ERROR   0x72
 100 /* multi-bank error status (banks 0-3) */
 101 #define NAND_CMD_STATUS_ERROR0  0x73
 102 #define NAND_CMD_STATUS_ERROR1  0x74
 103 #define NAND_CMD_STATUS_ERROR2  0x75
 104 #define NAND_CMD_STATUS_ERROR3  0x76
 105 #define NAND_CMD_STATUS_RESET   0x7f
 106 #define NAND_CMD_STATUS_CLEAR   0xff
 107
 108 #define NAND_CMD_NONE           -1
 109
 110 /* Status bits */
 111 #define NAND_STATUS_FAIL        0x01
 112 #define NAND_STATUS_FAIL_N1     0x02
 113 #define NAND_STATUS_TRUE_READY  0x20
 114 #define NAND_STATUS_READY       0x40
 115 #define NAND_STATUS_WP          0x80
 116
 117 /*
 118  * Constants for ECC_MODES
 119  */
 120 typedef enum {
 121         NAND_ECC_NONE,
 122         NAND_ECC_SOFT,
 123         NAND_ECC_HW,
 124         NAND_ECC_HW_SYNDROME,
 125         NAND_ECC_HW_OOB_FIRST,
 126 } nand_ecc_modes_t;
 127
 128 /*
 129  * Constants for Hardware ECC
 130  */
 131 /* Reset Hardware ECC for read */
 132 #define NAND_ECC_READ           0
 133 /* Reset Hardware ECC for write */
 134 #define NAND_ECC_WRITE          1
 135 /* Enable Hardware ECC before syndrom is read back from flash */
 136 #define NAND_ECC_READSYN        2
 137
 138 /* Bit mask for flags passed to do_nand_read_ecc */
 139 #define NAND_GET_DEVICE         0x80
 140
 141
 142 /* Option constants for bizarre disfunctionality and real
 143 *  features
 144 */
 145 /* Chip can not auto increment pages */
 146 #define NAND_NO_AUTOINCR        0x00000001
 147 /* Buswitdh is 16 bit */
 148 #define NAND_BUSWIDTH_16        0x00000002
 149 /* Device supports partial programming without padding */
 150 #define NAND_NO_PADDING         0x00000004
 151 /* Chip has cache program function */
 152 #define NAND_CACHEPRG           0x00000008
 153 /* Chip has copy back function */
 154 #define NAND_COPYBACK           0x00000010
 155 /* AND Chip which has 4 banks and a confusing page / block
 156  * assignment. See Renesas datasheet for further information */
 157 #define NAND_IS_AND             0x00000020
 158 /* Chip has a array of 4 pages which can be read without
 159  * additional ready /busy waits */
 160 #define NAND_4PAGE_ARRAY        0x00000040
 161 /* Chip requires that BBT is periodically rewritten to prevent
 162  * bits from adjacent blocks from 'leaking' in altering data.
 163  * This happens with the Renesas AG-AND chips, possibly others.  */
 164 #define BBT_AUTO_REFRESH        0x00000080
 165 /* Chip does not require ready check on read. True
 166  * for all large page devices, as they do not support
 167  * autoincrement.*/
 168 #define NAND_NO_READRDY         0x00000100
 169 /* Chip does not allow subpage writes */
 170 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 171
 172
 173 /* Options valid for Samsung large page devices */
 174 #define NAND_SAMSUNG_LP_OPTIONS \
 175         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 176
 177 /* Macros to identify the above */
 178 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 179 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 180 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 181 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 182 /* Large page NAND with SOFT_ECC should support subpage reads */
 183 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
 184                                         && (chip->page_shift > 9))
 185
 186 /* Mask to zero out the chip options, which come from the id table */
 187 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 188
 189 /* Non chip related options */
 190 /* Use a flash based bad block table. This option is passed to the
 191  * default bad block table function. */
 192 #define NAND_USE_FLASH_BBT      0x00010000
 193 /* This option skips the bbt scan during initialization. */
 194 #define NAND_SKIP_BBTSCAN       0x00020000
 195 /* This option is defined if the board driver allocates its own buffers
 196    (e.g. because it needs them DMA-coherent */
 197 #define NAND_OWN_BUFFERS        0x00040000
 198 /* Options set by nand scan */
 199 /* Nand scan has allocated controller struct */
 200 #define NAND_CONTROLLER_ALLOC   0x80000000
 201
 202 /* Cell info constants */
 203 #define NAND_CI_CHIPNR_MSK      0x03
 204 #define NAND_CI_CELLTYPE_MSK    0x0C
 205
 206 /*
 207  * nand_state_t - chip states
 208  * Enumeration for NAND flash chip state
 209  */
 210 typedef enum {
 211         FL_READY,
 212         FL_READING,
 213         FL_WRITING,
 214         FL_ERASING,
 215         FL_SYNCING,
 216         FL_CACHEDPRG,
 217         FL_PM_SUSPENDED,
 218 } nand_state_t;
 219
 220 /* Keep gcc happy */
 221 struct nand_chip;
 222
 223 /**
 224  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 225  * @lock:               protection lock
 226  * @active:             the mtd device which holds the controller currently
 227  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 228  *                      used instead of the per chip wait queue when a hw controller is available
 229  */
 230 struct nand_hw_control {
 231         spinlock_t       lock;
 232         struct nand_chip *active;
 233         wait_queue_head_t wq;
 234 };
 235
 236 /**
 237  * struct nand_ecc_ctrl - Control structure for ecc
 238  * @mode:       ecc mode
 239  * @steps:      number of ecc steps per page
 240  * @size:       data bytes per ecc step
 241  * @bytes:      ecc bytes per step
 242  * @total:      total number of ecc bytes per page
 243  * @prepad:     padding information for syndrome based ecc generators
 244  * @postpad:    padding information for syndrome based ecc generators
 245  * @layout:     ECC layout control struct pointer
 246  * @hwctl:      function to control hardware ecc generator. Must only
 247  *              be provided if an hardware ECC is available
 248  * @calculate:  function for ecc calculation or readback from ecc hardware
 249  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 250  * @read_page_raw:      function to read a raw page without ECC
 251  * @write_page_raw:     function to write a raw page without ECC
 252  * @read_page:  function to read a page according to the ecc generator requirements
 253  * @read_subpage:       function to read parts of the page covered by ECC.
 254  * @write_page: function to write a page according to the ecc generator requirements
 255  * @read_oob:   function to read chip OOB data
 256  * @write_oob:  function to write chip OOB data
 257  */
 258 struct nand_ecc_ctrl {
 259         nand_ecc_modes_t        mode;
 260         int                     steps;
 261         int                     size;
 262         int                     bytes;
 263         int                     total;
 264         int                     prepad;
 265         int                     postpad;
 266         struct nand_ecclayout   *layout;
 267         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 268         int                     (*calculate)(struct mtd_info *mtd,
 269                                              const uint8_t *dat,
 270                                              uint8_t *ecc_code);
 271         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 272                                            uint8_t *read_ecc,
 273                                            uint8_t *calc_ecc);
 274         int                     (*read_page_raw)(struct mtd_info *mtd,
 275                                                  struct nand_chip *chip,
 276                                                  uint8_t *buf, int page);
 277         void                    (*write_page_raw)(struct mtd_info *mtd,
 278                                                   struct nand_chip *chip,
 279                                                   const uint8_t *buf);
 280         int                     (*read_page)(struct mtd_info *mtd,
 281                                              struct nand_chip *chip,
 282                                              uint8_t *buf, int page);
 283         int                     (*read_subpage)(struct mtd_info *mtd,
 284                                              struct nand_chip *chip,
 285                                              uint32_t offs, uint32_t len,
 286                                              uint8_t *buf);
 287         void                    (*write_page)(struct mtd_info *mtd,
 288                                               struct nand_chip *chip,
 289                                               const uint8_t *buf);
 290         int                     (*read_oob)(struct mtd_info *mtd,
 291                                             struct nand_chip *chip,
 292                                             int page,
 293                                             int sndcmd);
 294         int                     (*write_oob)(struct mtd_info *mtd,
 295                                              struct nand_chip *chip,
 296                                              int page);
 297 };
 298
 299 /**
 300  * struct nand_buffers - buffer structure for read/write
 301  * @ecccalc:    buffer for calculated ecc
 302  * @ecccode:    buffer for ecc read from flash
 303  * @databuf:    buffer for data - dynamically sized
 304  *
 305  * Do not change the order of buffers. databuf and oobrbuf must be in
 306  * consecutive order.
 307  */
 308 struct nand_buffers {
 309         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 310         uint8_t ecccode[NAND_MAX_OOBSIZE];
 311         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 312 };
 313
 314 /**
 315  * struct nand_chip - NAND Private Flash Chip Data
 316  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 317  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 318  * @read_byte:          [REPLACEABLE] read one byte from the chip
 319  * @read_word:          [REPLACEABLE] read one word from the chip
 320  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 321  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 322  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 323  * @select_chip:        [REPLACEABLE] select chip nr
 324  * @block_bad:          [REPLACEABLE] check, if the block is bad
 325  * @block_markbad:      [REPLACEABLE] mark the block bad
 326  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 327  *                      ALE/CLE/nCE. Also used to write command and address
 328  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 329  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 330  *                      is read from the chip status register
 331  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 332  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 333  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 334  * @buffers:            buffer structure for read/write
 335  * @hwcontrol:          platform-specific hardware control structure
 336  * @ops:                oob operation operands
 337  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 338  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 339  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 340  * @state:              [INTERN] the current state of the NAND device
 341  * @oob_poi:            poison value buffer
 342  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 343  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 344  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 345  * @chip_shift:         [INTERN] number of address bits in one chip
 346  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 347  *                      special functionality. See the defines for further explanation
 348  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 349  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 350  * @numchips:           [INTERN] number of physical chips
 351  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 352  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 353  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 354  * @subpagesize:        [INTERN] holds the subpagesize
 355  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 356  * @bbt:                [INTERN] bad block table pointer
 357  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 358  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 359  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 360  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 361  *                      which is shared among multiple independend devices
 362  * @priv:               [OPTIONAL] pointer to private chip date
 363  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 364  *                      (determine if errors are correctable)
 365  * @write_page:         [REPLACEABLE] High-level page write function
 366  */
 367
 368 struct nand_chip {
 369         void  __iomem   *IO_ADDR_R;
 370         void  __iomem   *IO_ADDR_W;
 371
 372         uint8_t         (*read_byte)(struct mtd_info *mtd);
 373         u16             (*read_word)(struct mtd_info *mtd);
 374         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 375         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 376         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 377         void            (*select_chip)(struct mtd_info *mtd, int chip);
 378         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 379         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 380         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 381                                     unsigned int ctrl);
 382         int             (*dev_ready)(struct mtd_info *mtd);
 383         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 384         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 385         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 386         int             (*scan_bbt)(struct mtd_info *mtd);
 387         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 388         int             (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 389                                       const uint8_t *buf, int page, int cached, int raw);
 390
 391         int             chip_delay;
 392         unsigned int    options;
 393
 394         int             page_shift;
 395         int             phys_erase_shift;
 396         int             bbt_erase_shift;
 397         int             chip_shift;
 398         int             numchips;
 399         uint64_t        chipsize;
 400         int             pagemask;
 401         int             pagebuf;
 402         int             subpagesize;
 403         uint8_t         cellinfo;
 404         int             badblockpos;
 405
 406         nand_state_t    state;
 407
 408         uint8_t         *oob_poi;
 409         struct nand_hw_control  *controller;
 410         struct nand_ecclayout   *ecclayout;
 411
 412         struct nand_ecc_ctrl ecc;
 413         struct nand_buffers *buffers;
 414         struct nand_hw_control hwcontrol;
 415
 416         struct mtd_oob_ops ops;
 417
 418         uint8_t         *bbt;
 419         struct nand_bbt_descr   *bbt_td;
 420         struct nand_bbt_descr   *bbt_md;
 421
 422         struct nand_bbt_descr   *badblock_pattern;
 423
 424         void            *priv;
 425 };
 426
 427 /*
 428  * NAND Flash Manufacturer ID Codes
 429  */
 430 #define NAND_MFR_TOSHIBA        0x98
 431 #define NAND_MFR_SAMSUNG        0xec
 432 #define NAND_MFR_FUJITSU        0x04
 433 #define NAND_MFR_NATIONAL       0x8f
 434 #define NAND_MFR_RENESAS        0x07
 435 #define NAND_MFR_STMICRO        0x20
 436 #define NAND_MFR_HYNIX          0xad
 437 #define NAND_MFR_MICRON         0x2c
 438 #define NAND_MFR_AMD            0x01
 439
 440 /**
 441  * struct nand_flash_dev - NAND Flash Device ID Structure
 442  * @name:       Identify the device type
 443  * @id:         device ID code
 444  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 445  *              If the pagesize is 0, then the real pagesize
 446  *              and the eraseize are determined from the
 447  *              extended id bytes in the chip
 448  * @erasesize:  Size of an erase block in the flash device.
 449  * @chipsize:   Total chipsize in Mega Bytes
 450  * @options:    Bitfield to store chip relevant options
 451  */
 452 struct nand_flash_dev {
 453         char *name;
 454         int id;
 455         unsigned long pagesize;
 456         unsigned long chipsize;
 457         unsigned long erasesize;
 458         unsigned long options;
 459 };
 460
 461 /**
 462  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 463  * @name:       Manufacturer name
 464  * @id:         manufacturer ID code of device.
 465 */
 466 struct nand_manufacturers {
 467         int id;
 468         char * name;
 469 };
 470
 471 extern struct nand_flash_dev nand_flash_ids[];
 472 extern struct nand_manufacturers nand_manuf_ids[];
 473
 474 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 475 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 476 extern int nand_default_bbt(struct mtd_info *mtd);
 477 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 478 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 479                            int allowbbt);
 480 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 481                         size_t * retlen, uint8_t * buf);
 482
 483 /**
 484  * struct platform_nand_chip - chip level device structure
 485  * @nr_chips:           max. number of chips to scan for
 486  * @chip_offset:        chip number offset
 487  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 488  * @partitions:         mtd partition list
 489  * @chip_delay:         R/B delay value in us
 490  * @options:            Option flags, e.g. 16bit buswidth
 491  * @ecclayout:          ecc layout info structure
 492  * @part_probe_types:   NULL-terminated array of probe types
 493  * @set_parts:          platform specific function to set partitions
 494  * @priv:               hardware controller specific settings
 495  */
 496 struct platform_nand_chip {
 497         int                     nr_chips;
 498         int                     chip_offset;
 499         int                     nr_partitions;
 500         struct mtd_partition    *partitions;
 501         struct nand_ecclayout   *ecclayout;
 502         int                     chip_delay;
 503         unsigned int            options;
 504         const char              **part_probe_types;
 505         void                    (*set_parts)(uint64_t size,
 506                                         struct platform_nand_chip *chip);
 507         void                    *priv;
 508 };
 509
 510 /* Keep gcc happy */
 511 struct platform_device;
 512
 513 /**
 514  * struct platform_nand_ctrl - controller level device structure
 515  * @probe:              platform specific function to probe/setup hardware
 516  * @remove:             platform specific function to remove/teardown hardware
 517  * @hwcontrol:          platform specific hardware control structure
 518  * @dev_ready:          platform specific function to read ready/busy pin
 519  * @select_chip:        platform specific chip select function
 520  * @cmd_ctrl:           platform specific function for controlling
 521  *                      ALE/CLE/nCE. Also used to write command and address
 522  * @write_buf:          platform specific function for write buffer
 523  * @read_buf:           platform specific function for read buffer
 524  * @priv:               private data to transport driver specific settings
 525  *
 526  * All fields are optional and depend on the hardware driver requirements
 527  */
 528 struct platform_nand_ctrl {
 529         int             (*probe)(struct platform_device *pdev);
 530         void            (*remove)(struct platform_device *pdev);
 531         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 532         int             (*dev_ready)(struct mtd_info *mtd);
 533         void            (*select_chip)(struct mtd_info *mtd, int chip);
 534         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 535                                     unsigned int ctrl);
 536         void            (*write_buf)(struct mtd_info *mtd,
 537                                     const uint8_t *buf, int len);
 538         void            (*read_buf)(struct mtd_info *mtd,
 539                                     uint8_t *buf, int len);
 540         void            *priv;
 541 };
 542
 543 /**
 544  * struct platform_nand_data - container structure for platform-specific data
 545  * @chip:               chip level chip structure
 546  * @ctrl:               controller level device structure
 547  */
 548 struct platform_nand_data {
 549         struct platform_nand_chip       chip;
 550         struct platform_nand_ctrl       ctrl;
 551 };
 552
 553 /* Some helpers to access the data structures */
 554 static inline
 555 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 556 {
 557         struct nand_chip *chip = mtd->priv;
 558
 559         return chip->priv;
 560 }
 561
 562 #endif /* __LINUX_MTD_NAND_H */