2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #ifndef __LINUX_MTD_SPI_NOR_H
11 #define __LINUX_MTD_SPI_NOR_H
13 #include <linux/bitops.h>
14 #include <linux/mtd/cfi.h>
15 #include <linux/mtd/mtd.h>
20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
21 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
23 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
24 #define SNOR_MFR_INTEL CFI_MFR_INTEL
25 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
26 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
27 #define SNOR_MFR_SPANSION CFI_MFR_AMD
28 #define SNOR_MFR_SST CFI_MFR_SST
29 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
32 * Note on opcode nomenclature: some opcodes have a format like
33 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
34 * of I/O lines used for the opcode, address, and data (respectively). The
35 * FUNCTION has an optional suffix of '4', to represent an opcode which
36 * requires a 4-byte (32-bit) address.
40 #define SPINOR_OP_WREN 0x06 /* Write enable */
41 #define SPINOR_OP_RDSR 0x05 /* Read status register */
42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
43 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
44 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
45 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
46 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
47 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
48 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
49 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
50 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
51 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
52 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
53 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
54 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
55 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
57 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
58 #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
59 #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
60 #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
61 #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
62 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
63 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
65 /* Used for SST flashes only. */
66 #define SPINOR_OP_BP 0x02 /* Byte program */
67 #define SPINOR_OP_WRDI 0x04 /* Write disable */
68 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
70 /* Used for Macronix and Winbond flashes. */
71 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
72 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
74 /* Used for Spansion flashes only. */
75 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
77 /* Used for Micron flashes only. */
78 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
79 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
81 /* Status Register bits. */
82 #define SR_WIP BIT(0) /* Write in progress */
83 #define SR_WEL BIT(1) /* Write enable latch */
84 /* meaning of other SR_* bits may differ between vendors */
85 #define SR_BP0 BIT(2) /* Block protect 0 */
86 #define SR_BP1 BIT(3) /* Block protect 1 */
87 #define SR_BP2 BIT(4) /* Block protect 2 */
88 #define SR_TB BIT(5) /* Top/Bottom protect */
89 #define SR_SRWD BIT(7) /* SR write protect */
91 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
93 /* Enhanced Volatile Configuration Register bits */
94 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
96 /* Flag Status Register bits */
97 #define FSR_READY BIT(7)
99 /* Configuration Register bits. */
100 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
109 #define SPI_NOR_MAX_CMD_SIZE 8
111 SPI_NOR_OPS_READ
= 0,
118 enum spi_nor_option_flags
{
119 SNOR_F_USE_FSR
= BIT(0),
120 SNOR_F_HAS_SR_TB
= BIT(1),
124 * struct spi_nor - Structure for defining a the SPI NOR layer
125 * @mtd: point to a mtd_info structure
126 * @lock: the lock for the read/write/erase/lock/unlock operations
127 * @dev: point to a spi device, or a spi nor controller device.
128 * @page_size: the page size of the SPI NOR
129 * @addr_width: number of address bytes
130 * @erase_opcode: the opcode for erasing a sector
131 * @read_opcode: the read opcode
132 * @read_dummy: the dummy needed by the read operation
133 * @program_opcode: the program opcode
134 * @flash_read: the mode of the read
135 * @sst_write_second: used by the SST write operation
136 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
137 * @cmd_buf: used by the write_reg
138 * @prepare: [OPTIONAL] do some preparations for the
139 * read/write/erase/lock/unlock operations
140 * @unprepare: [OPTIONAL] do some post work after the
141 * read/write/erase/lock/unlock operations
142 * @read_reg: [DRIVER-SPECIFIC] read out the register
143 * @write_reg: [DRIVER-SPECIFIC] write data to the register
144 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
145 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
146 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
147 * at the offset @offs; if not provided by the driver,
148 * spi-nor will send the erase opcode via write_reg()
149 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
150 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
151 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
153 * @priv: the private data
165 enum read_mode flash_read
;
166 bool sst_write_second
;
168 u8 cmd_buf
[SPI_NOR_MAX_CMD_SIZE
];
170 int (*prepare
)(struct spi_nor
*nor
, enum spi_nor_ops ops
);
171 void (*unprepare
)(struct spi_nor
*nor
, enum spi_nor_ops ops
);
172 int (*read_reg
)(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
);
173 int (*write_reg
)(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
);
175 int (*read
)(struct spi_nor
*nor
, loff_t from
,
176 size_t len
, size_t *retlen
, u_char
*read_buf
);
177 void (*write
)(struct spi_nor
*nor
, loff_t to
,
178 size_t len
, size_t *retlen
, const u_char
*write_buf
);
179 int (*erase
)(struct spi_nor
*nor
, loff_t offs
);
181 int (*flash_lock
)(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
);
182 int (*flash_unlock
)(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
);
183 int (*flash_is_locked
)(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
);
188 static inline void spi_nor_set_flash_node(struct spi_nor
*nor
,
189 struct device_node
*np
)
191 mtd_set_of_node(&nor
->mtd
, np
);
194 static inline struct device_node
*spi_nor_get_flash_node(struct spi_nor
*nor
)
196 return mtd_get_of_node(&nor
->mtd
);
200 * spi_nor_scan() - scan the SPI NOR
201 * @nor: the spi_nor structure
202 * @name: the chip type name
203 * @mode: the read mode supported by the driver
205 * The drivers can use this fuction to scan the SPI NOR.
206 * In the scanning, it will try to get all the necessary information to
207 * fill the mtd_info{} and the spi_nor{}.
209 * The chip type name can be provided through the @name parameter.
211 * Return: 0 for success, others for failure.
213 int spi_nor_scan(struct spi_nor
*nor
, const char *name
, enum read_mode mode
);
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