2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
21 NVME_REG_CAP
= 0x0000, /* Controller Capabilities */
22 NVME_REG_VS
= 0x0008, /* Version */
23 NVME_REG_INTMS
= 0x000c, /* Interrupt Mask Set */
24 NVME_REG_INTMC
= 0x0010, /* Interrupt Mask Clear */
25 NVME_REG_CC
= 0x0014, /* Controller Configuration */
26 NVME_REG_CSTS
= 0x001c, /* Controller Status */
27 NVME_REG_NSSR
= 0x0020, /* NVM Subsystem Reset */
28 NVME_REG_AQA
= 0x0024, /* Admin Queue Attributes */
29 NVME_REG_ASQ
= 0x0028, /* Admin SQ Base Address */
30 NVME_REG_ACQ
= 0x0030, /* Admin CQ Base Address */
31 NVME_REG_CMBLOC
= 0x0038, /* Controller Memory Buffer Location */
32 NVME_REG_CMBSZ
= 0x003c, /* Controller Memory Buffer Size */
35 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
36 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
37 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
38 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
39 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
40 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
42 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
43 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
44 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
45 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
47 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
48 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
49 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
50 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
51 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
54 * Submission and Completion Queue Entry Sizes for the NVM command set.
55 * (In bytes and specified as a power of two (2^n)).
57 #define NVME_NVM_IOSQES 6
58 #define NVME_NVM_IOCQES 4
61 NVME_CC_ENABLE
= 1 << 0,
62 NVME_CC_CSS_NVM
= 0 << 4,
63 NVME_CC_MPS_SHIFT
= 7,
64 NVME_CC_ARB_RR
= 0 << 11,
65 NVME_CC_ARB_WRRU
= 1 << 11,
66 NVME_CC_ARB_VS
= 7 << 11,
67 NVME_CC_SHN_NONE
= 0 << 14,
68 NVME_CC_SHN_NORMAL
= 1 << 14,
69 NVME_CC_SHN_ABRUPT
= 2 << 14,
70 NVME_CC_SHN_MASK
= 3 << 14,
71 NVME_CC_IOSQES
= NVME_NVM_IOSQES
<< 16,
72 NVME_CC_IOCQES
= NVME_NVM_IOCQES
<< 20,
73 NVME_CSTS_RDY
= 1 << 0,
74 NVME_CSTS_CFS
= 1 << 1,
75 NVME_CSTS_NSSRO
= 1 << 4,
76 NVME_CSTS_SHST_NORMAL
= 0 << 2,
77 NVME_CSTS_SHST_OCCUR
= 1 << 2,
78 NVME_CSTS_SHST_CMPLT
= 2 << 2,
79 NVME_CSTS_SHST_MASK
= 3 << 2,
82 struct nvme_id_power_state
{
83 __le16 max_power
; /* centiwatts */
86 __le32 entry_lat
; /* microseconds */
87 __le32 exit_lat
; /* microseconds */
96 __u8 active_work_scale
;
101 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
102 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
105 struct nvme_id_ctrl
{
149 struct nvme_id_power_state psd
[32];
154 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
155 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
156 NVME_CTRL_ONCS_DSM
= 1 << 2,
157 NVME_CTRL_VWC_PRESENT
= 1 << 0,
191 struct nvme_lbaf lbaf
[16];
197 NVME_NS_FEAT_THIN
= 1 << 0,
198 NVME_NS_FLBAS_LBA_MASK
= 0xf,
199 NVME_NS_FLBAS_META_EXT
= 0x10,
200 NVME_LBAF_RP_BEST
= 0,
201 NVME_LBAF_RP_BETTER
= 1,
202 NVME_LBAF_RP_GOOD
= 2,
203 NVME_LBAF_RP_DEGRADED
= 3,
204 NVME_NS_DPC_PI_LAST
= 1 << 4,
205 NVME_NS_DPC_PI_FIRST
= 1 << 3,
206 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
207 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
208 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
209 NVME_NS_DPS_PI_FIRST
= 1 << 3,
210 NVME_NS_DPS_PI_MASK
= 0x7,
211 NVME_NS_DPS_PI_TYPE1
= 1,
212 NVME_NS_DPS_PI_TYPE2
= 2,
213 NVME_NS_DPS_PI_TYPE3
= 3,
216 struct nvme_smart_log
{
217 __u8 critical_warning
;
223 __u8 data_units_read
[16];
224 __u8 data_units_written
[16];
226 __u8 host_writes
[16];
227 __u8 ctrl_busy_time
[16];
228 __u8 power_cycles
[16];
229 __u8 power_on_hours
[16];
230 __u8 unsafe_shutdowns
[16];
231 __u8 media_errors
[16];
232 __u8 num_err_log_entries
[16];
233 __le32 warning_temp_time
;
234 __le32 critical_comp_time
;
235 __le16 temp_sensor
[8];
240 NVME_SMART_CRIT_SPARE
= 1 << 0,
241 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
242 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
243 NVME_SMART_CRIT_MEDIA
= 1 << 3,
244 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
248 NVME_AER_NOTICE_NS_CHANGED
= 0x0002,
251 struct nvme_lba_range_type
{
262 NVME_LBART_TYPE_FS
= 0x01,
263 NVME_LBART_TYPE_RAID
= 0x02,
264 NVME_LBART_TYPE_CACHE
= 0x03,
265 NVME_LBART_TYPE_SWAP
= 0x04,
267 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
268 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
271 struct nvme_reservation_status
{
287 enum nvme_async_event_type
{
288 NVME_AER_TYPE_ERROR
= 0,
289 NVME_AER_TYPE_SMART
= 1,
290 NVME_AER_TYPE_NOTICE
= 2,
296 nvme_cmd_flush
= 0x00,
297 nvme_cmd_write
= 0x01,
298 nvme_cmd_read
= 0x02,
299 nvme_cmd_write_uncor
= 0x04,
300 nvme_cmd_compare
= 0x05,
301 nvme_cmd_write_zeroes
= 0x08,
303 nvme_cmd_resv_register
= 0x0d,
304 nvme_cmd_resv_report
= 0x0e,
305 nvme_cmd_resv_acquire
= 0x11,
306 nvme_cmd_resv_release
= 0x15,
310 * Lowest two bits of our flags field (FUSE field in the spec):
312 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
313 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
315 * Highest two bits in our flags field (PSDT field in the spec):
317 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
318 * If used, MPTR contains addr of single physical buffer (byte aligned).
319 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
320 * If used, MPTR contains an address of an SGL segment containing
321 * exactly 1 SGL descriptor (qword aligned).
324 NVME_CMD_FUSE_FIRST
= (1 << 0),
325 NVME_CMD_FUSE_SECOND
= (1 << 1),
327 NVME_CMD_SGL_METABUF
= (1 << 6),
328 NVME_CMD_SGL_METASEG
= (1 << 7),
329 NVME_CMD_SGL_ALL
= NVME_CMD_SGL_METABUF
| NVME_CMD_SGL_METASEG
,
332 struct nvme_common_command
{
344 struct nvme_rw_command
{
363 NVME_RW_LR
= 1 << 15,
364 NVME_RW_FUA
= 1 << 14,
365 NVME_RW_DSM_FREQ_UNSPEC
= 0,
366 NVME_RW_DSM_FREQ_TYPICAL
= 1,
367 NVME_RW_DSM_FREQ_RARE
= 2,
368 NVME_RW_DSM_FREQ_READS
= 3,
369 NVME_RW_DSM_FREQ_WRITES
= 4,
370 NVME_RW_DSM_FREQ_RW
= 5,
371 NVME_RW_DSM_FREQ_ONCE
= 6,
372 NVME_RW_DSM_FREQ_PREFETCH
= 7,
373 NVME_RW_DSM_FREQ_TEMP
= 8,
374 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
375 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
376 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
377 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
378 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
379 NVME_RW_DSM_COMPRESSED
= 1 << 7,
380 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
381 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
382 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
383 NVME_RW_PRINFO_PRACT
= 1 << 13,
386 struct nvme_dsm_cmd
{
400 NVME_DSMGMT_IDR
= 1 << 0,
401 NVME_DSMGMT_IDW
= 1 << 1,
402 NVME_DSMGMT_AD
= 1 << 2,
405 struct nvme_dsm_range
{
413 enum nvme_admin_opcode
{
414 nvme_admin_delete_sq
= 0x00,
415 nvme_admin_create_sq
= 0x01,
416 nvme_admin_get_log_page
= 0x02,
417 nvme_admin_delete_cq
= 0x04,
418 nvme_admin_create_cq
= 0x05,
419 nvme_admin_identify
= 0x06,
420 nvme_admin_abort_cmd
= 0x08,
421 nvme_admin_set_features
= 0x09,
422 nvme_admin_get_features
= 0x0a,
423 nvme_admin_async_event
= 0x0c,
424 nvme_admin_activate_fw
= 0x10,
425 nvme_admin_download_fw
= 0x11,
426 nvme_admin_format_nvm
= 0x80,
427 nvme_admin_security_send
= 0x81,
428 nvme_admin_security_recv
= 0x82,
432 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
433 NVME_CQ_IRQ_ENABLED
= (1 << 1),
434 NVME_SQ_PRIO_URGENT
= (0 << 1),
435 NVME_SQ_PRIO_HIGH
= (1 << 1),
436 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
437 NVME_SQ_PRIO_LOW
= (3 << 1),
438 NVME_FEAT_ARBITRATION
= 0x01,
439 NVME_FEAT_POWER_MGMT
= 0x02,
440 NVME_FEAT_LBA_RANGE
= 0x03,
441 NVME_FEAT_TEMP_THRESH
= 0x04,
442 NVME_FEAT_ERR_RECOVERY
= 0x05,
443 NVME_FEAT_VOLATILE_WC
= 0x06,
444 NVME_FEAT_NUM_QUEUES
= 0x07,
445 NVME_FEAT_IRQ_COALESCE
= 0x08,
446 NVME_FEAT_IRQ_CONFIG
= 0x09,
447 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
448 NVME_FEAT_ASYNC_EVENT
= 0x0b,
449 NVME_FEAT_AUTO_PST
= 0x0c,
450 NVME_FEAT_SW_PROGRESS
= 0x80,
451 NVME_FEAT_HOST_ID
= 0x81,
452 NVME_FEAT_RESV_MASK
= 0x82,
453 NVME_FEAT_RESV_PERSIST
= 0x83,
454 NVME_LOG_ERROR
= 0x01,
455 NVME_LOG_SMART
= 0x02,
456 NVME_LOG_FW_SLOT
= 0x03,
457 NVME_LOG_RESERVATION
= 0x80,
458 NVME_FWACT_REPL
= (0 << 3),
459 NVME_FWACT_REPL_ACTV
= (1 << 3),
460 NVME_FWACT_ACTV
= (2 << 3),
463 struct nvme_identify
{
475 struct nvme_features
{
488 struct nvme_create_cq
{
502 struct nvme_create_sq
{
516 struct nvme_delete_queue
{
526 struct nvme_abort_cmd
{
536 struct nvme_download_firmware
{
548 struct nvme_format_cmd
{
558 struct nvme_get_log_page_command
{
576 struct nvme_command
{
578 struct nvme_common_command common
;
579 struct nvme_rw_command rw
;
580 struct nvme_identify identify
;
581 struct nvme_features features
;
582 struct nvme_create_cq create_cq
;
583 struct nvme_create_sq create_sq
;
584 struct nvme_delete_queue delete_queue
;
585 struct nvme_download_firmware dlfw
;
586 struct nvme_format_cmd format
;
587 struct nvme_dsm_cmd dsm
;
588 struct nvme_abort_cmd abort
;
589 struct nvme_get_log_page_command get_log_page
;
593 static inline bool nvme_is_write(struct nvme_command
*cmd
)
595 return cmd
->common
.opcode
& 1;
599 NVME_SC_SUCCESS
= 0x0,
600 NVME_SC_INVALID_OPCODE
= 0x1,
601 NVME_SC_INVALID_FIELD
= 0x2,
602 NVME_SC_CMDID_CONFLICT
= 0x3,
603 NVME_SC_DATA_XFER_ERROR
= 0x4,
604 NVME_SC_POWER_LOSS
= 0x5,
605 NVME_SC_INTERNAL
= 0x6,
606 NVME_SC_ABORT_REQ
= 0x7,
607 NVME_SC_ABORT_QUEUE
= 0x8,
608 NVME_SC_FUSED_FAIL
= 0x9,
609 NVME_SC_FUSED_MISSING
= 0xa,
610 NVME_SC_INVALID_NS
= 0xb,
611 NVME_SC_CMD_SEQ_ERROR
= 0xc,
612 NVME_SC_SGL_INVALID_LAST
= 0xd,
613 NVME_SC_SGL_INVALID_COUNT
= 0xe,
614 NVME_SC_SGL_INVALID_DATA
= 0xf,
615 NVME_SC_SGL_INVALID_METADATA
= 0x10,
616 NVME_SC_SGL_INVALID_TYPE
= 0x11,
617 NVME_SC_LBA_RANGE
= 0x80,
618 NVME_SC_CAP_EXCEEDED
= 0x81,
619 NVME_SC_NS_NOT_READY
= 0x82,
620 NVME_SC_RESERVATION_CONFLICT
= 0x83,
621 NVME_SC_CQ_INVALID
= 0x100,
622 NVME_SC_QID_INVALID
= 0x101,
623 NVME_SC_QUEUE_SIZE
= 0x102,
624 NVME_SC_ABORT_LIMIT
= 0x103,
625 NVME_SC_ABORT_MISSING
= 0x104,
626 NVME_SC_ASYNC_LIMIT
= 0x105,
627 NVME_SC_FIRMWARE_SLOT
= 0x106,
628 NVME_SC_FIRMWARE_IMAGE
= 0x107,
629 NVME_SC_INVALID_VECTOR
= 0x108,
630 NVME_SC_INVALID_LOG_PAGE
= 0x109,
631 NVME_SC_INVALID_FORMAT
= 0x10a,
632 NVME_SC_FIRMWARE_NEEDS_RESET
= 0x10b,
633 NVME_SC_INVALID_QUEUE
= 0x10c,
634 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
635 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
636 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
637 NVME_SC_FW_NEEDS_RESET_SUBSYS
= 0x110,
638 NVME_SC_BAD_ATTRIBUTES
= 0x180,
639 NVME_SC_INVALID_PI
= 0x181,
640 NVME_SC_READ_ONLY
= 0x182,
641 NVME_SC_WRITE_FAULT
= 0x280,
642 NVME_SC_READ_ERROR
= 0x281,
643 NVME_SC_GUARD_CHECK
= 0x282,
644 NVME_SC_APPTAG_CHECK
= 0x283,
645 NVME_SC_REFTAG_CHECK
= 0x284,
646 NVME_SC_COMPARE_FAILED
= 0x285,
647 NVME_SC_ACCESS_DENIED
= 0x286,
648 NVME_SC_DNR
= 0x4000,
651 struct nvme_completion
{
652 __le32 result
; /* Used by admin commands to return data */
654 __le16 sq_head
; /* how much of this queue may be reclaimed */
655 __le16 sq_id
; /* submission queue that generated this entry */
656 __u16 command_id
; /* of the command which completed */
657 __le16 status
; /* did the command fail, and if so, why? */
660 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
662 #endif /* _LINUX_NVME_H */