include/linux/omap-gpmc.h

   1 /*
   2  *  OMAP GPMC (General Purpose Memory Controller) defines
   3  *
   4  *  This program is free software; you can redistribute  it and/or modify it
   5  *  under  the terms of  the GNU General  Public License as published by the
   6  *  Free Software Foundation;  either version 2 of the  License, or (at your
   7  *  option) any later version.
   8  */
   9
  10 /* Maximum Number of Chip Selects */
  11 #define GPMC_CS_NUM             8
  12
  13 #define GPMC_CONFIG_WP          0x00000005
  14
  15 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
  16 #define GPMC_IRQ_COUNT_EVENT            0x02
  17
  18 #define GPMC_BURST_4                    4       /* 4 word burst */
  19 #define GPMC_BURST_8                    8       /* 8 word burst */
  20 #define GPMC_BURST_16                   16      /* 16 word burst */
  21 #define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
  22 #define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
  23 #define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
  24 #define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
  25
  26 /* bool type time settings */
  27 struct gpmc_bool_timings {
  28         bool cycle2cyclediffcsen;
  29         bool cycle2cyclesamecsen;
  30         bool we_extra_delay;
  31         bool oe_extra_delay;
  32         bool adv_extra_delay;
  33         bool cs_extra_delay;
  34         bool time_para_granularity;
  35 };
  36
  37 /*
  38  * Note that all values in this struct are in nanoseconds except sync_clk
  39  * (which is in picoseconds), while the register values are in gpmc_fck cycles.
  40  */
  41 struct gpmc_timings {
  42         /* Minimum clock period for synchronous mode (in picoseconds) */
  43         u32 sync_clk;
  44
  45         /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
  46         u32 cs_on;              /* Assertion time */
  47         u32 cs_rd_off;          /* Read deassertion time */
  48         u32 cs_wr_off;          /* Write deassertion time */
  49
  50         /* ADV signal timings corresponding to GPMC_CONFIG3 */
  51         u32 adv_on;             /* Assertion time */
  52         u32 adv_rd_off;         /* Read deassertion time */
  53         u32 adv_wr_off;         /* Write deassertion time */
  54         u32 adv_aad_mux_on;     /* ADV assertion time for AAD */
  55         u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
  56         u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
  57
  58         /* WE signals timings corresponding to GPMC_CONFIG4 */
  59         u32 we_on;              /* WE assertion time */
  60         u32 we_off;             /* WE deassertion time */
  61
  62         /* OE signals timings corresponding to GPMC_CONFIG4 */
  63         u32 oe_on;              /* OE assertion time */
  64         u32 oe_off;             /* OE deassertion time */
  65         u32 oe_aad_mux_on;      /* OE assertion time for AAD */
  66         u32 oe_aad_mux_off;     /* OE deassertion time for AAD */
  67
  68         /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
  69         u32 page_burst_access;  /* Multiple access word delay */
  70         u32 access;             /* Start-cycle to first data valid delay */
  71         u32 rd_cycle;           /* Total read cycle time */
  72         u32 wr_cycle;           /* Total write cycle time */
  73
  74         u32 bus_turnaround;
  75         u32 cycle2cycle_delay;
  76
  77         u32 wait_monitoring;
  78         u32 clk_activation;
  79
  80         /* The following are only on OMAP3430 */
  81         u32 wr_access;          /* WRACCESSTIME */
  82         u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
  83
  84         struct gpmc_bool_timings bool_timings;
  85 };
  86
  87 /* Device timings in picoseconds */
  88 struct gpmc_device_timings {
  89         u32 t_ceasu;    /* address setup to CS valid */
  90         u32 t_avdasu;   /* address setup to ADV valid */
  91         /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
  92          * of tusb using these timings even for sync whilst
  93          * ideally for adv_rd/(wr)_off it should have considered
  94          * t_avdh instead. This indirectly necessitates r/w
  95          * variations of t_avdp as it is possible to have one
  96          * sync & other async
  97          */
  98         u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
  99         u32 t_avdp_w;
 100         u32 t_aavdh;    /* address hold time */
 101         u32 t_oeasu;    /* address setup to OE valid */
 102         u32 t_aa;       /* access time from ADV assertion */
 103         u32 t_iaa;      /* initial access time */
 104         u32 t_oe;       /* access time from OE assertion */
 105         u32 t_ce;       /* access time from CS asertion */
 106         u32 t_rd_cycle; /* read cycle time */
 107         u32 t_cez_r;    /* read CS deassertion to high Z */
 108         u32 t_cez_w;    /* write CS deassertion to high Z */
 109         u32 t_oez;      /* OE deassertion to high Z */
 110         u32 t_weasu;    /* address setup to WE valid */
 111         u32 t_wpl;      /* write assertion time */
 112         u32 t_wph;      /* write deassertion time */
 113         u32 t_wr_cycle; /* write cycle time */
 114
 115         u32 clk;
 116         u32 t_bacc;     /* burst access valid clock to output delay */
 117         u32 t_ces;      /* CS setup time to clk */
 118         u32 t_avds;     /* ADV setup time to clk */
 119         u32 t_avdh;     /* ADV hold time from clk */
 120         u32 t_ach;      /* address hold time from clk */
 121         u32 t_rdyo;     /* clk to ready valid */
 122
 123         u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
 124         u32 t_ce_avd;   /* CS on to ADV on delay */
 125
 126         /* XXX: check the possibility of combining
 127          * cyc_aavhd_oe & cyc_aavdh_we
 128          */
 129         u8 cyc_aavdh_oe;/* read address hold time in cycles */
 130         u8 cyc_aavdh_we;/* write address hold time in cycles */
 131         u8 cyc_oe;      /* access time from OE assertion in cycles */
 132         u8 cyc_wpl;     /* write deassertion time in cycles */
 133         u32 cyc_iaa;    /* initial access time in cycles */
 134
 135         /* extra delays */
 136         bool ce_xdelay;
 137         bool avd_xdelay;
 138         bool oe_xdelay;
 139         bool we_xdelay;
 140 };
 141
 142 struct gpmc_settings {
 143         bool burst_wrap;        /* enables wrap bursting */
 144         bool burst_read;        /* enables read page/burst mode */
 145         bool burst_write;       /* enables write page/burst mode */
 146         bool device_nand;       /* device is NAND */
 147         bool sync_read;         /* enables synchronous reads */
 148         bool sync_write;        /* enables synchronous writes */
 149         bool wait_on_read;      /* monitor wait on reads */
 150         bool wait_on_write;     /* monitor wait on writes */
 151         u32 burst_len;          /* page/burst length */
 152         u32 device_width;       /* device bus width (8 or 16 bit) */
 153         u32 mux_add_data;       /* multiplex address & data */
 154         u32 wait_pin;           /* wait-pin to be used */
 155 };
 156
 157 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
 158                              struct gpmc_settings *gpmc_s,
 159                              struct gpmc_device_timings *dev_t);
 160
 161 struct gpmc_nand_regs;
 162 struct device_node;
 163
 164 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 165 extern int gpmc_get_client_irq(unsigned irq_config);
 166
 167 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
 168
 169 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 170 extern int gpmc_calc_divider(unsigned int sync_clk);
 171 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 172                                const struct gpmc_settings *s);
 173 extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 174 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 175 extern void gpmc_cs_free(int cs);
 176 extern int gpmc_configure(int cmd, int wval);
 177 extern void gpmc_read_settings_dt(struct device_node *np,
 178                                   struct gpmc_settings *p);
 179
 180 extern void omap3_gpmc_save_context(void);
 181 extern void omap3_gpmc_restore_context(void);
 182
 183 struct gpmc_timings;
 184 struct omap_nand_platform_data;
 185 struct omap_onenand_platform_data;
 186
 187 #if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
 188 extern int gpmc_nand_init(struct omap_nand_platform_data *d,
 189                           struct gpmc_timings *gpmc_t);
 190 #else
 191 static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
 192                                  struct gpmc_timings *gpmc_t)
 193 {
 194         return 0;
 195 }
 196 #endif
 197
 198 #if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
 199 extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
 200 #else
 201 #define board_onenand_data      NULL
 202 static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
 203 {
 204 }
 205 #endif