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ELF loader support for auxvec base platform string
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54
55 /* Include the ID list */
56 #include <linux/pci_ids.h>
57
58 /* pci_slot represents a physical slot */
59 struct pci_slot {
60 struct pci_bus *bus; /* The bus this slot is on */
61 struct list_head list; /* node in list of slots on this bus */
62 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
63 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 struct kobject kobj;
65 };
66
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
68 enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71 };
72
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
78
79 #define DEVICE_COUNT_RESOURCE 12
80
81 typedef int __bitwise pci_power_t;
82
83 #define PCI_D0 ((pci_power_t __force) 0)
84 #define PCI_D1 ((pci_power_t __force) 1)
85 #define PCI_D2 ((pci_power_t __force) 2)
86 #define PCI_D3hot ((pci_power_t __force) 3)
87 #define PCI_D3cold ((pci_power_t __force) 4)
88 #define PCI_UNKNOWN ((pci_power_t __force) 5)
89 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
90
91 /** The pci_channel state describes connectivity between the CPU and
92 * the pci device. If some PCI bus between here and the pci device
93 * has crashed or locked up, this info is reflected here.
94 */
95 typedef unsigned int __bitwise pci_channel_state_t;
96
97 enum pci_channel_state {
98 /* I/O channel is in normal state */
99 pci_channel_io_normal = (__force pci_channel_state_t) 1,
100
101 /* I/O to channel is blocked */
102 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
103
104 /* PCI card is dead */
105 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
106 };
107
108 typedef unsigned int __bitwise pcie_reset_state_t;
109
110 enum pcie_reset_state {
111 /* Reset is NOT asserted (Use to deassert reset) */
112 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
113
114 /* Use #PERST to reset PCI-E device */
115 pcie_warm_reset = (__force pcie_reset_state_t) 2,
116
117 /* Use PCI-E Hot Reset to reset device */
118 pcie_hot_reset = (__force pcie_reset_state_t) 3
119 };
120
121 typedef unsigned short __bitwise pci_dev_flags_t;
122 enum pci_dev_flags {
123 /* INTX_DISABLE in PCI_COMMAND register disables MSI
124 * generation too.
125 */
126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
127 };
128
129 typedef unsigned short __bitwise pci_bus_flags_t;
130 enum pci_bus_flags {
131 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
132 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
133 };
134
135 struct pci_cap_saved_state {
136 struct hlist_node next;
137 char cap_nr;
138 u32 data[0];
139 };
140
141 struct pcie_link_state;
142 struct pci_vpd;
143
144 /*
145 * The pci_dev structure is used to describe PCI devices.
146 */
147 struct pci_dev {
148 struct list_head bus_list; /* node in per-bus list */
149 struct pci_bus *bus; /* bus this device is on */
150 struct pci_bus *subordinate; /* bus this device bridges to */
151
152 void *sysdata; /* hook for sys-specific extension */
153 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
154 struct pci_slot *slot; /* Physical slot this device is in */
155
156 unsigned int devfn; /* encoded device & function index */
157 unsigned short vendor;
158 unsigned short device;
159 unsigned short subsystem_vendor;
160 unsigned short subsystem_device;
161 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
162 u8 revision; /* PCI revision, low byte of class word */
163 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
164 u8 pcie_type; /* PCI-E device/port type */
165 u8 rom_base_reg; /* which config register controls the ROM */
166 u8 pin; /* which interrupt pin this device uses */
167
168 struct pci_driver *driver; /* which driver has allocated this device */
169 u64 dma_mask; /* Mask of the bits of bus address this
170 device implements. Normally this is
171 0xffffffff. You only need to change
172 this if your device has broken DMA
173 or supports 64-bit transfers. */
174
175 struct device_dma_parameters dma_parms;
176
177 pci_power_t current_state; /* Current operating state. In ACPI-speak,
178 this is D0-D3, D0 being fully functional,
179 and D3 being off. */
180 int pm_cap; /* PM capability offset in the
181 configuration space */
182 unsigned int pme_support:5; /* Bitmask of states from which PME#
183 can be generated */
184 unsigned int d1_support:1; /* Low power state D1 is supported */
185 unsigned int d2_support:1; /* Low power state D2 is supported */
186 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
187
188 #ifdef CONFIG_PCIEASPM
189 struct pcie_link_state *link_state; /* ASPM link state. */
190 #endif
191
192 pci_channel_state_t error_state; /* current connectivity state */
193 struct device dev; /* Generic device interface */
194
195 int cfg_size; /* Size of configuration space */
196
197 /*
198 * Instead of touching interrupt line and base address registers
199 * directly, use the values stored here. They might be different!
200 */
201 unsigned int irq;
202 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
203
204 /* These fields are used by common fixups */
205 unsigned int transparent:1; /* Transparent PCI bridge */
206 unsigned int multifunction:1;/* Part of multi-function device */
207 /* keep track of device state */
208 unsigned int is_added:1;
209 unsigned int is_busmaster:1; /* device is busmaster */
210 unsigned int no_msi:1; /* device may not use msi */
211 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
212 unsigned int broken_parity_status:1; /* Device generates false positive parity */
213 unsigned int msi_enabled:1;
214 unsigned int msix_enabled:1;
215 unsigned int is_managed:1;
216 unsigned int is_pcie:1;
217 pci_dev_flags_t dev_flags;
218 atomic_t enable_cnt; /* pci_enable_device has been called */
219
220 u32 saved_config_space[16]; /* config space saved at suspend time */
221 struct hlist_head saved_cap_space;
222 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
223 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
224 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
225 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
226 #ifdef CONFIG_PCI_MSI
227 struct list_head msi_list;
228 #endif
229 struct pci_vpd *vpd;
230 };
231
232 extern struct pci_dev *alloc_pci_dev(void);
233
234 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
235 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
236 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
237
238 static inline int pci_channel_offline(struct pci_dev *pdev)
239 {
240 return (pdev->error_state != pci_channel_io_normal);
241 }
242
243 static inline struct pci_cap_saved_state *pci_find_saved_cap(
244 struct pci_dev *pci_dev, char cap)
245 {
246 struct pci_cap_saved_state *tmp;
247 struct hlist_node *pos;
248
249 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
250 if (tmp->cap_nr == cap)
251 return tmp;
252 }
253 return NULL;
254 }
255
256 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
257 struct pci_cap_saved_state *new_cap)
258 {
259 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
260 }
261
262 /*
263 * For PCI devices, the region numbers are assigned this way:
264 *
265 * 0-5 standard PCI regions
266 * 6 expansion ROM
267 * 7-10 bridges: address space assigned to buses behind the bridge
268 */
269
270 #define PCI_ROM_RESOURCE 6
271 #define PCI_BRIDGE_RESOURCES 7
272 #define PCI_NUM_RESOURCES 11
273
274 #ifndef PCI_BUS_NUM_RESOURCES
275 #define PCI_BUS_NUM_RESOURCES 16
276 #endif
277
278 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
279
280 struct pci_bus {
281 struct list_head node; /* node in list of buses */
282 struct pci_bus *parent; /* parent bus this bridge is on */
283 struct list_head children; /* list of child buses */
284 struct list_head devices; /* list of devices on this bus */
285 struct pci_dev *self; /* bridge device as seen by parent */
286 struct list_head slots; /* list of slots on this bus */
287 struct resource *resource[PCI_BUS_NUM_RESOURCES];
288 /* address space routed to this bus */
289
290 struct pci_ops *ops; /* configuration access functions */
291 void *sysdata; /* hook for sys-specific extension */
292 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
293
294 unsigned char number; /* bus number */
295 unsigned char primary; /* number of primary bridge */
296 unsigned char secondary; /* number of secondary bridge */
297 unsigned char subordinate; /* max number of subordinate buses */
298
299 char name[48];
300
301 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
302 pci_bus_flags_t bus_flags; /* Inherited by child busses */
303 struct device *bridge;
304 struct device dev;
305 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
306 struct bin_attribute *legacy_mem; /* legacy mem */
307 unsigned int is_added:1;
308 };
309
310 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
311 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
312
313 /*
314 * Error values that may be returned by PCI functions.
315 */
316 #define PCIBIOS_SUCCESSFUL 0x00
317 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
318 #define PCIBIOS_BAD_VENDOR_ID 0x83
319 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
320 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
321 #define PCIBIOS_SET_FAILED 0x88
322 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
323
324 /* Low-level architecture-dependent routines */
325
326 struct pci_ops {
327 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
328 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
329 };
330
331 /*
332 * ACPI needs to be able to access PCI config space before we've done a
333 * PCI bus scan and created pci_bus structures.
334 */
335 extern int raw_pci_read(unsigned int domain, unsigned int bus,
336 unsigned int devfn, int reg, int len, u32 *val);
337 extern int raw_pci_write(unsigned int domain, unsigned int bus,
338 unsigned int devfn, int reg, int len, u32 val);
339
340 struct pci_bus_region {
341 resource_size_t start;
342 resource_size_t end;
343 };
344
345 struct pci_dynids {
346 spinlock_t lock; /* protects list, index */
347 struct list_head list; /* for IDs added at runtime */
348 unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */
349 };
350
351 /* ---------------------------------------------------------------- */
352 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
353 * a set of callbacks in struct pci_error_handlers, then that device driver
354 * will be notified of PCI bus errors, and will be driven to recovery
355 * when an error occurs.
356 */
357
358 typedef unsigned int __bitwise pci_ers_result_t;
359
360 enum pci_ers_result {
361 /* no result/none/not supported in device driver */
362 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
363
364 /* Device driver can recover without slot reset */
365 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
366
367 /* Device driver wants slot to be reset. */
368 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
369
370 /* Device has completely failed, is unrecoverable */
371 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
372
373 /* Device driver is fully recovered and operational */
374 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
375 };
376
377 /* PCI bus error event callbacks */
378 struct pci_error_handlers {
379 /* PCI bus error detected on this device */
380 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
381 enum pci_channel_state error);
382
383 /* MMIO has been re-enabled, but not DMA */
384 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
385
386 /* PCI Express link has been reset */
387 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
388
389 /* PCI slot has been reset */
390 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
391
392 /* Device driver may resume normal operations */
393 void (*resume)(struct pci_dev *dev);
394 };
395
396 /* ---------------------------------------------------------------- */
397
398 struct module;
399 struct pci_driver {
400 struct list_head node;
401 char *name;
402 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
403 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
404 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
405 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
406 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
407 int (*resume_early) (struct pci_dev *dev);
408 int (*resume) (struct pci_dev *dev); /* Device woken up */
409 void (*shutdown) (struct pci_dev *dev);
410 struct pm_ext_ops *pm;
411 struct pci_error_handlers *err_handler;
412 struct device_driver driver;
413 struct pci_dynids dynids;
414 };
415
416 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
417
418 /**
419 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
420 * @_table: device table name
421 *
422 * This macro is used to create a struct pci_device_id array (a device table)
423 * in a generic manner.
424 */
425 #define DEFINE_PCI_DEVICE_TABLE(_table) \
426 const struct pci_device_id _table[] __devinitconst
427
428 /**
429 * PCI_DEVICE - macro used to describe a specific pci device
430 * @vend: the 16 bit PCI Vendor ID
431 * @dev: the 16 bit PCI Device ID
432 *
433 * This macro is used to create a struct pci_device_id that matches a
434 * specific device. The subvendor and subdevice fields will be set to
435 * PCI_ANY_ID.
436 */
437 #define PCI_DEVICE(vend,dev) \
438 .vendor = (vend), .device = (dev), \
439 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
440
441 /**
442 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
443 * @dev_class: the class, subclass, prog-if triple for this device
444 * @dev_class_mask: the class mask for this device
445 *
446 * This macro is used to create a struct pci_device_id that matches a
447 * specific PCI class. The vendor, device, subvendor, and subdevice
448 * fields will be set to PCI_ANY_ID.
449 */
450 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
451 .class = (dev_class), .class_mask = (dev_class_mask), \
452 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
453 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
454
455 /**
456 * PCI_VDEVICE - macro used to describe a specific pci device in short form
457 * @vend: the vendor name
458 * @dev: the 16 bit PCI Device ID
459 *
460 * This macro is used to create a struct pci_device_id that matches a
461 * specific PCI device. The subvendor, and subdevice fields will be set
462 * to PCI_ANY_ID. The macro allows the next field to follow as the device
463 * private data.
464 */
465
466 #define PCI_VDEVICE(vendor, device) \
467 PCI_VENDOR_ID_##vendor, (device), \
468 PCI_ANY_ID, PCI_ANY_ID, 0, 0
469
470 /* these external functions are only available when PCI support is enabled */
471 #ifdef CONFIG_PCI
472
473 extern struct bus_type pci_bus_type;
474
475 /* Do NOT directly access these two variables, unless you are arch specific pci
476 * code, or pci core code. */
477 extern struct list_head pci_root_buses; /* list of all known PCI buses */
478 /* Some device drivers need know if pci is initiated */
479 extern int no_pci_devices(void);
480
481 void pcibios_fixup_bus(struct pci_bus *);
482 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
483 char *pcibios_setup(char *str);
484
485 /* Used only when drivers/pci/setup.c is used */
486 void pcibios_align_resource(void *, struct resource *, resource_size_t,
487 resource_size_t);
488 void pcibios_update_irq(struct pci_dev *, int irq);
489
490 /* Generic PCI functions used internally */
491
492 extern struct pci_bus *pci_find_bus(int domain, int busnr);
493 void pci_bus_add_devices(struct pci_bus *bus);
494 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
495 struct pci_ops *ops, void *sysdata);
496 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
497 void *sysdata)
498 {
499 struct pci_bus *root_bus;
500 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
501 if (root_bus)
502 pci_bus_add_devices(root_bus);
503 return root_bus;
504 }
505 struct pci_bus *pci_create_bus(struct device *parent, int bus,
506 struct pci_ops *ops, void *sysdata);
507 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
508 int busnr);
509 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
510 const char *name);
511 void pci_destroy_slot(struct pci_slot *slot);
512 void pci_update_slot_number(struct pci_slot *slot, int slot_nr);
513 int pci_scan_slot(struct pci_bus *bus, int devfn);
514 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
515 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
516 unsigned int pci_scan_child_bus(struct pci_bus *bus);
517 int __must_check pci_bus_add_device(struct pci_dev *dev);
518 void pci_read_bridge_bases(struct pci_bus *child);
519 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
520 struct resource *res);
521 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
522 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
523 extern void pci_dev_put(struct pci_dev *dev);
524 extern void pci_remove_bus(struct pci_bus *b);
525 extern void pci_remove_bus_device(struct pci_dev *dev);
526 extern void pci_stop_bus_device(struct pci_dev *dev);
527 void pci_setup_cardbus(struct pci_bus *bus);
528 extern void pci_sort_breadthfirst(void);
529
530 /* Generic PCI functions exported to card drivers */
531
532 #ifdef CONFIG_PCI_LEGACY
533 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
534 unsigned int device,
535 const struct pci_dev *from);
536 struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
537 unsigned int devfn);
538 #endif /* CONFIG_PCI_LEGACY */
539
540 int pci_find_capability(struct pci_dev *dev, int cap);
541 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
542 int pci_find_ext_capability(struct pci_dev *dev, int cap);
543 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
544 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
545 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
546
547 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
548 struct pci_dev *from);
549 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
550 unsigned int ss_vendor, unsigned int ss_device,
551 const struct pci_dev *from);
552 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
553 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
554 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
555 int pci_dev_present(const struct pci_device_id *ids);
556
557 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
558 int where, u8 *val);
559 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
560 int where, u16 *val);
561 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
562 int where, u32 *val);
563 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
564 int where, u8 val);
565 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
566 int where, u16 val);
567 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
568 int where, u32 val);
569
570 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
571 {
572 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
573 }
574 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
575 {
576 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
577 }
578 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
579 u32 *val)
580 {
581 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
582 }
583 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
584 {
585 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
586 }
587 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
588 {
589 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
590 }
591 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
592 u32 val)
593 {
594 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
595 }
596
597 int __must_check pci_enable_device(struct pci_dev *dev);
598 int __must_check pci_enable_device_io(struct pci_dev *dev);
599 int __must_check pci_enable_device_mem(struct pci_dev *dev);
600 int __must_check pci_reenable_device(struct pci_dev *);
601 int __must_check pcim_enable_device(struct pci_dev *pdev);
602 void pcim_pin_device(struct pci_dev *pdev);
603
604 static inline int pci_is_managed(struct pci_dev *pdev)
605 {
606 return pdev->is_managed;
607 }
608
609 void pci_disable_device(struct pci_dev *dev);
610 void pci_set_master(struct pci_dev *dev);
611 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
612 #define HAVE_PCI_SET_MWI
613 int __must_check pci_set_mwi(struct pci_dev *dev);
614 int pci_try_set_mwi(struct pci_dev *dev);
615 void pci_clear_mwi(struct pci_dev *dev);
616 void pci_intx(struct pci_dev *dev, int enable);
617 void pci_msi_off(struct pci_dev *dev);
618 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
619 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
620 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
621 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
622 int pcix_get_max_mmrbc(struct pci_dev *dev);
623 int pcix_get_mmrbc(struct pci_dev *dev);
624 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
625 int pcie_get_readrq(struct pci_dev *dev);
626 int pcie_set_readrq(struct pci_dev *dev, int rq);
627 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
628 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
629 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
630
631 /* ROM control related routines */
632 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
633 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
634 size_t pci_get_rom_size(void __iomem *rom, size_t size);
635
636 /* Power management related routines */
637 int pci_save_state(struct pci_dev *dev);
638 int pci_restore_state(struct pci_dev *dev);
639 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
640 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
641 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
642 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
643 pci_power_t pci_target_state(struct pci_dev *dev);
644 int pci_prepare_to_sleep(struct pci_dev *dev);
645 int pci_back_from_sleep(struct pci_dev *dev);
646
647 /* Functions for PCI Hotplug drivers to use */
648 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
649
650 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
651 void pci_bus_assign_resources(struct pci_bus *bus);
652 void pci_bus_size_bridges(struct pci_bus *bus);
653 int pci_claim_resource(struct pci_dev *, int);
654 void pci_assign_unassigned_resources(void);
655 void pdev_enable_device(struct pci_dev *);
656 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
657 int pci_enable_resources(struct pci_dev *, int mask);
658 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
659 int (*)(struct pci_dev *, u8, u8));
660 #define HAVE_PCI_REQ_REGIONS 2
661 int __must_check pci_request_regions(struct pci_dev *, const char *);
662 void pci_release_regions(struct pci_dev *);
663 int __must_check pci_request_region(struct pci_dev *, int, const char *);
664 void pci_release_region(struct pci_dev *, int);
665 int pci_request_selected_regions(struct pci_dev *, int, const char *);
666 void pci_release_selected_regions(struct pci_dev *, int);
667
668 /* drivers/pci/bus.c */
669 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
670 struct resource *res, resource_size_t size,
671 resource_size_t align, resource_size_t min,
672 unsigned int type_mask,
673 void (*alignf)(void *, struct resource *,
674 resource_size_t, resource_size_t),
675 void *alignf_data);
676 void pci_enable_bridges(struct pci_bus *bus);
677
678 /* Proper probing supporting hot-pluggable devices */
679 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
680 const char *mod_name);
681 static inline int __must_check pci_register_driver(struct pci_driver *driver)
682 {
683 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
684 }
685
686 void pci_unregister_driver(struct pci_driver *dev);
687 void pci_remove_behind_bridge(struct pci_dev *dev);
688 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
689 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
690 struct pci_dev *dev);
691 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
692 int pass);
693
694 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
695 void *userdata);
696 int pci_cfg_space_size_ext(struct pci_dev *dev);
697 int pci_cfg_space_size(struct pci_dev *dev);
698 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
699
700 /* kmem_cache style wrapper around pci_alloc_consistent() */
701
702 #include <linux/dmapool.h>
703
704 #define pci_pool dma_pool
705 #define pci_pool_create(name, pdev, size, align, allocation) \
706 dma_pool_create(name, &pdev->dev, size, align, allocation)
707 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
708 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
709 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
710
711 enum pci_dma_burst_strategy {
712 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
713 strategy_parameter is N/A */
714 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
715 byte boundaries */
716 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
717 strategy_parameter byte boundaries */
718 };
719
720 struct msix_entry {
721 u16 vector; /* kernel uses to write allocated vector */
722 u16 entry; /* driver uses to specify entry, OS writes */
723 };
724
725
726 #ifndef CONFIG_PCI_MSI
727 static inline int pci_enable_msi(struct pci_dev *dev)
728 {
729 return -1;
730 }
731
732 static inline void pci_msi_shutdown(struct pci_dev *dev)
733 { }
734 static inline void pci_disable_msi(struct pci_dev *dev)
735 { }
736
737 static inline int pci_enable_msix(struct pci_dev *dev,
738 struct msix_entry *entries, int nvec)
739 {
740 return -1;
741 }
742
743 static inline void pci_msix_shutdown(struct pci_dev *dev)
744 { }
745 static inline void pci_disable_msix(struct pci_dev *dev)
746 { }
747
748 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
749 { }
750
751 static inline void pci_restore_msi_state(struct pci_dev *dev)
752 { }
753 #else
754 extern int pci_enable_msi(struct pci_dev *dev);
755 extern void pci_msi_shutdown(struct pci_dev *dev);
756 extern void pci_disable_msi(struct pci_dev *dev);
757 extern int pci_enable_msix(struct pci_dev *dev,
758 struct msix_entry *entries, int nvec);
759 extern void pci_msix_shutdown(struct pci_dev *dev);
760 extern void pci_disable_msix(struct pci_dev *dev);
761 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
762 extern void pci_restore_msi_state(struct pci_dev *dev);
763 #endif
764
765 #ifdef CONFIG_HT_IRQ
766 /* The functions a driver should call */
767 int ht_create_irq(struct pci_dev *dev, int idx);
768 void ht_destroy_irq(unsigned int irq);
769 #endif /* CONFIG_HT_IRQ */
770
771 extern void pci_block_user_cfg_access(struct pci_dev *dev);
772 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
773
774 /*
775 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
776 * a PCI domain is defined to be a set of PCI busses which share
777 * configuration space.
778 */
779 #ifdef CONFIG_PCI_DOMAINS
780 extern int pci_domains_supported;
781 #else
782 enum { pci_domains_supported = 0 };
783 static inline int pci_domain_nr(struct pci_bus *bus)
784 {
785 return 0;
786 }
787
788 static inline int pci_proc_domain(struct pci_bus *bus)
789 {
790 return 0;
791 }
792 #endif /* CONFIG_PCI_DOMAINS */
793
794 #else /* CONFIG_PCI is not enabled */
795
796 /*
797 * If the system does not have PCI, clearly these return errors. Define
798 * these as simple inline functions to avoid hair in drivers.
799 */
800
801 #define _PCI_NOP(o, s, t) \
802 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
803 int where, t val) \
804 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
805
806 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
807 _PCI_NOP(o, word, u16 x) \
808 _PCI_NOP(o, dword, u32 x)
809 _PCI_NOP_ALL(read, *)
810 _PCI_NOP_ALL(write,)
811
812 static inline struct pci_dev *pci_find_device(unsigned int vendor,
813 unsigned int device,
814 const struct pci_dev *from)
815 {
816 return NULL;
817 }
818
819 static inline struct pci_dev *pci_find_slot(unsigned int bus,
820 unsigned int devfn)
821 {
822 return NULL;
823 }
824
825 static inline struct pci_dev *pci_get_device(unsigned int vendor,
826 unsigned int device,
827 struct pci_dev *from)
828 {
829 return NULL;
830 }
831
832 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
833 unsigned int device,
834 unsigned int ss_vendor,
835 unsigned int ss_device,
836 const struct pci_dev *from)
837 {
838 return NULL;
839 }
840
841 static inline struct pci_dev *pci_get_class(unsigned int class,
842 struct pci_dev *from)
843 {
844 return NULL;
845 }
846
847 #define pci_dev_present(ids) (0)
848 #define no_pci_devices() (1)
849 #define pci_dev_put(dev) do { } while (0)
850
851 static inline void pci_set_master(struct pci_dev *dev)
852 { }
853
854 static inline int pci_enable_device(struct pci_dev *dev)
855 {
856 return -EIO;
857 }
858
859 static inline void pci_disable_device(struct pci_dev *dev)
860 { }
861
862 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
863 {
864 return -EIO;
865 }
866
867 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
868 {
869 return -EIO;
870 }
871
872 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
873 unsigned int size)
874 {
875 return -EIO;
876 }
877
878 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
879 unsigned long mask)
880 {
881 return -EIO;
882 }
883
884 static inline int pci_assign_resource(struct pci_dev *dev, int i)
885 {
886 return -EBUSY;
887 }
888
889 static inline int __pci_register_driver(struct pci_driver *drv,
890 struct module *owner)
891 {
892 return 0;
893 }
894
895 static inline int pci_register_driver(struct pci_driver *drv)
896 {
897 return 0;
898 }
899
900 static inline void pci_unregister_driver(struct pci_driver *drv)
901 { }
902
903 static inline int pci_find_capability(struct pci_dev *dev, int cap)
904 {
905 return 0;
906 }
907
908 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
909 int cap)
910 {
911 return 0;
912 }
913
914 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
915 {
916 return 0;
917 }
918
919 /* Power management related routines */
920 static inline int pci_save_state(struct pci_dev *dev)
921 {
922 return 0;
923 }
924
925 static inline int pci_restore_state(struct pci_dev *dev)
926 {
927 return 0;
928 }
929
930 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
931 {
932 return 0;
933 }
934
935 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
936 pm_message_t state)
937 {
938 return PCI_D0;
939 }
940
941 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
942 int enable)
943 {
944 return 0;
945 }
946
947 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
948 {
949 return -EIO;
950 }
951
952 static inline void pci_release_regions(struct pci_dev *dev)
953 { }
954
955 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
956
957 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
958 { }
959
960 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
961 { }
962
963 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
964 { return NULL; }
965
966 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
967 unsigned int devfn)
968 { return NULL; }
969
970 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
971 unsigned int devfn)
972 { return NULL; }
973
974 #endif /* CONFIG_PCI */
975
976 /* Include architecture-dependent settings and functions */
977
978 #include <asm/pci.h>
979
980 /* these helpers provide future and backwards compatibility
981 * for accessing popular PCI BAR info */
982 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
983 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
984 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
985 #define pci_resource_len(dev,bar) \
986 ((pci_resource_start((dev), (bar)) == 0 && \
987 pci_resource_end((dev), (bar)) == \
988 pci_resource_start((dev), (bar))) ? 0 : \
989 \
990 (pci_resource_end((dev), (bar)) - \
991 pci_resource_start((dev), (bar)) + 1))
992
993 /* Similar to the helpers above, these manipulate per-pci_dev
994 * driver-specific data. They are really just a wrapper around
995 * the generic device structure functions of these calls.
996 */
997 static inline void *pci_get_drvdata(struct pci_dev *pdev)
998 {
999 return dev_get_drvdata(&pdev->dev);
1000 }
1001
1002 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1003 {
1004 dev_set_drvdata(&pdev->dev, data);
1005 }
1006
1007 /* If you want to know what to call your pci_dev, ask this function.
1008 * Again, it's a wrapper around the generic device.
1009 */
1010 static inline const char *pci_name(struct pci_dev *pdev)
1011 {
1012 return dev_name(&pdev->dev);
1013 }
1014
1015
1016 /* Some archs don't want to expose struct resource to userland as-is
1017 * in sysfs and /proc
1018 */
1019 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1020 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1021 const struct resource *rsrc, resource_size_t *start,
1022 resource_size_t *end)
1023 {
1024 *start = rsrc->start;
1025 *end = rsrc->end;
1026 }
1027 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1028
1029
1030 /*
1031 * The world is not perfect and supplies us with broken PCI devices.
1032 * For at least a part of these bugs we need a work-around, so both
1033 * generic (drivers/pci/quirks.c) and per-architecture code can define
1034 * fixup hooks to be called for particular buggy devices.
1035 */
1036
1037 struct pci_fixup {
1038 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1039 void (*hook)(struct pci_dev *dev);
1040 };
1041
1042 enum pci_fixup_pass {
1043 pci_fixup_early, /* Before probing BARs */
1044 pci_fixup_header, /* After reading configuration header */
1045 pci_fixup_final, /* Final phase of device fixups */
1046 pci_fixup_enable, /* pci_enable_device() time */
1047 pci_fixup_resume, /* pci_device_resume() */
1048 pci_fixup_suspend, /* pci_device_suspend */
1049 pci_fixup_resume_early, /* pci_device_resume_early() */
1050 };
1051
1052 /* Anonymous variables would be nice... */
1053 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1054 static const struct pci_fixup __pci_fixup_##name __used \
1055 __attribute__((__section__(#section))) = { vendor, device, hook };
1056 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1058 vendor##device##hook, vendor, device, hook)
1059 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1060 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1061 vendor##device##hook, vendor, device, hook)
1062 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1063 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1064 vendor##device##hook, vendor, device, hook)
1065 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1066 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1067 vendor##device##hook, vendor, device, hook)
1068 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1070 resume##vendor##device##hook, vendor, device, hook)
1071 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1072 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1073 resume_early##vendor##device##hook, vendor, device, hook)
1074 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1075 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1076 suspend##vendor##device##hook, vendor, device, hook)
1077
1078
1079 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1080
1081 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1082 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1083 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1084 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1085 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1086 const char *name);
1087 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1088
1089 extern int pci_pci_problems;
1090 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1091 #define PCIPCI_TRITON 2
1092 #define PCIPCI_NATOMA 4
1093 #define PCIPCI_VIAETBF 8
1094 #define PCIPCI_VSFX 16
1095 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1096 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1097
1098 extern unsigned long pci_cardbus_io_size;
1099 extern unsigned long pci_cardbus_mem_size;
1100
1101 int pcibios_add_platform_entries(struct pci_dev *dev);
1102 void pcibios_disable_device(struct pci_dev *dev);
1103 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1104 enum pcie_reset_state state);
1105
1106 #ifdef CONFIG_PCI_MMCONFIG
1107 extern void __init pci_mmcfg_early_init(void);
1108 extern void __init pci_mmcfg_late_init(void);
1109 #else
1110 static inline void pci_mmcfg_early_init(void) { }
1111 static inline void pci_mmcfg_late_init(void) { }
1112 #endif
1113
1114 #endif /* __KERNEL__ */
1115 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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