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Merge branch 'for-2.6.33' of git://linux-nfs.org/~bfields/linux
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 struct pci_cap_saved_state {
191 struct hlist_node next;
192 char cap_nr;
193 u32 data[0];
194 };
195
196 struct pcie_link_state;
197 struct pci_vpd;
198 struct pci_sriov;
199 struct pci_ats;
200
201 /*
202 * The pci_dev structure is used to describe PCI devices.
203 */
204 struct pci_dev {
205 struct list_head bus_list; /* node in per-bus list */
206 struct pci_bus *bus; /* bus this device is on */
207 struct pci_bus *subordinate; /* bus this device bridges to */
208
209 void *sysdata; /* hook for sys-specific extension */
210 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
211 struct pci_slot *slot; /* Physical slot this device is in */
212
213 unsigned int devfn; /* encoded device & function index */
214 unsigned short vendor;
215 unsigned short device;
216 unsigned short subsystem_vendor;
217 unsigned short subsystem_device;
218 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
219 u8 revision; /* PCI revision, low byte of class word */
220 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
221 u8 pcie_cap; /* PCI-E capability offset */
222 u8 pcie_type; /* PCI-E device/port type */
223 u8 rom_base_reg; /* which config register controls the ROM */
224 u8 pin; /* which interrupt pin this device uses */
225
226 struct pci_driver *driver; /* which driver has allocated this device */
227 u64 dma_mask; /* Mask of the bits of bus address this
228 device implements. Normally this is
229 0xffffffff. You only need to change
230 this if your device has broken DMA
231 or supports 64-bit transfers. */
232
233 struct device_dma_parameters dma_parms;
234
235 pci_power_t current_state; /* Current operating state. In ACPI-speak,
236 this is D0-D3, D0 being fully functional,
237 and D3 being off. */
238 int pm_cap; /* PM capability offset in the
239 configuration space */
240 unsigned int pme_support:5; /* Bitmask of states from which PME#
241 can be generated */
242 unsigned int d1_support:1; /* Low power state D1 is supported */
243 unsigned int d2_support:1; /* Low power state D2 is supported */
244 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
245 unsigned int wakeup_prepared:1;
246
247 #ifdef CONFIG_PCIEASPM
248 struct pcie_link_state *link_state; /* ASPM link state. */
249 #endif
250
251 pci_channel_state_t error_state; /* current connectivity state */
252 struct device dev; /* Generic device interface */
253
254 int cfg_size; /* Size of configuration space */
255
256 /*
257 * Instead of touching interrupt line and base address registers
258 * directly, use the values stored here. They might be different!
259 */
260 unsigned int irq;
261 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
262
263 /* These fields are used by common fixups */
264 unsigned int transparent:1; /* Transparent PCI bridge */
265 unsigned int multifunction:1;/* Part of multi-function device */
266 /* keep track of device state */
267 unsigned int is_added:1;
268 unsigned int is_busmaster:1; /* device is busmaster */
269 unsigned int no_msi:1; /* device may not use msi */
270 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
271 unsigned int broken_parity_status:1; /* Device generates false positive parity */
272 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
273 unsigned int msi_enabled:1;
274 unsigned int msix_enabled:1;
275 unsigned int ari_enabled:1; /* ARI forwarding */
276 unsigned int is_managed:1;
277 unsigned int is_pcie:1;
278 unsigned int needs_freset:1; /* Dev requires fundamental reset */
279 unsigned int state_saved:1;
280 unsigned int is_physfn:1;
281 unsigned int is_virtfn:1;
282 unsigned int reset_fn:1;
283 unsigned int is_hotplug_bridge:1;
284 unsigned int aer_firmware_first:1;
285 pci_dev_flags_t dev_flags;
286 atomic_t enable_cnt; /* pci_enable_device has been called */
287
288 u32 saved_config_space[16]; /* config space saved at suspend time */
289 struct hlist_head saved_cap_space;
290 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
291 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
292 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
293 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
294 #ifdef CONFIG_PCI_MSI
295 struct list_head msi_list;
296 #endif
297 struct pci_vpd *vpd;
298 #ifdef CONFIG_PCI_IOV
299 union {
300 struct pci_sriov *sriov; /* SR-IOV capability related */
301 struct pci_dev *physfn; /* the PF this VF is associated with */
302 };
303 struct pci_ats *ats; /* Address Translation Service */
304 #endif
305 };
306
307 extern struct pci_dev *alloc_pci_dev(void);
308
309 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
310 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
311 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
312
313 static inline int pci_channel_offline(struct pci_dev *pdev)
314 {
315 return (pdev->error_state != pci_channel_io_normal);
316 }
317
318 static inline struct pci_cap_saved_state *pci_find_saved_cap(
319 struct pci_dev *pci_dev, char cap)
320 {
321 struct pci_cap_saved_state *tmp;
322 struct hlist_node *pos;
323
324 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
325 if (tmp->cap_nr == cap)
326 return tmp;
327 }
328 return NULL;
329 }
330
331 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
332 struct pci_cap_saved_state *new_cap)
333 {
334 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
335 }
336
337 #ifndef PCI_BUS_NUM_RESOURCES
338 #define PCI_BUS_NUM_RESOURCES 16
339 #endif
340
341 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
342
343 struct pci_bus {
344 struct list_head node; /* node in list of buses */
345 struct pci_bus *parent; /* parent bus this bridge is on */
346 struct list_head children; /* list of child buses */
347 struct list_head devices; /* list of devices on this bus */
348 struct pci_dev *self; /* bridge device as seen by parent */
349 struct list_head slots; /* list of slots on this bus */
350 struct resource *resource[PCI_BUS_NUM_RESOURCES];
351 /* address space routed to this bus */
352
353 struct pci_ops *ops; /* configuration access functions */
354 void *sysdata; /* hook for sys-specific extension */
355 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
356
357 unsigned char number; /* bus number */
358 unsigned char primary; /* number of primary bridge */
359 unsigned char secondary; /* number of secondary bridge */
360 unsigned char subordinate; /* max number of subordinate buses */
361
362 char name[48];
363
364 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
365 pci_bus_flags_t bus_flags; /* Inherited by child busses */
366 struct device *bridge;
367 struct device dev;
368 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
369 struct bin_attribute *legacy_mem; /* legacy mem */
370 unsigned int is_added:1;
371 };
372
373 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
374 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
375
376 /*
377 * Returns true if the pci bus is root (behind host-pci bridge),
378 * false otherwise
379 */
380 static inline bool pci_is_root_bus(struct pci_bus *pbus)
381 {
382 return !(pbus->parent);
383 }
384
385 #ifdef CONFIG_PCI_MSI
386 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
387 {
388 return pci_dev->msi_enabled || pci_dev->msix_enabled;
389 }
390 #else
391 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
392 #endif
393
394 /*
395 * Error values that may be returned by PCI functions.
396 */
397 #define PCIBIOS_SUCCESSFUL 0x00
398 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
399 #define PCIBIOS_BAD_VENDOR_ID 0x83
400 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
401 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
402 #define PCIBIOS_SET_FAILED 0x88
403 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
404
405 /* Low-level architecture-dependent routines */
406
407 struct pci_ops {
408 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
409 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
410 };
411
412 /*
413 * ACPI needs to be able to access PCI config space before we've done a
414 * PCI bus scan and created pci_bus structures.
415 */
416 extern int raw_pci_read(unsigned int domain, unsigned int bus,
417 unsigned int devfn, int reg, int len, u32 *val);
418 extern int raw_pci_write(unsigned int domain, unsigned int bus,
419 unsigned int devfn, int reg, int len, u32 val);
420
421 struct pci_bus_region {
422 resource_size_t start;
423 resource_size_t end;
424 };
425
426 struct pci_dynids {
427 spinlock_t lock; /* protects list, index */
428 struct list_head list; /* for IDs added at runtime */
429 };
430
431 /* ---------------------------------------------------------------- */
432 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
433 * a set of callbacks in struct pci_error_handlers, then that device driver
434 * will be notified of PCI bus errors, and will be driven to recovery
435 * when an error occurs.
436 */
437
438 typedef unsigned int __bitwise pci_ers_result_t;
439
440 enum pci_ers_result {
441 /* no result/none/not supported in device driver */
442 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
443
444 /* Device driver can recover without slot reset */
445 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
446
447 /* Device driver wants slot to be reset. */
448 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
449
450 /* Device has completely failed, is unrecoverable */
451 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
452
453 /* Device driver is fully recovered and operational */
454 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
455 };
456
457 /* PCI bus error event callbacks */
458 struct pci_error_handlers {
459 /* PCI bus error detected on this device */
460 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
461 enum pci_channel_state error);
462
463 /* MMIO has been re-enabled, but not DMA */
464 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
465
466 /* PCI Express link has been reset */
467 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
468
469 /* PCI slot has been reset */
470 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
471
472 /* Device driver may resume normal operations */
473 void (*resume)(struct pci_dev *dev);
474 };
475
476 /* ---------------------------------------------------------------- */
477
478 struct module;
479 struct pci_driver {
480 struct list_head node;
481 char *name;
482 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
483 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
484 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
485 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
486 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
487 int (*resume_early) (struct pci_dev *dev);
488 int (*resume) (struct pci_dev *dev); /* Device woken up */
489 void (*shutdown) (struct pci_dev *dev);
490 struct pci_error_handlers *err_handler;
491 struct device_driver driver;
492 struct pci_dynids dynids;
493 };
494
495 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
496
497 /**
498 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
499 * @_table: device table name
500 *
501 * This macro is used to create a struct pci_device_id array (a device table)
502 * in a generic manner.
503 */
504 #define DEFINE_PCI_DEVICE_TABLE(_table) \
505 const struct pci_device_id _table[] __devinitconst
506
507 /**
508 * PCI_DEVICE - macro used to describe a specific pci device
509 * @vend: the 16 bit PCI Vendor ID
510 * @dev: the 16 bit PCI Device ID
511 *
512 * This macro is used to create a struct pci_device_id that matches a
513 * specific device. The subvendor and subdevice fields will be set to
514 * PCI_ANY_ID.
515 */
516 #define PCI_DEVICE(vend,dev) \
517 .vendor = (vend), .device = (dev), \
518 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
519
520 /**
521 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
522 * @dev_class: the class, subclass, prog-if triple for this device
523 * @dev_class_mask: the class mask for this device
524 *
525 * This macro is used to create a struct pci_device_id that matches a
526 * specific PCI class. The vendor, device, subvendor, and subdevice
527 * fields will be set to PCI_ANY_ID.
528 */
529 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
530 .class = (dev_class), .class_mask = (dev_class_mask), \
531 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
532 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
533
534 /**
535 * PCI_VDEVICE - macro used to describe a specific pci device in short form
536 * @vendor: the vendor name
537 * @device: the 16 bit PCI Device ID
538 *
539 * This macro is used to create a struct pci_device_id that matches a
540 * specific PCI device. The subvendor, and subdevice fields will be set
541 * to PCI_ANY_ID. The macro allows the next field to follow as the device
542 * private data.
543 */
544
545 #define PCI_VDEVICE(vendor, device) \
546 PCI_VENDOR_ID_##vendor, (device), \
547 PCI_ANY_ID, PCI_ANY_ID, 0, 0
548
549 /* these external functions are only available when PCI support is enabled */
550 #ifdef CONFIG_PCI
551
552 extern struct bus_type pci_bus_type;
553
554 /* Do NOT directly access these two variables, unless you are arch specific pci
555 * code, or pci core code. */
556 extern struct list_head pci_root_buses; /* list of all known PCI buses */
557 /* Some device drivers need know if pci is initiated */
558 extern int no_pci_devices(void);
559
560 void pcibios_fixup_bus(struct pci_bus *);
561 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
562 char *pcibios_setup(char *str);
563
564 /* Used only when drivers/pci/setup.c is used */
565 void pcibios_align_resource(void *, struct resource *, resource_size_t,
566 resource_size_t);
567 void pcibios_update_irq(struct pci_dev *, int irq);
568
569 /* Weak but can be overriden by arch */
570 void pci_fixup_cardbus(struct pci_bus *);
571
572 /* Generic PCI functions used internally */
573
574 extern struct pci_bus *pci_find_bus(int domain, int busnr);
575 void pci_bus_add_devices(const struct pci_bus *bus);
576 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
577 struct pci_ops *ops, void *sysdata);
578 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
579 void *sysdata)
580 {
581 struct pci_bus *root_bus;
582 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
583 if (root_bus)
584 pci_bus_add_devices(root_bus);
585 return root_bus;
586 }
587 struct pci_bus *pci_create_bus(struct device *parent, int bus,
588 struct pci_ops *ops, void *sysdata);
589 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
590 int busnr);
591 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
592 const char *name,
593 struct hotplug_slot *hotplug);
594 void pci_destroy_slot(struct pci_slot *slot);
595 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
596 int pci_scan_slot(struct pci_bus *bus, int devfn);
597 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
598 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
599 unsigned int pci_scan_child_bus(struct pci_bus *bus);
600 int __must_check pci_bus_add_device(struct pci_dev *dev);
601 void pci_read_bridge_bases(struct pci_bus *child);
602 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
603 struct resource *res);
604 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
605 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
606 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
607 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
608 extern void pci_dev_put(struct pci_dev *dev);
609 extern void pci_remove_bus(struct pci_bus *b);
610 extern void pci_remove_bus_device(struct pci_dev *dev);
611 extern void pci_stop_bus_device(struct pci_dev *dev);
612 void pci_setup_cardbus(struct pci_bus *bus);
613 extern void pci_sort_breadthfirst(void);
614
615 /* Generic PCI functions exported to card drivers */
616
617 #ifdef CONFIG_PCI_LEGACY
618 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
619 unsigned int device,
620 struct pci_dev *from);
621 #endif /* CONFIG_PCI_LEGACY */
622
623 enum pci_lost_interrupt_reason {
624 PCI_LOST_IRQ_NO_INFORMATION = 0,
625 PCI_LOST_IRQ_DISABLE_MSI,
626 PCI_LOST_IRQ_DISABLE_MSIX,
627 PCI_LOST_IRQ_DISABLE_ACPI,
628 };
629 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
630 int pci_find_capability(struct pci_dev *dev, int cap);
631 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
632 int pci_find_ext_capability(struct pci_dev *dev, int cap);
633 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
634 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
635 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
636
637 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
638 struct pci_dev *from);
639 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
640 unsigned int ss_vendor, unsigned int ss_device,
641 struct pci_dev *from);
642 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
643 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
644 unsigned int devfn);
645 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
646 unsigned int devfn)
647 {
648 return pci_get_domain_bus_and_slot(0, bus, devfn);
649 }
650 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
651 int pci_dev_present(const struct pci_device_id *ids);
652
653 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
654 int where, u8 *val);
655 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
656 int where, u16 *val);
657 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
658 int where, u32 *val);
659 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
660 int where, u8 val);
661 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
662 int where, u16 val);
663 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
664 int where, u32 val);
665 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
666
667 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
668 {
669 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
670 }
671 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
672 {
673 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
674 }
675 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
676 u32 *val)
677 {
678 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
679 }
680 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
681 {
682 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
683 }
684 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
685 {
686 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
687 }
688 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
689 u32 val)
690 {
691 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
692 }
693
694 int __must_check pci_enable_device(struct pci_dev *dev);
695 int __must_check pci_enable_device_io(struct pci_dev *dev);
696 int __must_check pci_enable_device_mem(struct pci_dev *dev);
697 int __must_check pci_reenable_device(struct pci_dev *);
698 int __must_check pcim_enable_device(struct pci_dev *pdev);
699 void pcim_pin_device(struct pci_dev *pdev);
700
701 static inline int pci_is_enabled(struct pci_dev *pdev)
702 {
703 return (atomic_read(&pdev->enable_cnt) > 0);
704 }
705
706 static inline int pci_is_managed(struct pci_dev *pdev)
707 {
708 return pdev->is_managed;
709 }
710
711 void pci_disable_device(struct pci_dev *dev);
712 void pci_set_master(struct pci_dev *dev);
713 void pci_clear_master(struct pci_dev *dev);
714 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
715 int pci_set_cacheline_size(struct pci_dev *dev);
716 #define HAVE_PCI_SET_MWI
717 int __must_check pci_set_mwi(struct pci_dev *dev);
718 int pci_try_set_mwi(struct pci_dev *dev);
719 void pci_clear_mwi(struct pci_dev *dev);
720 void pci_intx(struct pci_dev *dev, int enable);
721 void pci_msi_off(struct pci_dev *dev);
722 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
723 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
724 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
725 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
726 int pcix_get_max_mmrbc(struct pci_dev *dev);
727 int pcix_get_mmrbc(struct pci_dev *dev);
728 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
729 int pcie_get_readrq(struct pci_dev *dev);
730 int pcie_set_readrq(struct pci_dev *dev, int rq);
731 int __pci_reset_function(struct pci_dev *dev);
732 int pci_reset_function(struct pci_dev *dev);
733 void pci_update_resource(struct pci_dev *dev, int resno);
734 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
735 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
736
737 /* ROM control related routines */
738 int pci_enable_rom(struct pci_dev *pdev);
739 void pci_disable_rom(struct pci_dev *pdev);
740 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
741 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
742 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
743
744 /* Power management related routines */
745 int pci_save_state(struct pci_dev *dev);
746 int pci_restore_state(struct pci_dev *dev);
747 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
748 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
749 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
750 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
751 void pci_pme_active(struct pci_dev *dev, bool enable);
752 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
753 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
754 pci_power_t pci_target_state(struct pci_dev *dev);
755 int pci_prepare_to_sleep(struct pci_dev *dev);
756 int pci_back_from_sleep(struct pci_dev *dev);
757
758 /* Functions for PCI Hotplug drivers to use */
759 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
760 #ifdef CONFIG_HOTPLUG
761 unsigned int pci_rescan_bus(struct pci_bus *bus);
762 #endif
763
764 /* Vital product data routines */
765 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
766 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
767 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
768
769 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
770 void pci_bus_assign_resources(const struct pci_bus *bus);
771 void pci_bus_size_bridges(struct pci_bus *bus);
772 int pci_claim_resource(struct pci_dev *, int);
773 void pci_assign_unassigned_resources(void);
774 void pdev_enable_device(struct pci_dev *);
775 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
776 int pci_enable_resources(struct pci_dev *, int mask);
777 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
778 int (*)(struct pci_dev *, u8, u8));
779 #define HAVE_PCI_REQ_REGIONS 2
780 int __must_check pci_request_regions(struct pci_dev *, const char *);
781 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
782 void pci_release_regions(struct pci_dev *);
783 int __must_check pci_request_region(struct pci_dev *, int, const char *);
784 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
785 void pci_release_region(struct pci_dev *, int);
786 int pci_request_selected_regions(struct pci_dev *, int, const char *);
787 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
788 void pci_release_selected_regions(struct pci_dev *, int);
789
790 /* drivers/pci/bus.c */
791 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
792 struct resource *res, resource_size_t size,
793 resource_size_t align, resource_size_t min,
794 unsigned int type_mask,
795 void (*alignf)(void *, struct resource *,
796 resource_size_t, resource_size_t),
797 void *alignf_data);
798 void pci_enable_bridges(struct pci_bus *bus);
799
800 /* Proper probing supporting hot-pluggable devices */
801 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
802 const char *mod_name);
803
804 /*
805 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
806 */
807 #define pci_register_driver(driver) \
808 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
809
810 void pci_unregister_driver(struct pci_driver *dev);
811 void pci_remove_behind_bridge(struct pci_dev *dev);
812 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
813 int pci_add_dynid(struct pci_driver *drv,
814 unsigned int vendor, unsigned int device,
815 unsigned int subvendor, unsigned int subdevice,
816 unsigned int class, unsigned int class_mask,
817 unsigned long driver_data);
818 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
819 struct pci_dev *dev);
820 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
821 int pass);
822
823 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
824 void *userdata);
825 int pci_cfg_space_size_ext(struct pci_dev *dev);
826 int pci_cfg_space_size(struct pci_dev *dev);
827 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
828
829 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
830 unsigned int command_bits, bool change_bridge);
831 /* kmem_cache style wrapper around pci_alloc_consistent() */
832
833 #include <linux/dmapool.h>
834
835 #define pci_pool dma_pool
836 #define pci_pool_create(name, pdev, size, align, allocation) \
837 dma_pool_create(name, &pdev->dev, size, align, allocation)
838 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
839 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
840 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
841
842 enum pci_dma_burst_strategy {
843 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
844 strategy_parameter is N/A */
845 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
846 byte boundaries */
847 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
848 strategy_parameter byte boundaries */
849 };
850
851 struct msix_entry {
852 u32 vector; /* kernel uses to write allocated vector */
853 u16 entry; /* driver uses to specify entry, OS writes */
854 };
855
856
857 #ifndef CONFIG_PCI_MSI
858 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
859 {
860 return -1;
861 }
862
863 static inline void pci_msi_shutdown(struct pci_dev *dev)
864 { }
865 static inline void pci_disable_msi(struct pci_dev *dev)
866 { }
867
868 static inline int pci_msix_table_size(struct pci_dev *dev)
869 {
870 return 0;
871 }
872 static inline int pci_enable_msix(struct pci_dev *dev,
873 struct msix_entry *entries, int nvec)
874 {
875 return -1;
876 }
877
878 static inline void pci_msix_shutdown(struct pci_dev *dev)
879 { }
880 static inline void pci_disable_msix(struct pci_dev *dev)
881 { }
882
883 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
884 { }
885
886 static inline void pci_restore_msi_state(struct pci_dev *dev)
887 { }
888 static inline int pci_msi_enabled(void)
889 {
890 return 0;
891 }
892 #else
893 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
894 extern void pci_msi_shutdown(struct pci_dev *dev);
895 extern void pci_disable_msi(struct pci_dev *dev);
896 extern int pci_msix_table_size(struct pci_dev *dev);
897 extern int pci_enable_msix(struct pci_dev *dev,
898 struct msix_entry *entries, int nvec);
899 extern void pci_msix_shutdown(struct pci_dev *dev);
900 extern void pci_disable_msix(struct pci_dev *dev);
901 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
902 extern void pci_restore_msi_state(struct pci_dev *dev);
903 extern int pci_msi_enabled(void);
904 #endif
905
906 #ifndef CONFIG_PCIEASPM
907 static inline int pcie_aspm_enabled(void)
908 {
909 return 0;
910 }
911 #else
912 extern int pcie_aspm_enabled(void);
913 #endif
914
915 #ifndef CONFIG_PCIE_ECRC
916 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
917 {
918 return;
919 }
920 static inline void pcie_ecrc_get_policy(char *str) {};
921 #else
922 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
923 extern void pcie_ecrc_get_policy(char *str);
924 #endif
925
926 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
927
928 #ifdef CONFIG_HT_IRQ
929 /* The functions a driver should call */
930 int ht_create_irq(struct pci_dev *dev, int idx);
931 void ht_destroy_irq(unsigned int irq);
932 #endif /* CONFIG_HT_IRQ */
933
934 extern void pci_block_user_cfg_access(struct pci_dev *dev);
935 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
936
937 /*
938 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
939 * a PCI domain is defined to be a set of PCI busses which share
940 * configuration space.
941 */
942 #ifdef CONFIG_PCI_DOMAINS
943 extern int pci_domains_supported;
944 #else
945 enum { pci_domains_supported = 0 };
946 static inline int pci_domain_nr(struct pci_bus *bus)
947 {
948 return 0;
949 }
950
951 static inline int pci_proc_domain(struct pci_bus *bus)
952 {
953 return 0;
954 }
955 #endif /* CONFIG_PCI_DOMAINS */
956
957 #else /* CONFIG_PCI is not enabled */
958
959 /*
960 * If the system does not have PCI, clearly these return errors. Define
961 * these as simple inline functions to avoid hair in drivers.
962 */
963
964 #define _PCI_NOP(o, s, t) \
965 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
966 int where, t val) \
967 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
968
969 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
970 _PCI_NOP(o, word, u16 x) \
971 _PCI_NOP(o, dword, u32 x)
972 _PCI_NOP_ALL(read, *)
973 _PCI_NOP_ALL(write,)
974
975 static inline struct pci_dev *pci_find_device(unsigned int vendor,
976 unsigned int device,
977 struct pci_dev *from)
978 {
979 return NULL;
980 }
981
982 static inline struct pci_dev *pci_get_device(unsigned int vendor,
983 unsigned int device,
984 struct pci_dev *from)
985 {
986 return NULL;
987 }
988
989 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
990 unsigned int device,
991 unsigned int ss_vendor,
992 unsigned int ss_device,
993 struct pci_dev *from)
994 {
995 return NULL;
996 }
997
998 static inline struct pci_dev *pci_get_class(unsigned int class,
999 struct pci_dev *from)
1000 {
1001 return NULL;
1002 }
1003
1004 #define pci_dev_present(ids) (0)
1005 #define no_pci_devices() (1)
1006 #define pci_dev_put(dev) do { } while (0)
1007
1008 static inline void pci_set_master(struct pci_dev *dev)
1009 { }
1010
1011 static inline int pci_enable_device(struct pci_dev *dev)
1012 {
1013 return -EIO;
1014 }
1015
1016 static inline void pci_disable_device(struct pci_dev *dev)
1017 { }
1018
1019 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1020 {
1021 return -EIO;
1022 }
1023
1024 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1025 {
1026 return -EIO;
1027 }
1028
1029 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1030 unsigned int size)
1031 {
1032 return -EIO;
1033 }
1034
1035 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1036 unsigned long mask)
1037 {
1038 return -EIO;
1039 }
1040
1041 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1042 {
1043 return -EBUSY;
1044 }
1045
1046 static inline int __pci_register_driver(struct pci_driver *drv,
1047 struct module *owner)
1048 {
1049 return 0;
1050 }
1051
1052 static inline int pci_register_driver(struct pci_driver *drv)
1053 {
1054 return 0;
1055 }
1056
1057 static inline void pci_unregister_driver(struct pci_driver *drv)
1058 { }
1059
1060 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1061 {
1062 return 0;
1063 }
1064
1065 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1066 int cap)
1067 {
1068 return 0;
1069 }
1070
1071 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1072 {
1073 return 0;
1074 }
1075
1076 /* Power management related routines */
1077 static inline int pci_save_state(struct pci_dev *dev)
1078 {
1079 return 0;
1080 }
1081
1082 static inline int pci_restore_state(struct pci_dev *dev)
1083 {
1084 return 0;
1085 }
1086
1087 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1088 {
1089 return 0;
1090 }
1091
1092 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1093 pm_message_t state)
1094 {
1095 return PCI_D0;
1096 }
1097
1098 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1099 int enable)
1100 {
1101 return 0;
1102 }
1103
1104 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1105 {
1106 return -EIO;
1107 }
1108
1109 static inline void pci_release_regions(struct pci_dev *dev)
1110 { }
1111
1112 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1113
1114 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1115 { }
1116
1117 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1118 { }
1119
1120 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1121 { return NULL; }
1122
1123 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1124 unsigned int devfn)
1125 { return NULL; }
1126
1127 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1128 unsigned int devfn)
1129 { return NULL; }
1130
1131 #endif /* CONFIG_PCI */
1132
1133 /* Include architecture-dependent settings and functions */
1134
1135 #include <asm/pci.h>
1136
1137 #ifndef PCIBIOS_MAX_MEM_32
1138 #define PCIBIOS_MAX_MEM_32 (-1)
1139 #endif
1140
1141 /* these helpers provide future and backwards compatibility
1142 * for accessing popular PCI BAR info */
1143 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1144 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1145 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1146 #define pci_resource_len(dev,bar) \
1147 ((pci_resource_start((dev), (bar)) == 0 && \
1148 pci_resource_end((dev), (bar)) == \
1149 pci_resource_start((dev), (bar))) ? 0 : \
1150 \
1151 (pci_resource_end((dev), (bar)) - \
1152 pci_resource_start((dev), (bar)) + 1))
1153
1154 /* Similar to the helpers above, these manipulate per-pci_dev
1155 * driver-specific data. They are really just a wrapper around
1156 * the generic device structure functions of these calls.
1157 */
1158 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1159 {
1160 return dev_get_drvdata(&pdev->dev);
1161 }
1162
1163 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1164 {
1165 dev_set_drvdata(&pdev->dev, data);
1166 }
1167
1168 /* If you want to know what to call your pci_dev, ask this function.
1169 * Again, it's a wrapper around the generic device.
1170 */
1171 static inline const char *pci_name(const struct pci_dev *pdev)
1172 {
1173 return dev_name(&pdev->dev);
1174 }
1175
1176
1177 /* Some archs don't want to expose struct resource to userland as-is
1178 * in sysfs and /proc
1179 */
1180 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1181 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1182 const struct resource *rsrc, resource_size_t *start,
1183 resource_size_t *end)
1184 {
1185 *start = rsrc->start;
1186 *end = rsrc->end;
1187 }
1188 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1189
1190
1191 /*
1192 * The world is not perfect and supplies us with broken PCI devices.
1193 * For at least a part of these bugs we need a work-around, so both
1194 * generic (drivers/pci/quirks.c) and per-architecture code can define
1195 * fixup hooks to be called for particular buggy devices.
1196 */
1197
1198 struct pci_fixup {
1199 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1200 void (*hook)(struct pci_dev *dev);
1201 };
1202
1203 enum pci_fixup_pass {
1204 pci_fixup_early, /* Before probing BARs */
1205 pci_fixup_header, /* After reading configuration header */
1206 pci_fixup_final, /* Final phase of device fixups */
1207 pci_fixup_enable, /* pci_enable_device() time */
1208 pci_fixup_resume, /* pci_device_resume() */
1209 pci_fixup_suspend, /* pci_device_suspend */
1210 pci_fixup_resume_early, /* pci_device_resume_early() */
1211 };
1212
1213 /* Anonymous variables would be nice... */
1214 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1215 static const struct pci_fixup __pci_fixup_##name __used \
1216 __attribute__((__section__(#section))) = { vendor, device, hook };
1217 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1218 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1219 vendor##device##hook, vendor, device, hook)
1220 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1221 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1222 vendor##device##hook, vendor, device, hook)
1223 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1224 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1225 vendor##device##hook, vendor, device, hook)
1226 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1227 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1228 vendor##device##hook, vendor, device, hook)
1229 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1230 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1231 resume##vendor##device##hook, vendor, device, hook)
1232 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1233 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1234 resume_early##vendor##device##hook, vendor, device, hook)
1235 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1236 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1237 suspend##vendor##device##hook, vendor, device, hook)
1238
1239
1240 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1241
1242 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1243 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1244 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1245 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1246 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1247 const char *name);
1248 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1249
1250 extern int pci_pci_problems;
1251 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1252 #define PCIPCI_TRITON 2
1253 #define PCIPCI_NATOMA 4
1254 #define PCIPCI_VIAETBF 8
1255 #define PCIPCI_VSFX 16
1256 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1257 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1258
1259 extern unsigned long pci_cardbus_io_size;
1260 extern unsigned long pci_cardbus_mem_size;
1261 extern u8 __devinitdata pci_dfl_cache_line_size;
1262 extern u8 pci_cache_line_size;
1263
1264 extern unsigned long pci_hotplug_io_size;
1265 extern unsigned long pci_hotplug_mem_size;
1266
1267 int pcibios_add_platform_entries(struct pci_dev *dev);
1268 void pcibios_disable_device(struct pci_dev *dev);
1269 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1270 enum pcie_reset_state state);
1271
1272 #ifdef CONFIG_PCI_MMCONFIG
1273 extern void __init pci_mmcfg_early_init(void);
1274 extern void __init pci_mmcfg_late_init(void);
1275 #else
1276 static inline void pci_mmcfg_early_init(void) { }
1277 static inline void pci_mmcfg_late_init(void) { }
1278 #endif
1279
1280 int pci_ext_cfg_avail(struct pci_dev *dev);
1281
1282 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1283
1284 #ifdef CONFIG_PCI_IOV
1285 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1286 extern void pci_disable_sriov(struct pci_dev *dev);
1287 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1288 #else
1289 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1290 {
1291 return -ENODEV;
1292 }
1293 static inline void pci_disable_sriov(struct pci_dev *dev)
1294 {
1295 }
1296 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1297 {
1298 return IRQ_NONE;
1299 }
1300 #endif
1301
1302 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1303 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1304 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1305 #endif
1306
1307 /**
1308 * pci_pcie_cap - get the saved PCIe capability offset
1309 * @dev: PCI device
1310 *
1311 * PCIe capability offset is calculated at PCI device initialization
1312 * time and saved in the data structure. This function returns saved
1313 * PCIe capability offset. Using this instead of pci_find_capability()
1314 * reduces unnecessary search in the PCI configuration space. If you
1315 * need to calculate PCIe capability offset from raw device for some
1316 * reasons, please use pci_find_capability() instead.
1317 */
1318 static inline int pci_pcie_cap(struct pci_dev *dev)
1319 {
1320 return dev->pcie_cap;
1321 }
1322
1323 /**
1324 * pci_is_pcie - check if the PCI device is PCI Express capable
1325 * @dev: PCI device
1326 *
1327 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1328 */
1329 static inline bool pci_is_pcie(struct pci_dev *dev)
1330 {
1331 return !!pci_pcie_cap(dev);
1332 }
1333
1334 void pci_request_acs(void);
1335
1336 #endif /* __KERNEL__ */
1337 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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