4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus
*bus
; /* The bus this slot is on */
56 struct list_head list
; /* node in list of slots on this bus */
57 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
58 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
64 return kobject_name(&slot
->kobj
);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END
= 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
101 PCI_BRIDGE_RESOURCE_NUM
- 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
110 typedef int __bitwise pci_power_t
;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names
[];
123 static inline const char *pci_power_name(pci_power_t state
)
125 return pci_power_names
[1 + (int) state
];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t
;
139 enum pci_channel_state
{
140 /* I/O channel is in normal state */
141 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t
;
152 enum pcie_reset_state
{
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
163 typedef unsigned short __bitwise pci_dev_flags_t
;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
173 /* Flag for quirk use to store if quirk-specific ACS is enabled */
174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
175 /* Flag to indicate the device uses dma_alias_devfn */
176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
= (__force pci_dev_flags_t
) (1 << 4),
177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
179 /* Do not use bus resets for device */
180 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
181 /* Do not use PM reset even if device advertises NoSoftRst- */
182 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
183 /* Get VPD from function 0 VPD */
184 PCI_DEV_FLAGS_VPD_REF_F0
= (__force pci_dev_flags_t
) (1 << 8),
187 enum pci_irq_reroute_variant
{
188 INTEL_IRQ_REROUTE_VARIANT
= 1,
189 MAX_IRQ_REROUTE_VARIANTS
= 3
192 typedef unsigned short __bitwise pci_bus_flags_t
;
194 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
195 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
198 /* These values come from the PCI Express Spec */
199 enum pcie_link_width
{
200 PCIE_LNK_WIDTH_RESRV
= 0x00,
208 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
211 /* Based on the PCI Hotplug Spec, but some values are made up by us */
213 PCI_SPEED_33MHz
= 0x00,
214 PCI_SPEED_66MHz
= 0x01,
215 PCI_SPEED_66MHz_PCIX
= 0x02,
216 PCI_SPEED_100MHz_PCIX
= 0x03,
217 PCI_SPEED_133MHz_PCIX
= 0x04,
218 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
219 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
220 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
221 PCI_SPEED_66MHz_PCIX_266
= 0x09,
222 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
223 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
229 PCI_SPEED_66MHz_PCIX_533
= 0x11,
230 PCI_SPEED_100MHz_PCIX_533
= 0x12,
231 PCI_SPEED_133MHz_PCIX_533
= 0x13,
232 PCIE_SPEED_2_5GT
= 0x14,
233 PCIE_SPEED_5_0GT
= 0x15,
234 PCIE_SPEED_8_0GT
= 0x16,
235 PCI_SPEED_UNKNOWN
= 0xff,
238 struct pci_cap_saved_data
{
245 struct pci_cap_saved_state
{
246 struct hlist_node next
;
247 struct pci_cap_saved_data cap
;
250 struct pcie_link_state
;
256 * The pci_dev structure is used to describe PCI devices.
259 struct list_head bus_list
; /* node in per-bus list */
260 struct pci_bus
*bus
; /* bus this device is on */
261 struct pci_bus
*subordinate
; /* bus this device bridges to */
263 void *sysdata
; /* hook for sys-specific extension */
264 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
265 struct pci_slot
*slot
; /* Physical slot this device is in */
267 unsigned int devfn
; /* encoded device & function index */
268 unsigned short vendor
;
269 unsigned short device
;
270 unsigned short subsystem_vendor
;
271 unsigned short subsystem_device
;
272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
273 u8 revision
; /* PCI revision, low byte of class word */
274 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
275 u8 pcie_cap
; /* PCIe capability offset */
276 u8 msi_cap
; /* MSI capability offset */
277 u8 msix_cap
; /* MSI-X capability offset */
278 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
279 u8 rom_base_reg
; /* which config register controls the ROM */
280 u8 pin
; /* which interrupt pin this device uses */
281 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
282 u8 dma_alias_devfn
;/* devfn of DMA alias, if any */
284 struct pci_driver
*driver
; /* which driver has allocated this device */
285 u64 dma_mask
; /* Mask of the bits of bus address this
286 device implements. Normally this is
287 0xffffffff. You only need to change
288 this if your device has broken DMA
289 or supports 64-bit transfers. */
291 struct device_dma_parameters dma_parms
;
293 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
294 this is D0-D3, D0 being fully functional,
296 u8 pm_cap
; /* PM capability offset */
297 unsigned int pme_support
:5; /* Bitmask of states from which PME#
299 unsigned int pme_interrupt
:1;
300 unsigned int pme_poll
:1; /* Poll device's PME status bit */
301 unsigned int d1_support
:1; /* Low power state D1 is supported */
302 unsigned int d2_support
:1; /* Low power state D2 is supported */
303 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
304 unsigned int no_d3cold
:1; /* D3cold is forbidden */
305 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
306 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
307 decoding during bar sizing */
308 unsigned int wakeup_prepared
:1;
309 unsigned int runtime_d3cold
:1; /* whether go through runtime
310 D3cold, not set for devices
311 powered on/off by the
312 corresponding bridge */
313 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
314 unsigned int d3_delay
; /* D3->D0 transition time in ms */
315 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
317 #ifdef CONFIG_PCIEASPM
318 struct pcie_link_state
*link_state
; /* ASPM link state */
321 pci_channel_state_t error_state
; /* current connectivity state */
322 struct device dev
; /* Generic device interface */
324 int cfg_size
; /* Size of configuration space */
327 * Instead of touching interrupt line and base address registers
328 * directly, use the values stored here. They might be different!
331 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
333 bool match_driver
; /* Skip attaching driver */
334 /* These fields are used by common fixups */
335 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
336 unsigned int multifunction
:1;/* Part of multi-function device */
337 /* keep track of device state */
338 unsigned int is_added
:1;
339 unsigned int is_busmaster
:1; /* device is busmaster */
340 unsigned int no_msi
:1; /* device may not use msi */
341 unsigned int no_64bit_msi
:1; /* device may only use 32-bit MSIs */
342 unsigned int block_cfg_access
:1; /* config space access is blocked */
343 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
344 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
345 unsigned int msi_enabled
:1;
346 unsigned int msix_enabled
:1;
347 unsigned int ari_enabled
:1; /* ARI forwarding */
348 unsigned int ats_enabled
:1; /* Address Translation Service */
349 unsigned int is_managed
:1;
350 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
351 unsigned int state_saved
:1;
352 unsigned int is_physfn
:1;
353 unsigned int is_virtfn
:1;
354 unsigned int reset_fn
:1;
355 unsigned int is_hotplug_bridge
:1;
356 unsigned int __aer_firmware_first_valid
:1;
357 unsigned int __aer_firmware_first
:1;
358 unsigned int broken_intx_masking
:1;
359 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
360 unsigned int irq_managed
:1;
361 unsigned int has_secondary_link
:1;
362 pci_dev_flags_t dev_flags
;
363 atomic_t enable_cnt
; /* pci_enable_device has been called */
365 u32 saved_config_space
[16]; /* config space saved at suspend time */
366 struct hlist_head saved_cap_space
;
367 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
368 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
369 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
370 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
371 #ifdef CONFIG_PCI_MSI
372 struct list_head msi_list
;
373 const struct attribute_group
**msi_irq_groups
;
376 #ifdef CONFIG_PCI_ATS
378 struct pci_sriov
*sriov
; /* SR-IOV capability related */
379 struct pci_dev
*physfn
; /* the PF this VF is associated with */
381 u16 ats_cap
; /* ATS Capability offset */
382 u8 ats_stu
; /* ATS Smallest Translation Unit */
383 atomic_t ats_ref_cnt
; /* number of VFs with ATS enabled */
385 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
386 size_t romlen
; /* Length of ROM if it's not from the BAR */
387 char *driver_override
; /* Driver name to force a match */
390 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
392 #ifdef CONFIG_PCI_IOV
399 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
401 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
402 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
404 static inline int pci_channel_offline(struct pci_dev
*pdev
)
406 return (pdev
->error_state
!= pci_channel_io_normal
);
409 struct pci_host_bridge
{
411 struct pci_bus
*bus
; /* root bus */
412 struct list_head windows
; /* resource_entry */
413 void (*release_fn
)(struct pci_host_bridge
*);
415 unsigned int ignore_reset_delay
:1; /* for entire hierarchy */
418 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
419 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
420 void (*release_fn
)(struct pci_host_bridge
*),
423 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
426 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
427 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
428 * buses below host bridges or subtractive decode bridges) go in the list.
429 * Use pci_bus_for_each_resource() to iterate through all the resources.
433 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
434 * and there's no way to program the bridge with the details of the window.
435 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
436 * decode bit set, because they are explicit and can be programmed with _SRS.
438 #define PCI_SUBTRACTIVE_DECODE 0x1
440 struct pci_bus_resource
{
441 struct list_head list
;
442 struct resource
*res
;
446 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
449 struct list_head node
; /* node in list of buses */
450 struct pci_bus
*parent
; /* parent bus this bridge is on */
451 struct list_head children
; /* list of child buses */
452 struct list_head devices
; /* list of devices on this bus */
453 struct pci_dev
*self
; /* bridge device as seen by parent */
454 struct list_head slots
; /* list of slots on this bus;
455 protected by pci_slot_mutex */
456 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
457 struct list_head resources
; /* address space routed to this bus */
458 struct resource busn_res
; /* bus numbers routed to this bus */
460 struct pci_ops
*ops
; /* configuration access functions */
461 struct msi_controller
*msi
; /* MSI controller */
462 void *sysdata
; /* hook for sys-specific extension */
463 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
465 unsigned char number
; /* bus number */
466 unsigned char primary
; /* number of primary bridge */
467 unsigned char max_bus_speed
; /* enum pci_bus_speed */
468 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
469 #ifdef CONFIG_PCI_DOMAINS_GENERIC
475 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
476 pci_bus_flags_t bus_flags
; /* inherited by child buses */
477 struct device
*bridge
;
479 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
480 struct bin_attribute
*legacy_mem
; /* legacy mem */
481 unsigned int is_added
:1;
484 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
487 * Returns true if the PCI bus is root (behind host-PCI bridge),
490 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
491 * This is incorrect because "virtual" buses added for SR-IOV (via
492 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
494 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
496 return !(pbus
->parent
);
500 * pci_is_bridge - check if the PCI device is a bridge
503 * Return true if the PCI device is bridge whether it has subordinate
506 static inline bool pci_is_bridge(struct pci_dev
*dev
)
508 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
509 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
512 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
514 dev
= pci_physfn(dev
);
515 if (pci_is_root_bus(dev
->bus
))
518 return dev
->bus
->self
;
521 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
522 void pci_put_host_bridge_device(struct device
*dev
);
524 #ifdef CONFIG_PCI_MSI
525 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
527 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
530 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
534 * Error values that may be returned by PCI functions.
536 #define PCIBIOS_SUCCESSFUL 0x00
537 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
538 #define PCIBIOS_BAD_VENDOR_ID 0x83
539 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
540 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
541 #define PCIBIOS_SET_FAILED 0x88
542 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
545 * Translate above to generic errno for passing back through non-PCI code.
547 static inline int pcibios_err_to_errno(int err
)
549 if (err
<= PCIBIOS_SUCCESSFUL
)
550 return err
; /* Assume already errno */
553 case PCIBIOS_FUNC_NOT_SUPPORTED
:
555 case PCIBIOS_BAD_VENDOR_ID
:
557 case PCIBIOS_DEVICE_NOT_FOUND
:
559 case PCIBIOS_BAD_REGISTER_NUMBER
:
561 case PCIBIOS_SET_FAILED
:
563 case PCIBIOS_BUFFER_TOO_SMALL
:
570 /* Low-level architecture-dependent routines */
573 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
574 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
575 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
579 * ACPI needs to be able to access PCI config space before we've done a
580 * PCI bus scan and created pci_bus structures.
582 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
583 int reg
, int len
, u32
*val
);
584 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
585 int reg
, int len
, u32 val
);
587 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
588 typedef u64 pci_bus_addr_t
;
590 typedef u32 pci_bus_addr_t
;
593 struct pci_bus_region
{
594 pci_bus_addr_t start
;
599 spinlock_t lock
; /* protects list, index */
600 struct list_head list
; /* for IDs added at runtime */
605 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
606 * a set of callbacks in struct pci_error_handlers, that device driver
607 * will be notified of PCI bus errors, and will be driven to recovery
608 * when an error occurs.
611 typedef unsigned int __bitwise pci_ers_result_t
;
613 enum pci_ers_result
{
614 /* no result/none/not supported in device driver */
615 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
617 /* Device driver can recover without slot reset */
618 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
620 /* Device driver wants slot to be reset. */
621 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
623 /* Device has completely failed, is unrecoverable */
624 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
626 /* Device driver is fully recovered and operational */
627 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
629 /* No AER capabilities registered for the driver */
630 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
633 /* PCI bus error event callbacks */
634 struct pci_error_handlers
{
635 /* PCI bus error detected on this device */
636 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
637 enum pci_channel_state error
);
639 /* MMIO has been re-enabled, but not DMA */
640 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
642 /* PCI Express link has been reset */
643 pci_ers_result_t (*link_reset
)(struct pci_dev
*dev
);
645 /* PCI slot has been reset */
646 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
648 /* PCI function reset prepare or completed */
649 void (*reset_notify
)(struct pci_dev
*dev
, bool prepare
);
651 /* Device driver may resume normal operations */
652 void (*resume
)(struct pci_dev
*dev
);
658 struct list_head node
;
660 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
661 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
662 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
663 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
664 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
665 int (*resume_early
) (struct pci_dev
*dev
);
666 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
667 void (*shutdown
) (struct pci_dev
*dev
);
668 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
669 const struct pci_error_handlers
*err_handler
;
670 struct device_driver driver
;
671 struct pci_dynids dynids
;
674 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
677 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
678 * @_table: device table name
680 * This macro is deprecated and should not be used in new code.
682 #define DEFINE_PCI_DEVICE_TABLE(_table) \
683 const struct pci_device_id _table[]
686 * PCI_DEVICE - macro used to describe a specific pci device
687 * @vend: the 16 bit PCI Vendor ID
688 * @dev: the 16 bit PCI Device ID
690 * This macro is used to create a struct pci_device_id that matches a
691 * specific device. The subvendor and subdevice fields will be set to
694 #define PCI_DEVICE(vend,dev) \
695 .vendor = (vend), .device = (dev), \
696 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
699 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
700 * @vend: the 16 bit PCI Vendor ID
701 * @dev: the 16 bit PCI Device ID
702 * @subvend: the 16 bit PCI Subvendor ID
703 * @subdev: the 16 bit PCI Subdevice ID
705 * This macro is used to create a struct pci_device_id that matches a
706 * specific device with subsystem information.
708 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
709 .vendor = (vend), .device = (dev), \
710 .subvendor = (subvend), .subdevice = (subdev)
713 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
714 * @dev_class: the class, subclass, prog-if triple for this device
715 * @dev_class_mask: the class mask for this device
717 * This macro is used to create a struct pci_device_id that matches a
718 * specific PCI class. The vendor, device, subvendor, and subdevice
719 * fields will be set to PCI_ANY_ID.
721 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
722 .class = (dev_class), .class_mask = (dev_class_mask), \
723 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
724 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
727 * PCI_VDEVICE - macro used to describe a specific pci device in short form
728 * @vend: the vendor name
729 * @dev: the 16 bit PCI Device ID
731 * This macro is used to create a struct pci_device_id that matches a
732 * specific PCI device. The subvendor, and subdevice fields will be set
733 * to PCI_ANY_ID. The macro allows the next field to follow as the device
737 #define PCI_VDEVICE(vend, dev) \
738 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
739 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
741 /* these external functions are only available when PCI support is enabled */
744 void pcie_bus_configure_settings(struct pci_bus
*bus
);
746 enum pcie_bus_config_types
{
749 PCIE_BUS_PERFORMANCE
,
753 extern enum pcie_bus_config_types pcie_bus_config
;
755 extern struct bus_type pci_bus_type
;
757 /* Do NOT directly access these two variables, unless you are arch-specific PCI
758 * code, or PCI core code. */
759 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
760 /* Some device drivers need know if PCI is initiated */
761 int no_pci_devices(void);
763 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
764 void pcibios_add_bus(struct pci_bus
*bus
);
765 void pcibios_remove_bus(struct pci_bus
*bus
);
766 void pcibios_fixup_bus(struct pci_bus
*);
767 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
768 /* Architecture-specific versions may override this (weak) */
769 char *pcibios_setup(char *str
);
771 /* Used only when drivers/pci/setup.c is used */
772 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
775 void pcibios_update_irq(struct pci_dev
*, int irq
);
777 /* Weak but can be overriden by arch */
778 void pci_fixup_cardbus(struct pci_bus
*);
780 /* Generic PCI functions used internally */
782 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
783 struct resource
*res
);
784 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
785 struct pci_bus_region
*region
);
786 void pcibios_scan_specific_bus(int busn
);
787 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
788 void pci_bus_add_devices(const struct pci_bus
*bus
);
789 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
790 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
791 struct pci_ops
*ops
, void *sysdata
,
792 struct list_head
*resources
);
793 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
794 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
795 void pci_bus_release_busn_res(struct pci_bus
*b
);
796 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
797 struct pci_ops
*ops
, void *sysdata
,
798 struct list_head
*resources
);
799 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
801 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
802 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
804 struct hotplug_slot
*hotplug
);
805 void pci_destroy_slot(struct pci_slot
*slot
);
807 void pci_dev_assign_slot(struct pci_dev
*dev
);
809 static inline void pci_dev_assign_slot(struct pci_dev
*dev
) { }
811 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
812 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
813 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
814 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
815 void pci_bus_add_device(struct pci_dev
*dev
);
816 void pci_read_bridge_bases(struct pci_bus
*child
);
817 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
818 struct resource
*res
);
819 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
820 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
821 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
822 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
823 void pci_dev_put(struct pci_dev
*dev
);
824 void pci_remove_bus(struct pci_bus
*b
);
825 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
826 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
827 void pci_stop_root_bus(struct pci_bus
*bus
);
828 void pci_remove_root_bus(struct pci_bus
*bus
);
829 void pci_setup_cardbus(struct pci_bus
*bus
);
830 void pci_sort_breadthfirst(void);
831 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
832 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
833 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
835 /* Generic PCI functions exported to card drivers */
837 enum pci_lost_interrupt_reason
{
838 PCI_LOST_IRQ_NO_INFORMATION
= 0,
839 PCI_LOST_IRQ_DISABLE_MSI
,
840 PCI_LOST_IRQ_DISABLE_MSIX
,
841 PCI_LOST_IRQ_DISABLE_ACPI
,
843 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
844 int pci_find_capability(struct pci_dev
*dev
, int cap
);
845 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
846 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
847 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
848 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
849 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
850 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
852 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
853 struct pci_dev
*from
);
854 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
855 unsigned int ss_vendor
, unsigned int ss_device
,
856 struct pci_dev
*from
);
857 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
858 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
860 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
863 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
865 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
866 int pci_dev_present(const struct pci_device_id
*ids
);
868 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
870 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
871 int where
, u16
*val
);
872 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
873 int where
, u32
*val
);
874 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
876 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
878 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
881 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
882 int where
, int size
, u32
*val
);
883 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
884 int where
, int size
, u32 val
);
885 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
886 int where
, int size
, u32
*val
);
887 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
888 int where
, int size
, u32 val
);
890 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
892 static inline int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
)
894 return pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
896 static inline int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
)
898 return pci_bus_read_config_word(dev
->bus
, dev
->devfn
, where
, val
);
900 static inline int pci_read_config_dword(const struct pci_dev
*dev
, int where
,
903 return pci_bus_read_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
905 static inline int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
)
907 return pci_bus_write_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
909 static inline int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
)
911 return pci_bus_write_config_word(dev
->bus
, dev
->devfn
, where
, val
);
913 static inline int pci_write_config_dword(const struct pci_dev
*dev
, int where
,
916 return pci_bus_write_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
919 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
920 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
921 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
922 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
923 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
925 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
928 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
931 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
934 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
937 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
940 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
943 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
946 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
949 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
952 /* user-space driven config access */
953 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
954 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
955 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
956 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
957 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
958 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
960 int __must_check
pci_enable_device(struct pci_dev
*dev
);
961 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
962 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
963 int __must_check
pci_reenable_device(struct pci_dev
*);
964 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
965 void pcim_pin_device(struct pci_dev
*pdev
);
967 static inline int pci_is_enabled(struct pci_dev
*pdev
)
969 return (atomic_read(&pdev
->enable_cnt
) > 0);
972 static inline int pci_is_managed(struct pci_dev
*pdev
)
974 return pdev
->is_managed
;
977 static inline void pci_set_managed_irq(struct pci_dev
*pdev
, unsigned int irq
)
980 pdev
->irq_managed
= 1;
983 static inline void pci_reset_managed_irq(struct pci_dev
*pdev
)
986 pdev
->irq_managed
= 0;
989 static inline bool pci_has_managed_irq(struct pci_dev
*pdev
)
991 return pdev
->irq_managed
&& pdev
->irq
> 0;
994 void pci_disable_device(struct pci_dev
*dev
);
996 extern unsigned int pcibios_max_latency
;
997 void pci_set_master(struct pci_dev
*dev
);
998 void pci_clear_master(struct pci_dev
*dev
);
1000 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
1001 int pci_set_cacheline_size(struct pci_dev
*dev
);
1002 #define HAVE_PCI_SET_MWI
1003 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
1004 int pci_try_set_mwi(struct pci_dev
*dev
);
1005 void pci_clear_mwi(struct pci_dev
*dev
);
1006 void pci_intx(struct pci_dev
*dev
, int enable
);
1007 bool pci_intx_mask_supported(struct pci_dev
*dev
);
1008 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
1009 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
1010 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
);
1011 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
);
1012 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
1013 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
1014 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
1015 int pcix_get_mmrbc(struct pci_dev
*dev
);
1016 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
1017 int pcie_get_readrq(struct pci_dev
*dev
);
1018 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
1019 int pcie_get_mps(struct pci_dev
*dev
);
1020 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
1021 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
1022 enum pcie_link_width
*width
);
1023 int __pci_reset_function(struct pci_dev
*dev
);
1024 int __pci_reset_function_locked(struct pci_dev
*dev
);
1025 int pci_reset_function(struct pci_dev
*dev
);
1026 int pci_try_reset_function(struct pci_dev
*dev
);
1027 int pci_probe_reset_slot(struct pci_slot
*slot
);
1028 int pci_reset_slot(struct pci_slot
*slot
);
1029 int pci_try_reset_slot(struct pci_slot
*slot
);
1030 int pci_probe_reset_bus(struct pci_bus
*bus
);
1031 int pci_reset_bus(struct pci_bus
*bus
);
1032 int pci_try_reset_bus(struct pci_bus
*bus
);
1033 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1034 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1035 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
1036 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1037 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1038 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1039 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1040 bool pci_device_is_present(struct pci_dev
*pdev
);
1041 void pci_ignore_hotplug(struct pci_dev
*dev
);
1043 /* ROM control related routines */
1044 int pci_enable_rom(struct pci_dev
*pdev
);
1045 void pci_disable_rom(struct pci_dev
*pdev
);
1046 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1047 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1048 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
1049 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1051 /* Power management related routines */
1052 int pci_save_state(struct pci_dev
*dev
);
1053 void pci_restore_state(struct pci_dev
*dev
);
1054 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1055 int pci_load_saved_state(struct pci_dev
*dev
,
1056 struct pci_saved_state
*state
);
1057 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1058 struct pci_saved_state
**state
);
1059 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1060 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1062 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1063 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1064 u16 cap
, unsigned int size
);
1065 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1066 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1067 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1068 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1069 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1070 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1071 bool runtime
, bool enable
);
1072 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1073 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1074 int pci_back_from_sleep(struct pci_dev
*dev
);
1075 bool pci_dev_run_wake(struct pci_dev
*dev
);
1076 bool pci_check_pme_status(struct pci_dev
*dev
);
1077 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1079 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1082 return __pci_enable_wake(dev
, state
, false, enable
);
1085 /* PCI Virtual Channel */
1086 int pci_save_vc_state(struct pci_dev
*dev
);
1087 void pci_restore_vc_state(struct pci_dev
*dev
);
1088 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1090 /* For use by arch with custom probe code */
1091 void set_pcie_port_type(struct pci_dev
*pdev
);
1092 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1094 /* Functions for PCI Hotplug drivers to use */
1095 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1096 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1097 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1098 void pci_lock_rescan_remove(void);
1099 void pci_unlock_rescan_remove(void);
1101 /* Vital product data routines */
1102 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1103 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1105 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1106 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1107 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1108 void pci_bus_size_bridges(struct pci_bus
*bus
);
1109 int pci_claim_resource(struct pci_dev
*, int);
1110 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1111 void pci_assign_unassigned_resources(void);
1112 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1113 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1114 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1115 void pdev_enable_device(struct pci_dev
*);
1116 int pci_enable_resources(struct pci_dev
*, int mask
);
1117 void pci_fixup_irqs(u8 (*)(struct pci_dev
*, u8
*),
1118 int (*)(const struct pci_dev
*, u8
, u8
));
1119 #define HAVE_PCI_REQ_REGIONS 2
1120 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1121 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1122 void pci_release_regions(struct pci_dev
*);
1123 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1124 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1125 void pci_release_region(struct pci_dev
*, int);
1126 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1127 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1128 void pci_release_selected_regions(struct pci_dev
*, int);
1130 /* drivers/pci/bus.c */
1131 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1132 void pci_bus_put(struct pci_bus
*bus
);
1133 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1134 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1135 resource_size_t offset
);
1136 void pci_free_resource_list(struct list_head
*resources
);
1137 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
, unsigned int flags
);
1138 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1139 void pci_bus_remove_resources(struct pci_bus
*bus
);
1141 #define pci_bus_for_each_resource(bus, res, i) \
1143 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1146 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1147 struct resource
*res
, resource_size_t size
,
1148 resource_size_t align
, resource_size_t min
,
1149 unsigned long type_mask
,
1150 resource_size_t (*alignf
)(void *,
1151 const struct resource
*,
1157 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1159 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1161 struct pci_bus_region region
;
1163 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1164 return region
.start
;
1167 /* Proper probing supporting hot-pluggable devices */
1168 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1169 const char *mod_name
);
1172 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1174 #define pci_register_driver(driver) \
1175 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1177 void pci_unregister_driver(struct pci_driver
*dev
);
1180 * module_pci_driver() - Helper macro for registering a PCI driver
1181 * @__pci_driver: pci_driver struct
1183 * Helper macro for PCI drivers which do not do anything special in module
1184 * init/exit. This eliminates a lot of boilerplate. Each module may only
1185 * use this macro once, and calling it replaces module_init() and module_exit()
1187 #define module_pci_driver(__pci_driver) \
1188 module_driver(__pci_driver, pci_register_driver, \
1189 pci_unregister_driver)
1191 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1192 int pci_add_dynid(struct pci_driver
*drv
,
1193 unsigned int vendor
, unsigned int device
,
1194 unsigned int subvendor
, unsigned int subdevice
,
1195 unsigned int class, unsigned int class_mask
,
1196 unsigned long driver_data
);
1197 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1198 struct pci_dev
*dev
);
1199 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1202 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1204 int pci_cfg_space_size(struct pci_dev
*dev
);
1205 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1206 void pci_setup_bridge(struct pci_bus
*bus
);
1207 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1208 unsigned long type
);
1209 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
1211 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1212 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1214 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1215 unsigned int command_bits
, u32 flags
);
1216 /* kmem_cache style wrapper around pci_alloc_consistent() */
1218 #include <linux/pci-dma.h>
1219 #include <linux/dmapool.h>
1221 #define pci_pool dma_pool
1222 #define pci_pool_create(name, pdev, size, align, allocation) \
1223 dma_pool_create(name, &pdev->dev, size, align, allocation)
1224 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1225 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1226 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1229 u32 vector
; /* kernel uses to write allocated vector */
1230 u16 entry
; /* driver uses to specify entry, OS writes */
1234 #ifdef CONFIG_PCI_MSI
1235 int pci_msi_vec_count(struct pci_dev
*dev
);
1236 void pci_msi_shutdown(struct pci_dev
*dev
);
1237 void pci_disable_msi(struct pci_dev
*dev
);
1238 int pci_msix_vec_count(struct pci_dev
*dev
);
1239 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
);
1240 void pci_msix_shutdown(struct pci_dev
*dev
);
1241 void pci_disable_msix(struct pci_dev
*dev
);
1242 void pci_restore_msi_state(struct pci_dev
*dev
);
1243 int pci_msi_enabled(void);
1244 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
);
1245 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1247 int rc
= pci_enable_msi_range(dev
, nvec
, nvec
);
1252 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1253 int minvec
, int maxvec
);
1254 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1255 struct msix_entry
*entries
, int nvec
)
1257 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1263 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1264 static inline void pci_msi_shutdown(struct pci_dev
*dev
) { }
1265 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1266 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1267 static inline int pci_enable_msix(struct pci_dev
*dev
,
1268 struct msix_entry
*entries
, int nvec
)
1270 static inline void pci_msix_shutdown(struct pci_dev
*dev
) { }
1271 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1272 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1273 static inline int pci_msi_enabled(void) { return 0; }
1274 static inline int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
,
1277 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1279 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1280 struct msix_entry
*entries
, int minvec
, int maxvec
)
1282 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1283 struct msix_entry
*entries
, int nvec
)
1287 #ifdef CONFIG_PCIEPORTBUS
1288 extern bool pcie_ports_disabled
;
1289 extern bool pcie_ports_auto
;
1291 #define pcie_ports_disabled true
1292 #define pcie_ports_auto false
1295 #ifdef CONFIG_PCIEASPM
1296 bool pcie_aspm_support_enabled(void);
1298 static inline bool pcie_aspm_support_enabled(void) { return false; }
1301 #ifdef CONFIG_PCIEAER
1302 void pci_no_aer(void);
1303 bool pci_aer_available(void);
1305 static inline void pci_no_aer(void) { }
1306 static inline bool pci_aer_available(void) { return false; }
1309 #ifdef CONFIG_PCIE_ECRC
1310 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1311 void pcie_ecrc_get_policy(char *str
);
1313 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1314 static inline void pcie_ecrc_get_policy(char *str
) { }
1317 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1319 #ifdef CONFIG_HT_IRQ
1320 /* The functions a driver should call */
1321 int ht_create_irq(struct pci_dev
*dev
, int idx
);
1322 void ht_destroy_irq(unsigned int irq
);
1323 #endif /* CONFIG_HT_IRQ */
1325 #ifdef CONFIG_PCI_ATS
1326 /* Address Translation Service */
1327 void pci_ats_init(struct pci_dev
*dev
);
1328 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1329 void pci_disable_ats(struct pci_dev
*dev
);
1330 int pci_ats_queue_depth(struct pci_dev
*dev
);
1332 static inline void pci_ats_init(struct pci_dev
*d
) { }
1333 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1334 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1335 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1338 void pci_cfg_access_lock(struct pci_dev
*dev
);
1339 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1340 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1343 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1344 * a PCI domain is defined to be a set of PCI buses which share
1345 * configuration space.
1347 #ifdef CONFIG_PCI_DOMAINS
1348 extern int pci_domains_supported
;
1349 int pci_get_new_domain_nr(void);
1351 enum { pci_domains_supported
= 0 };
1352 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1353 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1354 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1355 #endif /* CONFIG_PCI_DOMAINS */
1358 * Generic implementation for PCI domain support. If your
1359 * architecture does not need custom management of PCI
1360 * domains then this implementation will be used
1362 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1363 static inline int pci_domain_nr(struct pci_bus
*bus
)
1365 return bus
->domain_nr
;
1367 void pci_bus_assign_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1369 static inline void pci_bus_assign_domain_nr(struct pci_bus
*bus
,
1370 struct device
*parent
)
1375 /* some architectures require additional setup to direct VGA traffic */
1376 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1377 unsigned int command_bits
, u32 flags
);
1378 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1380 #else /* CONFIG_PCI is not enabled */
1383 * If the system does not have PCI, clearly these return errors. Define
1384 * these as simple inline functions to avoid hair in drivers.
1387 #define _PCI_NOP(o, s, t) \
1388 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1390 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1392 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1393 _PCI_NOP(o, word, u16 x) \
1394 _PCI_NOP(o, dword, u32 x)
1395 _PCI_NOP_ALL(read
, *)
1396 _PCI_NOP_ALL(write
,)
1398 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1399 unsigned int device
,
1400 struct pci_dev
*from
)
1403 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1404 unsigned int device
,
1405 unsigned int ss_vendor
,
1406 unsigned int ss_device
,
1407 struct pci_dev
*from
)
1410 static inline struct pci_dev
*pci_get_class(unsigned int class,
1411 struct pci_dev
*from
)
1414 #define pci_dev_present(ids) (0)
1415 #define no_pci_devices() (1)
1416 #define pci_dev_put(dev) do { } while (0)
1418 static inline void pci_set_master(struct pci_dev
*dev
) { }
1419 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1420 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1421 static inline int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1423 static inline int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1425 static inline int pci_set_dma_max_seg_size(struct pci_dev
*dev
,
1428 static inline int pci_set_dma_seg_boundary(struct pci_dev
*dev
,
1431 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1433 static inline int __pci_register_driver(struct pci_driver
*drv
,
1434 struct module
*owner
)
1436 static inline int pci_register_driver(struct pci_driver
*drv
)
1438 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1439 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1441 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1444 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1447 /* Power management related routines */
1448 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1449 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1450 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1452 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1454 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1457 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1461 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1463 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1465 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1466 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1468 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1470 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1472 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1475 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1479 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1480 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1481 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1483 #define dev_is_pci(d) (false)
1484 #define dev_is_pf(d) (false)
1485 #define dev_num_vf(d) (0)
1486 #endif /* CONFIG_PCI */
1488 /* Include architecture-dependent settings and functions */
1490 #include <asm/pci.h>
1492 /* these helpers provide future and backwards compatibility
1493 * for accessing popular PCI BAR info */
1494 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1495 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1496 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1497 #define pci_resource_len(dev,bar) \
1498 ((pci_resource_start((dev), (bar)) == 0 && \
1499 pci_resource_end((dev), (bar)) == \
1500 pci_resource_start((dev), (bar))) ? 0 : \
1502 (pci_resource_end((dev), (bar)) - \
1503 pci_resource_start((dev), (bar)) + 1))
1505 /* Similar to the helpers above, these manipulate per-pci_dev
1506 * driver-specific data. They are really just a wrapper around
1507 * the generic device structure functions of these calls.
1509 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1511 return dev_get_drvdata(&pdev
->dev
);
1514 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1516 dev_set_drvdata(&pdev
->dev
, data
);
1519 /* If you want to know what to call your pci_dev, ask this function.
1520 * Again, it's a wrapper around the generic device.
1522 static inline const char *pci_name(const struct pci_dev
*pdev
)
1524 return dev_name(&pdev
->dev
);
1528 /* Some archs don't want to expose struct resource to userland as-is
1529 * in sysfs and /proc
1531 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1532 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1533 const struct resource
*rsrc
, resource_size_t
*start
,
1534 resource_size_t
*end
)
1536 *start
= rsrc
->start
;
1539 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1543 * The world is not perfect and supplies us with broken PCI devices.
1544 * For at least a part of these bugs we need a work-around, so both
1545 * generic (drivers/pci/quirks.c) and per-architecture code can define
1546 * fixup hooks to be called for particular buggy devices.
1550 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1551 u16 device
; /* You can use PCI_ANY_ID here of course */
1552 u32
class; /* You can use PCI_ANY_ID here too */
1553 unsigned int class_shift
; /* should be 0, 8, 16 */
1554 void (*hook
)(struct pci_dev
*dev
);
1557 enum pci_fixup_pass
{
1558 pci_fixup_early
, /* Before probing BARs */
1559 pci_fixup_header
, /* After reading configuration header */
1560 pci_fixup_final
, /* Final phase of device fixups */
1561 pci_fixup_enable
, /* pci_enable_device() time */
1562 pci_fixup_resume
, /* pci_device_resume() */
1563 pci_fixup_suspend
, /* pci_device_suspend() */
1564 pci_fixup_resume_early
, /* pci_device_resume_early() */
1565 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1568 /* Anonymous variables would be nice... */
1569 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1570 class_shift, hook) \
1571 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1572 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1573 = { vendor, device, class, class_shift, hook };
1575 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1576 class_shift, hook) \
1577 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1578 hook, vendor, device, class, class_shift, hook)
1579 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1580 class_shift, hook) \
1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1582 hook, vendor, device, class, class_shift, hook)
1583 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1584 class_shift, hook) \
1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1586 hook, vendor, device, class, class_shift, hook)
1587 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1588 class_shift, hook) \
1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1590 hook, vendor, device, class, class_shift, hook)
1591 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1592 class_shift, hook) \
1593 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1594 resume##hook, vendor, device, class, \
1596 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1597 class_shift, hook) \
1598 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1599 resume_early##hook, vendor, device, \
1600 class, class_shift, hook)
1601 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1602 class_shift, hook) \
1603 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1604 suspend##hook, vendor, device, class, \
1606 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1607 class_shift, hook) \
1608 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1609 suspend_late##hook, vendor, device, \
1610 class, class_shift, hook)
1612 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1613 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1614 hook, vendor, device, PCI_ANY_ID, 0, hook)
1615 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1616 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1617 hook, vendor, device, PCI_ANY_ID, 0, hook)
1618 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1620 hook, vendor, device, PCI_ANY_ID, 0, hook)
1621 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1622 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1623 hook, vendor, device, PCI_ANY_ID, 0, hook)
1624 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1626 resume##hook, vendor, device, \
1627 PCI_ANY_ID, 0, hook)
1628 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1629 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1630 resume_early##hook, vendor, device, \
1631 PCI_ANY_ID, 0, hook)
1632 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1633 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1634 suspend##hook, vendor, device, \
1635 PCI_ANY_ID, 0, hook)
1636 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1637 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1638 suspend_late##hook, vendor, device, \
1639 PCI_ANY_ID, 0, hook)
1641 #ifdef CONFIG_PCI_QUIRKS
1642 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1643 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1644 void pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1646 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1647 struct pci_dev
*dev
) { }
1648 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1653 static inline void pci_dev_specific_enable_acs(struct pci_dev
*dev
) { }
1656 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1657 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1658 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1659 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1660 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1662 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1664 extern int pci_pci_problems
;
1665 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1666 #define PCIPCI_TRITON 2
1667 #define PCIPCI_NATOMA 4
1668 #define PCIPCI_VIAETBF 8
1669 #define PCIPCI_VSFX 16
1670 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1671 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1673 extern unsigned long pci_cardbus_io_size
;
1674 extern unsigned long pci_cardbus_mem_size
;
1675 extern u8 pci_dfl_cache_line_size
;
1676 extern u8 pci_cache_line_size
;
1678 extern unsigned long pci_hotplug_io_size
;
1679 extern unsigned long pci_hotplug_mem_size
;
1681 /* Architecture-specific versions may override these (weak) */
1682 void pcibios_disable_device(struct pci_dev
*dev
);
1683 void pcibios_set_master(struct pci_dev
*dev
);
1684 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1685 enum pcie_reset_state state
);
1686 int pcibios_add_device(struct pci_dev
*dev
);
1687 void pcibios_release_device(struct pci_dev
*dev
);
1688 void pcibios_penalize_isa_irq(int irq
, int active
);
1689 int pcibios_alloc_irq(struct pci_dev
*dev
);
1690 void pcibios_free_irq(struct pci_dev
*dev
);
1692 #ifdef CONFIG_HIBERNATE_CALLBACKS
1693 extern struct dev_pm_ops pcibios_pm_ops
;
1696 #ifdef CONFIG_PCI_MMCONFIG
1697 void __init
pci_mmcfg_early_init(void);
1698 void __init
pci_mmcfg_late_init(void);
1700 static inline void pci_mmcfg_early_init(void) { }
1701 static inline void pci_mmcfg_late_init(void) { }
1704 int pci_ext_cfg_avail(void);
1706 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1708 #ifdef CONFIG_PCI_IOV
1709 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1710 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1712 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1713 void pci_disable_sriov(struct pci_dev
*dev
);
1714 int pci_num_vf(struct pci_dev
*dev
);
1715 int pci_vfs_assigned(struct pci_dev
*dev
);
1716 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1717 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1718 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1720 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
1724 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
1728 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1730 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
1731 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
1732 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1734 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1736 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1738 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
1742 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1743 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
1744 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
1748 * pci_pcie_cap - get the saved PCIe capability offset
1751 * PCIe capability offset is calculated at PCI device initialization
1752 * time and saved in the data structure. This function returns saved
1753 * PCIe capability offset. Using this instead of pci_find_capability()
1754 * reduces unnecessary search in the PCI configuration space. If you
1755 * need to calculate PCIe capability offset from raw device for some
1756 * reasons, please use pci_find_capability() instead.
1758 static inline int pci_pcie_cap(struct pci_dev
*dev
)
1760 return dev
->pcie_cap
;
1764 * pci_is_pcie - check if the PCI device is PCI Express capable
1767 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1769 static inline bool pci_is_pcie(struct pci_dev
*dev
)
1771 return pci_pcie_cap(dev
);
1775 * pcie_caps_reg - get the PCIe Capabilities Register
1778 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
1780 return dev
->pcie_flags_reg
;
1784 * pci_pcie_type - get the PCIe device/port type
1787 static inline int pci_pcie_type(const struct pci_dev
*dev
)
1789 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
1792 void pci_request_acs(void);
1793 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
1794 bool pci_acs_path_enabled(struct pci_dev
*start
,
1795 struct pci_dev
*end
, u16 acs_flags
);
1797 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1798 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1800 /* Large Resource Data Type Tag Item Names */
1801 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1802 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1803 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1805 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1806 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1807 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1809 /* Small Resource Data Type Tag Item Names */
1810 #define PCI_VPD_STIN_END 0x78 /* End */
1812 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1814 #define PCI_VPD_SRDT_TIN_MASK 0x78
1815 #define PCI_VPD_SRDT_LEN_MASK 0x07
1817 #define PCI_VPD_LRDT_TAG_SIZE 3
1818 #define PCI_VPD_SRDT_TAG_SIZE 1
1820 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1822 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1823 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1824 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1825 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1828 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1829 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1831 * Returns the extracted Large Resource Data Type length.
1833 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
1835 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
1839 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1840 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1842 * Returns the extracted Small Resource Data Type length.
1844 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
1846 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
1850 * pci_vpd_info_field_size - Extracts the information field length
1851 * @lrdt: Pointer to the beginning of an information field header
1853 * Returns the extracted information field length.
1855 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
1857 return info_field
[2];
1861 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1862 * @buf: Pointer to buffered vpd data
1863 * @off: The offset into the buffer at which to begin the search
1864 * @len: The length of the vpd buffer
1865 * @rdt: The Resource Data Type to search for
1867 * Returns the index where the Resource Data Type was found or
1868 * -ENOENT otherwise.
1870 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
1873 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1874 * @buf: Pointer to buffered vpd data
1875 * @off: The offset into the buffer at which to begin the search
1876 * @len: The length of the buffer area, relative to off, in which to search
1877 * @kw: The keyword to search for
1879 * Returns the index where the information field keyword was found or
1880 * -ENOENT otherwise.
1882 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
1883 unsigned int len
, const char *kw
);
1885 /* PCI <-> OF binding helpers */
1888 void pci_set_of_node(struct pci_dev
*dev
);
1889 void pci_release_of_node(struct pci_dev
*dev
);
1890 void pci_set_bus_of_node(struct pci_bus
*bus
);
1891 void pci_release_bus_of_node(struct pci_bus
*bus
);
1893 /* Arch may override this (weak) */
1894 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
1896 static inline struct device_node
*
1897 pci_device_to_OF_node(const struct pci_dev
*pdev
)
1899 return pdev
? pdev
->dev
.of_node
: NULL
;
1902 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
1904 return bus
? bus
->dev
.of_node
: NULL
;
1907 #else /* CONFIG_OF */
1908 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
1909 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
1910 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
1911 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
1912 static inline struct device_node
*
1913 pci_device_to_OF_node(const struct pci_dev
*pdev
) { return NULL
; }
1914 #endif /* CONFIG_OF */
1917 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
1919 return pdev
->dev
.archdata
.edev
;
1923 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
1924 int (*fn
)(struct pci_dev
*pdev
,
1925 u16 alias
, void *data
), void *data
);
1927 /* helper functions for operation of device flag */
1928 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
1930 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
1932 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
1934 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
1936 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
1938 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
1942 * pci_ari_enabled - query ARI forwarding status
1945 * Returns true if ARI forwarding is enabled.
1947 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
1949 return bus
->self
&& bus
->self
->ari_enabled
;
1951 #endif /* LINUX_PCI_H */