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PCI: change MSI-x vector to 32bit
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54
55 /* Include the ID list */
56 #include <linux/pci_ids.h>
57
58 /* pci_slot represents a physical slot */
59 struct pci_slot {
60 struct pci_bus *bus; /* The bus this slot is on */
61 struct list_head list; /* node in list of slots on this bus */
62 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
63 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 struct kobject kobj;
65 };
66
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
68 enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71 };
72
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
78
79 #define DEVICE_COUNT_RESOURCE 12
80
81 typedef int __bitwise pci_power_t;
82
83 #define PCI_D0 ((pci_power_t __force) 0)
84 #define PCI_D1 ((pci_power_t __force) 1)
85 #define PCI_D2 ((pci_power_t __force) 2)
86 #define PCI_D3hot ((pci_power_t __force) 3)
87 #define PCI_D3cold ((pci_power_t __force) 4)
88 #define PCI_UNKNOWN ((pci_power_t __force) 5)
89 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
90
91 /** The pci_channel state describes connectivity between the CPU and
92 * the pci device. If some PCI bus between here and the pci device
93 * has crashed or locked up, this info is reflected here.
94 */
95 typedef unsigned int __bitwise pci_channel_state_t;
96
97 enum pci_channel_state {
98 /* I/O channel is in normal state */
99 pci_channel_io_normal = (__force pci_channel_state_t) 1,
100
101 /* I/O to channel is blocked */
102 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
103
104 /* PCI card is dead */
105 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
106 };
107
108 typedef unsigned int __bitwise pcie_reset_state_t;
109
110 enum pcie_reset_state {
111 /* Reset is NOT asserted (Use to deassert reset) */
112 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
113
114 /* Use #PERST to reset PCI-E device */
115 pcie_warm_reset = (__force pcie_reset_state_t) 2,
116
117 /* Use PCI-E Hot Reset to reset device */
118 pcie_hot_reset = (__force pcie_reset_state_t) 3
119 };
120
121 typedef unsigned short __bitwise pci_dev_flags_t;
122 enum pci_dev_flags {
123 /* INTX_DISABLE in PCI_COMMAND register disables MSI
124 * generation too.
125 */
126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
127 /* Device configuration is irrevocably lost if disabled into D3 */
128 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
129 };
130
131 typedef unsigned short __bitwise pci_bus_flags_t;
132 enum pci_bus_flags {
133 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
134 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
135 };
136
137 struct pci_cap_saved_state {
138 struct hlist_node next;
139 char cap_nr;
140 u32 data[0];
141 };
142
143 struct pcie_link_state;
144 struct pci_vpd;
145
146 /*
147 * The pci_dev structure is used to describe PCI devices.
148 */
149 struct pci_dev {
150 struct list_head bus_list; /* node in per-bus list */
151 struct pci_bus *bus; /* bus this device is on */
152 struct pci_bus *subordinate; /* bus this device bridges to */
153
154 void *sysdata; /* hook for sys-specific extension */
155 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
156 struct pci_slot *slot; /* Physical slot this device is in */
157
158 unsigned int devfn; /* encoded device & function index */
159 unsigned short vendor;
160 unsigned short device;
161 unsigned short subsystem_vendor;
162 unsigned short subsystem_device;
163 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
164 u8 revision; /* PCI revision, low byte of class word */
165 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
166 u8 pcie_type; /* PCI-E device/port type */
167 u8 rom_base_reg; /* which config register controls the ROM */
168 u8 pin; /* which interrupt pin this device uses */
169
170 struct pci_driver *driver; /* which driver has allocated this device */
171 u64 dma_mask; /* Mask of the bits of bus address this
172 device implements. Normally this is
173 0xffffffff. You only need to change
174 this if your device has broken DMA
175 or supports 64-bit transfers. */
176
177 struct device_dma_parameters dma_parms;
178
179 pci_power_t current_state; /* Current operating state. In ACPI-speak,
180 this is D0-D3, D0 being fully functional,
181 and D3 being off. */
182 int pm_cap; /* PM capability offset in the
183 configuration space */
184 unsigned int pme_support:5; /* Bitmask of states from which PME#
185 can be generated */
186 unsigned int d1_support:1; /* Low power state D1 is supported */
187 unsigned int d2_support:1; /* Low power state D2 is supported */
188 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
189
190 #ifdef CONFIG_PCIEASPM
191 struct pcie_link_state *link_state; /* ASPM link state. */
192 #endif
193
194 pci_channel_state_t error_state; /* current connectivity state */
195 struct device dev; /* Generic device interface */
196
197 int cfg_size; /* Size of configuration space */
198
199 /*
200 * Instead of touching interrupt line and base address registers
201 * directly, use the values stored here. They might be different!
202 */
203 unsigned int irq;
204 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
205
206 /* These fields are used by common fixups */
207 unsigned int transparent:1; /* Transparent PCI bridge */
208 unsigned int multifunction:1;/* Part of multi-function device */
209 /* keep track of device state */
210 unsigned int is_added:1;
211 unsigned int is_busmaster:1; /* device is busmaster */
212 unsigned int no_msi:1; /* device may not use msi */
213 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
214 unsigned int broken_parity_status:1; /* Device generates false positive parity */
215 unsigned int msi_enabled:1;
216 unsigned int msix_enabled:1;
217 unsigned int is_managed:1;
218 unsigned int is_pcie:1;
219 pci_dev_flags_t dev_flags;
220 atomic_t enable_cnt; /* pci_enable_device has been called */
221
222 u32 saved_config_space[16]; /* config space saved at suspend time */
223 struct hlist_head saved_cap_space;
224 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
225 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
226 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
227 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
228 #ifdef CONFIG_PCI_MSI
229 struct list_head msi_list;
230 #endif
231 struct pci_vpd *vpd;
232 };
233
234 extern struct pci_dev *alloc_pci_dev(void);
235
236 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
237 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
238 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
239
240 static inline int pci_channel_offline(struct pci_dev *pdev)
241 {
242 return (pdev->error_state != pci_channel_io_normal);
243 }
244
245 static inline struct pci_cap_saved_state *pci_find_saved_cap(
246 struct pci_dev *pci_dev, char cap)
247 {
248 struct pci_cap_saved_state *tmp;
249 struct hlist_node *pos;
250
251 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
252 if (tmp->cap_nr == cap)
253 return tmp;
254 }
255 return NULL;
256 }
257
258 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
259 struct pci_cap_saved_state *new_cap)
260 {
261 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
262 }
263
264 /*
265 * For PCI devices, the region numbers are assigned this way:
266 *
267 * 0-5 standard PCI regions
268 * 6 expansion ROM
269 * 7-10 bridges: address space assigned to buses behind the bridge
270 */
271
272 #define PCI_ROM_RESOURCE 6
273 #define PCI_BRIDGE_RESOURCES 7
274 #define PCI_NUM_RESOURCES 11
275
276 #ifndef PCI_BUS_NUM_RESOURCES
277 #define PCI_BUS_NUM_RESOURCES 16
278 #endif
279
280 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
281
282 struct pci_bus {
283 struct list_head node; /* node in list of buses */
284 struct pci_bus *parent; /* parent bus this bridge is on */
285 struct list_head children; /* list of child buses */
286 struct list_head devices; /* list of devices on this bus */
287 struct pci_dev *self; /* bridge device as seen by parent */
288 struct list_head slots; /* list of slots on this bus */
289 struct resource *resource[PCI_BUS_NUM_RESOURCES];
290 /* address space routed to this bus */
291
292 struct pci_ops *ops; /* configuration access functions */
293 void *sysdata; /* hook for sys-specific extension */
294 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
295
296 unsigned char number; /* bus number */
297 unsigned char primary; /* number of primary bridge */
298 unsigned char secondary; /* number of secondary bridge */
299 unsigned char subordinate; /* max number of subordinate buses */
300
301 char name[48];
302
303 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
304 pci_bus_flags_t bus_flags; /* Inherited by child busses */
305 struct device *bridge;
306 struct device dev;
307 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
308 struct bin_attribute *legacy_mem; /* legacy mem */
309 unsigned int is_added:1;
310 };
311
312 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
313 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
314
315 /*
316 * Error values that may be returned by PCI functions.
317 */
318 #define PCIBIOS_SUCCESSFUL 0x00
319 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
320 #define PCIBIOS_BAD_VENDOR_ID 0x83
321 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
322 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
323 #define PCIBIOS_SET_FAILED 0x88
324 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
325
326 /* Low-level architecture-dependent routines */
327
328 struct pci_ops {
329 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
330 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
331 };
332
333 /*
334 * ACPI needs to be able to access PCI config space before we've done a
335 * PCI bus scan and created pci_bus structures.
336 */
337 extern int raw_pci_read(unsigned int domain, unsigned int bus,
338 unsigned int devfn, int reg, int len, u32 *val);
339 extern int raw_pci_write(unsigned int domain, unsigned int bus,
340 unsigned int devfn, int reg, int len, u32 val);
341
342 struct pci_bus_region {
343 resource_size_t start;
344 resource_size_t end;
345 };
346
347 struct pci_dynids {
348 spinlock_t lock; /* protects list, index */
349 struct list_head list; /* for IDs added at runtime */
350 };
351
352 /* ---------------------------------------------------------------- */
353 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
354 * a set of callbacks in struct pci_error_handlers, then that device driver
355 * will be notified of PCI bus errors, and will be driven to recovery
356 * when an error occurs.
357 */
358
359 typedef unsigned int __bitwise pci_ers_result_t;
360
361 enum pci_ers_result {
362 /* no result/none/not supported in device driver */
363 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
364
365 /* Device driver can recover without slot reset */
366 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
367
368 /* Device driver wants slot to be reset. */
369 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
370
371 /* Device has completely failed, is unrecoverable */
372 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
373
374 /* Device driver is fully recovered and operational */
375 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
376 };
377
378 /* PCI bus error event callbacks */
379 struct pci_error_handlers {
380 /* PCI bus error detected on this device */
381 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
382 enum pci_channel_state error);
383
384 /* MMIO has been re-enabled, but not DMA */
385 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
386
387 /* PCI Express link has been reset */
388 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
389
390 /* PCI slot has been reset */
391 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
392
393 /* Device driver may resume normal operations */
394 void (*resume)(struct pci_dev *dev);
395 };
396
397 /* ---------------------------------------------------------------- */
398
399 struct module;
400 struct pci_driver {
401 struct list_head node;
402 char *name;
403 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
404 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
405 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
406 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
407 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
408 int (*resume_early) (struct pci_dev *dev);
409 int (*resume) (struct pci_dev *dev); /* Device woken up */
410 void (*shutdown) (struct pci_dev *dev);
411 struct pm_ext_ops *pm;
412 struct pci_error_handlers *err_handler;
413 struct device_driver driver;
414 struct pci_dynids dynids;
415 };
416
417 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
418
419 /**
420 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
421 * @_table: device table name
422 *
423 * This macro is used to create a struct pci_device_id array (a device table)
424 * in a generic manner.
425 */
426 #define DEFINE_PCI_DEVICE_TABLE(_table) \
427 const struct pci_device_id _table[] __devinitconst
428
429 /**
430 * PCI_DEVICE - macro used to describe a specific pci device
431 * @vend: the 16 bit PCI Vendor ID
432 * @dev: the 16 bit PCI Device ID
433 *
434 * This macro is used to create a struct pci_device_id that matches a
435 * specific device. The subvendor and subdevice fields will be set to
436 * PCI_ANY_ID.
437 */
438 #define PCI_DEVICE(vend,dev) \
439 .vendor = (vend), .device = (dev), \
440 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
441
442 /**
443 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
444 * @dev_class: the class, subclass, prog-if triple for this device
445 * @dev_class_mask: the class mask for this device
446 *
447 * This macro is used to create a struct pci_device_id that matches a
448 * specific PCI class. The vendor, device, subvendor, and subdevice
449 * fields will be set to PCI_ANY_ID.
450 */
451 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
452 .class = (dev_class), .class_mask = (dev_class_mask), \
453 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
454 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
455
456 /**
457 * PCI_VDEVICE - macro used to describe a specific pci device in short form
458 * @vend: the vendor name
459 * @dev: the 16 bit PCI Device ID
460 *
461 * This macro is used to create a struct pci_device_id that matches a
462 * specific PCI device. The subvendor, and subdevice fields will be set
463 * to PCI_ANY_ID. The macro allows the next field to follow as the device
464 * private data.
465 */
466
467 #define PCI_VDEVICE(vendor, device) \
468 PCI_VENDOR_ID_##vendor, (device), \
469 PCI_ANY_ID, PCI_ANY_ID, 0, 0
470
471 /* these external functions are only available when PCI support is enabled */
472 #ifdef CONFIG_PCI
473
474 extern struct bus_type pci_bus_type;
475
476 /* Do NOT directly access these two variables, unless you are arch specific pci
477 * code, or pci core code. */
478 extern struct list_head pci_root_buses; /* list of all known PCI buses */
479 /* Some device drivers need know if pci is initiated */
480 extern int no_pci_devices(void);
481
482 void pcibios_fixup_bus(struct pci_bus *);
483 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
484 char *pcibios_setup(char *str);
485
486 /* Used only when drivers/pci/setup.c is used */
487 void pcibios_align_resource(void *, struct resource *, resource_size_t,
488 resource_size_t);
489 void pcibios_update_irq(struct pci_dev *, int irq);
490
491 /* Generic PCI functions used internally */
492
493 extern struct pci_bus *pci_find_bus(int domain, int busnr);
494 void pci_bus_add_devices(struct pci_bus *bus);
495 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
496 struct pci_ops *ops, void *sysdata);
497 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
498 void *sysdata)
499 {
500 struct pci_bus *root_bus;
501 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
502 if (root_bus)
503 pci_bus_add_devices(root_bus);
504 return root_bus;
505 }
506 struct pci_bus *pci_create_bus(struct device *parent, int bus,
507 struct pci_ops *ops, void *sysdata);
508 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
509 int busnr);
510 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
511 const char *name);
512 void pci_destroy_slot(struct pci_slot *slot);
513 void pci_update_slot_number(struct pci_slot *slot, int slot_nr);
514 int pci_scan_slot(struct pci_bus *bus, int devfn);
515 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
516 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
517 unsigned int pci_scan_child_bus(struct pci_bus *bus);
518 int __must_check pci_bus_add_device(struct pci_dev *dev);
519 void pci_read_bridge_bases(struct pci_bus *child);
520 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
521 struct resource *res);
522 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
523 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
524 extern void pci_dev_put(struct pci_dev *dev);
525 extern void pci_remove_bus(struct pci_bus *b);
526 extern void pci_remove_bus_device(struct pci_dev *dev);
527 extern void pci_stop_bus_device(struct pci_dev *dev);
528 void pci_setup_cardbus(struct pci_bus *bus);
529 extern void pci_sort_breadthfirst(void);
530
531 /* Generic PCI functions exported to card drivers */
532
533 #ifdef CONFIG_PCI_LEGACY
534 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
535 unsigned int device,
536 struct pci_dev *from);
537 struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
538 unsigned int devfn);
539 #endif /* CONFIG_PCI_LEGACY */
540
541 int pci_find_capability(struct pci_dev *dev, int cap);
542 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
543 int pci_find_ext_capability(struct pci_dev *dev, int cap);
544 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
545 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
546 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
547
548 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
549 struct pci_dev *from);
550 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
551 unsigned int ss_vendor, unsigned int ss_device,
552 struct pci_dev *from);
553 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
554 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
555 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
556 int pci_dev_present(const struct pci_device_id *ids);
557
558 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
559 int where, u8 *val);
560 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
561 int where, u16 *val);
562 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
563 int where, u32 *val);
564 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
565 int where, u8 val);
566 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
567 int where, u16 val);
568 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
569 int where, u32 val);
570
571 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
572 {
573 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
574 }
575 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
576 {
577 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
578 }
579 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
580 u32 *val)
581 {
582 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
583 }
584 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
585 {
586 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
587 }
588 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
589 {
590 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
591 }
592 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
593 u32 val)
594 {
595 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
596 }
597
598 int __must_check pci_enable_device(struct pci_dev *dev);
599 int __must_check pci_enable_device_io(struct pci_dev *dev);
600 int __must_check pci_enable_device_mem(struct pci_dev *dev);
601 int __must_check pci_reenable_device(struct pci_dev *);
602 int __must_check pcim_enable_device(struct pci_dev *pdev);
603 void pcim_pin_device(struct pci_dev *pdev);
604
605 static inline int pci_is_managed(struct pci_dev *pdev)
606 {
607 return pdev->is_managed;
608 }
609
610 void pci_disable_device(struct pci_dev *dev);
611 void pci_set_master(struct pci_dev *dev);
612 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
613 #define HAVE_PCI_SET_MWI
614 int __must_check pci_set_mwi(struct pci_dev *dev);
615 int pci_try_set_mwi(struct pci_dev *dev);
616 void pci_clear_mwi(struct pci_dev *dev);
617 void pci_intx(struct pci_dev *dev, int enable);
618 void pci_msi_off(struct pci_dev *dev);
619 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
620 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
621 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
622 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
623 int pcix_get_max_mmrbc(struct pci_dev *dev);
624 int pcix_get_mmrbc(struct pci_dev *dev);
625 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
626 int pcie_get_readrq(struct pci_dev *dev);
627 int pcie_set_readrq(struct pci_dev *dev, int rq);
628 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
629 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
630 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
631
632 /* ROM control related routines */
633 int pci_enable_rom(struct pci_dev *pdev);
634 void pci_disable_rom(struct pci_dev *pdev);
635 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
636 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
637 size_t pci_get_rom_size(void __iomem *rom, size_t size);
638
639 /* Power management related routines */
640 int pci_save_state(struct pci_dev *dev);
641 int pci_restore_state(struct pci_dev *dev);
642 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
643 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
644 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
645 void pci_pme_active(struct pci_dev *dev, bool enable);
646 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
647 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
648 pci_power_t pci_target_state(struct pci_dev *dev);
649 int pci_prepare_to_sleep(struct pci_dev *dev);
650 int pci_back_from_sleep(struct pci_dev *dev);
651
652 /* Functions for PCI Hotplug drivers to use */
653 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
654
655 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
656 void pci_bus_assign_resources(struct pci_bus *bus);
657 void pci_bus_size_bridges(struct pci_bus *bus);
658 int pci_claim_resource(struct pci_dev *, int);
659 void pci_assign_unassigned_resources(void);
660 void pdev_enable_device(struct pci_dev *);
661 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
662 int pci_enable_resources(struct pci_dev *, int mask);
663 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
664 int (*)(struct pci_dev *, u8, u8));
665 #define HAVE_PCI_REQ_REGIONS 2
666 int __must_check pci_request_regions(struct pci_dev *, const char *);
667 void pci_release_regions(struct pci_dev *);
668 int __must_check pci_request_region(struct pci_dev *, int, const char *);
669 void pci_release_region(struct pci_dev *, int);
670 int pci_request_selected_regions(struct pci_dev *, int, const char *);
671 void pci_release_selected_regions(struct pci_dev *, int);
672
673 /* drivers/pci/bus.c */
674 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
675 struct resource *res, resource_size_t size,
676 resource_size_t align, resource_size_t min,
677 unsigned int type_mask,
678 void (*alignf)(void *, struct resource *,
679 resource_size_t, resource_size_t),
680 void *alignf_data);
681 void pci_enable_bridges(struct pci_bus *bus);
682
683 /* Proper probing supporting hot-pluggable devices */
684 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
685 const char *mod_name);
686
687 /*
688 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
689 */
690 #define pci_register_driver(driver) \
691 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
692
693 void pci_unregister_driver(struct pci_driver *dev);
694 void pci_remove_behind_bridge(struct pci_dev *dev);
695 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
696 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
697 struct pci_dev *dev);
698 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
699 int pass);
700
701 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
702 void *userdata);
703 int pci_cfg_space_size_ext(struct pci_dev *dev);
704 int pci_cfg_space_size(struct pci_dev *dev);
705 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
706
707 /* kmem_cache style wrapper around pci_alloc_consistent() */
708
709 #include <linux/dmapool.h>
710
711 #define pci_pool dma_pool
712 #define pci_pool_create(name, pdev, size, align, allocation) \
713 dma_pool_create(name, &pdev->dev, size, align, allocation)
714 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
715 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
716 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
717
718 enum pci_dma_burst_strategy {
719 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
720 strategy_parameter is N/A */
721 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
722 byte boundaries */
723 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
724 strategy_parameter byte boundaries */
725 };
726
727 struct msix_entry {
728 u32 vector; /* kernel uses to write allocated vector */
729 u16 entry; /* driver uses to specify entry, OS writes */
730 };
731
732
733 #ifndef CONFIG_PCI_MSI
734 static inline int pci_enable_msi(struct pci_dev *dev)
735 {
736 return -1;
737 }
738
739 static inline void pci_msi_shutdown(struct pci_dev *dev)
740 { }
741 static inline void pci_disable_msi(struct pci_dev *dev)
742 { }
743
744 static inline int pci_enable_msix(struct pci_dev *dev,
745 struct msix_entry *entries, int nvec)
746 {
747 return -1;
748 }
749
750 static inline void pci_msix_shutdown(struct pci_dev *dev)
751 { }
752 static inline void pci_disable_msix(struct pci_dev *dev)
753 { }
754
755 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
756 { }
757
758 static inline void pci_restore_msi_state(struct pci_dev *dev)
759 { }
760 #else
761 extern int pci_enable_msi(struct pci_dev *dev);
762 extern void pci_msi_shutdown(struct pci_dev *dev);
763 extern void pci_disable_msi(struct pci_dev *dev);
764 extern int pci_enable_msix(struct pci_dev *dev,
765 struct msix_entry *entries, int nvec);
766 extern void pci_msix_shutdown(struct pci_dev *dev);
767 extern void pci_disable_msix(struct pci_dev *dev);
768 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
769 extern void pci_restore_msi_state(struct pci_dev *dev);
770 #endif
771
772 #ifdef CONFIG_HT_IRQ
773 /* The functions a driver should call */
774 int ht_create_irq(struct pci_dev *dev, int idx);
775 void ht_destroy_irq(unsigned int irq);
776 #endif /* CONFIG_HT_IRQ */
777
778 extern void pci_block_user_cfg_access(struct pci_dev *dev);
779 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
780
781 /*
782 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
783 * a PCI domain is defined to be a set of PCI busses which share
784 * configuration space.
785 */
786 #ifdef CONFIG_PCI_DOMAINS
787 extern int pci_domains_supported;
788 #else
789 enum { pci_domains_supported = 0 };
790 static inline int pci_domain_nr(struct pci_bus *bus)
791 {
792 return 0;
793 }
794
795 static inline int pci_proc_domain(struct pci_bus *bus)
796 {
797 return 0;
798 }
799 #endif /* CONFIG_PCI_DOMAINS */
800
801 #else /* CONFIG_PCI is not enabled */
802
803 /*
804 * If the system does not have PCI, clearly these return errors. Define
805 * these as simple inline functions to avoid hair in drivers.
806 */
807
808 #define _PCI_NOP(o, s, t) \
809 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
810 int where, t val) \
811 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
812
813 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
814 _PCI_NOP(o, word, u16 x) \
815 _PCI_NOP(o, dword, u32 x)
816 _PCI_NOP_ALL(read, *)
817 _PCI_NOP_ALL(write,)
818
819 static inline struct pci_dev *pci_find_device(unsigned int vendor,
820 unsigned int device,
821 struct pci_dev *from)
822 {
823 return NULL;
824 }
825
826 static inline struct pci_dev *pci_find_slot(unsigned int bus,
827 unsigned int devfn)
828 {
829 return NULL;
830 }
831
832 static inline struct pci_dev *pci_get_device(unsigned int vendor,
833 unsigned int device,
834 struct pci_dev *from)
835 {
836 return NULL;
837 }
838
839 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
840 unsigned int device,
841 unsigned int ss_vendor,
842 unsigned int ss_device,
843 struct pci_dev *from)
844 {
845 return NULL;
846 }
847
848 static inline struct pci_dev *pci_get_class(unsigned int class,
849 struct pci_dev *from)
850 {
851 return NULL;
852 }
853
854 #define pci_dev_present(ids) (0)
855 #define no_pci_devices() (1)
856 #define pci_dev_put(dev) do { } while (0)
857
858 static inline void pci_set_master(struct pci_dev *dev)
859 { }
860
861 static inline int pci_enable_device(struct pci_dev *dev)
862 {
863 return -EIO;
864 }
865
866 static inline void pci_disable_device(struct pci_dev *dev)
867 { }
868
869 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
870 {
871 return -EIO;
872 }
873
874 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
875 {
876 return -EIO;
877 }
878
879 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
880 unsigned int size)
881 {
882 return -EIO;
883 }
884
885 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
886 unsigned long mask)
887 {
888 return -EIO;
889 }
890
891 static inline int pci_assign_resource(struct pci_dev *dev, int i)
892 {
893 return -EBUSY;
894 }
895
896 static inline int __pci_register_driver(struct pci_driver *drv,
897 struct module *owner)
898 {
899 return 0;
900 }
901
902 static inline int pci_register_driver(struct pci_driver *drv)
903 {
904 return 0;
905 }
906
907 static inline void pci_unregister_driver(struct pci_driver *drv)
908 { }
909
910 static inline int pci_find_capability(struct pci_dev *dev, int cap)
911 {
912 return 0;
913 }
914
915 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
916 int cap)
917 {
918 return 0;
919 }
920
921 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
922 {
923 return 0;
924 }
925
926 /* Power management related routines */
927 static inline int pci_save_state(struct pci_dev *dev)
928 {
929 return 0;
930 }
931
932 static inline int pci_restore_state(struct pci_dev *dev)
933 {
934 return 0;
935 }
936
937 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
938 {
939 return 0;
940 }
941
942 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
943 pm_message_t state)
944 {
945 return PCI_D0;
946 }
947
948 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
949 int enable)
950 {
951 return 0;
952 }
953
954 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
955 {
956 return -EIO;
957 }
958
959 static inline void pci_release_regions(struct pci_dev *dev)
960 { }
961
962 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
963
964 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
965 { }
966
967 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
968 { }
969
970 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
971 { return NULL; }
972
973 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
974 unsigned int devfn)
975 { return NULL; }
976
977 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
978 unsigned int devfn)
979 { return NULL; }
980
981 #endif /* CONFIG_PCI */
982
983 /* Include architecture-dependent settings and functions */
984
985 #include <asm/pci.h>
986
987 /* these helpers provide future and backwards compatibility
988 * for accessing popular PCI BAR info */
989 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
990 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
991 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
992 #define pci_resource_len(dev,bar) \
993 ((pci_resource_start((dev), (bar)) == 0 && \
994 pci_resource_end((dev), (bar)) == \
995 pci_resource_start((dev), (bar))) ? 0 : \
996 \
997 (pci_resource_end((dev), (bar)) - \
998 pci_resource_start((dev), (bar)) + 1))
999
1000 /* Similar to the helpers above, these manipulate per-pci_dev
1001 * driver-specific data. They are really just a wrapper around
1002 * the generic device structure functions of these calls.
1003 */
1004 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1005 {
1006 return dev_get_drvdata(&pdev->dev);
1007 }
1008
1009 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1010 {
1011 dev_set_drvdata(&pdev->dev, data);
1012 }
1013
1014 /* If you want to know what to call your pci_dev, ask this function.
1015 * Again, it's a wrapper around the generic device.
1016 */
1017 static inline const char *pci_name(struct pci_dev *pdev)
1018 {
1019 return dev_name(&pdev->dev);
1020 }
1021
1022
1023 /* Some archs don't want to expose struct resource to userland as-is
1024 * in sysfs and /proc
1025 */
1026 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1027 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1028 const struct resource *rsrc, resource_size_t *start,
1029 resource_size_t *end)
1030 {
1031 *start = rsrc->start;
1032 *end = rsrc->end;
1033 }
1034 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1035
1036
1037 /*
1038 * The world is not perfect and supplies us with broken PCI devices.
1039 * For at least a part of these bugs we need a work-around, so both
1040 * generic (drivers/pci/quirks.c) and per-architecture code can define
1041 * fixup hooks to be called for particular buggy devices.
1042 */
1043
1044 struct pci_fixup {
1045 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1046 void (*hook)(struct pci_dev *dev);
1047 };
1048
1049 enum pci_fixup_pass {
1050 pci_fixup_early, /* Before probing BARs */
1051 pci_fixup_header, /* After reading configuration header */
1052 pci_fixup_final, /* Final phase of device fixups */
1053 pci_fixup_enable, /* pci_enable_device() time */
1054 pci_fixup_resume, /* pci_device_resume() */
1055 pci_fixup_suspend, /* pci_device_suspend */
1056 pci_fixup_resume_early, /* pci_device_resume_early() */
1057 };
1058
1059 /* Anonymous variables would be nice... */
1060 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1061 static const struct pci_fixup __pci_fixup_##name __used \
1062 __attribute__((__section__(#section))) = { vendor, device, hook };
1063 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1064 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1065 vendor##device##hook, vendor, device, hook)
1066 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1068 vendor##device##hook, vendor, device, hook)
1069 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1070 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1071 vendor##device##hook, vendor, device, hook)
1072 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1074 vendor##device##hook, vendor, device, hook)
1075 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1076 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1077 resume##vendor##device##hook, vendor, device, hook)
1078 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1079 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1080 resume_early##vendor##device##hook, vendor, device, hook)
1081 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1082 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1083 suspend##vendor##device##hook, vendor, device, hook)
1084
1085
1086 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1087
1088 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1089 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1090 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1091 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1092 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1093 const char *name);
1094 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1095
1096 extern int pci_pci_problems;
1097 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1098 #define PCIPCI_TRITON 2
1099 #define PCIPCI_NATOMA 4
1100 #define PCIPCI_VIAETBF 8
1101 #define PCIPCI_VSFX 16
1102 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1103 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1104
1105 extern unsigned long pci_cardbus_io_size;
1106 extern unsigned long pci_cardbus_mem_size;
1107
1108 int pcibios_add_platform_entries(struct pci_dev *dev);
1109 void pcibios_disable_device(struct pci_dev *dev);
1110 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1111 enum pcie_reset_state state);
1112
1113 #ifdef CONFIG_PCI_MMCONFIG
1114 extern void __init pci_mmcfg_early_init(void);
1115 extern void __init pci_mmcfg_late_init(void);
1116 #else
1117 static inline void pci_mmcfg_early_init(void) { }
1118 static inline void pci_mmcfg_late_init(void) { }
1119 #endif
1120
1121 #endif /* __KERNEL__ */
1122 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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