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PCI: Add pcie_flags_reg to cache PCIe capabilities register
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_D3COLD_WAIT 100
138 #define PCI_PM_BUS_WAIT 50
139
140 /** The pci_channel state describes connectivity between the CPU and
141 * the pci device. If some PCI bus between here and the pci device
142 * has crashed or locked up, this info is reflected here.
143 */
144 typedef unsigned int __bitwise pci_channel_state_t;
145
146 enum pci_channel_state {
147 /* I/O channel is in normal state */
148 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149
150 /* I/O to channel is blocked */
151 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152
153 /* PCI card is dead */
154 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
155 };
156
157 typedef unsigned int __bitwise pcie_reset_state_t;
158
159 enum pcie_reset_state {
160 /* Reset is NOT asserted (Use to deassert reset) */
161 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162
163 /* Use #PERST to reset PCI-E device */
164 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165
166 /* Use PCI-E Hot Reset to reset device */
167 pcie_hot_reset = (__force pcie_reset_state_t) 3
168 };
169
170 typedef unsigned short __bitwise pci_dev_flags_t;
171 enum pci_dev_flags {
172 /* INTX_DISABLE in PCI_COMMAND register disables MSI
173 * generation too.
174 */
175 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
176 /* Device configuration is irrevocably lost if disabled into D3 */
177 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
178 /* Provide indication device is assigned by a Virtual Machine Manager */
179 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
180 };
181
182 enum pci_irq_reroute_variant {
183 INTEL_IRQ_REROUTE_VARIANT = 1,
184 MAX_IRQ_REROUTE_VARIANTS = 3
185 };
186
187 typedef unsigned short __bitwise pci_bus_flags_t;
188 enum pci_bus_flags {
189 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
190 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
191 };
192
193 /* Based on the PCI Hotplug Spec, but some values are made up by us */
194 enum pci_bus_speed {
195 PCI_SPEED_33MHz = 0x00,
196 PCI_SPEED_66MHz = 0x01,
197 PCI_SPEED_66MHz_PCIX = 0x02,
198 PCI_SPEED_100MHz_PCIX = 0x03,
199 PCI_SPEED_133MHz_PCIX = 0x04,
200 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
201 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
202 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
203 PCI_SPEED_66MHz_PCIX_266 = 0x09,
204 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
205 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
206 AGP_UNKNOWN = 0x0c,
207 AGP_1X = 0x0d,
208 AGP_2X = 0x0e,
209 AGP_4X = 0x0f,
210 AGP_8X = 0x10,
211 PCI_SPEED_66MHz_PCIX_533 = 0x11,
212 PCI_SPEED_100MHz_PCIX_533 = 0x12,
213 PCI_SPEED_133MHz_PCIX_533 = 0x13,
214 PCIE_SPEED_2_5GT = 0x14,
215 PCIE_SPEED_5_0GT = 0x15,
216 PCIE_SPEED_8_0GT = 0x16,
217 PCI_SPEED_UNKNOWN = 0xff,
218 };
219
220 struct pci_cap_saved_data {
221 char cap_nr;
222 unsigned int size;
223 u32 data[0];
224 };
225
226 struct pci_cap_saved_state {
227 struct hlist_node next;
228 struct pci_cap_saved_data cap;
229 };
230
231 struct pcie_link_state;
232 struct pci_vpd;
233 struct pci_sriov;
234 struct pci_ats;
235
236 /*
237 * The pci_dev structure is used to describe PCI devices.
238 */
239 struct pci_dev {
240 struct list_head bus_list; /* node in per-bus list */
241 struct pci_bus *bus; /* bus this device is on */
242 struct pci_bus *subordinate; /* bus this device bridges to */
243
244 void *sysdata; /* hook for sys-specific extension */
245 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
246 struct pci_slot *slot; /* Physical slot this device is in */
247
248 unsigned int devfn; /* encoded device & function index */
249 unsigned short vendor;
250 unsigned short device;
251 unsigned short subsystem_vendor;
252 unsigned short subsystem_device;
253 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
254 u8 revision; /* PCI revision, low byte of class word */
255 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
256 u8 pcie_cap; /* PCI-E capability offset */
257 u8 pcie_type:4; /* PCI-E device/port type */
258 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
259 u8 rom_base_reg; /* which config register controls the ROM */
260 u8 pin; /* which interrupt pin this device uses */
261 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
262
263 struct pci_driver *driver; /* which driver has allocated this device */
264 u64 dma_mask; /* Mask of the bits of bus address this
265 device implements. Normally this is
266 0xffffffff. You only need to change
267 this if your device has broken DMA
268 or supports 64-bit transfers. */
269
270 struct device_dma_parameters dma_parms;
271
272 pci_power_t current_state; /* Current operating state. In ACPI-speak,
273 this is D0-D3, D0 being fully functional,
274 and D3 being off. */
275 int pm_cap; /* PM capability offset in the
276 configuration space */
277 unsigned int pme_support:5; /* Bitmask of states from which PME#
278 can be generated */
279 unsigned int pme_interrupt:1;
280 unsigned int pme_poll:1; /* Poll device's PME status bit */
281 unsigned int d1_support:1; /* Low power state D1 is supported */
282 unsigned int d2_support:1; /* Low power state D2 is supported */
283 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
284 unsigned int no_d3cold:1; /* D3cold is forbidden */
285 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
286 unsigned int mmio_always_on:1; /* disallow turning off io/mem
287 decoding during bar sizing */
288 unsigned int wakeup_prepared:1;
289 unsigned int runtime_d3cold:1; /* whether go through runtime
290 D3cold, not set for devices
291 powered on/off by the
292 corresponding bridge */
293 unsigned int d3_delay; /* D3->D0 transition time in ms */
294 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
295
296 #ifdef CONFIG_PCIEASPM
297 struct pcie_link_state *link_state; /* ASPM link state. */
298 #endif
299
300 pci_channel_state_t error_state; /* current connectivity state */
301 struct device dev; /* Generic device interface */
302
303 int cfg_size; /* Size of configuration space */
304
305 /*
306 * Instead of touching interrupt line and base address registers
307 * directly, use the values stored here. They might be different!
308 */
309 unsigned int irq;
310 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
311
312 /* These fields are used by common fixups */
313 unsigned int transparent:1; /* Transparent PCI bridge */
314 unsigned int multifunction:1;/* Part of multi-function device */
315 /* keep track of device state */
316 unsigned int is_added:1;
317 unsigned int is_busmaster:1; /* device is busmaster */
318 unsigned int no_msi:1; /* device may not use msi */
319 unsigned int block_cfg_access:1; /* config space access is blocked */
320 unsigned int broken_parity_status:1; /* Device generates false positive parity */
321 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
322 unsigned int msi_enabled:1;
323 unsigned int msix_enabled:1;
324 unsigned int ari_enabled:1; /* ARI forwarding */
325 unsigned int is_managed:1;
326 unsigned int is_pcie:1; /* Obsolete. Will be removed.
327 Use pci_is_pcie() instead */
328 unsigned int needs_freset:1; /* Dev requires fundamental reset */
329 unsigned int state_saved:1;
330 unsigned int is_physfn:1;
331 unsigned int is_virtfn:1;
332 unsigned int reset_fn:1;
333 unsigned int is_hotplug_bridge:1;
334 unsigned int __aer_firmware_first_valid:1;
335 unsigned int __aer_firmware_first:1;
336 unsigned int broken_intx_masking:1;
337 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
338 pci_dev_flags_t dev_flags;
339 atomic_t enable_cnt; /* pci_enable_device has been called */
340
341 u32 saved_config_space[16]; /* config space saved at suspend time */
342 struct hlist_head saved_cap_space;
343 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
344 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
345 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
346 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
347 #ifdef CONFIG_PCI_MSI
348 struct list_head msi_list;
349 struct kset *msi_kset;
350 #endif
351 struct pci_vpd *vpd;
352 #ifdef CONFIG_PCI_ATS
353 union {
354 struct pci_sriov *sriov; /* SR-IOV capability related */
355 struct pci_dev *physfn; /* the PF this VF is associated with */
356 };
357 struct pci_ats *ats; /* Address Translation Service */
358 #endif
359 };
360
361 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
362 {
363 #ifdef CONFIG_PCI_IOV
364 if (dev->is_virtfn)
365 dev = dev->physfn;
366 #endif
367
368 return dev;
369 }
370
371 extern struct pci_dev *alloc_pci_dev(void);
372
373 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
374 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
375 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
376
377 static inline int pci_channel_offline(struct pci_dev *pdev)
378 {
379 return (pdev->error_state != pci_channel_io_normal);
380 }
381
382 extern struct resource busn_resource;
383
384 struct pci_host_bridge_window {
385 struct list_head list;
386 struct resource *res; /* host bridge aperture (CPU address) */
387 resource_size_t offset; /* bus address + offset = CPU address */
388 };
389
390 struct pci_host_bridge {
391 struct device dev;
392 struct pci_bus *bus; /* root bus */
393 struct list_head windows; /* pci_host_bridge_windows */
394 void (*release_fn)(struct pci_host_bridge *);
395 void *release_data;
396 };
397
398 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
399 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
400 void (*release_fn)(struct pci_host_bridge *),
401 void *release_data);
402
403 /*
404 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
405 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
406 * buses below host bridges or subtractive decode bridges) go in the list.
407 * Use pci_bus_for_each_resource() to iterate through all the resources.
408 */
409
410 /*
411 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
412 * and there's no way to program the bridge with the details of the window.
413 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
414 * decode bit set, because they are explicit and can be programmed with _SRS.
415 */
416 #define PCI_SUBTRACTIVE_DECODE 0x1
417
418 struct pci_bus_resource {
419 struct list_head list;
420 struct resource *res;
421 unsigned int flags;
422 };
423
424 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
425
426 struct pci_bus {
427 struct list_head node; /* node in list of buses */
428 struct pci_bus *parent; /* parent bus this bridge is on */
429 struct list_head children; /* list of child buses */
430 struct list_head devices; /* list of devices on this bus */
431 struct pci_dev *self; /* bridge device as seen by parent */
432 struct list_head slots; /* list of slots on this bus */
433 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
434 struct list_head resources; /* address space routed to this bus */
435 struct resource busn_res; /* bus numbers routed to this bus */
436
437 struct pci_ops *ops; /* configuration access functions */
438 void *sysdata; /* hook for sys-specific extension */
439 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
440
441 unsigned char number; /* bus number */
442 unsigned char primary; /* number of primary bridge */
443 unsigned char max_bus_speed; /* enum pci_bus_speed */
444 unsigned char cur_bus_speed; /* enum pci_bus_speed */
445
446 char name[48];
447
448 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
449 pci_bus_flags_t bus_flags; /* Inherited by child busses */
450 struct device *bridge;
451 struct device dev;
452 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
453 struct bin_attribute *legacy_mem; /* legacy mem */
454 unsigned int is_added:1;
455 };
456
457 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
458 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
459
460 /*
461 * Returns true if the pci bus is root (behind host-pci bridge),
462 * false otherwise
463 */
464 static inline bool pci_is_root_bus(struct pci_bus *pbus)
465 {
466 return !(pbus->parent);
467 }
468
469 #ifdef CONFIG_PCI_MSI
470 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
471 {
472 return pci_dev->msi_enabled || pci_dev->msix_enabled;
473 }
474 #else
475 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
476 #endif
477
478 /*
479 * Error values that may be returned by PCI functions.
480 */
481 #define PCIBIOS_SUCCESSFUL 0x00
482 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
483 #define PCIBIOS_BAD_VENDOR_ID 0x83
484 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
485 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
486 #define PCIBIOS_SET_FAILED 0x88
487 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
488
489 /*
490 * Translate above to generic errno for passing back through non-pci.
491 */
492 static inline int pcibios_err_to_errno(int err)
493 {
494 if (err <= PCIBIOS_SUCCESSFUL)
495 return err; /* Assume already errno */
496
497 switch (err) {
498 case PCIBIOS_FUNC_NOT_SUPPORTED:
499 return -ENOENT;
500 case PCIBIOS_BAD_VENDOR_ID:
501 return -EINVAL;
502 case PCIBIOS_DEVICE_NOT_FOUND:
503 return -ENODEV;
504 case PCIBIOS_BAD_REGISTER_NUMBER:
505 return -EFAULT;
506 case PCIBIOS_SET_FAILED:
507 return -EIO;
508 case PCIBIOS_BUFFER_TOO_SMALL:
509 return -ENOSPC;
510 }
511
512 return -ENOTTY;
513 }
514
515 /* Low-level architecture-dependent routines */
516
517 struct pci_ops {
518 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
519 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
520 };
521
522 /*
523 * ACPI needs to be able to access PCI config space before we've done a
524 * PCI bus scan and created pci_bus structures.
525 */
526 extern int raw_pci_read(unsigned int domain, unsigned int bus,
527 unsigned int devfn, int reg, int len, u32 *val);
528 extern int raw_pci_write(unsigned int domain, unsigned int bus,
529 unsigned int devfn, int reg, int len, u32 val);
530
531 struct pci_bus_region {
532 resource_size_t start;
533 resource_size_t end;
534 };
535
536 struct pci_dynids {
537 spinlock_t lock; /* protects list, index */
538 struct list_head list; /* for IDs added at runtime */
539 };
540
541 /* ---------------------------------------------------------------- */
542 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
543 * a set of callbacks in struct pci_error_handlers, then that device driver
544 * will be notified of PCI bus errors, and will be driven to recovery
545 * when an error occurs.
546 */
547
548 typedef unsigned int __bitwise pci_ers_result_t;
549
550 enum pci_ers_result {
551 /* no result/none/not supported in device driver */
552 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
553
554 /* Device driver can recover without slot reset */
555 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
556
557 /* Device driver wants slot to be reset. */
558 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
559
560 /* Device has completely failed, is unrecoverable */
561 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
562
563 /* Device driver is fully recovered and operational */
564 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
565 };
566
567 /* PCI bus error event callbacks */
568 struct pci_error_handlers {
569 /* PCI bus error detected on this device */
570 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
571 enum pci_channel_state error);
572
573 /* MMIO has been re-enabled, but not DMA */
574 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
575
576 /* PCI Express link has been reset */
577 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
578
579 /* PCI slot has been reset */
580 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
581
582 /* Device driver may resume normal operations */
583 void (*resume)(struct pci_dev *dev);
584 };
585
586 /* ---------------------------------------------------------------- */
587
588 struct module;
589 struct pci_driver {
590 struct list_head node;
591 const char *name;
592 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
593 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
594 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
595 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
596 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
597 int (*resume_early) (struct pci_dev *dev);
598 int (*resume) (struct pci_dev *dev); /* Device woken up */
599 void (*shutdown) (struct pci_dev *dev);
600 struct pci_error_handlers *err_handler;
601 struct device_driver driver;
602 struct pci_dynids dynids;
603 };
604
605 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
606
607 /**
608 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
609 * @_table: device table name
610 *
611 * This macro is used to create a struct pci_device_id array (a device table)
612 * in a generic manner.
613 */
614 #define DEFINE_PCI_DEVICE_TABLE(_table) \
615 const struct pci_device_id _table[] __devinitconst
616
617 /**
618 * PCI_DEVICE - macro used to describe a specific pci device
619 * @vend: the 16 bit PCI Vendor ID
620 * @dev: the 16 bit PCI Device ID
621 *
622 * This macro is used to create a struct pci_device_id that matches a
623 * specific device. The subvendor and subdevice fields will be set to
624 * PCI_ANY_ID.
625 */
626 #define PCI_DEVICE(vend,dev) \
627 .vendor = (vend), .device = (dev), \
628 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
629
630 /**
631 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
632 * @dev_class: the class, subclass, prog-if triple for this device
633 * @dev_class_mask: the class mask for this device
634 *
635 * This macro is used to create a struct pci_device_id that matches a
636 * specific PCI class. The vendor, device, subvendor, and subdevice
637 * fields will be set to PCI_ANY_ID.
638 */
639 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
640 .class = (dev_class), .class_mask = (dev_class_mask), \
641 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
642 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
643
644 /**
645 * PCI_VDEVICE - macro used to describe a specific pci device in short form
646 * @vendor: the vendor name
647 * @device: the 16 bit PCI Device ID
648 *
649 * This macro is used to create a struct pci_device_id that matches a
650 * specific PCI device. The subvendor, and subdevice fields will be set
651 * to PCI_ANY_ID. The macro allows the next field to follow as the device
652 * private data.
653 */
654
655 #define PCI_VDEVICE(vendor, device) \
656 PCI_VENDOR_ID_##vendor, (device), \
657 PCI_ANY_ID, PCI_ANY_ID, 0, 0
658
659 /* these external functions are only available when PCI support is enabled */
660 #ifdef CONFIG_PCI
661
662 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
663
664 enum pcie_bus_config_types {
665 PCIE_BUS_TUNE_OFF,
666 PCIE_BUS_SAFE,
667 PCIE_BUS_PERFORMANCE,
668 PCIE_BUS_PEER2PEER,
669 };
670
671 extern enum pcie_bus_config_types pcie_bus_config;
672
673 extern struct bus_type pci_bus_type;
674
675 /* Do NOT directly access these two variables, unless you are arch specific pci
676 * code, or pci core code. */
677 extern struct list_head pci_root_buses; /* list of all known PCI buses */
678 /* Some device drivers need know if pci is initiated */
679 extern int no_pci_devices(void);
680
681 void pcibios_fixup_bus(struct pci_bus *);
682 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
683 /* Architecture specific versions may override this (weak) */
684 char *pcibios_setup(char *str);
685
686 /* Used only when drivers/pci/setup.c is used */
687 resource_size_t pcibios_align_resource(void *, const struct resource *,
688 resource_size_t,
689 resource_size_t);
690 void pcibios_update_irq(struct pci_dev *, int irq);
691
692 /* Weak but can be overriden by arch */
693 void pci_fixup_cardbus(struct pci_bus *);
694
695 /* Generic PCI functions used internally */
696
697 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
698 struct resource *res);
699 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
700 struct pci_bus_region *region);
701 void pcibios_scan_specific_bus(int busn);
702 extern struct pci_bus *pci_find_bus(int domain, int busnr);
703 void pci_bus_add_devices(const struct pci_bus *bus);
704 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
705 struct pci_ops *ops, void *sysdata);
706 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
707 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
708 struct pci_ops *ops, void *sysdata,
709 struct list_head *resources);
710 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
711 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
712 void pci_bus_release_busn_res(struct pci_bus *b);
713 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
714 struct pci_ops *ops, void *sysdata,
715 struct list_head *resources);
716 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
717 int busnr);
718 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
719 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
720 const char *name,
721 struct hotplug_slot *hotplug);
722 void pci_destroy_slot(struct pci_slot *slot);
723 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
724 int pci_scan_slot(struct pci_bus *bus, int devfn);
725 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
726 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
727 unsigned int pci_scan_child_bus(struct pci_bus *bus);
728 int __must_check pci_bus_add_device(struct pci_dev *dev);
729 void pci_read_bridge_bases(struct pci_bus *child);
730 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
731 struct resource *res);
732 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
733 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
734 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
735 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
736 extern void pci_dev_put(struct pci_dev *dev);
737 extern void pci_remove_bus(struct pci_bus *b);
738 extern void __pci_remove_bus_device(struct pci_dev *dev);
739 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
740 extern void pci_stop_bus_device(struct pci_dev *dev);
741 void pci_setup_cardbus(struct pci_bus *bus);
742 extern void pci_sort_breadthfirst(void);
743 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
744 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
745 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
746
747 /* Generic PCI functions exported to card drivers */
748
749 enum pci_lost_interrupt_reason {
750 PCI_LOST_IRQ_NO_INFORMATION = 0,
751 PCI_LOST_IRQ_DISABLE_MSI,
752 PCI_LOST_IRQ_DISABLE_MSIX,
753 PCI_LOST_IRQ_DISABLE_ACPI,
754 };
755 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
756 int pci_find_capability(struct pci_dev *dev, int cap);
757 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
758 int pci_find_ext_capability(struct pci_dev *dev, int cap);
759 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
760 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
761 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
762
763 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
764 struct pci_dev *from);
765 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
766 unsigned int ss_vendor, unsigned int ss_device,
767 struct pci_dev *from);
768 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
769 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
770 unsigned int devfn);
771 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
772 unsigned int devfn)
773 {
774 return pci_get_domain_bus_and_slot(0, bus, devfn);
775 }
776 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
777 int pci_dev_present(const struct pci_device_id *ids);
778
779 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
780 int where, u8 *val);
781 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
782 int where, u16 *val);
783 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
784 int where, u32 *val);
785 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
786 int where, u8 val);
787 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
788 int where, u16 val);
789 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
790 int where, u32 val);
791 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
792
793 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
794 {
795 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
796 }
797 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
798 {
799 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
800 }
801 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
802 u32 *val)
803 {
804 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
805 }
806 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
807 {
808 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
809 }
810 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
811 {
812 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
813 }
814 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
815 u32 val)
816 {
817 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
818 }
819
820 /* user-space driven config access */
821 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
822 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
823 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
824 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
825 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
826 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
827
828 int __must_check pci_enable_device(struct pci_dev *dev);
829 int __must_check pci_enable_device_io(struct pci_dev *dev);
830 int __must_check pci_enable_device_mem(struct pci_dev *dev);
831 int __must_check pci_reenable_device(struct pci_dev *);
832 int __must_check pcim_enable_device(struct pci_dev *pdev);
833 void pcim_pin_device(struct pci_dev *pdev);
834
835 static inline int pci_is_enabled(struct pci_dev *pdev)
836 {
837 return (atomic_read(&pdev->enable_cnt) > 0);
838 }
839
840 static inline int pci_is_managed(struct pci_dev *pdev)
841 {
842 return pdev->is_managed;
843 }
844
845 void pci_disable_device(struct pci_dev *dev);
846
847 extern unsigned int pcibios_max_latency;
848 void pci_set_master(struct pci_dev *dev);
849 void pci_clear_master(struct pci_dev *dev);
850
851 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
852 int pci_set_cacheline_size(struct pci_dev *dev);
853 #define HAVE_PCI_SET_MWI
854 int __must_check pci_set_mwi(struct pci_dev *dev);
855 int pci_try_set_mwi(struct pci_dev *dev);
856 void pci_clear_mwi(struct pci_dev *dev);
857 void pci_intx(struct pci_dev *dev, int enable);
858 bool pci_intx_mask_supported(struct pci_dev *dev);
859 bool pci_check_and_mask_intx(struct pci_dev *dev);
860 bool pci_check_and_unmask_intx(struct pci_dev *dev);
861 void pci_msi_off(struct pci_dev *dev);
862 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
863 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
864 int pcix_get_max_mmrbc(struct pci_dev *dev);
865 int pcix_get_mmrbc(struct pci_dev *dev);
866 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
867 int pcie_get_readrq(struct pci_dev *dev);
868 int pcie_set_readrq(struct pci_dev *dev, int rq);
869 int pcie_get_mps(struct pci_dev *dev);
870 int pcie_set_mps(struct pci_dev *dev, int mps);
871 int __pci_reset_function(struct pci_dev *dev);
872 int __pci_reset_function_locked(struct pci_dev *dev);
873 int pci_reset_function(struct pci_dev *dev);
874 void pci_update_resource(struct pci_dev *dev, int resno);
875 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
876 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
877 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
878
879 /* ROM control related routines */
880 int pci_enable_rom(struct pci_dev *pdev);
881 void pci_disable_rom(struct pci_dev *pdev);
882 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
883 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
884 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
885
886 /* Power management related routines */
887 int pci_save_state(struct pci_dev *dev);
888 void pci_restore_state(struct pci_dev *dev);
889 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
890 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
891 int pci_load_and_free_saved_state(struct pci_dev *dev,
892 struct pci_saved_state **state);
893 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
894 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
895 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
896 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
897 void pci_pme_active(struct pci_dev *dev, bool enable);
898 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
899 bool runtime, bool enable);
900 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
901 pci_power_t pci_target_state(struct pci_dev *dev);
902 int pci_prepare_to_sleep(struct pci_dev *dev);
903 int pci_back_from_sleep(struct pci_dev *dev);
904 bool pci_dev_run_wake(struct pci_dev *dev);
905 bool pci_check_pme_status(struct pci_dev *dev);
906 void pci_pme_wakeup_bus(struct pci_bus *bus);
907
908 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
909 bool enable)
910 {
911 return __pci_enable_wake(dev, state, false, enable);
912 }
913
914 #define PCI_EXP_IDO_REQUEST (1<<0)
915 #define PCI_EXP_IDO_COMPLETION (1<<1)
916 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
917 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
918
919 enum pci_obff_signal_type {
920 PCI_EXP_OBFF_SIGNAL_L0 = 0,
921 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
922 };
923 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
924 void pci_disable_obff(struct pci_dev *dev);
925
926 int pci_enable_ltr(struct pci_dev *dev);
927 void pci_disable_ltr(struct pci_dev *dev);
928 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
929
930 /* For use by arch with custom probe code */
931 void set_pcie_port_type(struct pci_dev *pdev);
932 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
933
934 /* Functions for PCI Hotplug drivers to use */
935 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
936 #ifdef CONFIG_HOTPLUG
937 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
938 unsigned int pci_rescan_bus(struct pci_bus *bus);
939 #endif
940
941 /* Vital product data routines */
942 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
943 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
944 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
945
946 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
947 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
948 void pci_bus_assign_resources(const struct pci_bus *bus);
949 void pci_bus_size_bridges(struct pci_bus *bus);
950 int pci_claim_resource(struct pci_dev *, int);
951 void pci_assign_unassigned_resources(void);
952 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
953 void pdev_enable_device(struct pci_dev *);
954 int pci_enable_resources(struct pci_dev *, int mask);
955 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
956 int (*)(const struct pci_dev *, u8, u8));
957 #define HAVE_PCI_REQ_REGIONS 2
958 int __must_check pci_request_regions(struct pci_dev *, const char *);
959 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
960 void pci_release_regions(struct pci_dev *);
961 int __must_check pci_request_region(struct pci_dev *, int, const char *);
962 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
963 void pci_release_region(struct pci_dev *, int);
964 int pci_request_selected_regions(struct pci_dev *, int, const char *);
965 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
966 void pci_release_selected_regions(struct pci_dev *, int);
967
968 /* drivers/pci/bus.c */
969 void pci_add_resource(struct list_head *resources, struct resource *res);
970 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
971 resource_size_t offset);
972 void pci_free_resource_list(struct list_head *resources);
973 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
974 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
975 void pci_bus_remove_resources(struct pci_bus *bus);
976
977 #define pci_bus_for_each_resource(bus, res, i) \
978 for (i = 0; \
979 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
980 i++)
981
982 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
983 struct resource *res, resource_size_t size,
984 resource_size_t align, resource_size_t min,
985 unsigned int type_mask,
986 resource_size_t (*alignf)(void *,
987 const struct resource *,
988 resource_size_t,
989 resource_size_t),
990 void *alignf_data);
991 void pci_enable_bridges(struct pci_bus *bus);
992
993 /* Proper probing supporting hot-pluggable devices */
994 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
995 const char *mod_name);
996
997 /*
998 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
999 */
1000 #define pci_register_driver(driver) \
1001 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1002
1003 void pci_unregister_driver(struct pci_driver *dev);
1004
1005 /**
1006 * module_pci_driver() - Helper macro for registering a PCI driver
1007 * @__pci_driver: pci_driver struct
1008 *
1009 * Helper macro for PCI drivers which do not do anything special in module
1010 * init/exit. This eliminates a lot of boilerplate. Each module may only
1011 * use this macro once, and calling it replaces module_init() and module_exit()
1012 */
1013 #define module_pci_driver(__pci_driver) \
1014 module_driver(__pci_driver, pci_register_driver, \
1015 pci_unregister_driver)
1016
1017 void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
1018 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1019 int pci_add_dynid(struct pci_driver *drv,
1020 unsigned int vendor, unsigned int device,
1021 unsigned int subvendor, unsigned int subdevice,
1022 unsigned int class, unsigned int class_mask,
1023 unsigned long driver_data);
1024 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1025 struct pci_dev *dev);
1026 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1027 int pass);
1028
1029 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1030 void *userdata);
1031 int pci_cfg_space_size_ext(struct pci_dev *dev);
1032 int pci_cfg_space_size(struct pci_dev *dev);
1033 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1034 void pci_setup_bridge(struct pci_bus *bus);
1035
1036 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1037 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1038
1039 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1040 unsigned int command_bits, u32 flags);
1041 /* kmem_cache style wrapper around pci_alloc_consistent() */
1042
1043 #include <linux/pci-dma.h>
1044 #include <linux/dmapool.h>
1045
1046 #define pci_pool dma_pool
1047 #define pci_pool_create(name, pdev, size, align, allocation) \
1048 dma_pool_create(name, &pdev->dev, size, align, allocation)
1049 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1050 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1051 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1052
1053 enum pci_dma_burst_strategy {
1054 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1055 strategy_parameter is N/A */
1056 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1057 byte boundaries */
1058 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1059 strategy_parameter byte boundaries */
1060 };
1061
1062 struct msix_entry {
1063 u32 vector; /* kernel uses to write allocated vector */
1064 u16 entry; /* driver uses to specify entry, OS writes */
1065 };
1066
1067
1068 #ifndef CONFIG_PCI_MSI
1069 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1070 {
1071 return -1;
1072 }
1073
1074 static inline void pci_msi_shutdown(struct pci_dev *dev)
1075 { }
1076 static inline void pci_disable_msi(struct pci_dev *dev)
1077 { }
1078
1079 static inline int pci_msix_table_size(struct pci_dev *dev)
1080 {
1081 return 0;
1082 }
1083 static inline int pci_enable_msix(struct pci_dev *dev,
1084 struct msix_entry *entries, int nvec)
1085 {
1086 return -1;
1087 }
1088
1089 static inline void pci_msix_shutdown(struct pci_dev *dev)
1090 { }
1091 static inline void pci_disable_msix(struct pci_dev *dev)
1092 { }
1093
1094 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1095 { }
1096
1097 static inline void pci_restore_msi_state(struct pci_dev *dev)
1098 { }
1099 static inline int pci_msi_enabled(void)
1100 {
1101 return 0;
1102 }
1103 #else
1104 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1105 extern void pci_msi_shutdown(struct pci_dev *dev);
1106 extern void pci_disable_msi(struct pci_dev *dev);
1107 extern int pci_msix_table_size(struct pci_dev *dev);
1108 extern int pci_enable_msix(struct pci_dev *dev,
1109 struct msix_entry *entries, int nvec);
1110 extern void pci_msix_shutdown(struct pci_dev *dev);
1111 extern void pci_disable_msix(struct pci_dev *dev);
1112 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1113 extern void pci_restore_msi_state(struct pci_dev *dev);
1114 extern int pci_msi_enabled(void);
1115 #endif
1116
1117 #ifdef CONFIG_PCIEPORTBUS
1118 extern bool pcie_ports_disabled;
1119 extern bool pcie_ports_auto;
1120 #else
1121 #define pcie_ports_disabled true
1122 #define pcie_ports_auto false
1123 #endif
1124
1125 #ifndef CONFIG_PCIEASPM
1126 static inline int pcie_aspm_enabled(void) { return 0; }
1127 static inline bool pcie_aspm_support_enabled(void) { return false; }
1128 #else
1129 extern int pcie_aspm_enabled(void);
1130 extern bool pcie_aspm_support_enabled(void);
1131 #endif
1132
1133 #ifdef CONFIG_PCIEAER
1134 void pci_no_aer(void);
1135 bool pci_aer_available(void);
1136 #else
1137 static inline void pci_no_aer(void) { }
1138 static inline bool pci_aer_available(void) { return false; }
1139 #endif
1140
1141 #ifndef CONFIG_PCIE_ECRC
1142 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1143 {
1144 return;
1145 }
1146 static inline void pcie_ecrc_get_policy(char *str) {};
1147 #else
1148 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1149 extern void pcie_ecrc_get_policy(char *str);
1150 #endif
1151
1152 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1153
1154 #ifdef CONFIG_HT_IRQ
1155 /* The functions a driver should call */
1156 int ht_create_irq(struct pci_dev *dev, int idx);
1157 void ht_destroy_irq(unsigned int irq);
1158 #endif /* CONFIG_HT_IRQ */
1159
1160 extern void pci_cfg_access_lock(struct pci_dev *dev);
1161 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1162 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1163
1164 /*
1165 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1166 * a PCI domain is defined to be a set of PCI busses which share
1167 * configuration space.
1168 */
1169 #ifdef CONFIG_PCI_DOMAINS
1170 extern int pci_domains_supported;
1171 #else
1172 enum { pci_domains_supported = 0 };
1173 static inline int pci_domain_nr(struct pci_bus *bus)
1174 {
1175 return 0;
1176 }
1177
1178 static inline int pci_proc_domain(struct pci_bus *bus)
1179 {
1180 return 0;
1181 }
1182 #endif /* CONFIG_PCI_DOMAINS */
1183
1184 /* some architectures require additional setup to direct VGA traffic */
1185 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1186 unsigned int command_bits, u32 flags);
1187 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1188
1189 #else /* CONFIG_PCI is not enabled */
1190
1191 /*
1192 * If the system does not have PCI, clearly these return errors. Define
1193 * these as simple inline functions to avoid hair in drivers.
1194 */
1195
1196 #define _PCI_NOP(o, s, t) \
1197 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1198 int where, t val) \
1199 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1200
1201 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1202 _PCI_NOP(o, word, u16 x) \
1203 _PCI_NOP(o, dword, u32 x)
1204 _PCI_NOP_ALL(read, *)
1205 _PCI_NOP_ALL(write,)
1206
1207 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1208 unsigned int device,
1209 struct pci_dev *from)
1210 {
1211 return NULL;
1212 }
1213
1214 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1215 unsigned int device,
1216 unsigned int ss_vendor,
1217 unsigned int ss_device,
1218 struct pci_dev *from)
1219 {
1220 return NULL;
1221 }
1222
1223 static inline struct pci_dev *pci_get_class(unsigned int class,
1224 struct pci_dev *from)
1225 {
1226 return NULL;
1227 }
1228
1229 #define pci_dev_present(ids) (0)
1230 #define no_pci_devices() (1)
1231 #define pci_dev_put(dev) do { } while (0)
1232
1233 static inline void pci_set_master(struct pci_dev *dev)
1234 { }
1235
1236 static inline int pci_enable_device(struct pci_dev *dev)
1237 {
1238 return -EIO;
1239 }
1240
1241 static inline void pci_disable_device(struct pci_dev *dev)
1242 { }
1243
1244 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1245 {
1246 return -EIO;
1247 }
1248
1249 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1250 {
1251 return -EIO;
1252 }
1253
1254 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1255 unsigned int size)
1256 {
1257 return -EIO;
1258 }
1259
1260 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1261 unsigned long mask)
1262 {
1263 return -EIO;
1264 }
1265
1266 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1267 {
1268 return -EBUSY;
1269 }
1270
1271 static inline int __pci_register_driver(struct pci_driver *drv,
1272 struct module *owner)
1273 {
1274 return 0;
1275 }
1276
1277 static inline int pci_register_driver(struct pci_driver *drv)
1278 {
1279 return 0;
1280 }
1281
1282 static inline void pci_unregister_driver(struct pci_driver *drv)
1283 { }
1284
1285 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1286 {
1287 return 0;
1288 }
1289
1290 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1291 int cap)
1292 {
1293 return 0;
1294 }
1295
1296 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1297 {
1298 return 0;
1299 }
1300
1301 /* Power management related routines */
1302 static inline int pci_save_state(struct pci_dev *dev)
1303 {
1304 return 0;
1305 }
1306
1307 static inline void pci_restore_state(struct pci_dev *dev)
1308 { }
1309
1310 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1311 {
1312 return 0;
1313 }
1314
1315 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1316 {
1317 return 0;
1318 }
1319
1320 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1321 pm_message_t state)
1322 {
1323 return PCI_D0;
1324 }
1325
1326 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1327 int enable)
1328 {
1329 return 0;
1330 }
1331
1332 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1333 {
1334 }
1335
1336 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1337 {
1338 }
1339
1340 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1341 {
1342 return 0;
1343 }
1344
1345 static inline void pci_disable_obff(struct pci_dev *dev)
1346 {
1347 }
1348
1349 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1350 {
1351 return -EIO;
1352 }
1353
1354 static inline void pci_release_regions(struct pci_dev *dev)
1355 { }
1356
1357 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1358
1359 static inline void pci_block_cfg_access(struct pci_dev *dev)
1360 { }
1361
1362 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1363 { return 0; }
1364
1365 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1366 { }
1367
1368 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1369 { return NULL; }
1370
1371 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1372 unsigned int devfn)
1373 { return NULL; }
1374
1375 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1376 unsigned int devfn)
1377 { return NULL; }
1378
1379 static inline int pci_domain_nr(struct pci_bus *bus)
1380 { return 0; }
1381
1382 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1383 { return NULL; }
1384
1385 #define dev_is_pci(d) (false)
1386 #define dev_is_pf(d) (false)
1387 #define dev_num_vf(d) (0)
1388 #endif /* CONFIG_PCI */
1389
1390 /* Include architecture-dependent settings and functions */
1391
1392 #include <asm/pci.h>
1393
1394 #ifndef PCIBIOS_MAX_MEM_32
1395 #define PCIBIOS_MAX_MEM_32 (-1)
1396 #endif
1397
1398 /* these helpers provide future and backwards compatibility
1399 * for accessing popular PCI BAR info */
1400 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1401 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1402 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1403 #define pci_resource_len(dev,bar) \
1404 ((pci_resource_start((dev), (bar)) == 0 && \
1405 pci_resource_end((dev), (bar)) == \
1406 pci_resource_start((dev), (bar))) ? 0 : \
1407 \
1408 (pci_resource_end((dev), (bar)) - \
1409 pci_resource_start((dev), (bar)) + 1))
1410
1411 /* Similar to the helpers above, these manipulate per-pci_dev
1412 * driver-specific data. They are really just a wrapper around
1413 * the generic device structure functions of these calls.
1414 */
1415 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1416 {
1417 return dev_get_drvdata(&pdev->dev);
1418 }
1419
1420 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1421 {
1422 dev_set_drvdata(&pdev->dev, data);
1423 }
1424
1425 /* If you want to know what to call your pci_dev, ask this function.
1426 * Again, it's a wrapper around the generic device.
1427 */
1428 static inline const char *pci_name(const struct pci_dev *pdev)
1429 {
1430 return dev_name(&pdev->dev);
1431 }
1432
1433
1434 /* Some archs don't want to expose struct resource to userland as-is
1435 * in sysfs and /proc
1436 */
1437 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1438 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1439 const struct resource *rsrc, resource_size_t *start,
1440 resource_size_t *end)
1441 {
1442 *start = rsrc->start;
1443 *end = rsrc->end;
1444 }
1445 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1446
1447
1448 /*
1449 * The world is not perfect and supplies us with broken PCI devices.
1450 * For at least a part of these bugs we need a work-around, so both
1451 * generic (drivers/pci/quirks.c) and per-architecture code can define
1452 * fixup hooks to be called for particular buggy devices.
1453 */
1454
1455 struct pci_fixup {
1456 u16 vendor; /* You can use PCI_ANY_ID here of course */
1457 u16 device; /* You can use PCI_ANY_ID here of course */
1458 u32 class; /* You can use PCI_ANY_ID here too */
1459 unsigned int class_shift; /* should be 0, 8, 16 */
1460 void (*hook)(struct pci_dev *dev);
1461 };
1462
1463 enum pci_fixup_pass {
1464 pci_fixup_early, /* Before probing BARs */
1465 pci_fixup_header, /* After reading configuration header */
1466 pci_fixup_final, /* Final phase of device fixups */
1467 pci_fixup_enable, /* pci_enable_device() time */
1468 pci_fixup_resume, /* pci_device_resume() */
1469 pci_fixup_suspend, /* pci_device_suspend */
1470 pci_fixup_resume_early, /* pci_device_resume_early() */
1471 };
1472
1473 /* Anonymous variables would be nice... */
1474 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1475 class_shift, hook) \
1476 static const struct pci_fixup const __pci_fixup_##name __used \
1477 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1478 = { vendor, device, class, class_shift, hook };
1479
1480 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1481 class_shift, hook) \
1482 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1483 vendor##device##hook, vendor, device, class, class_shift, hook)
1484 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1485 class_shift, hook) \
1486 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1487 vendor##device##hook, vendor, device, class, class_shift, hook)
1488 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1489 class_shift, hook) \
1490 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1491 vendor##device##hook, vendor, device, class, class_shift, hook)
1492 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1493 class_shift, hook) \
1494 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1495 vendor##device##hook, vendor, device, class, class_shift, hook)
1496 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1497 class_shift, hook) \
1498 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1499 resume##vendor##device##hook, vendor, device, class, \
1500 class_shift, hook)
1501 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1502 class_shift, hook) \
1503 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1504 resume_early##vendor##device##hook, vendor, device, \
1505 class, class_shift, hook)
1506 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1507 class_shift, hook) \
1508 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1509 suspend##vendor##device##hook, vendor, device, class, \
1510 class_shift, hook)
1511
1512 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1513 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1514 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1515 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1516 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1517 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1518 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1519 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1520 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1521 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1522 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1523 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1524 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1525 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1526 resume##vendor##device##hook, vendor, device, \
1527 PCI_ANY_ID, 0, hook)
1528 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1529 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1530 resume_early##vendor##device##hook, vendor, device, \
1531 PCI_ANY_ID, 0, hook)
1532 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1533 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1534 suspend##vendor##device##hook, vendor, device, \
1535 PCI_ANY_ID, 0, hook)
1536
1537 #ifdef CONFIG_PCI_QUIRKS
1538 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1539 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1540 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1541 #else
1542 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1543 struct pci_dev *dev) {}
1544 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1545 {
1546 return pci_dev_get(dev);
1547 }
1548 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1549 u16 acs_flags)
1550 {
1551 return -ENOTTY;
1552 }
1553 #endif
1554
1555 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1556 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1557 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1558 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1559 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1560 const char *name);
1561 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1562
1563 extern int pci_pci_problems;
1564 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1565 #define PCIPCI_TRITON 2
1566 #define PCIPCI_NATOMA 4
1567 #define PCIPCI_VIAETBF 8
1568 #define PCIPCI_VSFX 16
1569 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1570 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1571
1572 extern unsigned long pci_cardbus_io_size;
1573 extern unsigned long pci_cardbus_mem_size;
1574 extern u8 __devinitdata pci_dfl_cache_line_size;
1575 extern u8 pci_cache_line_size;
1576
1577 extern unsigned long pci_hotplug_io_size;
1578 extern unsigned long pci_hotplug_mem_size;
1579
1580 /* Architecture specific versions may override these (weak) */
1581 int pcibios_add_platform_entries(struct pci_dev *dev);
1582 void pcibios_disable_device(struct pci_dev *dev);
1583 void pcibios_set_master(struct pci_dev *dev);
1584 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1585 enum pcie_reset_state state);
1586
1587 #ifdef CONFIG_PCI_MMCONFIG
1588 extern void __init pci_mmcfg_early_init(void);
1589 extern void __init pci_mmcfg_late_init(void);
1590 #else
1591 static inline void pci_mmcfg_early_init(void) { }
1592 static inline void pci_mmcfg_late_init(void) { }
1593 #endif
1594
1595 int pci_ext_cfg_avail(struct pci_dev *dev);
1596
1597 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1598
1599 #ifdef CONFIG_PCI_IOV
1600 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1601 extern void pci_disable_sriov(struct pci_dev *dev);
1602 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1603 extern int pci_num_vf(struct pci_dev *dev);
1604 #else
1605 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1606 {
1607 return -ENODEV;
1608 }
1609 static inline void pci_disable_sriov(struct pci_dev *dev)
1610 {
1611 }
1612 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1613 {
1614 return IRQ_NONE;
1615 }
1616 static inline int pci_num_vf(struct pci_dev *dev)
1617 {
1618 return 0;
1619 }
1620 #endif
1621
1622 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1623 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1624 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1625 #endif
1626
1627 /**
1628 * pci_pcie_cap - get the saved PCIe capability offset
1629 * @dev: PCI device
1630 *
1631 * PCIe capability offset is calculated at PCI device initialization
1632 * time and saved in the data structure. This function returns saved
1633 * PCIe capability offset. Using this instead of pci_find_capability()
1634 * reduces unnecessary search in the PCI configuration space. If you
1635 * need to calculate PCIe capability offset from raw device for some
1636 * reasons, please use pci_find_capability() instead.
1637 */
1638 static inline int pci_pcie_cap(struct pci_dev *dev)
1639 {
1640 return dev->pcie_cap;
1641 }
1642
1643 /**
1644 * pci_is_pcie - check if the PCI device is PCI Express capable
1645 * @dev: PCI device
1646 *
1647 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1648 */
1649 static inline bool pci_is_pcie(struct pci_dev *dev)
1650 {
1651 return !!pci_pcie_cap(dev);
1652 }
1653
1654 /**
1655 * pci_pcie_type - get the PCIe device/port type
1656 * @dev: PCI device
1657 */
1658 static inline int pci_pcie_type(const struct pci_dev *dev)
1659 {
1660 return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
1661 }
1662
1663 void pci_request_acs(void);
1664 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1665 bool pci_acs_path_enabled(struct pci_dev *start,
1666 struct pci_dev *end, u16 acs_flags);
1667
1668 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1669 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1670
1671 /* Large Resource Data Type Tag Item Names */
1672 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1673 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1674 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1675
1676 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1677 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1678 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1679
1680 /* Small Resource Data Type Tag Item Names */
1681 #define PCI_VPD_STIN_END 0x78 /* End */
1682
1683 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1684
1685 #define PCI_VPD_SRDT_TIN_MASK 0x78
1686 #define PCI_VPD_SRDT_LEN_MASK 0x07
1687
1688 #define PCI_VPD_LRDT_TAG_SIZE 3
1689 #define PCI_VPD_SRDT_TAG_SIZE 1
1690
1691 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1692
1693 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1694 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1695 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1696 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1697
1698 /**
1699 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1700 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1701 *
1702 * Returns the extracted Large Resource Data Type length.
1703 */
1704 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1705 {
1706 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1707 }
1708
1709 /**
1710 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1711 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1712 *
1713 * Returns the extracted Small Resource Data Type length.
1714 */
1715 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1716 {
1717 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1718 }
1719
1720 /**
1721 * pci_vpd_info_field_size - Extracts the information field length
1722 * @lrdt: Pointer to the beginning of an information field header
1723 *
1724 * Returns the extracted information field length.
1725 */
1726 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1727 {
1728 return info_field[2];
1729 }
1730
1731 /**
1732 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1733 * @buf: Pointer to buffered vpd data
1734 * @off: The offset into the buffer at which to begin the search
1735 * @len: The length of the vpd buffer
1736 * @rdt: The Resource Data Type to search for
1737 *
1738 * Returns the index where the Resource Data Type was found or
1739 * -ENOENT otherwise.
1740 */
1741 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1742
1743 /**
1744 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1745 * @buf: Pointer to buffered vpd data
1746 * @off: The offset into the buffer at which to begin the search
1747 * @len: The length of the buffer area, relative to off, in which to search
1748 * @kw: The keyword to search for
1749 *
1750 * Returns the index where the information field keyword was found or
1751 * -ENOENT otherwise.
1752 */
1753 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1754 unsigned int len, const char *kw);
1755
1756 /* PCI <-> OF binding helpers */
1757 #ifdef CONFIG_OF
1758 struct device_node;
1759 extern void pci_set_of_node(struct pci_dev *dev);
1760 extern void pci_release_of_node(struct pci_dev *dev);
1761 extern void pci_set_bus_of_node(struct pci_bus *bus);
1762 extern void pci_release_bus_of_node(struct pci_bus *bus);
1763
1764 /* Arch may override this (weak) */
1765 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1766
1767 static inline struct device_node *
1768 pci_device_to_OF_node(const struct pci_dev *pdev)
1769 {
1770 return pdev ? pdev->dev.of_node : NULL;
1771 }
1772
1773 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1774 {
1775 return bus ? bus->dev.of_node : NULL;
1776 }
1777
1778 #else /* CONFIG_OF */
1779 static inline void pci_set_of_node(struct pci_dev *dev) { }
1780 static inline void pci_release_of_node(struct pci_dev *dev) { }
1781 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1782 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1783 #endif /* CONFIG_OF */
1784
1785 #ifdef CONFIG_EEH
1786 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1787 {
1788 return pdev->dev.archdata.edev;
1789 }
1790 #endif
1791
1792 /**
1793 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1794 * @pdev: the PCI device
1795 *
1796 * if the device is PCIE, return NULL
1797 * if the device isn't connected to a PCIe bridge (that is its parent is a
1798 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1799 * parent
1800 */
1801 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1802
1803 #endif /* __KERNEL__ */
1804 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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