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rcu: optionally leave lockdep enabled after RCU lockdep splat
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221 };
222
223 struct pcie_link_state;
224 struct pci_vpd;
225 struct pci_sriov;
226 struct pci_ats;
227
228 /*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231 struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1; /* Low power state D1 is supported */
271 unsigned int d2_support:1; /* Low power state D2 is supported */
272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
273 unsigned int wakeup_prepared:1;
274 unsigned int d3_delay; /* D3->D0 transition time in ms */
275
276 #ifdef CONFIG_PCIEASPM
277 struct pcie_link_state *link_state; /* ASPM link state. */
278 #endif
279
280 pci_channel_state_t error_state; /* current connectivity state */
281 struct device dev; /* Generic device interface */
282
283 int cfg_size; /* Size of configuration space */
284
285 /*
286 * Instead of touching interrupt line and base address registers
287 * directly, use the values stored here. They might be different!
288 */
289 unsigned int irq;
290 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
291
292 /* These fields are used by common fixups */
293 unsigned int transparent:1; /* Transparent PCI bridge */
294 unsigned int multifunction:1;/* Part of multi-function device */
295 /* keep track of device state */
296 unsigned int is_added:1;
297 unsigned int is_busmaster:1; /* device is busmaster */
298 unsigned int no_msi:1; /* device may not use msi */
299 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
300 unsigned int broken_parity_status:1; /* Device generates false positive parity */
301 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
302 unsigned int msi_enabled:1;
303 unsigned int msix_enabled:1;
304 unsigned int ari_enabled:1; /* ARI forwarding */
305 unsigned int is_managed:1;
306 unsigned int is_pcie:1; /* Obsolete. Will be removed.
307 Use pci_is_pcie() instead */
308 unsigned int needs_freset:1; /* Dev requires fundamental reset */
309 unsigned int state_saved:1;
310 unsigned int is_physfn:1;
311 unsigned int is_virtfn:1;
312 unsigned int reset_fn:1;
313 unsigned int is_hotplug_bridge:1;
314 unsigned int aer_firmware_first:1;
315 pci_dev_flags_t dev_flags;
316 atomic_t enable_cnt; /* pci_enable_device has been called */
317
318 u32 saved_config_space[16]; /* config space saved at suspend time */
319 struct hlist_head saved_cap_space;
320 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
321 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
322 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
323 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
324 #ifdef CONFIG_PCI_MSI
325 struct list_head msi_list;
326 #endif
327 struct pci_vpd *vpd;
328 #ifdef CONFIG_PCI_IOV
329 union {
330 struct pci_sriov *sriov; /* SR-IOV capability related */
331 struct pci_dev *physfn; /* the PF this VF is associated with */
332 };
333 struct pci_ats *ats; /* Address Translation Service */
334 #endif
335 };
336
337 extern struct pci_dev *alloc_pci_dev(void);
338
339 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
340 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
341 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
342
343 static inline int pci_channel_offline(struct pci_dev *pdev)
344 {
345 return (pdev->error_state != pci_channel_io_normal);
346 }
347
348 static inline struct pci_cap_saved_state *pci_find_saved_cap(
349 struct pci_dev *pci_dev, char cap)
350 {
351 struct pci_cap_saved_state *tmp;
352 struct hlist_node *pos;
353
354 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
355 if (tmp->cap_nr == cap)
356 return tmp;
357 }
358 return NULL;
359 }
360
361 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
362 struct pci_cap_saved_state *new_cap)
363 {
364 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
365 }
366
367 /*
368 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
369 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
370 * buses below host bridges or subtractive decode bridges) go in the list.
371 * Use pci_bus_for_each_resource() to iterate through all the resources.
372 */
373
374 /*
375 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
376 * and there's no way to program the bridge with the details of the window.
377 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
378 * decode bit set, because they are explicit and can be programmed with _SRS.
379 */
380 #define PCI_SUBTRACTIVE_DECODE 0x1
381
382 struct pci_bus_resource {
383 struct list_head list;
384 struct resource *res;
385 unsigned int flags;
386 };
387
388 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
389
390 struct pci_bus {
391 struct list_head node; /* node in list of buses */
392 struct pci_bus *parent; /* parent bus this bridge is on */
393 struct list_head children; /* list of child buses */
394 struct list_head devices; /* list of devices on this bus */
395 struct pci_dev *self; /* bridge device as seen by parent */
396 struct list_head slots; /* list of slots on this bus */
397 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
398 struct list_head resources; /* address space routed to this bus */
399
400 struct pci_ops *ops; /* configuration access functions */
401 void *sysdata; /* hook for sys-specific extension */
402 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
403
404 unsigned char number; /* bus number */
405 unsigned char primary; /* number of primary bridge */
406 unsigned char secondary; /* number of secondary bridge */
407 unsigned char subordinate; /* max number of subordinate buses */
408 unsigned char max_bus_speed; /* enum pci_bus_speed */
409 unsigned char cur_bus_speed; /* enum pci_bus_speed */
410
411 char name[48];
412
413 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
414 pci_bus_flags_t bus_flags; /* Inherited by child busses */
415 struct device *bridge;
416 struct device dev;
417 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
418 struct bin_attribute *legacy_mem; /* legacy mem */
419 unsigned int is_added:1;
420 };
421
422 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
423 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
424
425 /*
426 * Returns true if the pci bus is root (behind host-pci bridge),
427 * false otherwise
428 */
429 static inline bool pci_is_root_bus(struct pci_bus *pbus)
430 {
431 return !(pbus->parent);
432 }
433
434 #ifdef CONFIG_PCI_MSI
435 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
436 {
437 return pci_dev->msi_enabled || pci_dev->msix_enabled;
438 }
439 #else
440 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
441 #endif
442
443 /*
444 * Error values that may be returned by PCI functions.
445 */
446 #define PCIBIOS_SUCCESSFUL 0x00
447 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
448 #define PCIBIOS_BAD_VENDOR_ID 0x83
449 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
450 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
451 #define PCIBIOS_SET_FAILED 0x88
452 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
453
454 /* Low-level architecture-dependent routines */
455
456 struct pci_ops {
457 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
458 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
459 };
460
461 /*
462 * ACPI needs to be able to access PCI config space before we've done a
463 * PCI bus scan and created pci_bus structures.
464 */
465 extern int raw_pci_read(unsigned int domain, unsigned int bus,
466 unsigned int devfn, int reg, int len, u32 *val);
467 extern int raw_pci_write(unsigned int domain, unsigned int bus,
468 unsigned int devfn, int reg, int len, u32 val);
469
470 struct pci_bus_region {
471 resource_size_t start;
472 resource_size_t end;
473 };
474
475 struct pci_dynids {
476 spinlock_t lock; /* protects list, index */
477 struct list_head list; /* for IDs added at runtime */
478 };
479
480 /* ---------------------------------------------------------------- */
481 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
482 * a set of callbacks in struct pci_error_handlers, then that device driver
483 * will be notified of PCI bus errors, and will be driven to recovery
484 * when an error occurs.
485 */
486
487 typedef unsigned int __bitwise pci_ers_result_t;
488
489 enum pci_ers_result {
490 /* no result/none/not supported in device driver */
491 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
492
493 /* Device driver can recover without slot reset */
494 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
495
496 /* Device driver wants slot to be reset. */
497 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
498
499 /* Device has completely failed, is unrecoverable */
500 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
501
502 /* Device driver is fully recovered and operational */
503 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
504 };
505
506 /* PCI bus error event callbacks */
507 struct pci_error_handlers {
508 /* PCI bus error detected on this device */
509 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
510 enum pci_channel_state error);
511
512 /* MMIO has been re-enabled, but not DMA */
513 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
514
515 /* PCI Express link has been reset */
516 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
517
518 /* PCI slot has been reset */
519 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
520
521 /* Device driver may resume normal operations */
522 void (*resume)(struct pci_dev *dev);
523 };
524
525 /* ---------------------------------------------------------------- */
526
527 struct module;
528 struct pci_driver {
529 struct list_head node;
530 char *name;
531 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
532 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
533 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
534 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
535 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
536 int (*resume_early) (struct pci_dev *dev);
537 int (*resume) (struct pci_dev *dev); /* Device woken up */
538 void (*shutdown) (struct pci_dev *dev);
539 struct pci_error_handlers *err_handler;
540 struct device_driver driver;
541 struct pci_dynids dynids;
542 };
543
544 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
545
546 /**
547 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
548 * @_table: device table name
549 *
550 * This macro is used to create a struct pci_device_id array (a device table)
551 * in a generic manner.
552 */
553 #define DEFINE_PCI_DEVICE_TABLE(_table) \
554 const struct pci_device_id _table[] __devinitconst
555
556 /**
557 * PCI_DEVICE - macro used to describe a specific pci device
558 * @vend: the 16 bit PCI Vendor ID
559 * @dev: the 16 bit PCI Device ID
560 *
561 * This macro is used to create a struct pci_device_id that matches a
562 * specific device. The subvendor and subdevice fields will be set to
563 * PCI_ANY_ID.
564 */
565 #define PCI_DEVICE(vend,dev) \
566 .vendor = (vend), .device = (dev), \
567 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
568
569 /**
570 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
571 * @dev_class: the class, subclass, prog-if triple for this device
572 * @dev_class_mask: the class mask for this device
573 *
574 * This macro is used to create a struct pci_device_id that matches a
575 * specific PCI class. The vendor, device, subvendor, and subdevice
576 * fields will be set to PCI_ANY_ID.
577 */
578 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
579 .class = (dev_class), .class_mask = (dev_class_mask), \
580 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
581 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
582
583 /**
584 * PCI_VDEVICE - macro used to describe a specific pci device in short form
585 * @vendor: the vendor name
586 * @device: the 16 bit PCI Device ID
587 *
588 * This macro is used to create a struct pci_device_id that matches a
589 * specific PCI device. The subvendor, and subdevice fields will be set
590 * to PCI_ANY_ID. The macro allows the next field to follow as the device
591 * private data.
592 */
593
594 #define PCI_VDEVICE(vendor, device) \
595 PCI_VENDOR_ID_##vendor, (device), \
596 PCI_ANY_ID, PCI_ANY_ID, 0, 0
597
598 /* these external functions are only available when PCI support is enabled */
599 #ifdef CONFIG_PCI
600
601 extern struct bus_type pci_bus_type;
602
603 /* Do NOT directly access these two variables, unless you are arch specific pci
604 * code, or pci core code. */
605 extern struct list_head pci_root_buses; /* list of all known PCI buses */
606 /* Some device drivers need know if pci is initiated */
607 extern int no_pci_devices(void);
608
609 void pcibios_fixup_bus(struct pci_bus *);
610 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
611 char *pcibios_setup(char *str);
612
613 /* Used only when drivers/pci/setup.c is used */
614 resource_size_t pcibios_align_resource(void *, const struct resource *,
615 resource_size_t,
616 resource_size_t);
617 void pcibios_update_irq(struct pci_dev *, int irq);
618
619 /* Weak but can be overriden by arch */
620 void pci_fixup_cardbus(struct pci_bus *);
621
622 /* Generic PCI functions used internally */
623
624 extern struct pci_bus *pci_find_bus(int domain, int busnr);
625 void pci_bus_add_devices(const struct pci_bus *bus);
626 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
627 struct pci_ops *ops, void *sysdata);
628 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
629 void *sysdata)
630 {
631 struct pci_bus *root_bus;
632 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
633 if (root_bus)
634 pci_bus_add_devices(root_bus);
635 return root_bus;
636 }
637 struct pci_bus *pci_create_bus(struct device *parent, int bus,
638 struct pci_ops *ops, void *sysdata);
639 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
640 int busnr);
641 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
642 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
643 const char *name,
644 struct hotplug_slot *hotplug);
645 void pci_destroy_slot(struct pci_slot *slot);
646 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
647 int pci_scan_slot(struct pci_bus *bus, int devfn);
648 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
649 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
650 unsigned int pci_scan_child_bus(struct pci_bus *bus);
651 int __must_check pci_bus_add_device(struct pci_dev *dev);
652 void pci_read_bridge_bases(struct pci_bus *child);
653 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
654 struct resource *res);
655 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
656 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
657 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
658 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
659 extern void pci_dev_put(struct pci_dev *dev);
660 extern void pci_remove_bus(struct pci_bus *b);
661 extern void pci_remove_bus_device(struct pci_dev *dev);
662 extern void pci_stop_bus_device(struct pci_dev *dev);
663 void pci_setup_cardbus(struct pci_bus *bus);
664 extern void pci_sort_breadthfirst(void);
665 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
666 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
667 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
668
669 /* Generic PCI functions exported to card drivers */
670
671 enum pci_lost_interrupt_reason {
672 PCI_LOST_IRQ_NO_INFORMATION = 0,
673 PCI_LOST_IRQ_DISABLE_MSI,
674 PCI_LOST_IRQ_DISABLE_MSIX,
675 PCI_LOST_IRQ_DISABLE_ACPI,
676 };
677 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
678 int pci_find_capability(struct pci_dev *dev, int cap);
679 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
680 int pci_find_ext_capability(struct pci_dev *dev, int cap);
681 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
682 int cap);
683 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
684 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
685 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
686
687 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
688 struct pci_dev *from);
689 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
690 unsigned int ss_vendor, unsigned int ss_device,
691 struct pci_dev *from);
692 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
693 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
694 unsigned int devfn);
695 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
696 unsigned int devfn)
697 {
698 return pci_get_domain_bus_and_slot(0, bus, devfn);
699 }
700 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
701 int pci_dev_present(const struct pci_device_id *ids);
702
703 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
704 int where, u8 *val);
705 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
706 int where, u16 *val);
707 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
708 int where, u32 *val);
709 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
710 int where, u8 val);
711 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
712 int where, u16 val);
713 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
714 int where, u32 val);
715 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
716
717 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
718 {
719 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
720 }
721 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
722 {
723 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
724 }
725 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
726 u32 *val)
727 {
728 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
729 }
730 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
731 {
732 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
733 }
734 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
735 {
736 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
737 }
738 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
739 u32 val)
740 {
741 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
742 }
743
744 int __must_check pci_enable_device(struct pci_dev *dev);
745 int __must_check pci_enable_device_io(struct pci_dev *dev);
746 int __must_check pci_enable_device_mem(struct pci_dev *dev);
747 int __must_check pci_reenable_device(struct pci_dev *);
748 int __must_check pcim_enable_device(struct pci_dev *pdev);
749 void pcim_pin_device(struct pci_dev *pdev);
750
751 static inline int pci_is_enabled(struct pci_dev *pdev)
752 {
753 return (atomic_read(&pdev->enable_cnt) > 0);
754 }
755
756 static inline int pci_is_managed(struct pci_dev *pdev)
757 {
758 return pdev->is_managed;
759 }
760
761 void pci_disable_device(struct pci_dev *dev);
762 void pci_set_master(struct pci_dev *dev);
763 void pci_clear_master(struct pci_dev *dev);
764 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
765 int pci_set_cacheline_size(struct pci_dev *dev);
766 #define HAVE_PCI_SET_MWI
767 int __must_check pci_set_mwi(struct pci_dev *dev);
768 int pci_try_set_mwi(struct pci_dev *dev);
769 void pci_clear_mwi(struct pci_dev *dev);
770 void pci_intx(struct pci_dev *dev, int enable);
771 void pci_msi_off(struct pci_dev *dev);
772 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
773 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
774 int pcix_get_max_mmrbc(struct pci_dev *dev);
775 int pcix_get_mmrbc(struct pci_dev *dev);
776 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
777 int pcie_get_readrq(struct pci_dev *dev);
778 int pcie_set_readrq(struct pci_dev *dev, int rq);
779 int __pci_reset_function(struct pci_dev *dev);
780 int pci_reset_function(struct pci_dev *dev);
781 void pci_update_resource(struct pci_dev *dev, int resno);
782 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
783 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
784
785 /* ROM control related routines */
786 int pci_enable_rom(struct pci_dev *pdev);
787 void pci_disable_rom(struct pci_dev *pdev);
788 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
789 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
790 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
791
792 /* Power management related routines */
793 int pci_save_state(struct pci_dev *dev);
794 int pci_restore_state(struct pci_dev *dev);
795 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
796 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
797 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
798 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
799 void pci_pme_active(struct pci_dev *dev, bool enable);
800 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
801 bool runtime, bool enable);
802 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
803 pci_power_t pci_target_state(struct pci_dev *dev);
804 int pci_prepare_to_sleep(struct pci_dev *dev);
805 int pci_back_from_sleep(struct pci_dev *dev);
806 bool pci_dev_run_wake(struct pci_dev *dev);
807
808 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
809 bool enable)
810 {
811 return __pci_enable_wake(dev, state, false, enable);
812 }
813
814 /* For use by arch with custom probe code */
815 void set_pcie_port_type(struct pci_dev *pdev);
816 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
817
818 /* Functions for PCI Hotplug drivers to use */
819 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
820 #ifdef CONFIG_HOTPLUG
821 unsigned int pci_rescan_bus(struct pci_bus *bus);
822 #endif
823
824 /* Vital product data routines */
825 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
826 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
827 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
828
829 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
830 void pci_bus_assign_resources(const struct pci_bus *bus);
831 void pci_bus_size_bridges(struct pci_bus *bus);
832 int pci_claim_resource(struct pci_dev *, int);
833 void pci_assign_unassigned_resources(void);
834 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
835 void pdev_enable_device(struct pci_dev *);
836 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
837 int pci_enable_resources(struct pci_dev *, int mask);
838 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
839 int (*)(struct pci_dev *, u8, u8));
840 #define HAVE_PCI_REQ_REGIONS 2
841 int __must_check pci_request_regions(struct pci_dev *, const char *);
842 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
843 void pci_release_regions(struct pci_dev *);
844 int __must_check pci_request_region(struct pci_dev *, int, const char *);
845 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
846 void pci_release_region(struct pci_dev *, int);
847 int pci_request_selected_regions(struct pci_dev *, int, const char *);
848 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
849 void pci_release_selected_regions(struct pci_dev *, int);
850
851 /* drivers/pci/bus.c */
852 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
853 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
854 void pci_bus_remove_resources(struct pci_bus *bus);
855
856 #define pci_bus_for_each_resource(bus, res, i) \
857 for (i = 0; \
858 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
859 i++)
860
861 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
862 struct resource *res, resource_size_t size,
863 resource_size_t align, resource_size_t min,
864 unsigned int type_mask,
865 resource_size_t (*alignf)(void *,
866 const struct resource *,
867 resource_size_t,
868 resource_size_t),
869 void *alignf_data);
870 void pci_enable_bridges(struct pci_bus *bus);
871
872 /* Proper probing supporting hot-pluggable devices */
873 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
874 const char *mod_name);
875
876 /*
877 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
878 */
879 #define pci_register_driver(driver) \
880 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
881
882 void pci_unregister_driver(struct pci_driver *dev);
883 void pci_remove_behind_bridge(struct pci_dev *dev);
884 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
885 int pci_add_dynid(struct pci_driver *drv,
886 unsigned int vendor, unsigned int device,
887 unsigned int subvendor, unsigned int subdevice,
888 unsigned int class, unsigned int class_mask,
889 unsigned long driver_data);
890 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
891 struct pci_dev *dev);
892 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
893 int pass);
894
895 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
896 void *userdata);
897 int pci_cfg_space_size_ext(struct pci_dev *dev);
898 int pci_cfg_space_size(struct pci_dev *dev);
899 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
900
901 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
902 unsigned int command_bits, bool change_bridge);
903 /* kmem_cache style wrapper around pci_alloc_consistent() */
904
905 #include <linux/pci-dma.h>
906 #include <linux/dmapool.h>
907
908 #define pci_pool dma_pool
909 #define pci_pool_create(name, pdev, size, align, allocation) \
910 dma_pool_create(name, &pdev->dev, size, align, allocation)
911 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
912 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
913 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
914
915 enum pci_dma_burst_strategy {
916 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
917 strategy_parameter is N/A */
918 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
919 byte boundaries */
920 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
921 strategy_parameter byte boundaries */
922 };
923
924 struct msix_entry {
925 u32 vector; /* kernel uses to write allocated vector */
926 u16 entry; /* driver uses to specify entry, OS writes */
927 };
928
929
930 #ifndef CONFIG_PCI_MSI
931 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
932 {
933 return -1;
934 }
935
936 static inline void pci_msi_shutdown(struct pci_dev *dev)
937 { }
938 static inline void pci_disable_msi(struct pci_dev *dev)
939 { }
940
941 static inline int pci_msix_table_size(struct pci_dev *dev)
942 {
943 return 0;
944 }
945 static inline int pci_enable_msix(struct pci_dev *dev,
946 struct msix_entry *entries, int nvec)
947 {
948 return -1;
949 }
950
951 static inline void pci_msix_shutdown(struct pci_dev *dev)
952 { }
953 static inline void pci_disable_msix(struct pci_dev *dev)
954 { }
955
956 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
957 { }
958
959 static inline void pci_restore_msi_state(struct pci_dev *dev)
960 { }
961 static inline int pci_msi_enabled(void)
962 {
963 return 0;
964 }
965 #else
966 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
967 extern void pci_msi_shutdown(struct pci_dev *dev);
968 extern void pci_disable_msi(struct pci_dev *dev);
969 extern int pci_msix_table_size(struct pci_dev *dev);
970 extern int pci_enable_msix(struct pci_dev *dev,
971 struct msix_entry *entries, int nvec);
972 extern void pci_msix_shutdown(struct pci_dev *dev);
973 extern void pci_disable_msix(struct pci_dev *dev);
974 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
975 extern void pci_restore_msi_state(struct pci_dev *dev);
976 extern int pci_msi_enabled(void);
977 #endif
978
979 #ifndef CONFIG_PCIEASPM
980 static inline int pcie_aspm_enabled(void)
981 {
982 return 0;
983 }
984 #else
985 extern int pcie_aspm_enabled(void);
986 #endif
987
988 #ifndef CONFIG_PCIE_ECRC
989 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
990 {
991 return;
992 }
993 static inline void pcie_ecrc_get_policy(char *str) {};
994 #else
995 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
996 extern void pcie_ecrc_get_policy(char *str);
997 #endif
998
999 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1000
1001 #ifdef CONFIG_HT_IRQ
1002 /* The functions a driver should call */
1003 int ht_create_irq(struct pci_dev *dev, int idx);
1004 void ht_destroy_irq(unsigned int irq);
1005 #endif /* CONFIG_HT_IRQ */
1006
1007 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1008 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1009
1010 /*
1011 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1012 * a PCI domain is defined to be a set of PCI busses which share
1013 * configuration space.
1014 */
1015 #ifdef CONFIG_PCI_DOMAINS
1016 extern int pci_domains_supported;
1017 #else
1018 enum { pci_domains_supported = 0 };
1019 static inline int pci_domain_nr(struct pci_bus *bus)
1020 {
1021 return 0;
1022 }
1023
1024 static inline int pci_proc_domain(struct pci_bus *bus)
1025 {
1026 return 0;
1027 }
1028 #endif /* CONFIG_PCI_DOMAINS */
1029
1030 /* some architectures require additional setup to direct VGA traffic */
1031 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1032 unsigned int command_bits, bool change_bridge);
1033 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1034
1035 #else /* CONFIG_PCI is not enabled */
1036
1037 /*
1038 * If the system does not have PCI, clearly these return errors. Define
1039 * these as simple inline functions to avoid hair in drivers.
1040 */
1041
1042 #define _PCI_NOP(o, s, t) \
1043 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1044 int where, t val) \
1045 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1046
1047 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1048 _PCI_NOP(o, word, u16 x) \
1049 _PCI_NOP(o, dword, u32 x)
1050 _PCI_NOP_ALL(read, *)
1051 _PCI_NOP_ALL(write,)
1052
1053 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1054 unsigned int device,
1055 struct pci_dev *from)
1056 {
1057 return NULL;
1058 }
1059
1060 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1061 unsigned int device,
1062 unsigned int ss_vendor,
1063 unsigned int ss_device,
1064 struct pci_dev *from)
1065 {
1066 return NULL;
1067 }
1068
1069 static inline struct pci_dev *pci_get_class(unsigned int class,
1070 struct pci_dev *from)
1071 {
1072 return NULL;
1073 }
1074
1075 #define pci_dev_present(ids) (0)
1076 #define no_pci_devices() (1)
1077 #define pci_dev_put(dev) do { } while (0)
1078
1079 static inline void pci_set_master(struct pci_dev *dev)
1080 { }
1081
1082 static inline int pci_enable_device(struct pci_dev *dev)
1083 {
1084 return -EIO;
1085 }
1086
1087 static inline void pci_disable_device(struct pci_dev *dev)
1088 { }
1089
1090 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1091 {
1092 return -EIO;
1093 }
1094
1095 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1096 {
1097 return -EIO;
1098 }
1099
1100 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1101 unsigned int size)
1102 {
1103 return -EIO;
1104 }
1105
1106 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1107 unsigned long mask)
1108 {
1109 return -EIO;
1110 }
1111
1112 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1113 {
1114 return -EBUSY;
1115 }
1116
1117 static inline int __pci_register_driver(struct pci_driver *drv,
1118 struct module *owner)
1119 {
1120 return 0;
1121 }
1122
1123 static inline int pci_register_driver(struct pci_driver *drv)
1124 {
1125 return 0;
1126 }
1127
1128 static inline void pci_unregister_driver(struct pci_driver *drv)
1129 { }
1130
1131 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1132 {
1133 return 0;
1134 }
1135
1136 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1137 int cap)
1138 {
1139 return 0;
1140 }
1141
1142 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1143 {
1144 return 0;
1145 }
1146
1147 /* Power management related routines */
1148 static inline int pci_save_state(struct pci_dev *dev)
1149 {
1150 return 0;
1151 }
1152
1153 static inline int pci_restore_state(struct pci_dev *dev)
1154 {
1155 return 0;
1156 }
1157
1158 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1159 {
1160 return 0;
1161 }
1162
1163 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1164 pm_message_t state)
1165 {
1166 return PCI_D0;
1167 }
1168
1169 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1170 int enable)
1171 {
1172 return 0;
1173 }
1174
1175 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1176 {
1177 return -EIO;
1178 }
1179
1180 static inline void pci_release_regions(struct pci_dev *dev)
1181 { }
1182
1183 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1184
1185 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1186 { }
1187
1188 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1189 { }
1190
1191 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1192 { return NULL; }
1193
1194 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1195 unsigned int devfn)
1196 { return NULL; }
1197
1198 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1199 unsigned int devfn)
1200 { return NULL; }
1201
1202 #define dev_is_pci(d) (false)
1203 #define dev_is_pf(d) (false)
1204 #define dev_num_vf(d) (0)
1205 #endif /* CONFIG_PCI */
1206
1207 /* Include architecture-dependent settings and functions */
1208
1209 #include <asm/pci.h>
1210
1211 #ifndef PCIBIOS_MAX_MEM_32
1212 #define PCIBIOS_MAX_MEM_32 (-1)
1213 #endif
1214
1215 /* these helpers provide future and backwards compatibility
1216 * for accessing popular PCI BAR info */
1217 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1218 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1219 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1220 #define pci_resource_len(dev,bar) \
1221 ((pci_resource_start((dev), (bar)) == 0 && \
1222 pci_resource_end((dev), (bar)) == \
1223 pci_resource_start((dev), (bar))) ? 0 : \
1224 \
1225 (pci_resource_end((dev), (bar)) - \
1226 pci_resource_start((dev), (bar)) + 1))
1227
1228 /* Similar to the helpers above, these manipulate per-pci_dev
1229 * driver-specific data. They are really just a wrapper around
1230 * the generic device structure functions of these calls.
1231 */
1232 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1233 {
1234 return dev_get_drvdata(&pdev->dev);
1235 }
1236
1237 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1238 {
1239 dev_set_drvdata(&pdev->dev, data);
1240 }
1241
1242 /* If you want to know what to call your pci_dev, ask this function.
1243 * Again, it's a wrapper around the generic device.
1244 */
1245 static inline const char *pci_name(const struct pci_dev *pdev)
1246 {
1247 return dev_name(&pdev->dev);
1248 }
1249
1250
1251 /* Some archs don't want to expose struct resource to userland as-is
1252 * in sysfs and /proc
1253 */
1254 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1255 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1256 const struct resource *rsrc, resource_size_t *start,
1257 resource_size_t *end)
1258 {
1259 *start = rsrc->start;
1260 *end = rsrc->end;
1261 }
1262 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1263
1264
1265 /*
1266 * The world is not perfect and supplies us with broken PCI devices.
1267 * For at least a part of these bugs we need a work-around, so both
1268 * generic (drivers/pci/quirks.c) and per-architecture code can define
1269 * fixup hooks to be called for particular buggy devices.
1270 */
1271
1272 struct pci_fixup {
1273 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1274 void (*hook)(struct pci_dev *dev);
1275 };
1276
1277 enum pci_fixup_pass {
1278 pci_fixup_early, /* Before probing BARs */
1279 pci_fixup_header, /* After reading configuration header */
1280 pci_fixup_final, /* Final phase of device fixups */
1281 pci_fixup_enable, /* pci_enable_device() time */
1282 pci_fixup_resume, /* pci_device_resume() */
1283 pci_fixup_suspend, /* pci_device_suspend */
1284 pci_fixup_resume_early, /* pci_device_resume_early() */
1285 };
1286
1287 /* Anonymous variables would be nice... */
1288 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1289 static const struct pci_fixup __pci_fixup_##name __used \
1290 __attribute__((__section__(#section))) = { vendor, device, hook };
1291 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1292 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1293 vendor##device##hook, vendor, device, hook)
1294 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1295 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1296 vendor##device##hook, vendor, device, hook)
1297 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1298 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1299 vendor##device##hook, vendor, device, hook)
1300 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1301 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1302 vendor##device##hook, vendor, device, hook)
1303 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1304 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1305 resume##vendor##device##hook, vendor, device, hook)
1306 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1307 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1308 resume_early##vendor##device##hook, vendor, device, hook)
1309 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1310 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1311 suspend##vendor##device##hook, vendor, device, hook)
1312
1313 #ifdef CONFIG_PCI_QUIRKS
1314 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1315 #else
1316 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1317 struct pci_dev *dev) {}
1318 #endif
1319
1320 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1321 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1322 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1323 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1324 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1325 const char *name);
1326 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1327
1328 extern int pci_pci_problems;
1329 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1330 #define PCIPCI_TRITON 2
1331 #define PCIPCI_NATOMA 4
1332 #define PCIPCI_VIAETBF 8
1333 #define PCIPCI_VSFX 16
1334 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1335 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1336
1337 extern unsigned long pci_cardbus_io_size;
1338 extern unsigned long pci_cardbus_mem_size;
1339 extern u8 __devinitdata pci_dfl_cache_line_size;
1340 extern u8 pci_cache_line_size;
1341
1342 extern unsigned long pci_hotplug_io_size;
1343 extern unsigned long pci_hotplug_mem_size;
1344
1345 int pcibios_add_platform_entries(struct pci_dev *dev);
1346 void pcibios_disable_device(struct pci_dev *dev);
1347 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1348 enum pcie_reset_state state);
1349
1350 #ifdef CONFIG_PCI_MMCONFIG
1351 extern void __init pci_mmcfg_early_init(void);
1352 extern void __init pci_mmcfg_late_init(void);
1353 #else
1354 static inline void pci_mmcfg_early_init(void) { }
1355 static inline void pci_mmcfg_late_init(void) { }
1356 #endif
1357
1358 int pci_ext_cfg_avail(struct pci_dev *dev);
1359
1360 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1361
1362 #ifdef CONFIG_PCI_IOV
1363 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1364 extern void pci_disable_sriov(struct pci_dev *dev);
1365 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1366 extern int pci_num_vf(struct pci_dev *dev);
1367 #else
1368 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1369 {
1370 return -ENODEV;
1371 }
1372 static inline void pci_disable_sriov(struct pci_dev *dev)
1373 {
1374 }
1375 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1376 {
1377 return IRQ_NONE;
1378 }
1379 static inline int pci_num_vf(struct pci_dev *dev)
1380 {
1381 return 0;
1382 }
1383 #endif
1384
1385 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1386 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1387 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1388 #endif
1389
1390 /**
1391 * pci_pcie_cap - get the saved PCIe capability offset
1392 * @dev: PCI device
1393 *
1394 * PCIe capability offset is calculated at PCI device initialization
1395 * time and saved in the data structure. This function returns saved
1396 * PCIe capability offset. Using this instead of pci_find_capability()
1397 * reduces unnecessary search in the PCI configuration space. If you
1398 * need to calculate PCIe capability offset from raw device for some
1399 * reasons, please use pci_find_capability() instead.
1400 */
1401 static inline int pci_pcie_cap(struct pci_dev *dev)
1402 {
1403 return dev->pcie_cap;
1404 }
1405
1406 /**
1407 * pci_is_pcie - check if the PCI device is PCI Express capable
1408 * @dev: PCI device
1409 *
1410 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1411 */
1412 static inline bool pci_is_pcie(struct pci_dev *dev)
1413 {
1414 return !!pci_pcie_cap(dev);
1415 }
1416
1417 void pci_request_acs(void);
1418
1419
1420 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1421 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1422
1423 /* Large Resource Data Type Tag Item Names */
1424 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1425 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1426 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1427
1428 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1429 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1430 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1431
1432 /* Small Resource Data Type Tag Item Names */
1433 #define PCI_VPD_STIN_END 0x78 /* End */
1434
1435 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1436
1437 #define PCI_VPD_SRDT_TIN_MASK 0x78
1438 #define PCI_VPD_SRDT_LEN_MASK 0x07
1439
1440 #define PCI_VPD_LRDT_TAG_SIZE 3
1441 #define PCI_VPD_SRDT_TAG_SIZE 1
1442
1443 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1444
1445 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1446 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1447 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1448
1449 /**
1450 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1451 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1452 *
1453 * Returns the extracted Large Resource Data Type length.
1454 */
1455 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1456 {
1457 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1458 }
1459
1460 /**
1461 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1462 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1463 *
1464 * Returns the extracted Small Resource Data Type length.
1465 */
1466 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1467 {
1468 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1469 }
1470
1471 /**
1472 * pci_vpd_info_field_size - Extracts the information field length
1473 * @lrdt: Pointer to the beginning of an information field header
1474 *
1475 * Returns the extracted information field length.
1476 */
1477 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1478 {
1479 return info_field[2];
1480 }
1481
1482 /**
1483 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1484 * @buf: Pointer to buffered vpd data
1485 * @off: The offset into the buffer at which to begin the search
1486 * @len: The length of the vpd buffer
1487 * @rdt: The Resource Data Type to search for
1488 *
1489 * Returns the index where the Resource Data Type was found or
1490 * -ENOENT otherwise.
1491 */
1492 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1493
1494 /**
1495 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1496 * @buf: Pointer to buffered vpd data
1497 * @off: The offset into the buffer at which to begin the search
1498 * @len: The length of the buffer area, relative to off, in which to search
1499 * @kw: The keyword to search for
1500 *
1501 * Returns the index where the information field keyword was found or
1502 * -ENOENT otherwise.
1503 */
1504 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1505 unsigned int len, const char *kw);
1506
1507 #endif /* __KERNEL__ */
1508 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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