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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad...
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221 };
222
223 struct pcie_link_state;
224 struct pci_vpd;
225 struct pci_sriov;
226 struct pci_ats;
227
228 /*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231 struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1; /* Low power state D1 is supported */
271 unsigned int d2_support:1; /* Low power state D2 is supported */
272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
273 unsigned int wakeup_prepared:1;
274 unsigned int d3_delay; /* D3->D0 transition time in ms */
275
276 #ifdef CONFIG_PCIEASPM
277 struct pcie_link_state *link_state; /* ASPM link state. */
278 #endif
279
280 pci_channel_state_t error_state; /* current connectivity state */
281 struct device dev; /* Generic device interface */
282
283 int cfg_size; /* Size of configuration space */
284
285 /*
286 * Instead of touching interrupt line and base address registers
287 * directly, use the values stored here. They might be different!
288 */
289 unsigned int irq;
290 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
291 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
292
293 /* These fields are used by common fixups */
294 unsigned int transparent:1; /* Transparent PCI bridge */
295 unsigned int multifunction:1;/* Part of multi-function device */
296 /* keep track of device state */
297 unsigned int is_added:1;
298 unsigned int is_busmaster:1; /* device is busmaster */
299 unsigned int no_msi:1; /* device may not use msi */
300 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
301 unsigned int broken_parity_status:1; /* Device generates false positive parity */
302 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
303 unsigned int msi_enabled:1;
304 unsigned int msix_enabled:1;
305 unsigned int ari_enabled:1; /* ARI forwarding */
306 unsigned int is_managed:1;
307 unsigned int is_pcie:1; /* Obsolete. Will be removed.
308 Use pci_is_pcie() instead */
309 unsigned int needs_freset:1; /* Dev requires fundamental reset */
310 unsigned int state_saved:1;
311 unsigned int is_physfn:1;
312 unsigned int is_virtfn:1;
313 unsigned int reset_fn:1;
314 unsigned int is_hotplug_bridge:1;
315 unsigned int __aer_firmware_first_valid:1;
316 unsigned int __aer_firmware_first:1;
317 pci_dev_flags_t dev_flags;
318 atomic_t enable_cnt; /* pci_enable_device has been called */
319
320 u32 saved_config_space[16]; /* config space saved at suspend time */
321 struct hlist_head saved_cap_space;
322 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
323 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
324 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
325 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
326 #ifdef CONFIG_PCI_MSI
327 struct list_head msi_list;
328 #endif
329 struct pci_vpd *vpd;
330 #ifdef CONFIG_PCI_IOV
331 union {
332 struct pci_sriov *sriov; /* SR-IOV capability related */
333 struct pci_dev *physfn; /* the PF this VF is associated with */
334 };
335 struct pci_ats *ats; /* Address Translation Service */
336 #endif
337 };
338
339 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
340 {
341 #ifdef CONFIG_PCI_IOV
342 if (dev->is_virtfn)
343 dev = dev->physfn;
344 #endif
345
346 return dev;
347 }
348
349 extern struct pci_dev *alloc_pci_dev(void);
350
351 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
352 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
353 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
354
355 static inline int pci_channel_offline(struct pci_dev *pdev)
356 {
357 return (pdev->error_state != pci_channel_io_normal);
358 }
359
360 static inline struct pci_cap_saved_state *pci_find_saved_cap(
361 struct pci_dev *pci_dev, char cap)
362 {
363 struct pci_cap_saved_state *tmp;
364 struct hlist_node *pos;
365
366 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
367 if (tmp->cap_nr == cap)
368 return tmp;
369 }
370 return NULL;
371 }
372
373 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
374 struct pci_cap_saved_state *new_cap)
375 {
376 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
377 }
378
379 /*
380 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
381 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
382 * buses below host bridges or subtractive decode bridges) go in the list.
383 * Use pci_bus_for_each_resource() to iterate through all the resources.
384 */
385
386 /*
387 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
388 * and there's no way to program the bridge with the details of the window.
389 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
390 * decode bit set, because they are explicit and can be programmed with _SRS.
391 */
392 #define PCI_SUBTRACTIVE_DECODE 0x1
393
394 struct pci_bus_resource {
395 struct list_head list;
396 struct resource *res;
397 unsigned int flags;
398 };
399
400 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
401
402 struct pci_bus {
403 struct list_head node; /* node in list of buses */
404 struct pci_bus *parent; /* parent bus this bridge is on */
405 struct list_head children; /* list of child buses */
406 struct list_head devices; /* list of devices on this bus */
407 struct pci_dev *self; /* bridge device as seen by parent */
408 struct list_head slots; /* list of slots on this bus */
409 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
410 struct list_head resources; /* address space routed to this bus */
411
412 struct pci_ops *ops; /* configuration access functions */
413 void *sysdata; /* hook for sys-specific extension */
414 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
415
416 unsigned char number; /* bus number */
417 unsigned char primary; /* number of primary bridge */
418 unsigned char secondary; /* number of secondary bridge */
419 unsigned char subordinate; /* max number of subordinate buses */
420 unsigned char max_bus_speed; /* enum pci_bus_speed */
421 unsigned char cur_bus_speed; /* enum pci_bus_speed */
422
423 char name[48];
424
425 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
426 pci_bus_flags_t bus_flags; /* Inherited by child busses */
427 struct device *bridge;
428 struct device dev;
429 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
430 struct bin_attribute *legacy_mem; /* legacy mem */
431 unsigned int is_added:1;
432 };
433
434 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
435 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
436
437 /*
438 * Returns true if the pci bus is root (behind host-pci bridge),
439 * false otherwise
440 */
441 static inline bool pci_is_root_bus(struct pci_bus *pbus)
442 {
443 return !(pbus->parent);
444 }
445
446 #ifdef CONFIG_PCI_MSI
447 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
448 {
449 return pci_dev->msi_enabled || pci_dev->msix_enabled;
450 }
451 #else
452 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
453 #endif
454
455 /*
456 * Error values that may be returned by PCI functions.
457 */
458 #define PCIBIOS_SUCCESSFUL 0x00
459 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
460 #define PCIBIOS_BAD_VENDOR_ID 0x83
461 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
462 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
463 #define PCIBIOS_SET_FAILED 0x88
464 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
465
466 /* Low-level architecture-dependent routines */
467
468 struct pci_ops {
469 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
470 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
471 };
472
473 /*
474 * ACPI needs to be able to access PCI config space before we've done a
475 * PCI bus scan and created pci_bus structures.
476 */
477 extern int raw_pci_read(unsigned int domain, unsigned int bus,
478 unsigned int devfn, int reg, int len, u32 *val);
479 extern int raw_pci_write(unsigned int domain, unsigned int bus,
480 unsigned int devfn, int reg, int len, u32 val);
481
482 struct pci_bus_region {
483 resource_size_t start;
484 resource_size_t end;
485 };
486
487 struct pci_dynids {
488 spinlock_t lock; /* protects list, index */
489 struct list_head list; /* for IDs added at runtime */
490 };
491
492 /* ---------------------------------------------------------------- */
493 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
494 * a set of callbacks in struct pci_error_handlers, then that device driver
495 * will be notified of PCI bus errors, and will be driven to recovery
496 * when an error occurs.
497 */
498
499 typedef unsigned int __bitwise pci_ers_result_t;
500
501 enum pci_ers_result {
502 /* no result/none/not supported in device driver */
503 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
504
505 /* Device driver can recover without slot reset */
506 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
507
508 /* Device driver wants slot to be reset. */
509 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
510
511 /* Device has completely failed, is unrecoverable */
512 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
513
514 /* Device driver is fully recovered and operational */
515 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
516 };
517
518 /* PCI bus error event callbacks */
519 struct pci_error_handlers {
520 /* PCI bus error detected on this device */
521 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
522 enum pci_channel_state error);
523
524 /* MMIO has been re-enabled, but not DMA */
525 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
526
527 /* PCI Express link has been reset */
528 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
529
530 /* PCI slot has been reset */
531 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
532
533 /* Device driver may resume normal operations */
534 void (*resume)(struct pci_dev *dev);
535 };
536
537 /* ---------------------------------------------------------------- */
538
539 struct module;
540 struct pci_driver {
541 struct list_head node;
542 char *name;
543 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
544 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
545 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
546 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
547 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
548 int (*resume_early) (struct pci_dev *dev);
549 int (*resume) (struct pci_dev *dev); /* Device woken up */
550 void (*shutdown) (struct pci_dev *dev);
551 struct pci_error_handlers *err_handler;
552 struct device_driver driver;
553 struct pci_dynids dynids;
554 };
555
556 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
557
558 /**
559 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
560 * @_table: device table name
561 *
562 * This macro is used to create a struct pci_device_id array (a device table)
563 * in a generic manner.
564 */
565 #define DEFINE_PCI_DEVICE_TABLE(_table) \
566 const struct pci_device_id _table[] __devinitconst
567
568 /**
569 * PCI_DEVICE - macro used to describe a specific pci device
570 * @vend: the 16 bit PCI Vendor ID
571 * @dev: the 16 bit PCI Device ID
572 *
573 * This macro is used to create a struct pci_device_id that matches a
574 * specific device. The subvendor and subdevice fields will be set to
575 * PCI_ANY_ID.
576 */
577 #define PCI_DEVICE(vend,dev) \
578 .vendor = (vend), .device = (dev), \
579 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
580
581 /**
582 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
583 * @dev_class: the class, subclass, prog-if triple for this device
584 * @dev_class_mask: the class mask for this device
585 *
586 * This macro is used to create a struct pci_device_id that matches a
587 * specific PCI class. The vendor, device, subvendor, and subdevice
588 * fields will be set to PCI_ANY_ID.
589 */
590 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
591 .class = (dev_class), .class_mask = (dev_class_mask), \
592 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
593 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
594
595 /**
596 * PCI_VDEVICE - macro used to describe a specific pci device in short form
597 * @vendor: the vendor name
598 * @device: the 16 bit PCI Device ID
599 *
600 * This macro is used to create a struct pci_device_id that matches a
601 * specific PCI device. The subvendor, and subdevice fields will be set
602 * to PCI_ANY_ID. The macro allows the next field to follow as the device
603 * private data.
604 */
605
606 #define PCI_VDEVICE(vendor, device) \
607 PCI_VENDOR_ID_##vendor, (device), \
608 PCI_ANY_ID, PCI_ANY_ID, 0, 0
609
610 /* these external functions are only available when PCI support is enabled */
611 #ifdef CONFIG_PCI
612
613 extern struct bus_type pci_bus_type;
614
615 /* Do NOT directly access these two variables, unless you are arch specific pci
616 * code, or pci core code. */
617 extern struct list_head pci_root_buses; /* list of all known PCI buses */
618 /* Some device drivers need know if pci is initiated */
619 extern int no_pci_devices(void);
620
621 void pcibios_fixup_bus(struct pci_bus *);
622 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
623 char *pcibios_setup(char *str);
624
625 /* Used only when drivers/pci/setup.c is used */
626 resource_size_t pcibios_align_resource(void *, const struct resource *,
627 resource_size_t,
628 resource_size_t);
629 void pcibios_update_irq(struct pci_dev *, int irq);
630
631 /* Weak but can be overriden by arch */
632 void pci_fixup_cardbus(struct pci_bus *);
633
634 /* Generic PCI functions used internally */
635
636 void pcibios_scan_specific_bus(int busn);
637 extern struct pci_bus *pci_find_bus(int domain, int busnr);
638 void pci_bus_add_devices(const struct pci_bus *bus);
639 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
640 struct pci_ops *ops, void *sysdata);
641 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
642 void *sysdata)
643 {
644 struct pci_bus *root_bus;
645 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
646 if (root_bus)
647 pci_bus_add_devices(root_bus);
648 return root_bus;
649 }
650 struct pci_bus *pci_create_bus(struct device *parent, int bus,
651 struct pci_ops *ops, void *sysdata);
652 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
653 int busnr);
654 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
655 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
656 const char *name,
657 struct hotplug_slot *hotplug);
658 void pci_destroy_slot(struct pci_slot *slot);
659 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
660 int pci_scan_slot(struct pci_bus *bus, int devfn);
661 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
662 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
663 unsigned int pci_scan_child_bus(struct pci_bus *bus);
664 int __must_check pci_bus_add_device(struct pci_dev *dev);
665 void pci_read_bridge_bases(struct pci_bus *child);
666 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
667 struct resource *res);
668 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
669 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
670 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
671 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
672 extern void pci_dev_put(struct pci_dev *dev);
673 extern void pci_remove_bus(struct pci_bus *b);
674 extern void pci_remove_bus_device(struct pci_dev *dev);
675 extern void pci_stop_bus_device(struct pci_dev *dev);
676 void pci_setup_cardbus(struct pci_bus *bus);
677 extern void pci_sort_breadthfirst(void);
678 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
679 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
680 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
681
682 /* Generic PCI functions exported to card drivers */
683
684 enum pci_lost_interrupt_reason {
685 PCI_LOST_IRQ_NO_INFORMATION = 0,
686 PCI_LOST_IRQ_DISABLE_MSI,
687 PCI_LOST_IRQ_DISABLE_MSIX,
688 PCI_LOST_IRQ_DISABLE_ACPI,
689 };
690 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
691 int pci_find_capability(struct pci_dev *dev, int cap);
692 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
693 int pci_find_ext_capability(struct pci_dev *dev, int cap);
694 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
695 int cap);
696 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
697 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
698 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
699
700 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
701 struct pci_dev *from);
702 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
703 unsigned int ss_vendor, unsigned int ss_device,
704 struct pci_dev *from);
705 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
706 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
707 unsigned int devfn);
708 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
709 unsigned int devfn)
710 {
711 return pci_get_domain_bus_and_slot(0, bus, devfn);
712 }
713 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
714 int pci_dev_present(const struct pci_device_id *ids);
715
716 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
717 int where, u8 *val);
718 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
719 int where, u16 *val);
720 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
721 int where, u32 *val);
722 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
723 int where, u8 val);
724 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
725 int where, u16 val);
726 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
727 int where, u32 val);
728 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
729
730 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
731 {
732 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
733 }
734 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
735 {
736 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
737 }
738 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
739 u32 *val)
740 {
741 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
742 }
743 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
744 {
745 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
746 }
747 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
748 {
749 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
750 }
751 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
752 u32 val)
753 {
754 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
755 }
756
757 int __must_check pci_enable_device(struct pci_dev *dev);
758 int __must_check pci_enable_device_io(struct pci_dev *dev);
759 int __must_check pci_enable_device_mem(struct pci_dev *dev);
760 int __must_check pci_reenable_device(struct pci_dev *);
761 int __must_check pcim_enable_device(struct pci_dev *pdev);
762 void pcim_pin_device(struct pci_dev *pdev);
763
764 static inline int pci_is_enabled(struct pci_dev *pdev)
765 {
766 return (atomic_read(&pdev->enable_cnt) > 0);
767 }
768
769 static inline int pci_is_managed(struct pci_dev *pdev)
770 {
771 return pdev->is_managed;
772 }
773
774 void pci_disable_device(struct pci_dev *dev);
775 void pci_set_master(struct pci_dev *dev);
776 void pci_clear_master(struct pci_dev *dev);
777 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
778 int pci_set_cacheline_size(struct pci_dev *dev);
779 #define HAVE_PCI_SET_MWI
780 int __must_check pci_set_mwi(struct pci_dev *dev);
781 int pci_try_set_mwi(struct pci_dev *dev);
782 void pci_clear_mwi(struct pci_dev *dev);
783 void pci_intx(struct pci_dev *dev, int enable);
784 void pci_msi_off(struct pci_dev *dev);
785 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
786 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
787 int pcix_get_max_mmrbc(struct pci_dev *dev);
788 int pcix_get_mmrbc(struct pci_dev *dev);
789 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
790 int pcie_get_readrq(struct pci_dev *dev);
791 int pcie_set_readrq(struct pci_dev *dev, int rq);
792 int __pci_reset_function(struct pci_dev *dev);
793 int pci_reset_function(struct pci_dev *dev);
794 void pci_update_resource(struct pci_dev *dev, int resno);
795 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
796 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
797
798 /* ROM control related routines */
799 int pci_enable_rom(struct pci_dev *pdev);
800 void pci_disable_rom(struct pci_dev *pdev);
801 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
802 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
803 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
804
805 /* Power management related routines */
806 int pci_save_state(struct pci_dev *dev);
807 int pci_restore_state(struct pci_dev *dev);
808 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
809 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
810 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
811 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
812 void pci_pme_active(struct pci_dev *dev, bool enable);
813 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
814 bool runtime, bool enable);
815 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
816 pci_power_t pci_target_state(struct pci_dev *dev);
817 int pci_prepare_to_sleep(struct pci_dev *dev);
818 int pci_back_from_sleep(struct pci_dev *dev);
819 bool pci_dev_run_wake(struct pci_dev *dev);
820
821 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
822 bool enable)
823 {
824 return __pci_enable_wake(dev, state, false, enable);
825 }
826
827 /* For use by arch with custom probe code */
828 void set_pcie_port_type(struct pci_dev *pdev);
829 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
830
831 /* Functions for PCI Hotplug drivers to use */
832 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
833 #ifdef CONFIG_HOTPLUG
834 unsigned int pci_rescan_bus(struct pci_bus *bus);
835 #endif
836
837 /* Vital product data routines */
838 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
839 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
840 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
841
842 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
843 void pci_bus_assign_resources(const struct pci_bus *bus);
844 void pci_bus_size_bridges(struct pci_bus *bus);
845 int pci_claim_resource(struct pci_dev *, int);
846 void pci_assign_unassigned_resources(void);
847 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
848 void pdev_enable_device(struct pci_dev *);
849 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
850 int pci_enable_resources(struct pci_dev *, int mask);
851 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
852 int (*)(struct pci_dev *, u8, u8));
853 #define HAVE_PCI_REQ_REGIONS 2
854 int __must_check pci_request_regions(struct pci_dev *, const char *);
855 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
856 void pci_release_regions(struct pci_dev *);
857 int __must_check pci_request_region(struct pci_dev *, int, const char *);
858 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
859 void pci_release_region(struct pci_dev *, int);
860 int pci_request_selected_regions(struct pci_dev *, int, const char *);
861 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
862 void pci_release_selected_regions(struct pci_dev *, int);
863
864 /* drivers/pci/bus.c */
865 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
866 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
867 void pci_bus_remove_resources(struct pci_bus *bus);
868
869 #define pci_bus_for_each_resource(bus, res, i) \
870 for (i = 0; \
871 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
872 i++)
873
874 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
875 struct resource *res, resource_size_t size,
876 resource_size_t align, resource_size_t min,
877 unsigned int type_mask,
878 resource_size_t (*alignf)(void *,
879 const struct resource *,
880 resource_size_t,
881 resource_size_t),
882 void *alignf_data);
883 void pci_enable_bridges(struct pci_bus *bus);
884
885 /* Proper probing supporting hot-pluggable devices */
886 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
887 const char *mod_name);
888
889 /*
890 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
891 */
892 #define pci_register_driver(driver) \
893 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
894
895 void pci_unregister_driver(struct pci_driver *dev);
896 void pci_remove_behind_bridge(struct pci_dev *dev);
897 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
898 int pci_add_dynid(struct pci_driver *drv,
899 unsigned int vendor, unsigned int device,
900 unsigned int subvendor, unsigned int subdevice,
901 unsigned int class, unsigned int class_mask,
902 unsigned long driver_data);
903 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
904 struct pci_dev *dev);
905 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
906 int pass);
907
908 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
909 void *userdata);
910 int pci_cfg_space_size_ext(struct pci_dev *dev);
911 int pci_cfg_space_size(struct pci_dev *dev);
912 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
913
914 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
915 unsigned int command_bits, bool change_bridge);
916 /* kmem_cache style wrapper around pci_alloc_consistent() */
917
918 #include <linux/pci-dma.h>
919 #include <linux/dmapool.h>
920
921 #define pci_pool dma_pool
922 #define pci_pool_create(name, pdev, size, align, allocation) \
923 dma_pool_create(name, &pdev->dev, size, align, allocation)
924 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
925 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
926 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
927
928 enum pci_dma_burst_strategy {
929 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
930 strategy_parameter is N/A */
931 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
932 byte boundaries */
933 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
934 strategy_parameter byte boundaries */
935 };
936
937 struct msix_entry {
938 u32 vector; /* kernel uses to write allocated vector */
939 u16 entry; /* driver uses to specify entry, OS writes */
940 };
941
942
943 #ifndef CONFIG_PCI_MSI
944 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
945 {
946 return -1;
947 }
948
949 static inline void pci_msi_shutdown(struct pci_dev *dev)
950 { }
951 static inline void pci_disable_msi(struct pci_dev *dev)
952 { }
953
954 static inline int pci_msix_table_size(struct pci_dev *dev)
955 {
956 return 0;
957 }
958 static inline int pci_enable_msix(struct pci_dev *dev,
959 struct msix_entry *entries, int nvec)
960 {
961 return -1;
962 }
963
964 static inline void pci_msix_shutdown(struct pci_dev *dev)
965 { }
966 static inline void pci_disable_msix(struct pci_dev *dev)
967 { }
968
969 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
970 { }
971
972 static inline void pci_restore_msi_state(struct pci_dev *dev)
973 { }
974 static inline int pci_msi_enabled(void)
975 {
976 return 0;
977 }
978 #else
979 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
980 extern void pci_msi_shutdown(struct pci_dev *dev);
981 extern void pci_disable_msi(struct pci_dev *dev);
982 extern int pci_msix_table_size(struct pci_dev *dev);
983 extern int pci_enable_msix(struct pci_dev *dev,
984 struct msix_entry *entries, int nvec);
985 extern void pci_msix_shutdown(struct pci_dev *dev);
986 extern void pci_disable_msix(struct pci_dev *dev);
987 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
988 extern void pci_restore_msi_state(struct pci_dev *dev);
989 extern int pci_msi_enabled(void);
990 #endif
991
992 #ifndef CONFIG_PCIEASPM
993 static inline int pcie_aspm_enabled(void)
994 {
995 return 0;
996 }
997 #else
998 extern int pcie_aspm_enabled(void);
999 #endif
1000
1001 #ifndef CONFIG_PCIE_ECRC
1002 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1003 {
1004 return;
1005 }
1006 static inline void pcie_ecrc_get_policy(char *str) {};
1007 #else
1008 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1009 extern void pcie_ecrc_get_policy(char *str);
1010 #endif
1011
1012 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1013
1014 #ifdef CONFIG_HT_IRQ
1015 /* The functions a driver should call */
1016 int ht_create_irq(struct pci_dev *dev, int idx);
1017 void ht_destroy_irq(unsigned int irq);
1018 #endif /* CONFIG_HT_IRQ */
1019
1020 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1021 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1022
1023 /*
1024 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1025 * a PCI domain is defined to be a set of PCI busses which share
1026 * configuration space.
1027 */
1028 #ifdef CONFIG_PCI_DOMAINS
1029 extern int pci_domains_supported;
1030 #else
1031 enum { pci_domains_supported = 0 };
1032 static inline int pci_domain_nr(struct pci_bus *bus)
1033 {
1034 return 0;
1035 }
1036
1037 static inline int pci_proc_domain(struct pci_bus *bus)
1038 {
1039 return 0;
1040 }
1041 #endif /* CONFIG_PCI_DOMAINS */
1042
1043 /* some architectures require additional setup to direct VGA traffic */
1044 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1045 unsigned int command_bits, bool change_bridge);
1046 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1047
1048 #else /* CONFIG_PCI is not enabled */
1049
1050 /*
1051 * If the system does not have PCI, clearly these return errors. Define
1052 * these as simple inline functions to avoid hair in drivers.
1053 */
1054
1055 #define _PCI_NOP(o, s, t) \
1056 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1057 int where, t val) \
1058 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1059
1060 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1061 _PCI_NOP(o, word, u16 x) \
1062 _PCI_NOP(o, dword, u32 x)
1063 _PCI_NOP_ALL(read, *)
1064 _PCI_NOP_ALL(write,)
1065
1066 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1067 unsigned int device,
1068 struct pci_dev *from)
1069 {
1070 return NULL;
1071 }
1072
1073 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1074 unsigned int device,
1075 unsigned int ss_vendor,
1076 unsigned int ss_device,
1077 struct pci_dev *from)
1078 {
1079 return NULL;
1080 }
1081
1082 static inline struct pci_dev *pci_get_class(unsigned int class,
1083 struct pci_dev *from)
1084 {
1085 return NULL;
1086 }
1087
1088 #define pci_dev_present(ids) (0)
1089 #define no_pci_devices() (1)
1090 #define pci_dev_put(dev) do { } while (0)
1091
1092 static inline void pci_set_master(struct pci_dev *dev)
1093 { }
1094
1095 static inline int pci_enable_device(struct pci_dev *dev)
1096 {
1097 return -EIO;
1098 }
1099
1100 static inline void pci_disable_device(struct pci_dev *dev)
1101 { }
1102
1103 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1104 {
1105 return -EIO;
1106 }
1107
1108 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1109 {
1110 return -EIO;
1111 }
1112
1113 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1114 unsigned int size)
1115 {
1116 return -EIO;
1117 }
1118
1119 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1120 unsigned long mask)
1121 {
1122 return -EIO;
1123 }
1124
1125 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1126 {
1127 return -EBUSY;
1128 }
1129
1130 static inline int __pci_register_driver(struct pci_driver *drv,
1131 struct module *owner)
1132 {
1133 return 0;
1134 }
1135
1136 static inline int pci_register_driver(struct pci_driver *drv)
1137 {
1138 return 0;
1139 }
1140
1141 static inline void pci_unregister_driver(struct pci_driver *drv)
1142 { }
1143
1144 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1145 {
1146 return 0;
1147 }
1148
1149 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1150 int cap)
1151 {
1152 return 0;
1153 }
1154
1155 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1156 {
1157 return 0;
1158 }
1159
1160 /* Power management related routines */
1161 static inline int pci_save_state(struct pci_dev *dev)
1162 {
1163 return 0;
1164 }
1165
1166 static inline int pci_restore_state(struct pci_dev *dev)
1167 {
1168 return 0;
1169 }
1170
1171 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1172 {
1173 return 0;
1174 }
1175
1176 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1177 pm_message_t state)
1178 {
1179 return PCI_D0;
1180 }
1181
1182 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1183 int enable)
1184 {
1185 return 0;
1186 }
1187
1188 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1189 {
1190 return -EIO;
1191 }
1192
1193 static inline void pci_release_regions(struct pci_dev *dev)
1194 { }
1195
1196 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1197
1198 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1199 { }
1200
1201 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1202 { }
1203
1204 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1205 { return NULL; }
1206
1207 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1208 unsigned int devfn)
1209 { return NULL; }
1210
1211 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1212 unsigned int devfn)
1213 { return NULL; }
1214
1215 #define dev_is_pci(d) (false)
1216 #define dev_is_pf(d) (false)
1217 #define dev_num_vf(d) (0)
1218 #endif /* CONFIG_PCI */
1219
1220 /* Include architecture-dependent settings and functions */
1221
1222 #include <asm/pci.h>
1223
1224 #ifndef PCIBIOS_MAX_MEM_32
1225 #define PCIBIOS_MAX_MEM_32 (-1)
1226 #endif
1227
1228 /* these helpers provide future and backwards compatibility
1229 * for accessing popular PCI BAR info */
1230 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1231 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1232 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1233 #define pci_resource_len(dev,bar) \
1234 ((pci_resource_start((dev), (bar)) == 0 && \
1235 pci_resource_end((dev), (bar)) == \
1236 pci_resource_start((dev), (bar))) ? 0 : \
1237 \
1238 (pci_resource_end((dev), (bar)) - \
1239 pci_resource_start((dev), (bar)) + 1))
1240
1241 /* Similar to the helpers above, these manipulate per-pci_dev
1242 * driver-specific data. They are really just a wrapper around
1243 * the generic device structure functions of these calls.
1244 */
1245 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1246 {
1247 return dev_get_drvdata(&pdev->dev);
1248 }
1249
1250 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1251 {
1252 dev_set_drvdata(&pdev->dev, data);
1253 }
1254
1255 /* If you want to know what to call your pci_dev, ask this function.
1256 * Again, it's a wrapper around the generic device.
1257 */
1258 static inline const char *pci_name(const struct pci_dev *pdev)
1259 {
1260 return dev_name(&pdev->dev);
1261 }
1262
1263
1264 /* Some archs don't want to expose struct resource to userland as-is
1265 * in sysfs and /proc
1266 */
1267 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1268 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1269 const struct resource *rsrc, resource_size_t *start,
1270 resource_size_t *end)
1271 {
1272 *start = rsrc->start;
1273 *end = rsrc->end;
1274 }
1275 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1276
1277
1278 /*
1279 * The world is not perfect and supplies us with broken PCI devices.
1280 * For at least a part of these bugs we need a work-around, so both
1281 * generic (drivers/pci/quirks.c) and per-architecture code can define
1282 * fixup hooks to be called for particular buggy devices.
1283 */
1284
1285 struct pci_fixup {
1286 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1287 void (*hook)(struct pci_dev *dev);
1288 };
1289
1290 enum pci_fixup_pass {
1291 pci_fixup_early, /* Before probing BARs */
1292 pci_fixup_header, /* After reading configuration header */
1293 pci_fixup_final, /* Final phase of device fixups */
1294 pci_fixup_enable, /* pci_enable_device() time */
1295 pci_fixup_resume, /* pci_device_resume() */
1296 pci_fixup_suspend, /* pci_device_suspend */
1297 pci_fixup_resume_early, /* pci_device_resume_early() */
1298 };
1299
1300 /* Anonymous variables would be nice... */
1301 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1302 static const struct pci_fixup __pci_fixup_##name __used \
1303 __attribute__((__section__(#section))) = { vendor, device, hook };
1304 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1305 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1306 vendor##device##hook, vendor, device, hook)
1307 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1308 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1309 vendor##device##hook, vendor, device, hook)
1310 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1311 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1312 vendor##device##hook, vendor, device, hook)
1313 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1314 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1315 vendor##device##hook, vendor, device, hook)
1316 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1317 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1318 resume##vendor##device##hook, vendor, device, hook)
1319 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1320 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1321 resume_early##vendor##device##hook, vendor, device, hook)
1322 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1323 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1324 suspend##vendor##device##hook, vendor, device, hook)
1325
1326 #ifdef CONFIG_PCI_QUIRKS
1327 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1328 #else
1329 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1330 struct pci_dev *dev) {}
1331 #endif
1332
1333 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1334 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1335 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1336 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1337 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1338 const char *name);
1339 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1340
1341 extern int pci_pci_problems;
1342 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1343 #define PCIPCI_TRITON 2
1344 #define PCIPCI_NATOMA 4
1345 #define PCIPCI_VIAETBF 8
1346 #define PCIPCI_VSFX 16
1347 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1348 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1349
1350 extern unsigned long pci_cardbus_io_size;
1351 extern unsigned long pci_cardbus_mem_size;
1352 extern u8 __devinitdata pci_dfl_cache_line_size;
1353 extern u8 pci_cache_line_size;
1354
1355 extern unsigned long pci_hotplug_io_size;
1356 extern unsigned long pci_hotplug_mem_size;
1357
1358 int pcibios_add_platform_entries(struct pci_dev *dev);
1359 void pcibios_disable_device(struct pci_dev *dev);
1360 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1361 enum pcie_reset_state state);
1362
1363 #ifdef CONFIG_PCI_MMCONFIG
1364 extern void __init pci_mmcfg_early_init(void);
1365 extern void __init pci_mmcfg_late_init(void);
1366 #else
1367 static inline void pci_mmcfg_early_init(void) { }
1368 static inline void pci_mmcfg_late_init(void) { }
1369 #endif
1370
1371 int pci_ext_cfg_avail(struct pci_dev *dev);
1372
1373 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1374
1375 #ifdef CONFIG_PCI_IOV
1376 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1377 extern void pci_disable_sriov(struct pci_dev *dev);
1378 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1379 extern int pci_num_vf(struct pci_dev *dev);
1380 #else
1381 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1382 {
1383 return -ENODEV;
1384 }
1385 static inline void pci_disable_sriov(struct pci_dev *dev)
1386 {
1387 }
1388 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1389 {
1390 return IRQ_NONE;
1391 }
1392 static inline int pci_num_vf(struct pci_dev *dev)
1393 {
1394 return 0;
1395 }
1396 #endif
1397
1398 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1399 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1400 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1401 #endif
1402
1403 /**
1404 * pci_pcie_cap - get the saved PCIe capability offset
1405 * @dev: PCI device
1406 *
1407 * PCIe capability offset is calculated at PCI device initialization
1408 * time and saved in the data structure. This function returns saved
1409 * PCIe capability offset. Using this instead of pci_find_capability()
1410 * reduces unnecessary search in the PCI configuration space. If you
1411 * need to calculate PCIe capability offset from raw device for some
1412 * reasons, please use pci_find_capability() instead.
1413 */
1414 static inline int pci_pcie_cap(struct pci_dev *dev)
1415 {
1416 return dev->pcie_cap;
1417 }
1418
1419 /**
1420 * pci_is_pcie - check if the PCI device is PCI Express capable
1421 * @dev: PCI device
1422 *
1423 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1424 */
1425 static inline bool pci_is_pcie(struct pci_dev *dev)
1426 {
1427 return !!pci_pcie_cap(dev);
1428 }
1429
1430 void pci_request_acs(void);
1431
1432
1433 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1434 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1435
1436 /* Large Resource Data Type Tag Item Names */
1437 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1438 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1439 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1440
1441 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1442 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1443 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1444
1445 /* Small Resource Data Type Tag Item Names */
1446 #define PCI_VPD_STIN_END 0x78 /* End */
1447
1448 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1449
1450 #define PCI_VPD_SRDT_TIN_MASK 0x78
1451 #define PCI_VPD_SRDT_LEN_MASK 0x07
1452
1453 #define PCI_VPD_LRDT_TAG_SIZE 3
1454 #define PCI_VPD_SRDT_TAG_SIZE 1
1455
1456 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1457
1458 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1459 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1460 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1461
1462 /**
1463 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1464 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1465 *
1466 * Returns the extracted Large Resource Data Type length.
1467 */
1468 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1469 {
1470 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1471 }
1472
1473 /**
1474 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1475 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1476 *
1477 * Returns the extracted Small Resource Data Type length.
1478 */
1479 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1480 {
1481 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1482 }
1483
1484 /**
1485 * pci_vpd_info_field_size - Extracts the information field length
1486 * @lrdt: Pointer to the beginning of an information field header
1487 *
1488 * Returns the extracted information field length.
1489 */
1490 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1491 {
1492 return info_field[2];
1493 }
1494
1495 /**
1496 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1497 * @buf: Pointer to buffered vpd data
1498 * @off: The offset into the buffer at which to begin the search
1499 * @len: The length of the vpd buffer
1500 * @rdt: The Resource Data Type to search for
1501 *
1502 * Returns the index where the Resource Data Type was found or
1503 * -ENOENT otherwise.
1504 */
1505 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1506
1507 /**
1508 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1509 * @buf: Pointer to buffered vpd data
1510 * @off: The offset into the buffer at which to begin the search
1511 * @len: The length of the buffer area, relative to off, in which to search
1512 * @kw: The keyword to search for
1513 *
1514 * Returns the index where the information field keyword was found or
1515 * -ENOENT otherwise.
1516 */
1517 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1518 unsigned int len, const char *kw);
1519
1520 #endif /* __KERNEL__ */
1521 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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