4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus
*bus
; /* The bus this slot is on */
56 struct list_head list
; /* node in list of slots on this bus */
57 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
58 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
64 return kobject_name(&slot
->kobj
);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END
= 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
101 PCI_BRIDGE_RESOURCE_NUM
- 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
110 typedef int __bitwise pci_power_t
;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names
[];
123 static inline const char *pci_power_name(pci_power_t state
)
125 return pci_power_names
[1 + (int) state
];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t
;
139 enum pci_channel_state
{
140 /* I/O channel is in normal state */
141 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t
;
152 enum pcie_reset_state
{
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
163 typedef unsigned short __bitwise pci_dev_flags_t
;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) 1,
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) 2,
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) 4,
175 enum pci_irq_reroute_variant
{
176 INTEL_IRQ_REROUTE_VARIANT
= 1,
177 MAX_IRQ_REROUTE_VARIANTS
= 3
180 typedef unsigned short __bitwise pci_bus_flags_t
;
182 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
183 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
186 /* These values come from the PCI Express Spec */
187 enum pcie_link_width
{
188 PCIE_LNK_WIDTH_RESRV
= 0x00,
196 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
199 /* Based on the PCI Hotplug Spec, but some values are made up by us */
201 PCI_SPEED_33MHz
= 0x00,
202 PCI_SPEED_66MHz
= 0x01,
203 PCI_SPEED_66MHz_PCIX
= 0x02,
204 PCI_SPEED_100MHz_PCIX
= 0x03,
205 PCI_SPEED_133MHz_PCIX
= 0x04,
206 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
207 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
208 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
209 PCI_SPEED_66MHz_PCIX_266
= 0x09,
210 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
211 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
217 PCI_SPEED_66MHz_PCIX_533
= 0x11,
218 PCI_SPEED_100MHz_PCIX_533
= 0x12,
219 PCI_SPEED_133MHz_PCIX_533
= 0x13,
220 PCIE_SPEED_2_5GT
= 0x14,
221 PCIE_SPEED_5_0GT
= 0x15,
222 PCIE_SPEED_8_0GT
= 0x16,
223 PCI_SPEED_UNKNOWN
= 0xff,
226 struct pci_cap_saved_data
{
233 struct pci_cap_saved_state
{
234 struct hlist_node next
;
235 struct pci_cap_saved_data cap
;
238 struct pcie_link_state
;
244 * The pci_dev structure is used to describe PCI devices.
247 struct list_head bus_list
; /* node in per-bus list */
248 struct pci_bus
*bus
; /* bus this device is on */
249 struct pci_bus
*subordinate
; /* bus this device bridges to */
251 void *sysdata
; /* hook for sys-specific extension */
252 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
253 struct pci_slot
*slot
; /* Physical slot this device is in */
255 unsigned int devfn
; /* encoded device & function index */
256 unsigned short vendor
;
257 unsigned short device
;
258 unsigned short subsystem_vendor
;
259 unsigned short subsystem_device
;
260 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
261 u8 revision
; /* PCI revision, low byte of class word */
262 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
263 u8 pcie_cap
; /* PCIe capability offset */
264 u8 msi_cap
; /* MSI capability offset */
265 u8 msix_cap
; /* MSI-X capability offset */
266 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
267 u8 rom_base_reg
; /* which config register controls the ROM */
268 u8 pin
; /* which interrupt pin this device uses */
269 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
271 struct pci_driver
*driver
; /* which driver has allocated this device */
272 u64 dma_mask
; /* Mask of the bits of bus address this
273 device implements. Normally this is
274 0xffffffff. You only need to change
275 this if your device has broken DMA
276 or supports 64-bit transfers. */
278 struct device_dma_parameters dma_parms
;
280 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
281 this is D0-D3, D0 being fully functional,
283 u8 pm_cap
; /* PM capability offset */
284 unsigned int pme_support
:5; /* Bitmask of states from which PME#
286 unsigned int pme_interrupt
:1;
287 unsigned int pme_poll
:1; /* Poll device's PME status bit */
288 unsigned int d1_support
:1; /* Low power state D1 is supported */
289 unsigned int d2_support
:1; /* Low power state D2 is supported */
290 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
291 unsigned int no_d3cold
:1; /* D3cold is forbidden */
292 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
293 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
294 decoding during bar sizing */
295 unsigned int wakeup_prepared
:1;
296 unsigned int runtime_d3cold
:1; /* whether go through runtime
297 D3cold, not set for devices
298 powered on/off by the
299 corresponding bridge */
300 unsigned int d3_delay
; /* D3->D0 transition time in ms */
301 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
303 #ifdef CONFIG_PCIEASPM
304 struct pcie_link_state
*link_state
; /* ASPM link state */
307 pci_channel_state_t error_state
; /* current connectivity state */
308 struct device dev
; /* Generic device interface */
310 int cfg_size
; /* Size of configuration space */
313 * Instead of touching interrupt line and base address registers
314 * directly, use the values stored here. They might be different!
317 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
319 bool match_driver
; /* Skip attaching driver */
320 /* These fields are used by common fixups */
321 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
322 unsigned int multifunction
:1;/* Part of multi-function device */
323 /* keep track of device state */
324 unsigned int is_added
:1;
325 unsigned int is_busmaster
:1; /* device is busmaster */
326 unsigned int no_msi
:1; /* device may not use msi */
327 unsigned int block_cfg_access
:1; /* config space access is blocked */
328 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
329 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
330 unsigned int msi_enabled
:1;
331 unsigned int msix_enabled
:1;
332 unsigned int ari_enabled
:1; /* ARI forwarding */
333 unsigned int is_managed
:1;
334 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
335 unsigned int state_saved
:1;
336 unsigned int is_physfn
:1;
337 unsigned int is_virtfn
:1;
338 unsigned int reset_fn
:1;
339 unsigned int is_hotplug_bridge
:1;
340 unsigned int __aer_firmware_first_valid
:1;
341 unsigned int __aer_firmware_first
:1;
342 unsigned int broken_intx_masking
:1;
343 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
344 pci_dev_flags_t dev_flags
;
345 atomic_t enable_cnt
; /* pci_enable_device has been called */
347 u32 saved_config_space
[16]; /* config space saved at suspend time */
348 struct hlist_head saved_cap_space
;
349 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
350 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
351 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
352 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
353 #ifdef CONFIG_PCI_MSI
354 struct list_head msi_list
;
355 const struct attribute_group
**msi_irq_groups
;
358 #ifdef CONFIG_PCI_ATS
360 struct pci_sriov
*sriov
; /* SR-IOV capability related */
361 struct pci_dev
*physfn
; /* the PF this VF is associated with */
363 struct pci_ats
*ats
; /* Address Translation Service */
365 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
366 size_t romlen
; /* Length of ROM if it's not from the BAR */
369 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
371 #ifdef CONFIG_PCI_IOV
378 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
379 struct pci_dev
* __deprecated
alloc_pci_dev(void);
381 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
382 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
384 static inline int pci_channel_offline(struct pci_dev
*pdev
)
386 return (pdev
->error_state
!= pci_channel_io_normal
);
389 extern struct resource busn_resource
;
391 struct pci_host_bridge_window
{
392 struct list_head list
;
393 struct resource
*res
; /* host bridge aperture (CPU address) */
394 resource_size_t offset
; /* bus address + offset = CPU address */
397 struct pci_host_bridge
{
399 struct pci_bus
*bus
; /* root bus */
400 struct list_head windows
; /* pci_host_bridge_windows */
401 void (*release_fn
)(struct pci_host_bridge
*);
405 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
406 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
407 void (*release_fn
)(struct pci_host_bridge
*),
410 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
413 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
414 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
415 * buses below host bridges or subtractive decode bridges) go in the list.
416 * Use pci_bus_for_each_resource() to iterate through all the resources.
420 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
421 * and there's no way to program the bridge with the details of the window.
422 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
423 * decode bit set, because they are explicit and can be programmed with _SRS.
425 #define PCI_SUBTRACTIVE_DECODE 0x1
427 struct pci_bus_resource
{
428 struct list_head list
;
429 struct resource
*res
;
433 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
436 struct list_head node
; /* node in list of buses */
437 struct pci_bus
*parent
; /* parent bus this bridge is on */
438 struct list_head children
; /* list of child buses */
439 struct list_head devices
; /* list of devices on this bus */
440 struct pci_dev
*self
; /* bridge device as seen by parent */
441 struct list_head slots
; /* list of slots on this bus */
442 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
443 struct list_head resources
; /* address space routed to this bus */
444 struct resource busn_res
; /* bus numbers routed to this bus */
446 struct pci_ops
*ops
; /* configuration access functions */
447 struct msi_chip
*msi
; /* MSI controller */
448 void *sysdata
; /* hook for sys-specific extension */
449 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
451 unsigned char number
; /* bus number */
452 unsigned char primary
; /* number of primary bridge */
453 unsigned char max_bus_speed
; /* enum pci_bus_speed */
454 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
458 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
459 pci_bus_flags_t bus_flags
; /* inherited by child buses */
460 struct device
*bridge
;
462 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
463 struct bin_attribute
*legacy_mem
; /* legacy mem */
464 unsigned int is_added
:1;
467 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
468 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
471 * Returns true if the PCI bus is root (behind host-PCI bridge),
474 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
475 * This is incorrect because "virtual" buses added for SR-IOV (via
476 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
478 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
480 return !(pbus
->parent
);
483 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
485 dev
= pci_physfn(dev
);
486 if (pci_is_root_bus(dev
->bus
))
489 return dev
->bus
->self
;
492 #ifdef CONFIG_PCI_MSI
493 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
495 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
498 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
502 * Error values that may be returned by PCI functions.
504 #define PCIBIOS_SUCCESSFUL 0x00
505 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
506 #define PCIBIOS_BAD_VENDOR_ID 0x83
507 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
508 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
509 #define PCIBIOS_SET_FAILED 0x88
510 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
513 * Translate above to generic errno for passing back through non-PCI code.
515 static inline int pcibios_err_to_errno(int err
)
517 if (err
<= PCIBIOS_SUCCESSFUL
)
518 return err
; /* Assume already errno */
521 case PCIBIOS_FUNC_NOT_SUPPORTED
:
523 case PCIBIOS_BAD_VENDOR_ID
:
525 case PCIBIOS_DEVICE_NOT_FOUND
:
527 case PCIBIOS_BAD_REGISTER_NUMBER
:
529 case PCIBIOS_SET_FAILED
:
531 case PCIBIOS_BUFFER_TOO_SMALL
:
538 /* Low-level architecture-dependent routines */
541 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
542 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
546 * ACPI needs to be able to access PCI config space before we've done a
547 * PCI bus scan and created pci_bus structures.
549 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
550 int reg
, int len
, u32
*val
);
551 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
552 int reg
, int len
, u32 val
);
554 struct pci_bus_region
{
555 resource_size_t start
;
560 spinlock_t lock
; /* protects list, index */
561 struct list_head list
; /* for IDs added at runtime */
566 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
567 * a set of callbacks in struct pci_error_handlers, that device driver
568 * will be notified of PCI bus errors, and will be driven to recovery
569 * when an error occurs.
572 typedef unsigned int __bitwise pci_ers_result_t
;
574 enum pci_ers_result
{
575 /* no result/none/not supported in device driver */
576 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
578 /* Device driver can recover without slot reset */
579 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
581 /* Device driver wants slot to be reset. */
582 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
584 /* Device has completely failed, is unrecoverable */
585 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
587 /* Device driver is fully recovered and operational */
588 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
590 /* No AER capabilities registered for the driver */
591 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
594 /* PCI bus error event callbacks */
595 struct pci_error_handlers
{
596 /* PCI bus error detected on this device */
597 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
598 enum pci_channel_state error
);
600 /* MMIO has been re-enabled, but not DMA */
601 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
603 /* PCI Express link has been reset */
604 pci_ers_result_t (*link_reset
)(struct pci_dev
*dev
);
606 /* PCI slot has been reset */
607 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
609 /* Device driver may resume normal operations */
610 void (*resume
)(struct pci_dev
*dev
);
616 struct list_head node
;
618 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
619 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
620 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
621 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
622 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
623 int (*resume_early
) (struct pci_dev
*dev
);
624 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
625 void (*shutdown
) (struct pci_dev
*dev
);
626 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
627 const struct pci_error_handlers
*err_handler
;
628 struct device_driver driver
;
629 struct pci_dynids dynids
;
632 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
635 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
636 * @_table: device table name
638 * This macro is deprecated and should not be used in new code.
640 #define DEFINE_PCI_DEVICE_TABLE(_table) \
641 const struct pci_device_id _table[]
644 * PCI_DEVICE - macro used to describe a specific pci device
645 * @vend: the 16 bit PCI Vendor ID
646 * @dev: the 16 bit PCI Device ID
648 * This macro is used to create a struct pci_device_id that matches a
649 * specific device. The subvendor and subdevice fields will be set to
652 #define PCI_DEVICE(vend,dev) \
653 .vendor = (vend), .device = (dev), \
654 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
657 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
658 * @vend: the 16 bit PCI Vendor ID
659 * @dev: the 16 bit PCI Device ID
660 * @subvend: the 16 bit PCI Subvendor ID
661 * @subdev: the 16 bit PCI Subdevice ID
663 * This macro is used to create a struct pci_device_id that matches a
664 * specific device with subsystem information.
666 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
667 .vendor = (vend), .device = (dev), \
668 .subvendor = (subvend), .subdevice = (subdev)
671 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
672 * @dev_class: the class, subclass, prog-if triple for this device
673 * @dev_class_mask: the class mask for this device
675 * This macro is used to create a struct pci_device_id that matches a
676 * specific PCI class. The vendor, device, subvendor, and subdevice
677 * fields will be set to PCI_ANY_ID.
679 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
680 .class = (dev_class), .class_mask = (dev_class_mask), \
681 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
682 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
685 * PCI_VDEVICE - macro used to describe a specific pci device in short form
686 * @vendor: the vendor name
687 * @device: the 16 bit PCI Device ID
689 * This macro is used to create a struct pci_device_id that matches a
690 * specific PCI device. The subvendor, and subdevice fields will be set
691 * to PCI_ANY_ID. The macro allows the next field to follow as the device
695 #define PCI_VDEVICE(vendor, device) \
696 PCI_VENDOR_ID_##vendor, (device), \
697 PCI_ANY_ID, PCI_ANY_ID, 0, 0
699 /* these external functions are only available when PCI support is enabled */
702 void pcie_bus_configure_settings(struct pci_bus
*bus
);
704 enum pcie_bus_config_types
{
707 PCIE_BUS_PERFORMANCE
,
711 extern enum pcie_bus_config_types pcie_bus_config
;
713 extern struct bus_type pci_bus_type
;
715 /* Do NOT directly access these two variables, unless you are arch-specific PCI
716 * code, or PCI core code. */
717 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
718 /* Some device drivers need know if PCI is initiated */
719 int no_pci_devices(void);
721 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
722 void pcibios_add_bus(struct pci_bus
*bus
);
723 void pcibios_remove_bus(struct pci_bus
*bus
);
724 void pcibios_fixup_bus(struct pci_bus
*);
725 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
726 /* Architecture-specific versions may override this (weak) */
727 char *pcibios_setup(char *str
);
729 /* Used only when drivers/pci/setup.c is used */
730 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
733 void pcibios_update_irq(struct pci_dev
*, int irq
);
735 /* Weak but can be overriden by arch */
736 void pci_fixup_cardbus(struct pci_bus
*);
738 /* Generic PCI functions used internally */
740 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
741 struct resource
*res
);
742 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
743 struct pci_bus_region
*region
);
744 void pcibios_scan_specific_bus(int busn
);
745 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
746 void pci_bus_add_devices(const struct pci_bus
*bus
);
747 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
, int bus
,
748 struct pci_ops
*ops
, void *sysdata
);
749 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
750 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
751 struct pci_ops
*ops
, void *sysdata
,
752 struct list_head
*resources
);
753 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
754 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
755 void pci_bus_release_busn_res(struct pci_bus
*b
);
756 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
757 struct pci_ops
*ops
, void *sysdata
,
758 struct list_head
*resources
);
759 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
761 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
762 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
764 struct hotplug_slot
*hotplug
);
765 void pci_destroy_slot(struct pci_slot
*slot
);
766 void pci_renumber_slot(struct pci_slot
*slot
, int slot_nr
);
767 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
768 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
769 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
770 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
771 int __must_check
pci_bus_add_device(struct pci_dev
*dev
);
772 void pci_read_bridge_bases(struct pci_bus
*child
);
773 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
774 struct resource
*res
);
775 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
776 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
777 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
778 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
779 void pci_dev_put(struct pci_dev
*dev
);
780 void pci_remove_bus(struct pci_bus
*b
);
781 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
782 void pci_stop_root_bus(struct pci_bus
*bus
);
783 void pci_remove_root_bus(struct pci_bus
*bus
);
784 void pci_setup_cardbus(struct pci_bus
*bus
);
785 void pci_sort_breadthfirst(void);
786 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
787 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
788 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
790 /* Generic PCI functions exported to card drivers */
792 enum pci_lost_interrupt_reason
{
793 PCI_LOST_IRQ_NO_INFORMATION
= 0,
794 PCI_LOST_IRQ_DISABLE_MSI
,
795 PCI_LOST_IRQ_DISABLE_MSIX
,
796 PCI_LOST_IRQ_DISABLE_ACPI
,
798 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
799 int pci_find_capability(struct pci_dev
*dev
, int cap
);
800 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
801 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
802 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
803 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
804 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
805 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
807 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
808 struct pci_dev
*from
);
809 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
810 unsigned int ss_vendor
, unsigned int ss_device
,
811 struct pci_dev
*from
);
812 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
813 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
815 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
818 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
820 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
821 int pci_dev_present(const struct pci_device_id
*ids
);
823 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
825 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
826 int where
, u16
*val
);
827 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
828 int where
, u32
*val
);
829 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
831 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
833 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
835 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
837 static inline int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
)
839 return pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
841 static inline int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
)
843 return pci_bus_read_config_word(dev
->bus
, dev
->devfn
, where
, val
);
845 static inline int pci_read_config_dword(const struct pci_dev
*dev
, int where
,
848 return pci_bus_read_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
850 static inline int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
)
852 return pci_bus_write_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
854 static inline int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
)
856 return pci_bus_write_config_word(dev
->bus
, dev
->devfn
, where
, val
);
858 static inline int pci_write_config_dword(const struct pci_dev
*dev
, int where
,
861 return pci_bus_write_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
864 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
865 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
866 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
867 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
868 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
870 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
873 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
876 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
879 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
882 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
885 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
888 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
891 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
894 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
897 /* user-space driven config access */
898 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
899 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
900 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
901 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
902 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
903 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
905 int __must_check
pci_enable_device(struct pci_dev
*dev
);
906 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
907 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
908 int __must_check
pci_reenable_device(struct pci_dev
*);
909 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
910 void pcim_pin_device(struct pci_dev
*pdev
);
912 static inline int pci_is_enabled(struct pci_dev
*pdev
)
914 return (atomic_read(&pdev
->enable_cnt
) > 0);
917 static inline int pci_is_managed(struct pci_dev
*pdev
)
919 return pdev
->is_managed
;
922 void pci_disable_device(struct pci_dev
*dev
);
924 extern unsigned int pcibios_max_latency
;
925 void pci_set_master(struct pci_dev
*dev
);
926 void pci_clear_master(struct pci_dev
*dev
);
928 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
929 int pci_set_cacheline_size(struct pci_dev
*dev
);
930 #define HAVE_PCI_SET_MWI
931 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
932 int pci_try_set_mwi(struct pci_dev
*dev
);
933 void pci_clear_mwi(struct pci_dev
*dev
);
934 void pci_intx(struct pci_dev
*dev
, int enable
);
935 bool pci_intx_mask_supported(struct pci_dev
*dev
);
936 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
937 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
938 void pci_msi_off(struct pci_dev
*dev
);
939 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
);
940 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
);
941 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
942 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
943 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
944 int pcix_get_mmrbc(struct pci_dev
*dev
);
945 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
946 int pcie_get_readrq(struct pci_dev
*dev
);
947 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
948 int pcie_get_mps(struct pci_dev
*dev
);
949 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
950 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
951 enum pcie_link_width
*width
);
952 int __pci_reset_function(struct pci_dev
*dev
);
953 int __pci_reset_function_locked(struct pci_dev
*dev
);
954 int pci_reset_function(struct pci_dev
*dev
);
955 int pci_probe_reset_slot(struct pci_slot
*slot
);
956 int pci_reset_slot(struct pci_slot
*slot
);
957 int pci_probe_reset_bus(struct pci_bus
*bus
);
958 int pci_reset_bus(struct pci_bus
*bus
);
959 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
960 void pci_update_resource(struct pci_dev
*dev
, int resno
);
961 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
962 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
963 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
965 /* ROM control related routines */
966 int pci_enable_rom(struct pci_dev
*pdev
);
967 void pci_disable_rom(struct pci_dev
*pdev
);
968 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
969 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
970 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
971 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
973 /* Power management related routines */
974 int pci_save_state(struct pci_dev
*dev
);
975 void pci_restore_state(struct pci_dev
*dev
);
976 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
977 int pci_load_saved_state(struct pci_dev
*dev
, struct pci_saved_state
*state
);
978 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
979 struct pci_saved_state
**state
);
980 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
981 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
983 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
984 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
985 u16 cap
, unsigned int size
);
986 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
987 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
988 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
989 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
990 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
991 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
992 bool runtime
, bool enable
);
993 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
994 pci_power_t
pci_target_state(struct pci_dev
*dev
);
995 int pci_prepare_to_sleep(struct pci_dev
*dev
);
996 int pci_back_from_sleep(struct pci_dev
*dev
);
997 bool pci_dev_run_wake(struct pci_dev
*dev
);
998 bool pci_check_pme_status(struct pci_dev
*dev
);
999 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1001 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1004 return __pci_enable_wake(dev
, state
, false, enable
);
1007 /* PCI Virtual Channel */
1008 int pci_save_vc_state(struct pci_dev
*dev
);
1009 void pci_restore_vc_state(struct pci_dev
*dev
);
1010 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1012 #define PCI_EXP_IDO_REQUEST (1<<0)
1013 #define PCI_EXP_IDO_COMPLETION (1<<1)
1014 void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
);
1015 void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
);
1017 enum pci_obff_signal_type
{
1018 PCI_EXP_OBFF_SIGNAL_L0
= 0,
1019 PCI_EXP_OBFF_SIGNAL_ALWAYS
= 1,
1021 int pci_enable_obff(struct pci_dev
*dev
, enum pci_obff_signal_type
);
1022 void pci_disable_obff(struct pci_dev
*dev
);
1024 int pci_enable_ltr(struct pci_dev
*dev
);
1025 void pci_disable_ltr(struct pci_dev
*dev
);
1026 int pci_set_ltr(struct pci_dev
*dev
, int snoop_lat_ns
, int nosnoop_lat_ns
);
1028 /* For use by arch with custom probe code */
1029 void set_pcie_port_type(struct pci_dev
*pdev
);
1030 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1032 /* Functions for PCI Hotplug drivers to use */
1033 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1034 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1035 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1037 /* Vital product data routines */
1038 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1039 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1040 int pci_vpd_truncate(struct pci_dev
*dev
, size_t size
);
1042 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1043 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1044 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1045 void pci_bus_size_bridges(struct pci_bus
*bus
);
1046 int pci_claim_resource(struct pci_dev
*, int);
1047 void pci_assign_unassigned_resources(void);
1048 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1049 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1050 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1051 void pdev_enable_device(struct pci_dev
*);
1052 int pci_enable_resources(struct pci_dev
*, int mask
);
1053 void pci_fixup_irqs(u8 (*)(struct pci_dev
*, u8
*),
1054 int (*)(const struct pci_dev
*, u8
, u8
));
1055 #define HAVE_PCI_REQ_REGIONS 2
1056 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1057 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1058 void pci_release_regions(struct pci_dev
*);
1059 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1060 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1061 void pci_release_region(struct pci_dev
*, int);
1062 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1063 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1064 void pci_release_selected_regions(struct pci_dev
*, int);
1066 /* drivers/pci/bus.c */
1067 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1068 void pci_bus_put(struct pci_bus
*bus
);
1069 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1070 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1071 resource_size_t offset
);
1072 void pci_free_resource_list(struct list_head
*resources
);
1073 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
, unsigned int flags
);
1074 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1075 void pci_bus_remove_resources(struct pci_bus
*bus
);
1077 #define pci_bus_for_each_resource(bus, res, i) \
1079 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1082 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1083 struct resource
*res
, resource_size_t size
,
1084 resource_size_t align
, resource_size_t min
,
1085 unsigned int type_mask
,
1086 resource_size_t (*alignf
)(void *,
1087 const struct resource
*,
1092 /* Proper probing supporting hot-pluggable devices */
1093 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1094 const char *mod_name
);
1097 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1099 #define pci_register_driver(driver) \
1100 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1102 void pci_unregister_driver(struct pci_driver
*dev
);
1105 * module_pci_driver() - Helper macro for registering a PCI driver
1106 * @__pci_driver: pci_driver struct
1108 * Helper macro for PCI drivers which do not do anything special in module
1109 * init/exit. This eliminates a lot of boilerplate. Each module may only
1110 * use this macro once, and calling it replaces module_init() and module_exit()
1112 #define module_pci_driver(__pci_driver) \
1113 module_driver(__pci_driver, pci_register_driver, \
1114 pci_unregister_driver)
1116 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1117 int pci_add_dynid(struct pci_driver
*drv
,
1118 unsigned int vendor
, unsigned int device
,
1119 unsigned int subvendor
, unsigned int subdevice
,
1120 unsigned int class, unsigned int class_mask
,
1121 unsigned long driver_data
);
1122 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1123 struct pci_dev
*dev
);
1124 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1127 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1129 int pci_cfg_space_size_ext(struct pci_dev
*dev
);
1130 int pci_cfg_space_size(struct pci_dev
*dev
);
1131 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1132 void pci_setup_bridge(struct pci_bus
*bus
);
1133 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1134 unsigned long type
);
1136 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1137 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1139 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1140 unsigned int command_bits
, u32 flags
);
1141 /* kmem_cache style wrapper around pci_alloc_consistent() */
1143 #include <linux/pci-dma.h>
1144 #include <linux/dmapool.h>
1146 #define pci_pool dma_pool
1147 #define pci_pool_create(name, pdev, size, align, allocation) \
1148 dma_pool_create(name, &pdev->dev, size, align, allocation)
1149 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1150 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1151 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1153 enum pci_dma_burst_strategy
{
1154 PCI_DMA_BURST_INFINITY
, /* make bursts as large as possible,
1155 strategy_parameter is N/A */
1156 PCI_DMA_BURST_BOUNDARY
, /* disconnect at every strategy_parameter
1158 PCI_DMA_BURST_MULTIPLE
, /* disconnect at some multiple of
1159 strategy_parameter byte boundaries */
1163 u32 vector
; /* kernel uses to write allocated vector */
1164 u16 entry
; /* driver uses to specify entry, OS writes */
1168 #ifndef CONFIG_PCI_MSI
1169 static inline int pci_enable_msi_block(struct pci_dev
*dev
, int nvec
)
1175 pci_enable_msi_block_auto(struct pci_dev
*dev
, int *maxvec
)
1180 static inline void pci_msi_shutdown(struct pci_dev
*dev
)
1182 static inline void pci_disable_msi(struct pci_dev
*dev
)
1185 static inline int pci_msix_table_size(struct pci_dev
*dev
)
1189 static inline int pci_enable_msix(struct pci_dev
*dev
,
1190 struct msix_entry
*entries
, int nvec
)
1195 static inline void pci_msix_shutdown(struct pci_dev
*dev
)
1197 static inline void pci_disable_msix(struct pci_dev
*dev
)
1200 static inline void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
1203 static inline void pci_restore_msi_state(struct pci_dev
*dev
)
1205 static inline int pci_msi_enabled(void)
1210 int pci_enable_msi_block(struct pci_dev
*dev
, int nvec
);
1211 int pci_enable_msi_block_auto(struct pci_dev
*dev
, int *maxvec
);
1212 void pci_msi_shutdown(struct pci_dev
*dev
);
1213 void pci_disable_msi(struct pci_dev
*dev
);
1214 int pci_msix_table_size(struct pci_dev
*dev
);
1215 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
);
1216 void pci_msix_shutdown(struct pci_dev
*dev
);
1217 void pci_disable_msix(struct pci_dev
*dev
);
1218 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
);
1219 void pci_restore_msi_state(struct pci_dev
*dev
);
1220 int pci_msi_enabled(void);
1223 #ifdef CONFIG_PCIEPORTBUS
1224 extern bool pcie_ports_disabled
;
1225 extern bool pcie_ports_auto
;
1227 #define pcie_ports_disabled true
1228 #define pcie_ports_auto false
1231 #ifndef CONFIG_PCIEASPM
1232 static inline int pcie_aspm_enabled(void) { return 0; }
1233 static inline bool pcie_aspm_support_enabled(void) { return false; }
1235 int pcie_aspm_enabled(void);
1236 bool pcie_aspm_support_enabled(void);
1239 #ifdef CONFIG_PCIEAER
1240 void pci_no_aer(void);
1241 bool pci_aer_available(void);
1243 static inline void pci_no_aer(void) { }
1244 static inline bool pci_aer_available(void) { return false; }
1247 #ifndef CONFIG_PCIE_ECRC
1248 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
)
1252 static inline void pcie_ecrc_get_policy(char *str
) {};
1254 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1255 void pcie_ecrc_get_policy(char *str
);
1258 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1260 #ifdef CONFIG_HT_IRQ
1261 /* The functions a driver should call */
1262 int ht_create_irq(struct pci_dev
*dev
, int idx
);
1263 void ht_destroy_irq(unsigned int irq
);
1264 #endif /* CONFIG_HT_IRQ */
1266 void pci_cfg_access_lock(struct pci_dev
*dev
);
1267 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1268 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1271 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1272 * a PCI domain is defined to be a set of PCI buses which share
1273 * configuration space.
1275 #ifdef CONFIG_PCI_DOMAINS
1276 extern int pci_domains_supported
;
1278 enum { pci_domains_supported
= 0 };
1279 static inline int pci_domain_nr(struct pci_bus
*bus
)
1284 static inline int pci_proc_domain(struct pci_bus
*bus
)
1288 #endif /* CONFIG_PCI_DOMAINS */
1290 /* some architectures require additional setup to direct VGA traffic */
1291 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1292 unsigned int command_bits
, u32 flags
);
1293 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1295 #else /* CONFIG_PCI is not enabled */
1298 * If the system does not have PCI, clearly these return errors. Define
1299 * these as simple inline functions to avoid hair in drivers.
1302 #define _PCI_NOP(o, s, t) \
1303 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1305 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1307 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1308 _PCI_NOP(o, word, u16 x) \
1309 _PCI_NOP(o, dword, u32 x)
1310 _PCI_NOP_ALL(read
, *)
1311 _PCI_NOP_ALL(write
,)
1313 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1314 unsigned int device
,
1315 struct pci_dev
*from
)
1320 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1321 unsigned int device
,
1322 unsigned int ss_vendor
,
1323 unsigned int ss_device
,
1324 struct pci_dev
*from
)
1329 static inline struct pci_dev
*pci_get_class(unsigned int class,
1330 struct pci_dev
*from
)
1335 #define pci_dev_present(ids) (0)
1336 #define no_pci_devices() (1)
1337 #define pci_dev_put(dev) do { } while (0)
1339 static inline void pci_set_master(struct pci_dev
*dev
)
1342 static inline int pci_enable_device(struct pci_dev
*dev
)
1347 static inline void pci_disable_device(struct pci_dev
*dev
)
1350 static inline int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1355 static inline int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1360 static inline int pci_set_dma_max_seg_size(struct pci_dev
*dev
,
1366 static inline int pci_set_dma_seg_boundary(struct pci_dev
*dev
,
1372 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1377 static inline int __pci_register_driver(struct pci_driver
*drv
,
1378 struct module
*owner
)
1383 static inline int pci_register_driver(struct pci_driver
*drv
)
1388 static inline void pci_unregister_driver(struct pci_driver
*drv
)
1391 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1396 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1402 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1407 /* Power management related routines */
1408 static inline int pci_save_state(struct pci_dev
*dev
)
1413 static inline void pci_restore_state(struct pci_dev
*dev
)
1416 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1421 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1426 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1432 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1438 static inline void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
)
1442 static inline void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
)
1446 static inline int pci_enable_obff(struct pci_dev
*dev
, unsigned long type
)
1451 static inline void pci_disable_obff(struct pci_dev
*dev
)
1455 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1460 static inline void pci_release_regions(struct pci_dev
*dev
)
1463 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1465 static inline void pci_block_cfg_access(struct pci_dev
*dev
)
1468 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1471 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
)
1474 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1477 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1481 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1485 static inline int pci_domain_nr(struct pci_bus
*bus
)
1488 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
)
1491 #define dev_is_pci(d) (false)
1492 #define dev_is_pf(d) (false)
1493 #define dev_num_vf(d) (0)
1494 #endif /* CONFIG_PCI */
1496 /* Include architecture-dependent settings and functions */
1498 #include <asm/pci.h>
1500 #ifndef PCIBIOS_MAX_MEM_32
1501 #define PCIBIOS_MAX_MEM_32 (-1)
1504 /* these helpers provide future and backwards compatibility
1505 * for accessing popular PCI BAR info */
1506 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1507 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1508 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1509 #define pci_resource_len(dev,bar) \
1510 ((pci_resource_start((dev), (bar)) == 0 && \
1511 pci_resource_end((dev), (bar)) == \
1512 pci_resource_start((dev), (bar))) ? 0 : \
1514 (pci_resource_end((dev), (bar)) - \
1515 pci_resource_start((dev), (bar)) + 1))
1517 /* Similar to the helpers above, these manipulate per-pci_dev
1518 * driver-specific data. They are really just a wrapper around
1519 * the generic device structure functions of these calls.
1521 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1523 return dev_get_drvdata(&pdev
->dev
);
1526 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1528 dev_set_drvdata(&pdev
->dev
, data
);
1531 /* If you want to know what to call your pci_dev, ask this function.
1532 * Again, it's a wrapper around the generic device.
1534 static inline const char *pci_name(const struct pci_dev
*pdev
)
1536 return dev_name(&pdev
->dev
);
1540 /* Some archs don't want to expose struct resource to userland as-is
1541 * in sysfs and /proc
1543 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1544 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1545 const struct resource
*rsrc
, resource_size_t
*start
,
1546 resource_size_t
*end
)
1548 *start
= rsrc
->start
;
1551 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1555 * The world is not perfect and supplies us with broken PCI devices.
1556 * For at least a part of these bugs we need a work-around, so both
1557 * generic (drivers/pci/quirks.c) and per-architecture code can define
1558 * fixup hooks to be called for particular buggy devices.
1562 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1563 u16 device
; /* You can use PCI_ANY_ID here of course */
1564 u32
class; /* You can use PCI_ANY_ID here too */
1565 unsigned int class_shift
; /* should be 0, 8, 16 */
1566 void (*hook
)(struct pci_dev
*dev
);
1569 enum pci_fixup_pass
{
1570 pci_fixup_early
, /* Before probing BARs */
1571 pci_fixup_header
, /* After reading configuration header */
1572 pci_fixup_final
, /* Final phase of device fixups */
1573 pci_fixup_enable
, /* pci_enable_device() time */
1574 pci_fixup_resume
, /* pci_device_resume() */
1575 pci_fixup_suspend
, /* pci_device_suspend */
1576 pci_fixup_resume_early
, /* pci_device_resume_early() */
1579 /* Anonymous variables would be nice... */
1580 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1581 class_shift, hook) \
1582 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1583 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1584 = { vendor, device, class, class_shift, hook };
1586 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1587 class_shift, hook) \
1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1589 hook, vendor, device, class, class_shift, hook)
1590 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1591 class_shift, hook) \
1592 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1593 hook, vendor, device, class, class_shift, hook)
1594 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1595 class_shift, hook) \
1596 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1597 hook, vendor, device, class, class_shift, hook)
1598 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1599 class_shift, hook) \
1600 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1601 hook, vendor, device, class, class_shift, hook)
1602 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1603 class_shift, hook) \
1604 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1605 resume##hook, vendor, device, class, \
1607 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1608 class_shift, hook) \
1609 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1610 resume_early##hook, vendor, device, \
1611 class, class_shift, hook)
1612 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1613 class_shift, hook) \
1614 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1615 suspend##hook, vendor, device, class, \
1618 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1620 hook, vendor, device, PCI_ANY_ID, 0, hook)
1621 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1622 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1623 hook, vendor, device, PCI_ANY_ID, 0, hook)
1624 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1626 hook, vendor, device, PCI_ANY_ID, 0, hook)
1627 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1628 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1629 hook, vendor, device, PCI_ANY_ID, 0, hook)
1630 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1631 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1632 resume##hook, vendor, device, \
1633 PCI_ANY_ID, 0, hook)
1634 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1635 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1636 resume_early##hook, vendor, device, \
1637 PCI_ANY_ID, 0, hook)
1638 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1639 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1640 suspend##hook, vendor, device, \
1641 PCI_ANY_ID, 0, hook)
1643 #ifdef CONFIG_PCI_QUIRKS
1644 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1645 struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
);
1646 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1648 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1649 struct pci_dev
*dev
) {}
1650 static inline struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
)
1652 return pci_dev_get(dev
);
1654 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1661 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1662 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1663 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1664 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1665 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1667 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1669 extern int pci_pci_problems
;
1670 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1671 #define PCIPCI_TRITON 2
1672 #define PCIPCI_NATOMA 4
1673 #define PCIPCI_VIAETBF 8
1674 #define PCIPCI_VSFX 16
1675 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1676 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1678 extern unsigned long pci_cardbus_io_size
;
1679 extern unsigned long pci_cardbus_mem_size
;
1680 extern u8 pci_dfl_cache_line_size
;
1681 extern u8 pci_cache_line_size
;
1683 extern unsigned long pci_hotplug_io_size
;
1684 extern unsigned long pci_hotplug_mem_size
;
1686 /* Architecture-specific versions may override these (weak) */
1687 int pcibios_add_platform_entries(struct pci_dev
*dev
);
1688 void pcibios_disable_device(struct pci_dev
*dev
);
1689 void pcibios_set_master(struct pci_dev
*dev
);
1690 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1691 enum pcie_reset_state state
);
1692 int pcibios_add_device(struct pci_dev
*dev
);
1693 void pcibios_release_device(struct pci_dev
*dev
);
1695 #ifdef CONFIG_HIBERNATE_CALLBACKS
1696 extern struct dev_pm_ops pcibios_pm_ops
;
1699 #ifdef CONFIG_PCI_MMCONFIG
1700 void __init
pci_mmcfg_early_init(void);
1701 void __init
pci_mmcfg_late_init(void);
1703 static inline void pci_mmcfg_early_init(void) { }
1704 static inline void pci_mmcfg_late_init(void) { }
1707 int pci_ext_cfg_avail(void);
1709 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1711 #ifdef CONFIG_PCI_IOV
1712 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1713 void pci_disable_sriov(struct pci_dev
*dev
);
1714 irqreturn_t
pci_sriov_migration(struct pci_dev
*dev
);
1715 int pci_num_vf(struct pci_dev
*dev
);
1716 int pci_vfs_assigned(struct pci_dev
*dev
);
1717 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1718 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1720 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1724 static inline void pci_disable_sriov(struct pci_dev
*dev
)
1727 static inline irqreturn_t
pci_sriov_migration(struct pci_dev
*dev
)
1731 static inline int pci_num_vf(struct pci_dev
*dev
)
1735 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1739 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1743 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1749 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1750 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
1751 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
1755 * pci_pcie_cap - get the saved PCIe capability offset
1758 * PCIe capability offset is calculated at PCI device initialization
1759 * time and saved in the data structure. This function returns saved
1760 * PCIe capability offset. Using this instead of pci_find_capability()
1761 * reduces unnecessary search in the PCI configuration space. If you
1762 * need to calculate PCIe capability offset from raw device for some
1763 * reasons, please use pci_find_capability() instead.
1765 static inline int pci_pcie_cap(struct pci_dev
*dev
)
1767 return dev
->pcie_cap
;
1771 * pci_is_pcie - check if the PCI device is PCI Express capable
1774 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1776 static inline bool pci_is_pcie(struct pci_dev
*dev
)
1778 return pci_pcie_cap(dev
);
1782 * pcie_caps_reg - get the PCIe Capabilities Register
1785 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
1787 return dev
->pcie_flags_reg
;
1791 * pci_pcie_type - get the PCIe device/port type
1794 static inline int pci_pcie_type(const struct pci_dev
*dev
)
1796 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
1799 void pci_request_acs(void);
1800 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
1801 bool pci_acs_path_enabled(struct pci_dev
*start
,
1802 struct pci_dev
*end
, u16 acs_flags
);
1804 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1805 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1807 /* Large Resource Data Type Tag Item Names */
1808 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1809 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1810 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1812 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1813 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1814 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1816 /* Small Resource Data Type Tag Item Names */
1817 #define PCI_VPD_STIN_END 0x78 /* End */
1819 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1821 #define PCI_VPD_SRDT_TIN_MASK 0x78
1822 #define PCI_VPD_SRDT_LEN_MASK 0x07
1824 #define PCI_VPD_LRDT_TAG_SIZE 3
1825 #define PCI_VPD_SRDT_TAG_SIZE 1
1827 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1829 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1830 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1831 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1832 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1835 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1836 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1838 * Returns the extracted Large Resource Data Type length.
1840 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
1842 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
1846 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1847 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1849 * Returns the extracted Small Resource Data Type length.
1851 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
1853 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
1857 * pci_vpd_info_field_size - Extracts the information field length
1858 * @lrdt: Pointer to the beginning of an information field header
1860 * Returns the extracted information field length.
1862 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
1864 return info_field
[2];
1868 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1869 * @buf: Pointer to buffered vpd data
1870 * @off: The offset into the buffer at which to begin the search
1871 * @len: The length of the vpd buffer
1872 * @rdt: The Resource Data Type to search for
1874 * Returns the index where the Resource Data Type was found or
1875 * -ENOENT otherwise.
1877 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
1880 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1881 * @buf: Pointer to buffered vpd data
1882 * @off: The offset into the buffer at which to begin the search
1883 * @len: The length of the buffer area, relative to off, in which to search
1884 * @kw: The keyword to search for
1886 * Returns the index where the information field keyword was found or
1887 * -ENOENT otherwise.
1889 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
1890 unsigned int len
, const char *kw
);
1892 /* PCI <-> OF binding helpers */
1895 void pci_set_of_node(struct pci_dev
*dev
);
1896 void pci_release_of_node(struct pci_dev
*dev
);
1897 void pci_set_bus_of_node(struct pci_bus
*bus
);
1898 void pci_release_bus_of_node(struct pci_bus
*bus
);
1900 /* Arch may override this (weak) */
1901 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
1903 static inline struct device_node
*
1904 pci_device_to_OF_node(const struct pci_dev
*pdev
)
1906 return pdev
? pdev
->dev
.of_node
: NULL
;
1909 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
1911 return bus
? bus
->dev
.of_node
: NULL
;
1914 #else /* CONFIG_OF */
1915 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
1916 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
1917 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
1918 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
1919 #endif /* CONFIG_OF */
1922 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
1924 return pdev
->dev
.archdata
.edev
;
1929 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1930 * @pdev: the PCI device
1932 * if the device is PCIE, return NULL
1933 * if the device isn't connected to a PCIe bridge (that is its parent is a
1934 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1937 struct pci_dev
*pci_find_upstream_pcie_bridge(struct pci_dev
*pdev
);
1939 #endif /* LINUX_PCI_H */