4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus
*bus
; /* The bus this slot is on */
56 struct list_head list
; /* node in list of slots on this bus */
57 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
58 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
64 return kobject_name(&slot
->kobj
);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END
= 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
101 PCI_BRIDGE_RESOURCE_NUM
- 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
110 typedef int __bitwise pci_power_t
;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names
[];
123 static inline const char *pci_power_name(pci_power_t state
)
125 return pci_power_names
[1 + (int) state
];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t
;
139 enum pci_channel_state
{
140 /* I/O channel is in normal state */
141 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t
;
152 enum pcie_reset_state
{
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
163 typedef unsigned short __bitwise pci_dev_flags_t
;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) 1,
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) 2,
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) 4,
175 enum pci_irq_reroute_variant
{
176 INTEL_IRQ_REROUTE_VARIANT
= 1,
177 MAX_IRQ_REROUTE_VARIANTS
= 3
180 typedef unsigned short __bitwise pci_bus_flags_t
;
182 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
183 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
186 /* These values come from the PCI Express Spec */
187 enum pcie_link_width
{
188 PCIE_LNK_WIDTH_RESRV
= 0x00,
196 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
199 /* Based on the PCI Hotplug Spec, but some values are made up by us */
201 PCI_SPEED_33MHz
= 0x00,
202 PCI_SPEED_66MHz
= 0x01,
203 PCI_SPEED_66MHz_PCIX
= 0x02,
204 PCI_SPEED_100MHz_PCIX
= 0x03,
205 PCI_SPEED_133MHz_PCIX
= 0x04,
206 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
207 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
208 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
209 PCI_SPEED_66MHz_PCIX_266
= 0x09,
210 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
211 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
217 PCI_SPEED_66MHz_PCIX_533
= 0x11,
218 PCI_SPEED_100MHz_PCIX_533
= 0x12,
219 PCI_SPEED_133MHz_PCIX_533
= 0x13,
220 PCIE_SPEED_2_5GT
= 0x14,
221 PCIE_SPEED_5_0GT
= 0x15,
222 PCIE_SPEED_8_0GT
= 0x16,
223 PCI_SPEED_UNKNOWN
= 0xff,
226 struct pci_cap_saved_data
{
233 struct pci_cap_saved_state
{
234 struct hlist_node next
;
235 struct pci_cap_saved_data cap
;
238 struct pcie_link_state
;
244 * The pci_dev structure is used to describe PCI devices.
247 struct list_head bus_list
; /* node in per-bus list */
248 struct pci_bus
*bus
; /* bus this device is on */
249 struct pci_bus
*subordinate
; /* bus this device bridges to */
251 void *sysdata
; /* hook for sys-specific extension */
252 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
253 struct pci_slot
*slot
; /* Physical slot this device is in */
255 unsigned int devfn
; /* encoded device & function index */
256 unsigned short vendor
;
257 unsigned short device
;
258 unsigned short subsystem_vendor
;
259 unsigned short subsystem_device
;
260 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
261 u8 revision
; /* PCI revision, low byte of class word */
262 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
263 u8 pcie_cap
; /* PCIe capability offset */
264 u8 msi_cap
; /* MSI capability offset */
265 u8 msix_cap
; /* MSI-X capability offset */
266 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
267 u8 rom_base_reg
; /* which config register controls the ROM */
268 u8 pin
; /* which interrupt pin this device uses */
269 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
271 struct pci_driver
*driver
; /* which driver has allocated this device */
272 u64 dma_mask
; /* Mask of the bits of bus address this
273 device implements. Normally this is
274 0xffffffff. You only need to change
275 this if your device has broken DMA
276 or supports 64-bit transfers. */
278 struct device_dma_parameters dma_parms
;
280 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
281 this is D0-D3, D0 being fully functional,
283 u8 pm_cap
; /* PM capability offset */
284 unsigned int pme_support
:5; /* Bitmask of states from which PME#
286 unsigned int pme_interrupt
:1;
287 unsigned int pme_poll
:1; /* Poll device's PME status bit */
288 unsigned int d1_support
:1; /* Low power state D1 is supported */
289 unsigned int d2_support
:1; /* Low power state D2 is supported */
290 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
291 unsigned int no_d3cold
:1; /* D3cold is forbidden */
292 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
293 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
294 decoding during bar sizing */
295 unsigned int wakeup_prepared
:1;
296 unsigned int runtime_d3cold
:1; /* whether go through runtime
297 D3cold, not set for devices
298 powered on/off by the
299 corresponding bridge */
300 unsigned int d3_delay
; /* D3->D0 transition time in ms */
301 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
303 #ifdef CONFIG_PCIEASPM
304 struct pcie_link_state
*link_state
; /* ASPM link state */
307 pci_channel_state_t error_state
; /* current connectivity state */
308 struct device dev
; /* Generic device interface */
310 int cfg_size
; /* Size of configuration space */
313 * Instead of touching interrupt line and base address registers
314 * directly, use the values stored here. They might be different!
317 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
319 bool match_driver
; /* Skip attaching driver */
320 /* These fields are used by common fixups */
321 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
322 unsigned int multifunction
:1;/* Part of multi-function device */
323 /* keep track of device state */
324 unsigned int is_added
:1;
325 unsigned int is_busmaster
:1; /* device is busmaster */
326 unsigned int no_msi
:1; /* device may not use msi */
327 unsigned int block_cfg_access
:1; /* config space access is blocked */
328 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
329 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
330 unsigned int msi_enabled
:1;
331 unsigned int msix_enabled
:1;
332 unsigned int ari_enabled
:1; /* ARI forwarding */
333 unsigned int is_managed
:1;
334 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
335 unsigned int state_saved
:1;
336 unsigned int is_physfn
:1;
337 unsigned int is_virtfn
:1;
338 unsigned int reset_fn
:1;
339 unsigned int is_hotplug_bridge
:1;
340 unsigned int __aer_firmware_first_valid
:1;
341 unsigned int __aer_firmware_first
:1;
342 unsigned int broken_intx_masking
:1;
343 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
344 pci_dev_flags_t dev_flags
;
345 atomic_t enable_cnt
; /* pci_enable_device has been called */
347 u32 saved_config_space
[16]; /* config space saved at suspend time */
348 struct hlist_head saved_cap_space
;
349 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
350 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
351 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
352 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
353 #ifdef CONFIG_PCI_MSI
354 struct list_head msi_list
;
355 const struct attribute_group
**msi_irq_groups
;
358 #ifdef CONFIG_PCI_ATS
360 struct pci_sriov
*sriov
; /* SR-IOV capability related */
361 struct pci_dev
*physfn
; /* the PF this VF is associated with */
363 struct pci_ats
*ats
; /* Address Translation Service */
365 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
366 size_t romlen
; /* Length of ROM if it's not from the BAR */
369 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
371 #ifdef CONFIG_PCI_IOV
378 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
380 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
381 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
383 static inline int pci_channel_offline(struct pci_dev
*pdev
)
385 return (pdev
->error_state
!= pci_channel_io_normal
);
388 struct pci_host_bridge_window
{
389 struct list_head list
;
390 struct resource
*res
; /* host bridge aperture (CPU address) */
391 resource_size_t offset
; /* bus address + offset = CPU address */
394 struct pci_host_bridge
{
396 struct pci_bus
*bus
; /* root bus */
397 struct list_head windows
; /* pci_host_bridge_windows */
398 void (*release_fn
)(struct pci_host_bridge
*);
402 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
403 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
404 void (*release_fn
)(struct pci_host_bridge
*),
407 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
410 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
411 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
412 * buses below host bridges or subtractive decode bridges) go in the list.
413 * Use pci_bus_for_each_resource() to iterate through all the resources.
417 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
418 * and there's no way to program the bridge with the details of the window.
419 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
420 * decode bit set, because they are explicit and can be programmed with _SRS.
422 #define PCI_SUBTRACTIVE_DECODE 0x1
424 struct pci_bus_resource
{
425 struct list_head list
;
426 struct resource
*res
;
430 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
433 struct list_head node
; /* node in list of buses */
434 struct pci_bus
*parent
; /* parent bus this bridge is on */
435 struct list_head children
; /* list of child buses */
436 struct list_head devices
; /* list of devices on this bus */
437 struct pci_dev
*self
; /* bridge device as seen by parent */
438 struct list_head slots
; /* list of slots on this bus */
439 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
440 struct list_head resources
; /* address space routed to this bus */
441 struct resource busn_res
; /* bus numbers routed to this bus */
443 struct pci_ops
*ops
; /* configuration access functions */
444 struct msi_chip
*msi
; /* MSI controller */
445 void *sysdata
; /* hook for sys-specific extension */
446 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
448 unsigned char number
; /* bus number */
449 unsigned char primary
; /* number of primary bridge */
450 unsigned char max_bus_speed
; /* enum pci_bus_speed */
451 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
455 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
456 pci_bus_flags_t bus_flags
; /* inherited by child buses */
457 struct device
*bridge
;
459 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
460 struct bin_attribute
*legacy_mem
; /* legacy mem */
461 unsigned int is_added
:1;
464 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
465 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
468 * Returns true if the PCI bus is root (behind host-PCI bridge),
471 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
472 * This is incorrect because "virtual" buses added for SR-IOV (via
473 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
475 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
477 return !(pbus
->parent
);
480 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
482 dev
= pci_physfn(dev
);
483 if (pci_is_root_bus(dev
->bus
))
486 return dev
->bus
->self
;
489 #ifdef CONFIG_PCI_MSI
490 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
492 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
495 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
499 * Error values that may be returned by PCI functions.
501 #define PCIBIOS_SUCCESSFUL 0x00
502 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
503 #define PCIBIOS_BAD_VENDOR_ID 0x83
504 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
505 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
506 #define PCIBIOS_SET_FAILED 0x88
507 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
510 * Translate above to generic errno for passing back through non-PCI code.
512 static inline int pcibios_err_to_errno(int err
)
514 if (err
<= PCIBIOS_SUCCESSFUL
)
515 return err
; /* Assume already errno */
518 case PCIBIOS_FUNC_NOT_SUPPORTED
:
520 case PCIBIOS_BAD_VENDOR_ID
:
522 case PCIBIOS_DEVICE_NOT_FOUND
:
524 case PCIBIOS_BAD_REGISTER_NUMBER
:
526 case PCIBIOS_SET_FAILED
:
528 case PCIBIOS_BUFFER_TOO_SMALL
:
535 /* Low-level architecture-dependent routines */
538 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
539 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
543 * ACPI needs to be able to access PCI config space before we've done a
544 * PCI bus scan and created pci_bus structures.
546 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
547 int reg
, int len
, u32
*val
);
548 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
549 int reg
, int len
, u32 val
);
551 struct pci_bus_region
{
557 spinlock_t lock
; /* protects list, index */
558 struct list_head list
; /* for IDs added at runtime */
563 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
564 * a set of callbacks in struct pci_error_handlers, that device driver
565 * will be notified of PCI bus errors, and will be driven to recovery
566 * when an error occurs.
569 typedef unsigned int __bitwise pci_ers_result_t
;
571 enum pci_ers_result
{
572 /* no result/none/not supported in device driver */
573 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
575 /* Device driver can recover without slot reset */
576 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
578 /* Device driver wants slot to be reset. */
579 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
581 /* Device has completely failed, is unrecoverable */
582 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
584 /* Device driver is fully recovered and operational */
585 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
587 /* No AER capabilities registered for the driver */
588 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
591 /* PCI bus error event callbacks */
592 struct pci_error_handlers
{
593 /* PCI bus error detected on this device */
594 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
595 enum pci_channel_state error
);
597 /* MMIO has been re-enabled, but not DMA */
598 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
600 /* PCI Express link has been reset */
601 pci_ers_result_t (*link_reset
)(struct pci_dev
*dev
);
603 /* PCI slot has been reset */
604 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
606 /* Device driver may resume normal operations */
607 void (*resume
)(struct pci_dev
*dev
);
613 struct list_head node
;
615 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
616 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
617 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
618 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
619 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
620 int (*resume_early
) (struct pci_dev
*dev
);
621 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
622 void (*shutdown
) (struct pci_dev
*dev
);
623 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
624 const struct pci_error_handlers
*err_handler
;
625 struct device_driver driver
;
626 struct pci_dynids dynids
;
629 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
632 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
633 * @_table: device table name
635 * This macro is deprecated and should not be used in new code.
637 #define DEFINE_PCI_DEVICE_TABLE(_table) \
638 const struct pci_device_id _table[]
641 * PCI_DEVICE - macro used to describe a specific pci device
642 * @vend: the 16 bit PCI Vendor ID
643 * @dev: the 16 bit PCI Device ID
645 * This macro is used to create a struct pci_device_id that matches a
646 * specific device. The subvendor and subdevice fields will be set to
649 #define PCI_DEVICE(vend,dev) \
650 .vendor = (vend), .device = (dev), \
651 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
654 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
655 * @vend: the 16 bit PCI Vendor ID
656 * @dev: the 16 bit PCI Device ID
657 * @subvend: the 16 bit PCI Subvendor ID
658 * @subdev: the 16 bit PCI Subdevice ID
660 * This macro is used to create a struct pci_device_id that matches a
661 * specific device with subsystem information.
663 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
664 .vendor = (vend), .device = (dev), \
665 .subvendor = (subvend), .subdevice = (subdev)
668 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
669 * @dev_class: the class, subclass, prog-if triple for this device
670 * @dev_class_mask: the class mask for this device
672 * This macro is used to create a struct pci_device_id that matches a
673 * specific PCI class. The vendor, device, subvendor, and subdevice
674 * fields will be set to PCI_ANY_ID.
676 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
677 .class = (dev_class), .class_mask = (dev_class_mask), \
678 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
679 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
682 * PCI_VDEVICE - macro used to describe a specific pci device in short form
683 * @vendor: the vendor name
684 * @device: the 16 bit PCI Device ID
686 * This macro is used to create a struct pci_device_id that matches a
687 * specific PCI device. The subvendor, and subdevice fields will be set
688 * to PCI_ANY_ID. The macro allows the next field to follow as the device
692 #define PCI_VDEVICE(vendor, device) \
693 PCI_VENDOR_ID_##vendor, (device), \
694 PCI_ANY_ID, PCI_ANY_ID, 0, 0
696 /* these external functions are only available when PCI support is enabled */
699 void pcie_bus_configure_settings(struct pci_bus
*bus
);
701 enum pcie_bus_config_types
{
704 PCIE_BUS_PERFORMANCE
,
708 extern enum pcie_bus_config_types pcie_bus_config
;
710 extern struct bus_type pci_bus_type
;
712 /* Do NOT directly access these two variables, unless you are arch-specific PCI
713 * code, or PCI core code. */
714 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
715 /* Some device drivers need know if PCI is initiated */
716 int no_pci_devices(void);
718 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
719 void pcibios_add_bus(struct pci_bus
*bus
);
720 void pcibios_remove_bus(struct pci_bus
*bus
);
721 void pcibios_fixup_bus(struct pci_bus
*);
722 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
723 /* Architecture-specific versions may override this (weak) */
724 char *pcibios_setup(char *str
);
726 /* Used only when drivers/pci/setup.c is used */
727 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
730 void pcibios_update_irq(struct pci_dev
*, int irq
);
732 /* Weak but can be overriden by arch */
733 void pci_fixup_cardbus(struct pci_bus
*);
735 /* Generic PCI functions used internally */
737 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
738 struct resource
*res
);
739 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
740 struct pci_bus_region
*region
);
741 void pcibios_scan_specific_bus(int busn
);
742 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
743 void pci_bus_add_devices(const struct pci_bus
*bus
);
744 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
, int bus
,
745 struct pci_ops
*ops
, void *sysdata
);
746 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
747 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
748 struct pci_ops
*ops
, void *sysdata
,
749 struct list_head
*resources
);
750 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
751 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
752 void pci_bus_release_busn_res(struct pci_bus
*b
);
753 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
754 struct pci_ops
*ops
, void *sysdata
,
755 struct list_head
*resources
);
756 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
758 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
759 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
761 struct hotplug_slot
*hotplug
);
762 void pci_destroy_slot(struct pci_slot
*slot
);
763 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
764 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
765 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
766 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
767 int __must_check
pci_bus_add_device(struct pci_dev
*dev
);
768 void pci_read_bridge_bases(struct pci_bus
*child
);
769 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
770 struct resource
*res
);
771 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
772 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
773 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
774 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
775 void pci_dev_put(struct pci_dev
*dev
);
776 void pci_remove_bus(struct pci_bus
*b
);
777 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
778 void pci_stop_root_bus(struct pci_bus
*bus
);
779 void pci_remove_root_bus(struct pci_bus
*bus
);
780 void pci_setup_cardbus(struct pci_bus
*bus
);
781 void pci_sort_breadthfirst(void);
782 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
783 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
784 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
786 /* Generic PCI functions exported to card drivers */
788 enum pci_lost_interrupt_reason
{
789 PCI_LOST_IRQ_NO_INFORMATION
= 0,
790 PCI_LOST_IRQ_DISABLE_MSI
,
791 PCI_LOST_IRQ_DISABLE_MSIX
,
792 PCI_LOST_IRQ_DISABLE_ACPI
,
794 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
795 int pci_find_capability(struct pci_dev
*dev
, int cap
);
796 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
797 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
798 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
799 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
800 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
801 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
803 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
804 struct pci_dev
*from
);
805 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
806 unsigned int ss_vendor
, unsigned int ss_device
,
807 struct pci_dev
*from
);
808 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
809 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
811 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
814 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
816 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
817 int pci_dev_present(const struct pci_device_id
*ids
);
819 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
821 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
822 int where
, u16
*val
);
823 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
824 int where
, u32
*val
);
825 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
827 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
829 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
831 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
833 static inline int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
)
835 return pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
837 static inline int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
)
839 return pci_bus_read_config_word(dev
->bus
, dev
->devfn
, where
, val
);
841 static inline int pci_read_config_dword(const struct pci_dev
*dev
, int where
,
844 return pci_bus_read_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
846 static inline int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
)
848 return pci_bus_write_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
850 static inline int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
)
852 return pci_bus_write_config_word(dev
->bus
, dev
->devfn
, where
, val
);
854 static inline int pci_write_config_dword(const struct pci_dev
*dev
, int where
,
857 return pci_bus_write_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
860 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
861 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
862 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
863 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
864 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
866 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
869 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
872 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
875 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
878 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
881 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
884 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
887 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
890 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
893 /* user-space driven config access */
894 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
895 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
896 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
897 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
898 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
899 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
901 int __must_check
pci_enable_device(struct pci_dev
*dev
);
902 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
903 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
904 int __must_check
pci_reenable_device(struct pci_dev
*);
905 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
906 void pcim_pin_device(struct pci_dev
*pdev
);
908 static inline int pci_is_enabled(struct pci_dev
*pdev
)
910 return (atomic_read(&pdev
->enable_cnt
) > 0);
913 static inline int pci_is_managed(struct pci_dev
*pdev
)
915 return pdev
->is_managed
;
918 void pci_disable_device(struct pci_dev
*dev
);
920 extern unsigned int pcibios_max_latency
;
921 void pci_set_master(struct pci_dev
*dev
);
922 void pci_clear_master(struct pci_dev
*dev
);
924 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
925 int pci_set_cacheline_size(struct pci_dev
*dev
);
926 #define HAVE_PCI_SET_MWI
927 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
928 int pci_try_set_mwi(struct pci_dev
*dev
);
929 void pci_clear_mwi(struct pci_dev
*dev
);
930 void pci_intx(struct pci_dev
*dev
, int enable
);
931 bool pci_intx_mask_supported(struct pci_dev
*dev
);
932 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
933 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
934 void pci_msi_off(struct pci_dev
*dev
);
935 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
);
936 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
);
937 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
938 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
939 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
940 int pcix_get_mmrbc(struct pci_dev
*dev
);
941 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
942 int pcie_get_readrq(struct pci_dev
*dev
);
943 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
944 int pcie_get_mps(struct pci_dev
*dev
);
945 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
946 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
947 enum pcie_link_width
*width
);
948 int __pci_reset_function(struct pci_dev
*dev
);
949 int __pci_reset_function_locked(struct pci_dev
*dev
);
950 int pci_reset_function(struct pci_dev
*dev
);
951 int pci_probe_reset_slot(struct pci_slot
*slot
);
952 int pci_reset_slot(struct pci_slot
*slot
);
953 int pci_probe_reset_bus(struct pci_bus
*bus
);
954 int pci_reset_bus(struct pci_bus
*bus
);
955 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
956 void pci_update_resource(struct pci_dev
*dev
, int resno
);
957 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
958 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
959 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
961 /* ROM control related routines */
962 int pci_enable_rom(struct pci_dev
*pdev
);
963 void pci_disable_rom(struct pci_dev
*pdev
);
964 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
965 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
966 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
967 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
969 /* Power management related routines */
970 int pci_save_state(struct pci_dev
*dev
);
971 void pci_restore_state(struct pci_dev
*dev
);
972 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
973 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
974 struct pci_saved_state
**state
);
975 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
976 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
978 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
979 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
980 u16 cap
, unsigned int size
);
981 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
982 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
983 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
984 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
985 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
986 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
987 bool runtime
, bool enable
);
988 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
989 int pci_prepare_to_sleep(struct pci_dev
*dev
);
990 int pci_back_from_sleep(struct pci_dev
*dev
);
991 bool pci_dev_run_wake(struct pci_dev
*dev
);
992 bool pci_check_pme_status(struct pci_dev
*dev
);
993 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
995 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
998 return __pci_enable_wake(dev
, state
, false, enable
);
1001 /* PCI Virtual Channel */
1002 int pci_save_vc_state(struct pci_dev
*dev
);
1003 void pci_restore_vc_state(struct pci_dev
*dev
);
1004 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1006 /* For use by arch with custom probe code */
1007 void set_pcie_port_type(struct pci_dev
*pdev
);
1008 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1010 /* Functions for PCI Hotplug drivers to use */
1011 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1012 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1013 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1015 /* Vital product data routines */
1016 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1017 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1019 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1020 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1021 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1022 void pci_bus_size_bridges(struct pci_bus
*bus
);
1023 int pci_claim_resource(struct pci_dev
*, int);
1024 void pci_assign_unassigned_resources(void);
1025 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1026 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1027 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1028 void pdev_enable_device(struct pci_dev
*);
1029 int pci_enable_resources(struct pci_dev
*, int mask
);
1030 void pci_fixup_irqs(u8 (*)(struct pci_dev
*, u8
*),
1031 int (*)(const struct pci_dev
*, u8
, u8
));
1032 #define HAVE_PCI_REQ_REGIONS 2
1033 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1034 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1035 void pci_release_regions(struct pci_dev
*);
1036 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1037 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1038 void pci_release_region(struct pci_dev
*, int);
1039 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1040 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1041 void pci_release_selected_regions(struct pci_dev
*, int);
1043 /* drivers/pci/bus.c */
1044 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1045 void pci_bus_put(struct pci_bus
*bus
);
1046 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1047 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1048 resource_size_t offset
);
1049 void pci_free_resource_list(struct list_head
*resources
);
1050 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
, unsigned int flags
);
1051 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1052 void pci_bus_remove_resources(struct pci_bus
*bus
);
1054 #define pci_bus_for_each_resource(bus, res, i) \
1056 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1059 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1060 struct resource
*res
, resource_size_t size
,
1061 resource_size_t align
, resource_size_t min
,
1062 unsigned int type_mask
,
1063 resource_size_t (*alignf
)(void *,
1064 const struct resource
*,
1069 static inline dma_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1071 struct pci_bus_region region
;
1073 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1074 return region
.start
;
1077 /* Proper probing supporting hot-pluggable devices */
1078 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1079 const char *mod_name
);
1082 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1084 #define pci_register_driver(driver) \
1085 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1087 void pci_unregister_driver(struct pci_driver
*dev
);
1090 * module_pci_driver() - Helper macro for registering a PCI driver
1091 * @__pci_driver: pci_driver struct
1093 * Helper macro for PCI drivers which do not do anything special in module
1094 * init/exit. This eliminates a lot of boilerplate. Each module may only
1095 * use this macro once, and calling it replaces module_init() and module_exit()
1097 #define module_pci_driver(__pci_driver) \
1098 module_driver(__pci_driver, pci_register_driver, \
1099 pci_unregister_driver)
1101 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1102 int pci_add_dynid(struct pci_driver
*drv
,
1103 unsigned int vendor
, unsigned int device
,
1104 unsigned int subvendor
, unsigned int subdevice
,
1105 unsigned int class, unsigned int class_mask
,
1106 unsigned long driver_data
);
1107 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1108 struct pci_dev
*dev
);
1109 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1112 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1114 int pci_cfg_space_size(struct pci_dev
*dev
);
1115 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1116 void pci_setup_bridge(struct pci_bus
*bus
);
1117 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1118 unsigned long type
);
1120 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1121 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1123 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1124 unsigned int command_bits
, u32 flags
);
1125 /* kmem_cache style wrapper around pci_alloc_consistent() */
1127 #include <linux/pci-dma.h>
1128 #include <linux/dmapool.h>
1130 #define pci_pool dma_pool
1131 #define pci_pool_create(name, pdev, size, align, allocation) \
1132 dma_pool_create(name, &pdev->dev, size, align, allocation)
1133 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1134 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1135 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1137 enum pci_dma_burst_strategy
{
1138 PCI_DMA_BURST_INFINITY
, /* make bursts as large as possible,
1139 strategy_parameter is N/A */
1140 PCI_DMA_BURST_BOUNDARY
, /* disconnect at every strategy_parameter
1142 PCI_DMA_BURST_MULTIPLE
, /* disconnect at some multiple of
1143 strategy_parameter byte boundaries */
1147 u32 vector
; /* kernel uses to write allocated vector */
1148 u16 entry
; /* driver uses to specify entry, OS writes */
1152 #ifdef CONFIG_PCI_MSI
1153 int pci_msi_vec_count(struct pci_dev
*dev
);
1154 int pci_enable_msi_block(struct pci_dev
*dev
, int nvec
);
1155 void pci_msi_shutdown(struct pci_dev
*dev
);
1156 void pci_disable_msi(struct pci_dev
*dev
);
1157 int pci_msix_vec_count(struct pci_dev
*dev
);
1158 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
);
1159 void pci_msix_shutdown(struct pci_dev
*dev
);
1160 void pci_disable_msix(struct pci_dev
*dev
);
1161 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
);
1162 void pci_restore_msi_state(struct pci_dev
*dev
);
1163 int pci_msi_enabled(void);
1164 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
);
1165 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1166 int minvec
, int maxvec
);
1168 static inline int pci_msi_vec_count(struct pci_dev
*dev
)
1173 static inline int pci_enable_msi_block(struct pci_dev
*dev
, int nvec
)
1178 static inline void pci_msi_shutdown(struct pci_dev
*dev
)
1180 static inline void pci_disable_msi(struct pci_dev
*dev
)
1183 static inline int pci_msix_vec_count(struct pci_dev
*dev
)
1187 static inline int pci_enable_msix(struct pci_dev
*dev
,
1188 struct msix_entry
*entries
, int nvec
)
1193 static inline void pci_msix_shutdown(struct pci_dev
*dev
)
1195 static inline void pci_disable_msix(struct pci_dev
*dev
)
1198 static inline void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
1201 static inline void pci_restore_msi_state(struct pci_dev
*dev
)
1203 static inline int pci_msi_enabled(void)
1208 static inline int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
,
1213 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1214 struct msix_entry
*entries
, int minvec
, int maxvec
)
1220 #ifdef CONFIG_PCIEPORTBUS
1221 extern bool pcie_ports_disabled
;
1222 extern bool pcie_ports_auto
;
1224 #define pcie_ports_disabled true
1225 #define pcie_ports_auto false
1228 #ifdef CONFIG_PCIEASPM
1229 bool pcie_aspm_support_enabled(void);
1231 static inline bool pcie_aspm_support_enabled(void) { return false; }
1234 #ifdef CONFIG_PCIEAER
1235 void pci_no_aer(void);
1236 bool pci_aer_available(void);
1238 static inline void pci_no_aer(void) { }
1239 static inline bool pci_aer_available(void) { return false; }
1242 #ifdef CONFIG_PCIE_ECRC
1243 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1244 void pcie_ecrc_get_policy(char *str
);
1246 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
)
1250 static inline void pcie_ecrc_get_policy(char *str
) {};
1253 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1255 #ifdef CONFIG_HT_IRQ
1256 /* The functions a driver should call */
1257 int ht_create_irq(struct pci_dev
*dev
, int idx
);
1258 void ht_destroy_irq(unsigned int irq
);
1259 #endif /* CONFIG_HT_IRQ */
1261 void pci_cfg_access_lock(struct pci_dev
*dev
);
1262 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1263 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1266 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1267 * a PCI domain is defined to be a set of PCI buses which share
1268 * configuration space.
1270 #ifdef CONFIG_PCI_DOMAINS
1271 extern int pci_domains_supported
;
1273 enum { pci_domains_supported
= 0 };
1274 static inline int pci_domain_nr(struct pci_bus
*bus
)
1279 static inline int pci_proc_domain(struct pci_bus
*bus
)
1283 #endif /* CONFIG_PCI_DOMAINS */
1285 /* some architectures require additional setup to direct VGA traffic */
1286 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1287 unsigned int command_bits
, u32 flags
);
1288 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1290 #else /* CONFIG_PCI is not enabled */
1293 * If the system does not have PCI, clearly these return errors. Define
1294 * these as simple inline functions to avoid hair in drivers.
1297 #define _PCI_NOP(o, s, t) \
1298 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1300 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1302 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1303 _PCI_NOP(o, word, u16 x) \
1304 _PCI_NOP(o, dword, u32 x)
1305 _PCI_NOP_ALL(read
, *)
1306 _PCI_NOP_ALL(write
,)
1308 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1309 unsigned int device
,
1310 struct pci_dev
*from
)
1315 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1316 unsigned int device
,
1317 unsigned int ss_vendor
,
1318 unsigned int ss_device
,
1319 struct pci_dev
*from
)
1324 static inline struct pci_dev
*pci_get_class(unsigned int class,
1325 struct pci_dev
*from
)
1330 #define pci_dev_present(ids) (0)
1331 #define no_pci_devices() (1)
1332 #define pci_dev_put(dev) do { } while (0)
1334 static inline void pci_set_master(struct pci_dev
*dev
)
1337 static inline int pci_enable_device(struct pci_dev
*dev
)
1342 static inline void pci_disable_device(struct pci_dev
*dev
)
1345 static inline int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1350 static inline int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1355 static inline int pci_set_dma_max_seg_size(struct pci_dev
*dev
,
1361 static inline int pci_set_dma_seg_boundary(struct pci_dev
*dev
,
1367 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1372 static inline int __pci_register_driver(struct pci_driver
*drv
,
1373 struct module
*owner
)
1378 static inline int pci_register_driver(struct pci_driver
*drv
)
1383 static inline void pci_unregister_driver(struct pci_driver
*drv
)
1386 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1391 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1397 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1402 /* Power management related routines */
1403 static inline int pci_save_state(struct pci_dev
*dev
)
1408 static inline void pci_restore_state(struct pci_dev
*dev
)
1411 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1416 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1421 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1427 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1433 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1438 static inline void pci_release_regions(struct pci_dev
*dev
)
1441 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1443 static inline void pci_block_cfg_access(struct pci_dev
*dev
)
1446 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1449 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
)
1452 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1455 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1459 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1463 static inline int pci_domain_nr(struct pci_bus
*bus
)
1466 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
)
1469 #define dev_is_pci(d) (false)
1470 #define dev_is_pf(d) (false)
1471 #define dev_num_vf(d) (0)
1472 #endif /* CONFIG_PCI */
1474 /* Include architecture-dependent settings and functions */
1476 #include <asm/pci.h>
1478 /* these helpers provide future and backwards compatibility
1479 * for accessing popular PCI BAR info */
1480 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1481 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1482 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1483 #define pci_resource_len(dev,bar) \
1484 ((pci_resource_start((dev), (bar)) == 0 && \
1485 pci_resource_end((dev), (bar)) == \
1486 pci_resource_start((dev), (bar))) ? 0 : \
1488 (pci_resource_end((dev), (bar)) - \
1489 pci_resource_start((dev), (bar)) + 1))
1491 /* Similar to the helpers above, these manipulate per-pci_dev
1492 * driver-specific data. They are really just a wrapper around
1493 * the generic device structure functions of these calls.
1495 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1497 return dev_get_drvdata(&pdev
->dev
);
1500 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1502 dev_set_drvdata(&pdev
->dev
, data
);
1505 /* If you want to know what to call your pci_dev, ask this function.
1506 * Again, it's a wrapper around the generic device.
1508 static inline const char *pci_name(const struct pci_dev
*pdev
)
1510 return dev_name(&pdev
->dev
);
1514 /* Some archs don't want to expose struct resource to userland as-is
1515 * in sysfs and /proc
1517 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1518 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1519 const struct resource
*rsrc
, resource_size_t
*start
,
1520 resource_size_t
*end
)
1522 *start
= rsrc
->start
;
1525 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1529 * The world is not perfect and supplies us with broken PCI devices.
1530 * For at least a part of these bugs we need a work-around, so both
1531 * generic (drivers/pci/quirks.c) and per-architecture code can define
1532 * fixup hooks to be called for particular buggy devices.
1536 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1537 u16 device
; /* You can use PCI_ANY_ID here of course */
1538 u32
class; /* You can use PCI_ANY_ID here too */
1539 unsigned int class_shift
; /* should be 0, 8, 16 */
1540 void (*hook
)(struct pci_dev
*dev
);
1543 enum pci_fixup_pass
{
1544 pci_fixup_early
, /* Before probing BARs */
1545 pci_fixup_header
, /* After reading configuration header */
1546 pci_fixup_final
, /* Final phase of device fixups */
1547 pci_fixup_enable
, /* pci_enable_device() time */
1548 pci_fixup_resume
, /* pci_device_resume() */
1549 pci_fixup_suspend
, /* pci_device_suspend */
1550 pci_fixup_resume_early
, /* pci_device_resume_early() */
1553 /* Anonymous variables would be nice... */
1554 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1555 class_shift, hook) \
1556 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1557 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1558 = { vendor, device, class, class_shift, hook };
1560 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1561 class_shift, hook) \
1562 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1563 hook, vendor, device, class, class_shift, hook)
1564 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1565 class_shift, hook) \
1566 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1567 hook, vendor, device, class, class_shift, hook)
1568 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1569 class_shift, hook) \
1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1571 hook, vendor, device, class, class_shift, hook)
1572 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1573 class_shift, hook) \
1574 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1575 hook, vendor, device, class, class_shift, hook)
1576 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1577 class_shift, hook) \
1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1579 resume##hook, vendor, device, class, \
1581 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1582 class_shift, hook) \
1583 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1584 resume_early##hook, vendor, device, \
1585 class, class_shift, hook)
1586 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1587 class_shift, hook) \
1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1589 suspend##hook, vendor, device, class, \
1592 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1593 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1594 hook, vendor, device, PCI_ANY_ID, 0, hook)
1595 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1596 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1597 hook, vendor, device, PCI_ANY_ID, 0, hook)
1598 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1599 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1600 hook, vendor, device, PCI_ANY_ID, 0, hook)
1601 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1602 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1603 hook, vendor, device, PCI_ANY_ID, 0, hook)
1604 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1605 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1606 resume##hook, vendor, device, \
1607 PCI_ANY_ID, 0, hook)
1608 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1609 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1610 resume_early##hook, vendor, device, \
1611 PCI_ANY_ID, 0, hook)
1612 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1613 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1614 suspend##hook, vendor, device, \
1615 PCI_ANY_ID, 0, hook)
1617 #ifdef CONFIG_PCI_QUIRKS
1618 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1619 struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
);
1620 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1622 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1623 struct pci_dev
*dev
) {}
1624 static inline struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
)
1626 return pci_dev_get(dev
);
1628 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1635 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1636 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1637 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1638 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1639 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1641 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1643 extern int pci_pci_problems
;
1644 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1645 #define PCIPCI_TRITON 2
1646 #define PCIPCI_NATOMA 4
1647 #define PCIPCI_VIAETBF 8
1648 #define PCIPCI_VSFX 16
1649 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1650 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1652 extern unsigned long pci_cardbus_io_size
;
1653 extern unsigned long pci_cardbus_mem_size
;
1654 extern u8 pci_dfl_cache_line_size
;
1655 extern u8 pci_cache_line_size
;
1657 extern unsigned long pci_hotplug_io_size
;
1658 extern unsigned long pci_hotplug_mem_size
;
1660 /* Architecture-specific versions may override these (weak) */
1661 int pcibios_add_platform_entries(struct pci_dev
*dev
);
1662 void pcibios_disable_device(struct pci_dev
*dev
);
1663 void pcibios_set_master(struct pci_dev
*dev
);
1664 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1665 enum pcie_reset_state state
);
1666 int pcibios_add_device(struct pci_dev
*dev
);
1667 void pcibios_release_device(struct pci_dev
*dev
);
1669 #ifdef CONFIG_HIBERNATE_CALLBACKS
1670 extern struct dev_pm_ops pcibios_pm_ops
;
1673 #ifdef CONFIG_PCI_MMCONFIG
1674 void __init
pci_mmcfg_early_init(void);
1675 void __init
pci_mmcfg_late_init(void);
1677 static inline void pci_mmcfg_early_init(void) { }
1678 static inline void pci_mmcfg_late_init(void) { }
1681 int pci_ext_cfg_avail(void);
1683 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1685 #ifdef CONFIG_PCI_IOV
1686 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1687 void pci_disable_sriov(struct pci_dev
*dev
);
1688 irqreturn_t
pci_sriov_migration(struct pci_dev
*dev
);
1689 int pci_num_vf(struct pci_dev
*dev
);
1690 int pci_vfs_assigned(struct pci_dev
*dev
);
1691 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1692 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1694 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1698 static inline void pci_disable_sriov(struct pci_dev
*dev
)
1701 static inline irqreturn_t
pci_sriov_migration(struct pci_dev
*dev
)
1705 static inline int pci_num_vf(struct pci_dev
*dev
)
1709 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1713 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1717 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1723 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1724 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
1725 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
1729 * pci_pcie_cap - get the saved PCIe capability offset
1732 * PCIe capability offset is calculated at PCI device initialization
1733 * time and saved in the data structure. This function returns saved
1734 * PCIe capability offset. Using this instead of pci_find_capability()
1735 * reduces unnecessary search in the PCI configuration space. If you
1736 * need to calculate PCIe capability offset from raw device for some
1737 * reasons, please use pci_find_capability() instead.
1739 static inline int pci_pcie_cap(struct pci_dev
*dev
)
1741 return dev
->pcie_cap
;
1745 * pci_is_pcie - check if the PCI device is PCI Express capable
1748 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1750 static inline bool pci_is_pcie(struct pci_dev
*dev
)
1752 return pci_pcie_cap(dev
);
1756 * pcie_caps_reg - get the PCIe Capabilities Register
1759 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
1761 return dev
->pcie_flags_reg
;
1765 * pci_pcie_type - get the PCIe device/port type
1768 static inline int pci_pcie_type(const struct pci_dev
*dev
)
1770 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
1773 void pci_request_acs(void);
1774 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
1775 bool pci_acs_path_enabled(struct pci_dev
*start
,
1776 struct pci_dev
*end
, u16 acs_flags
);
1778 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1779 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1781 /* Large Resource Data Type Tag Item Names */
1782 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1783 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1784 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1786 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1787 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1788 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1790 /* Small Resource Data Type Tag Item Names */
1791 #define PCI_VPD_STIN_END 0x78 /* End */
1793 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1795 #define PCI_VPD_SRDT_TIN_MASK 0x78
1796 #define PCI_VPD_SRDT_LEN_MASK 0x07
1798 #define PCI_VPD_LRDT_TAG_SIZE 3
1799 #define PCI_VPD_SRDT_TAG_SIZE 1
1801 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1803 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1804 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1805 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1806 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1809 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1810 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1812 * Returns the extracted Large Resource Data Type length.
1814 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
1816 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
1820 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1821 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1823 * Returns the extracted Small Resource Data Type length.
1825 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
1827 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
1831 * pci_vpd_info_field_size - Extracts the information field length
1832 * @lrdt: Pointer to the beginning of an information field header
1834 * Returns the extracted information field length.
1836 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
1838 return info_field
[2];
1842 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1843 * @buf: Pointer to buffered vpd data
1844 * @off: The offset into the buffer at which to begin the search
1845 * @len: The length of the vpd buffer
1846 * @rdt: The Resource Data Type to search for
1848 * Returns the index where the Resource Data Type was found or
1849 * -ENOENT otherwise.
1851 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
1854 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1855 * @buf: Pointer to buffered vpd data
1856 * @off: The offset into the buffer at which to begin the search
1857 * @len: The length of the buffer area, relative to off, in which to search
1858 * @kw: The keyword to search for
1860 * Returns the index where the information field keyword was found or
1861 * -ENOENT otherwise.
1863 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
1864 unsigned int len
, const char *kw
);
1866 /* PCI <-> OF binding helpers */
1869 void pci_set_of_node(struct pci_dev
*dev
);
1870 void pci_release_of_node(struct pci_dev
*dev
);
1871 void pci_set_bus_of_node(struct pci_bus
*bus
);
1872 void pci_release_bus_of_node(struct pci_bus
*bus
);
1874 /* Arch may override this (weak) */
1875 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
1877 static inline struct device_node
*
1878 pci_device_to_OF_node(const struct pci_dev
*pdev
)
1880 return pdev
? pdev
->dev
.of_node
: NULL
;
1883 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
1885 return bus
? bus
->dev
.of_node
: NULL
;
1888 #else /* CONFIG_OF */
1889 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
1890 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
1891 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
1892 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
1893 #endif /* CONFIG_OF */
1896 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
1898 return pdev
->dev
.archdata
.edev
;
1903 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1904 * @pdev: the PCI device
1906 * if the device is PCIE, return NULL
1907 * if the device isn't connected to a PCIe bridge (that is its parent is a
1908 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1911 struct pci_dev
*pci_find_upstream_pcie_bridge(struct pci_dev
*pdev
);
1913 #endif /* LINUX_PCI_H */