1 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
3 * ppc.h (PPC_OPCODE_E300): Define.
5 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
7 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
9 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
12 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
15 2005-07-27 Jan Beulich <jbeulich@novell.com>
17 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
18 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
19 Add movq-s as 64-bit variants of movd-s.
21 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
23 * hppa.h: Fix punctuation in comment.
25 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
26 implicit space-register addressing. Set space-register bits on opcodes
27 using implicit space-register addressing. Add various missing pa20
28 long-immediate opcodes. Remove various opcodes using implicit 3-bit
29 space-register addressing. Use "fE" instead of "fe" in various
32 2005-07-18 Jan Beulich <jbeulich@novell.com>
34 * i386.h (i386_optab): Operands of aam and aad are unsigned.
36 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
38 * i386.h (i386_optab): Support Intel VMX Instructions.
40 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
42 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
44 2005-07-05 Jan Beulich <jbeulich@novell.com>
46 * i386.h (i386_optab): Add new insns.
48 2005-07-01 Nick Clifton <nickc@redhat.com>
50 * sparc.h: Add typedefs to structure declarations.
52 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
55 * i386.h (i386_optab): Update comments for 64bit addressing on
56 mov. Allow 64bit addressing for mov and movq.
58 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
60 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
61 respectively, in various floating-point load and store patterns.
63 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
65 * hppa.h (FLAG_STRICT): Correct comment.
66 (pa_opcodes): Update load and store entries to allow both PA 1.X and
67 PA 2.0 mneumonics when equivalent. Entries with cache control
68 completers now require PA 1.1. Adjust whitespace.
70 2005-05-19 Anton Blanchard <anton@samba.org>
72 * ppc.h (PPC_OPCODE_POWER5): Define.
74 2005-05-10 Nick Clifton <nickc@redhat.com>
76 * Update the address and phone number of the FSF organization in
77 the GPL notices in the following files:
78 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
79 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
80 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
81 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
82 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
83 tic54x.h, tic80.h, v850.h, vax.h
85 2005-05-09 Jan Beulich <jbeulich@novell.com>
87 * i386.h (i386_optab): Add ht and hnt.
89 2005-04-18 Mark Kettenis <kettenis@gnu.org>
91 * i386.h: Insert hyphens into selected VIA PadLock extensions.
92 Add xcrypt-ctr. Provide aliases without hyphens.
94 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
96 Moved from ../ChangeLog
98 2005-04-12 Paul Brook <paul@codesourcery.com>
99 * m88k.h: Rename psr macros to avoid conflicts.
101 2005-03-12 Zack Weinberg <zack@codesourcery.com>
102 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
103 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
106 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
107 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
108 Remove redundant instruction types.
109 (struct argument): X_op - new field.
110 (struct cst4_entry): Remove.
111 (no_op_insn): Declare.
113 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
114 * crx.h (enum argtype): Rename types, remove unused types.
116 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
117 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
118 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
119 (enum operand_type): Rearrange operands, edit comments.
120 replace us<N> with ui<N> for unsigned immediate.
121 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
122 displacements (respectively).
123 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
124 (instruction type): Add NO_TYPE_INS.
125 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
126 (operand_entry): New field - 'flags'.
127 (operand flags): New.
129 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
130 * crx.h (operand_type): Remove redundant types i3, i4,
132 Add new unsigned immediate types us3, us4, us5, us16.
134 2005-04-12 Mark Kettenis <kettenis@gnu.org>
136 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
137 adjust them accordingly.
139 2005-04-01 Jan Beulich <jbeulich@novell.com>
141 * i386.h (i386_optab): Add rdtscp.
143 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
145 * i386.h (i386_optab): Don't allow the `l' suffix for moving
146 between memory and segment register. Allow movq for moving between
147 general-purpose register and segment register.
149 2005-02-09 Jan Beulich <jbeulich@novell.com>
152 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
153 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
156 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
158 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
159 * cgen.h (enum cgen_parse_operand_type): Add
160 CGEN_PARSE_OPERAND_SYMBOLIC.
162 2005-01-21 Fred Fish <fnf@specifixinc.com>
164 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
165 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
166 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
168 2005-01-19 Fred Fish <fnf@specifixinc.com>
170 * mips.h (struct mips_opcode): Add new pinfo2 member.
171 (INSN_ALIAS): New define for opcode table entries that are
172 specific instances of another entry, such as 'move' for an 'or'
174 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
175 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
177 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
179 * mips.h (CPU_RM9000): Define.
180 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
182 2004-11-25 Jan Beulich <jbeulich@novell.com>
184 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
185 to/from test registers are illegal in 64-bit mode. Add missing
186 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
187 (previously one had to explicitly encode a rex64 prefix). Re-enable
188 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
189 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
191 2004-11-23 Jan Beulich <jbeulich@novell.com>
193 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
194 available only with SSE2. Change the MMX additions introduced by SSE
195 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
196 instructions by their now designated identifier (since combining i686
197 and 3DNow! does not really imply 3DNow!A).
199 2004-11-19 Alan Modra <amodra@bigpond.net.au>
201 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
202 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
204 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
205 Vineet Sharma <vineets@noida.hcltech.com>
207 * maxq.h: New file: Disassembly information for the maxq port.
209 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
211 * i386.h (i386_optab): Put back "movzb".
213 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
215 * cris.h (enum cris_insn_version_usage): Tweak formatting and
216 comments. Remove member cris_ver_sim. Add members
217 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
218 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
219 (struct cris_support_reg, struct cris_cond15): New types.
220 (cris_conds15): Declare.
221 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
222 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
223 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
224 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
225 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
228 2004-11-04 Jan Beulich <jbeulich@novell.com>
230 * i386.h (sldx_Suf): Remove.
231 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
232 (q_FP): Define, implying no REX64.
233 (x_FP, sl_FP): Imply FloatMF.
234 (i386_optab): Split reg and mem forms of moving from segment registers
235 so that the memory forms can ignore the 16-/32-bit operand size
236 distinction. Adjust a few others for Intel mode. Remove *FP uses from
237 all non-floating-point instructions. Unite 32- and 64-bit forms of
238 movsx, movzx, and movd. Adjust floating point operations for the above
239 changes to the *FP macros. Add DefaultSize to floating point control
240 insns operating on larger memory ranges. Remove left over comments
241 hinting at certain insns being Intel-syntax ones where the ones
242 actually meant are already gone.
244 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
246 * crx.h: Add COPS_REG_INS - Coprocessor Special register
249 2004-09-30 Paul Brook <paul@codesourcery.com>
251 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
252 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
254 2004-09-11 Theodore A. Roth <troth@openavr.org>
256 * avr.h: Add support for
257 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
259 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
261 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
263 2004-08-24 Dmitry Diky <diwil@spec.ru>
265 * msp430.h (msp430_opc): Add new instructions.
266 (msp430_rcodes): Declare new instructions.
267 (msp430_hcodes): Likewise..
269 2004-08-13 Nick Clifton <nickc@redhat.com>
272 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
275 2004-08-30 Michal Ludvig <mludvig@suse.cz>
277 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
279 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
281 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
283 2004-07-21 Jan Beulich <jbeulich@novell.com>
285 * i386.h: Adjust instruction descriptions to better match the
288 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
290 * arm.h: Remove all old content. Replace with architecture defines
291 from gas/config/tc-arm.c.
293 2004-07-09 Andreas Schwab <schwab@suse.de>
295 * m68k.h: Fix comment.
297 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
301 2004-06-24 Alan Modra <amodra@bigpond.net.au>
303 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
305 2004-05-24 Peter Barada <peter@the-baradas.com>
307 * m68k.h: Add 'size' to m68k_opcode.
309 2004-05-05 Peter Barada <peter@the-baradas.com>
311 * m68k.h: Switch from ColdFire chip name to core variant.
313 2004-04-22 Peter Barada <peter@the-baradas.com>
315 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
316 descriptions for new EMAC cases.
317 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
318 handle Motorola MAC syntax.
319 Allow disassembly of ColdFire V4e object files.
321 2004-03-16 Alan Modra <amodra@bigpond.net.au>
323 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
325 2004-03-12 Jakub Jelinek <jakub@redhat.com>
327 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
329 2004-03-12 Michal Ludvig <mludvig@suse.cz>
331 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
333 2004-03-12 Michal Ludvig <mludvig@suse.cz>
335 * i386.h (i386_optab): Added xstore/xcrypt insns.
337 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
339 * h8300.h (32bit ldc/stc): Add relaxing support.
341 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
343 * h8300.h (BITOP): Pass MEMRELAX flag.
345 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
347 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
350 For older changes see ChangeLog-9103
356 version-control: never