include/opcode/ChangeLog

   1 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
   2             Joseph Myers  <joseph@codesourcery.com>
   3             Ian Lance Taylor  <ian@wasabisystems.com>
   4             Ben Elliston  <bje@wasabisystems.com>
   5
   6         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
   7
   8 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
   9
  10         * score-datadep.h: New file.
  11         * score-inst.h: New file.
  12
  13 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  16         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  17         movdq2q and movq2dq.
  18
  19 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  20            Michael Meissner             <michael.meissner@amd.com>
  21
  22         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  23
  24 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         * i386.h (i386_optab): Add "nop" with memory reference.
  27
  28 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386.h (i386_optab): Update comment for 64bit NOP.
  31
  32 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  33             Anton Blanchard  <anton@samba.org>
  34
  35         * ppc.h (PPC_OPCODE_POWER6): Define.
  36         Adjust whitespace.
  37
  38 2006-06-05  Thiemo Seufer  <ths@mips.com>
  39
  40         * mips.h: Improve description of MT flags.
  41
  42 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  43
  44         * m68k.h (mcf_mask): Define.
  45
  46 2006-05-05  Thiemo Seufer  <ths@mips.com>
  47             David Ung  <davidu@mips.com>
  48
  49         * mips.h (enum): Add macro M_CACHE_AB.
  50
  51 2006-05-04  Thiemo Seufer  <ths@mips.com>
  52             Nigel Stephens  <nigel@mips.com>
  53             David Ung  <davidu@mips.com>
  54
  55         * mips.h: Add INSN_SMARTMIPS define.
  56
  57 2006-04-30  Thiemo Seufer  <ths@mips.com>
  58             David Ung  <davidu@mips.com>
  59
  60         * mips.h: Defines udi bits and masks.  Add description of
  61         characters which may appear in the args field of udi
  62         instructions.
  63
  64 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  65
  66         * mips.h: Improve comments describing the bitfield instruction
  67         fields.
  68
  69 2006-04-26  Julian Brown  <julian@codesourcery.com>
  70
  71         * arm.h (FPU_VFP_EXT_V3): Define constant.
  72         (FPU_NEON_EXT_V1): Likewise.
  73         (FPU_VFP_HARD): Update.
  74         (FPU_VFP_V3): Define macro.
  75         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  76
  77 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  78
  79         * avr.h (AVR_ISA_PWMx): New.
  80
  81 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  82
  83         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  84         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  85         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  86         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  87         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  88
  89 2006-03-10  Paul Brook  <paul@codesourcery.com>
  90
  91         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  92
  93 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  94
  95         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  96         first.  Correct mask of bb "B" opcode.
  97
  98 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  99
 100         * i386.h (i386_optab): Support Intel Merom New Instructions.
 101
 102 2006-02-24  Paul Brook  <paul@codesourcery.com>
 103
 104         * arm.h: Add V7 feature bits.
 105
 106 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 107
 108         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 109
 110 2006-01-31  Paul Brook  <paul@codesourcery.com>
 111         Richard Earnshaw <rearnsha@arm.com>
 112
 113         * arm.h: Use ARM_CPU_FEATURE.
 114         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 115         (arm_feature_set): Change to a structure.
 116         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 117         ARM_FEATURE): New macros.
 118
 119 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 120
 121         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 122         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 123         (ADD_PC_INCR_OPCODE): Don't define.
 124
 125 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         PR gas/1874
 128         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 129
 130 2005-11-14  David Ung  <davidu@mips.com>
 131
 132         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 133         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 134         save/restore encoding of the args field.
 135
 136 2005-10-28  Dave Brolley  <brolley@redhat.com>
 137
 138         Contribute the following changes:
 139         2005-02-16  Dave Brolley  <brolley@redhat.com>
 140
 141         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 142         cgen_isa_mask_* to cgen_bitset_*.
 143         * cgen.h: Likewise.
 144
 145         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 146
 147         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 148         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 149         (CGEN_CPU_TABLE): Make isas a ponter.
 150
 151         2003-09-29  Dave Brolley  <brolley@redhat.com>
 152
 153         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 154         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 155         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 156
 157         2002-12-13  Dave Brolley  <brolley@redhat.com>
 158
 159         * cgen.h (symcat.h): #include it.
 160         (cgen-bitset.h): #include it.
 161         (CGEN_ATTR_VALUE_TYPE): Now a union.
 162         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 163         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 164         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 165         * cgen-bitset.h: New file.
 166
 167 2005-09-30  Catherine Moore  <clm@cm00re.com>
 168
 169         * bfin.h: New file.
 170
 171 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 172
 173         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 174         indirect operands.
 175
 176 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 177
 178         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 179         Add FLAG_STRICT to pa10 ftest opcode.
 180
 181 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 182
 183         * hppa.h (pa_opcodes): Remove lha entries.
 184
 185 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 186
 187         * hppa.h (FLAG_STRICT): Revise comment.
 188         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 189         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 190         entries for "fdc".
 191
 192 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 193
 194         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 195
 196 2005-09-06  Chao-ying Fu  <fu@mips.com>
 197
 198         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 199         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 200         define.
 201         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 202         (INSN_ASE_MASK): Update to include INSN_MT.
 203         (INSN_MT): New define for MT ASE.
 204
 205 2005-08-25  Chao-ying Fu  <fu@mips.com>
 206
 207         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 208         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 209         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 210         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 211         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 212         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 213         instructions.
 214         (INSN_DSP): New define for DSP ASE.
 215
 216 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 217
 218         * a29k.h: Delete.
 219
 220 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 221
 222         * ppc.h (PPC_OPCODE_E300): Define.
 223
 224 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 225
 226         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 227
 228 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 229
 230         PR gas/336
 231         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 232         and pitlb.
 233
 234 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 235
 236         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 237         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 238         Add movq-s as 64-bit variants of movd-s.
 239
 240 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 241
 242         * hppa.h: Fix punctuation in comment.
 243
 244         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 245         implicit space-register addressing.  Set space-register bits on opcodes
 246         using implicit space-register addressing.  Add various missing pa20
 247         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 248         space-register addressing.  Use "fE" instead of "fe" in various
 249         fstw opcodes.
 250
 251 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 252
 253         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 254
 255 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 256
 257         * i386.h (i386_optab): Support Intel VMX Instructions.
 258
 259 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 260
 261         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 262
 263 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 264
 265         * i386.h (i386_optab): Add new insns.
 266
 267 2005-07-01  Nick Clifton  <nickc@redhat.com>
 268
 269         * sparc.h: Add typedefs to structure declarations.
 270
 271 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 272
 273         PR 1013
 274         * i386.h (i386_optab): Update comments for 64bit addressing on
 275         mov. Allow 64bit addressing for mov and movq.
 276
 277 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 278
 279         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 280         respectively, in various floating-point load and store patterns.
 281
 282 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 283
 284         * hppa.h (FLAG_STRICT): Correct comment.
 285         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 286         PA 2.0 mneumonics when equivalent.  Entries with cache control
 287         completers now require PA 1.1.  Adjust whitespace.
 288
 289 2005-05-19  Anton Blanchard  <anton@samba.org>
 290
 291         * ppc.h (PPC_OPCODE_POWER5): Define.
 292
 293 2005-05-10  Nick Clifton  <nickc@redhat.com>
 294
 295         * Update the address and phone number of the FSF organization in
 296         the GPL notices in the following files:
 297         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 298         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 299         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 300         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 301         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 302         tic54x.h, tic80.h, v850.h, vax.h
 303
 304 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 305
 306         * i386.h (i386_optab): Add ht and hnt.
 307
 308 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 309
 310         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 311         Add xcrypt-ctr.  Provide aliases without hyphens.
 312
 313 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         Moved from ../ChangeLog
 316
 317         2005-04-12  Paul Brook  <paul@codesourcery.com>
 318         * m88k.h: Rename psr macros to avoid conflicts.
 319
 320         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 321         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 322         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 323         and ARM_ARCH_V6ZKT2.
 324
 325         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 326         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 327         Remove redundant instruction types.
 328         (struct argument): X_op - new field.
 329         (struct cst4_entry): Remove.
 330         (no_op_insn): Declare.
 331
 332         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 333         * crx.h (enum argtype): Rename types, remove unused types.
 334
 335         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 336         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 337         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 338         (enum operand_type): Rearrange operands, edit comments.
 339         replace us<N> with ui<N> for unsigned immediate.
 340         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 341         displacements (respectively).
 342         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 343         (instruction type): Add NO_TYPE_INS.
 344         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 345         (operand_entry): New field - 'flags'.
 346         (operand flags): New.
 347
 348         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 349         * crx.h (operand_type): Remove redundant types i3, i4,
 350         i5, i8, i12.
 351         Add new unsigned immediate types us3, us4, us5, us16.
 352
 353 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 354
 355         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 356         adjust them accordingly.
 357
 358 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 359
 360         * i386.h (i386_optab): Add rdtscp.
 361
 362 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 365         between memory and segment register. Allow movq for moving between
 366         general-purpose register and segment register.
 367
 368 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 369
 370         PR gas/707
 371         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 372         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 373         fnstsw.
 374
 375 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 376
 377         * m68k.h (m68008, m68ec030, m68882): Remove.
 378         (m68k_mask): New.
 379         (cpu_m68k, cpu_cf): New.
 380         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 381         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 382
 383 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 384
 385         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 386         * cgen.h (enum cgen_parse_operand_type): Add
 387         CGEN_PARSE_OPERAND_SYMBOLIC.
 388
 389 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 390
 391         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 392         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 393         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 394
 395 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 396
 397         * mips.h (struct mips_opcode): Add new pinfo2 member.
 398         (INSN_ALIAS): New define for opcode table entries that are
 399         specific instances of another entry, such as 'move' for an 'or'
 400         with a zero operand.
 401         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 402         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 403
 404 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 405
 406         * mips.h (CPU_RM9000): Define.
 407         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 408
 409 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 410
 411         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 412         to/from test registers are illegal in 64-bit mode. Add missing
 413         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 414         (previously one had to explicitly encode a rex64 prefix). Re-enable
 415         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 416         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 417
 418 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 419
 420         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 421         available only with SSE2. Change the MMX additions introduced by SSE
 422         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 423         instructions by their now designated identifier (since combining i686
 424         and 3DNow! does not really imply 3DNow!A).
 425
 426 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 427
 428         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 429         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 430
 431 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 432             Vineet Sharma      <vineets@noida.hcltech.com>
 433
 434         * maxq.h: New file: Disassembly information for the maxq port.
 435
 436 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 437
 438         * i386.h (i386_optab): Put back "movzb".
 439
 440 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 441
 442         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 443         comments.  Remove member cris_ver_sim.  Add members
 444         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 445         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 446         (struct cris_support_reg, struct cris_cond15): New types.
 447         (cris_conds15): Declare.
 448         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 449         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 450         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 451         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 452         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 453         SIZE_FIELD_UNSIGNED.
 454
 455 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 456
 457         * i386.h (sldx_Suf): Remove.
 458         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 459         (q_FP): Define, implying no REX64.
 460         (x_FP, sl_FP): Imply FloatMF.
 461         (i386_optab): Split reg and mem forms of moving from segment registers
 462         so that the memory forms can ignore the 16-/32-bit operand size
 463         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 464         all non-floating-point instructions. Unite 32- and 64-bit forms of
 465         movsx, movzx, and movd. Adjust floating point operations for the above
 466         changes to the *FP macros. Add DefaultSize to floating point control
 467         insns operating on larger memory ranges. Remove left over comments
 468         hinting at certain insns being Intel-syntax ones where the ones
 469         actually meant are already gone.
 470
 471 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 472
 473         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 474         instruction type.
 475
 476 2004-09-30  Paul Brook  <paul@codesourcery.com>
 477
 478         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 479         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 480
 481 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 482
 483         * avr.h: Add support for
 484         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 485
 486 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 487
 488         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 489
 490 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 491
 492         * msp430.h (msp430_opc): Add new instructions.
 493         (msp430_rcodes): Declare new instructions.
 494         (msp430_hcodes): Likewise..
 495
 496 2004-08-13  Nick Clifton  <nickc@redhat.com>
 497
 498         PR/301
 499         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 500         processors.
 501
 502 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 503
 504         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 505
 506 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 509
 510 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 511
 512         * i386.h: Adjust instruction descriptions to better match the
 513         specification.
 514
 515 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 516
 517         * arm.h: Remove all old content.  Replace with architecture defines
 518         from gas/config/tc-arm.c.
 519
 520 2004-07-09  Andreas Schwab  <schwab@suse.de>
 521
 522         * m68k.h: Fix comment.
 523
 524 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 525
 526         * crx.h: New file.
 527
 528 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 529
 530         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 531
 532 2004-05-24  Peter Barada  <peter@the-baradas.com>
 533
 534         * m68k.h: Add 'size' to m68k_opcode.
 535
 536 2004-05-05  Peter Barada  <peter@the-baradas.com>
 537
 538         * m68k.h: Switch from ColdFire chip name to core variant.
 539
 540 2004-04-22  Peter Barada  <peter@the-baradas.com>
 541
 542         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 543         descriptions for new EMAC cases.
 544         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 545         handle Motorola MAC syntax.
 546         Allow disassembly of ColdFire V4e object files.
 547
 548 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 549
 550         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 551
 552 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 553
 554         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 555
 556 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 557
 558         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 559
 560 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 561
 562         * i386.h (i386_optab): Added xstore/xcrypt insns.
 563
 564 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 565
 566         * h8300.h (32bit ldc/stc): Add relaxing support.
 567
 568 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 569
 570         * h8300.h (BITOP): Pass MEMRELAX flag.
 571
 572 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 573
 574         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 575         except for the H8S.
 576
 577 For older changes see ChangeLog-9103
 578 \f
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