1 2011-05-31 Paul Brook <paul@codesourcery.com>
3 * opcode/arm.h (ARM_ARCH_V7R_IDIV): Define.
5 2011-04-18 Julian Brown <julian@codesourcery.com>
7 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
9 2011-04-11 Dan McDonald <dan@wellkeeper.com>
12 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
14 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
16 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
17 New instruction set flags.
18 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
20 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
22 * mips.h (M_PREF_AB): New enum value.
24 2011-02-12 Mike Frysinger <vapier@gentoo.org>
26 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
28 (is_macmod_pmove, is_macmod_hmove): New functions.
30 2011-02-11 Mike Frysinger <vapier@gentoo.org>
32 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
34 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
36 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
37 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
39 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
42 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
45 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
48 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
50 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
52 * mips.h: Update commentary after last commit.
54 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
56 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
57 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
58 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
60 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
62 * mips.h: Fix previous commit.
64 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
66 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
67 (INSN_LOONGSON_3A): Clear bit 31.
69 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
72 * arm.h (ARM_AEXT_V6M_ONLY): New define.
73 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
74 (ARM_ARCH_V6M_ONLY): New define.
76 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
78 * mips.h (INSN_LOONGSON_3A): Defined.
79 (CPU_LOONGSON_3A): Defined.
80 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
82 2010-10-09 Matt Rice <ratmice@gmail.com>
84 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
85 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
87 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
89 * arm.h (ARM_EXT_VIRT): New define.
90 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
91 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
94 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
96 * arm.h (ARM_AEXT_ADIV): New define.
97 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
99 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
101 * arm.h (ARM_EXT_OS): New define.
102 (ARM_AEXT_V6SM): Likewise.
103 (ARM_ARCH_V6SM): Likewise.
105 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
107 * arm.h (ARM_EXT_MP): Add.
108 (ARM_ARCH_V7A_MP): Likewise.
110 2010-09-22 Mike Frysinger <vapier@gentoo.org>
112 * bfin.h: Declare pseudoChr structs/defines.
114 2010-09-21 Mike Frysinger <vapier@gentoo.org>
116 * bfin.h: Strip trailing whitespace.
118 2010-07-29 DJ Delorie <dj@redhat.com>
120 * rx.h (RX_Operand_Type): Add TwoReg.
121 (RX_Opcode_ID): Remove ediv and ediv2.
123 2010-07-27 DJ Delorie <dj@redhat.com>
125 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
127 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
128 Ina Pandit <ina.pandit@kpitcummins.com>
130 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
131 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
132 PROCESSOR_V850E2_ALL.
133 Remove PROCESSOR_V850EA support.
134 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
135 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
136 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
137 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
138 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
139 V850_OPERAND_PERCENT.
140 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
142 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
145 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
147 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
148 (MIPS16_INSN_BRANCH): Rename to...
149 (MIPS16_INSN_COND_BRANCH): ... this.
151 2010-07-03 Alan Modra <amodra@gmail.com>
153 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
154 Renumber other PPC_OPCODE defines.
156 2010-07-03 Alan Modra <amodra@gmail.com>
158 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
160 2010-06-29 Alan Modra <amodra@gmail.com>
162 * maxq.h: Delete file.
164 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
166 * ppc.h (PPC_OPCODE_E500): Define.
168 2010-05-26 Catherine Moore <clm@codesourcery.com>
170 * opcode/mips.h (INSN_MIPS16): Remove.
172 2010-04-21 Joseph Myers <joseph@codesourcery.com>
174 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
176 2010-04-15 Nick Clifton <nickc@redhat.com>
178 * alpha.h: Update copyright notice to use GPLv3.
184 * convex.h: Likewise.
198 * m68hc11.h: Likewise.
204 * mn10200.h: Likewise.
205 * mn10300.h: Likewise.
206 * msp430.h: Likewise.
217 * score-datadep.h: Likewise.
218 * score-inst.h: Likewise.
220 * spu-insns.h: Likewise.
224 * tic54x.h: Likewise.
229 2010-03-25 Joseph Myers <joseph@codesourcery.com>
231 * tic6x-control-registers.h, tic6x-insn-formats.h,
232 tic6x-opcode-table.h, tic6x.h: New.
234 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
236 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
238 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
240 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
242 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
244 * ia64.h (ia64_find_opcode): Remove argument name.
245 (ia64_find_next_opcode): Likewise.
246 (ia64_dis_opcode): Likewise.
247 (ia64_free_opcode): Likewise.
248 (ia64_find_dependency): Likewise.
250 2009-11-22 Doug Evans <dje@sebabeach.org>
252 * cgen.h: Include bfd_stdint.h.
253 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
255 2009-11-18 Paul Brook <paul@codesourcery.com>
257 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
259 2009-11-17 Paul Brook <paul@codesourcery.com>
260 Daniel Jacobowitz <dan@codesourcery.com>
262 * arm.h (ARM_EXT_V6_DSP): Define.
263 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
264 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
266 2009-11-04 DJ Delorie <dj@redhat.com>
268 * rx.h (rx_decode_opcode) (mvtipl): Add.
269 (mvtcp, mvfcp, opecp): Remove.
271 2009-11-02 Paul Brook <paul@codesourcery.com>
273 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
274 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
275 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
276 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
277 FPU_ARCH_NEON_VFP_V4): Define.
279 2009-10-23 Doug Evans <dje@sebabeach.org>
281 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
282 * cgen.h: Update. Improve multi-inclusion macro name.
284 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
286 * ppc.h (PPC_OPCODE_476): Define.
288 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
290 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
292 2009-09-29 DJ Delorie <dj@redhat.com>
296 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
298 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
300 2009-09-21 Ben Elliston <bje@au.ibm.com>
302 * ppc.h (PPC_OPCODE_PPCA2): New.
304 2009-09-05 Martin Thuresson <martin@mtme.org>
306 * ia64.h (struct ia64_operand): Renamed member class to op_class.
308 2009-08-29 Martin Thuresson <martin@mtme.org>
310 * tic30.h (template): Rename type template to
311 insn_template. Updated code to use new name.
312 * tic54x.h (template): Rename type template to
315 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
317 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
319 2009-06-11 Anthony Green <green@moxielogic.com>
321 * moxie.h (MOXIE_F3_PCREL): Define.
322 (moxie_form3_opc_info): Grow.
324 2009-06-06 Anthony Green <green@moxielogic.com>
326 * moxie.h (MOXIE_F1_M): Define.
328 2009-04-15 Anthony Green <green@moxielogic.com>
332 2009-04-06 DJ Delorie <dj@redhat.com>
334 * h8300.h: Add relaxation attributes to MOVA opcodes.
336 2009-03-10 Alan Modra <amodra@bigpond.net.au>
338 * ppc.h (ppc_parse_cpu): Declare.
340 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
342 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
343 and _IMM11 for mbitclr and mbitset.
344 * score-datadep.h: Update dependency information.
346 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
348 * ppc.h (PPC_OPCODE_POWER7): New.
350 2009-02-06 Doug Evans <dje@google.com>
352 * i386.h: Add comment regarding sse* insns and prefixes.
354 2009-02-03 Sandip Matte <sandip@rmicorp.com>
356 * mips.h (INSN_XLR): Define.
357 (INSN_CHIP_MASK): Update.
359 (OPCODE_IS_MEMBER): Update.
360 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
362 2009-01-28 Doug Evans <dje@google.com>
364 * opcode/i386.h: Add multiple inclusion protection.
365 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
366 (EDI_REG_NUM): New macros.
367 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
368 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
369 (REX_PREFIX_P): New macro.
371 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
373 * ppc.h (struct powerpc_opcode): New field "deprecated".
374 (PPC_OPCODE_NOPOWER4): Delete.
376 2008-11-28 Joshua Kinard <kumba@gentoo.org>
378 * mips.h: Define CPU_R14000, CPU_R16000.
379 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
381 2008-11-18 Catherine Moore <clm@codesourcery.com>
383 * arm.h (FPU_NEON_FP16): New.
384 (FPU_ARCH_NEON_FP16): New.
386 2008-11-06 Chao-ying Fu <fu@mips.com>
388 * mips.h: Doucument '1' for 5-bit sync type.
390 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
392 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
395 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
397 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
399 2008-07-30 Michael J. Eager <eager@eagercon.com>
401 * ppc.h (PPC_OPCODE_405): Define.
402 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
404 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
406 * ppc.h (ppc_cpu_t): New typedef.
407 (struct powerpc_opcode <flags>): Use it.
408 (struct powerpc_operand <insert, extract>): Likewise.
409 (struct powerpc_macro <flags>): Likewise.
411 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
413 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
414 Update comment before MIPS16 field descriptors to mention MIPS16.
415 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
417 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
418 New bit masks and shift counts for cins and exts.
420 * mips.h: Document new field descriptors +Q.
421 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
423 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
425 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
426 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
428 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
430 * ppc.h: (PPC_OPCODE_E500MC): New.
432 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
434 * i386.h (MAX_OPERANDS): Set to 5.
435 (MAX_MNEM_SIZE): Changed to 20.
437 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
439 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
441 2008-03-09 Paul Brook <paul@codesourcery.com>
443 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
445 2008-03-04 Paul Brook <paul@codesourcery.com>
447 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
448 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
449 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
451 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
452 Nick Clifton <nickc@redhat.com>
455 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
456 with a 32-bit displacement but without the top bit of the 4th byte
459 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
461 * cr16.h (cr16_num_optab): Declared.
463 2008-02-14 Hakan Ardo <hakan@debian.org>
466 * avr.h (AVR_ISA_2xxe): Define.
468 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
470 * mips.h: Update copyright.
471 (INSN_CHIP_MASK): New macro.
472 (INSN_OCTEON): New macro.
473 (CPU_OCTEON): New macro.
474 (OPCODE_IS_MEMBER): Handle Octeon instructions.
476 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
478 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
480 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
482 * avr.h (AVR_ISA_USB162): Add new opcode set.
483 (AVR_ISA_AVR3): Likewise.
485 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
487 * mips.h (INSN_LOONGSON_2E): New.
488 (INSN_LOONGSON_2F): New.
489 (CPU_LOONGSON_2E): New.
490 (CPU_LOONGSON_2F): New.
491 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
493 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
495 * mips.h (INSN_ISA*): Redefine certain values as an
496 enumeration. Update comments.
497 (mips_isa_table): New.
498 (ISA_MIPS*): Redefine to match enumeration.
499 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
502 2007-08-08 Ben Elliston <bje@au.ibm.com>
504 * ppc.h (PPC_OPCODE_PPCPS): New.
506 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
508 * m68k.h: Document j K & E.
510 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
512 * cr16.h: New file for CR16 target.
514 2007-05-02 Alan Modra <amodra@bigpond.net.au>
516 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
518 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
520 * m68k.h (mcfisa_c): New.
521 (mcfusp, mcf_mask): Adjust.
523 2007-04-20 Alan Modra <amodra@bigpond.net.au>
525 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
526 (num_powerpc_operands): Declare.
527 (PPC_OPERAND_SIGNED et al): Redefine as hex.
528 (PPC_OPERAND_PLUS1): Define.
530 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
532 * i386.h (REX_MODE64): Renamed to ...
534 (REX_EXTX): Renamed to ...
536 (REX_EXTY): Renamed to ...
538 (REX_EXTZ): Renamed to ...
541 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
543 * i386.h: Add entries from config/tc-i386.h and move tables
544 to opcodes/i386-opc.h.
546 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
548 * i386.h (FloatDR): Removed.
549 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
551 2007-03-01 Alan Modra <amodra@bigpond.net.au>
553 * spu-insns.h: Add soma double-float insns.
555 2007-02-20 Thiemo Seufer <ths@mips.com>
556 Chao-Ying Fu <fu@mips.com>
558 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
559 (INSN_DSPR2): Add flag for DSP R2 instructions.
560 (M_BALIGN): New macro.
562 2007-02-14 Alan Modra <amodra@bigpond.net.au>
564 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
565 and Seg3ShortFrom with Shortform.
567 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
570 * i386.h (i386_optab): Put the real "test" before the pseudo
573 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
575 * m68k.h (m68010up): OR fido_a.
577 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
579 * m68k.h (fido_a): New.
581 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
583 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
584 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
587 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
589 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
591 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
593 * score-inst.h (enum score_insn_type): Add Insn_internal.
595 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
596 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
597 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
598 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
599 Alan Modra <amodra@bigpond.net.au>
601 * spu-insns.h: New file.
604 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
606 * ppc.h (PPC_OPCODE_CELL): Define.
608 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
610 * i386.h : Modify opcode to support for the change in POPCNT opcode
611 in amdfam10 architecture.
613 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
615 * i386.h: Replace CpuMNI with CpuSSSE3.
617 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
618 Joseph Myers <joseph@codesourcery.com>
619 Ian Lance Taylor <ian@wasabisystems.com>
620 Ben Elliston <bje@wasabisystems.com>
622 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
624 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
626 * score-datadep.h: New file.
627 * score-inst.h: New file.
629 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
631 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
632 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
635 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
636 Michael Meissner <michael.meissner@amd.com>
638 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
640 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
642 * i386.h (i386_optab): Add "nop" with memory reference.
644 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
646 * i386.h (i386_optab): Update comment for 64bit NOP.
648 2006-06-06 Ben Elliston <bje@au.ibm.com>
649 Anton Blanchard <anton@samba.org>
651 * ppc.h (PPC_OPCODE_POWER6): Define.
654 2006-06-05 Thiemo Seufer <ths@mips.com>
656 * mips.h: Improve description of MT flags.
658 2006-05-25 Richard Sandiford <richard@codesourcery.com>
660 * m68k.h (mcf_mask): Define.
662 2006-05-05 Thiemo Seufer <ths@mips.com>
663 David Ung <davidu@mips.com>
665 * mips.h (enum): Add macro M_CACHE_AB.
667 2006-05-04 Thiemo Seufer <ths@mips.com>
668 Nigel Stephens <nigel@mips.com>
669 David Ung <davidu@mips.com>
671 * mips.h: Add INSN_SMARTMIPS define.
673 2006-04-30 Thiemo Seufer <ths@mips.com>
674 David Ung <davidu@mips.com>
676 * mips.h: Defines udi bits and masks. Add description of
677 characters which may appear in the args field of udi
680 2006-04-26 Thiemo Seufer <ths@networkno.de>
682 * mips.h: Improve comments describing the bitfield instruction
685 2006-04-26 Julian Brown <julian@codesourcery.com>
687 * arm.h (FPU_VFP_EXT_V3): Define constant.
688 (FPU_NEON_EXT_V1): Likewise.
689 (FPU_VFP_HARD): Update.
690 (FPU_VFP_V3): Define macro.
691 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
693 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
695 * avr.h (AVR_ISA_PWMx): New.
697 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
699 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
700 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
701 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
702 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
703 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
705 2006-03-10 Paul Brook <paul@codesourcery.com>
707 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
709 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
711 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
712 first. Correct mask of bb "B" opcode.
714 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
716 * i386.h (i386_optab): Support Intel Merom New Instructions.
718 2006-02-24 Paul Brook <paul@codesourcery.com>
720 * arm.h: Add V7 feature bits.
722 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
724 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
726 2006-01-31 Paul Brook <paul@codesourcery.com>
727 Richard Earnshaw <rearnsha@arm.com>
729 * arm.h: Use ARM_CPU_FEATURE.
730 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
731 (arm_feature_set): Change to a structure.
732 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
733 ARM_FEATURE): New macros.
735 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
737 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
738 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
739 (ADD_PC_INCR_OPCODE): Don't define.
741 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
744 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
746 2005-11-14 David Ung <davidu@mips.com>
748 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
749 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
750 save/restore encoding of the args field.
752 2005-10-28 Dave Brolley <brolley@redhat.com>
754 Contribute the following changes:
755 2005-02-16 Dave Brolley <brolley@redhat.com>
757 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
758 cgen_isa_mask_* to cgen_bitset_*.
761 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
763 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
764 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
765 (CGEN_CPU_TABLE): Make isas a ponter.
767 2003-09-29 Dave Brolley <brolley@redhat.com>
769 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
770 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
771 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
773 2002-12-13 Dave Brolley <brolley@redhat.com>
775 * cgen.h (symcat.h): #include it.
776 (cgen-bitset.h): #include it.
777 (CGEN_ATTR_VALUE_TYPE): Now a union.
778 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
779 (CGEN_ATTR_ENTRY): 'value' now unsigned.
780 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
781 * cgen-bitset.h: New file.
783 2005-09-30 Catherine Moore <clm@cm00re.com>
787 2005-10-24 Jan Beulich <jbeulich@novell.com>
789 * ia64.h (enum ia64_opnd): Move memory operand out of set of
792 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
794 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
795 Add FLAG_STRICT to pa10 ftest opcode.
797 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
799 * hppa.h (pa_opcodes): Remove lha entries.
801 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
803 * hppa.h (FLAG_STRICT): Revise comment.
804 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
805 before corresponding pa11 opcodes. Add strict pa10 register-immediate
808 2005-09-30 Catherine Moore <clm@cm00re.com>
812 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
814 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
816 2005-09-06 Chao-ying Fu <fu@mips.com>
818 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
819 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
821 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
822 (INSN_ASE_MASK): Update to include INSN_MT.
823 (INSN_MT): New define for MT ASE.
825 2005-08-25 Chao-ying Fu <fu@mips.com>
827 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
828 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
829 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
830 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
831 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
832 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
834 (INSN_DSP): New define for DSP ASE.
836 2005-08-18 Alan Modra <amodra@bigpond.net.au>
840 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
842 * ppc.h (PPC_OPCODE_E300): Define.
844 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
846 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
848 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
851 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
854 2005-07-27 Jan Beulich <jbeulich@novell.com>
856 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
857 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
858 Add movq-s as 64-bit variants of movd-s.
860 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
862 * hppa.h: Fix punctuation in comment.
864 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
865 implicit space-register addressing. Set space-register bits on opcodes
866 using implicit space-register addressing. Add various missing pa20
867 long-immediate opcodes. Remove various opcodes using implicit 3-bit
868 space-register addressing. Use "fE" instead of "fe" in various
871 2005-07-18 Jan Beulich <jbeulich@novell.com>
873 * i386.h (i386_optab): Operands of aam and aad are unsigned.
875 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
877 * i386.h (i386_optab): Support Intel VMX Instructions.
879 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
881 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
883 2005-07-05 Jan Beulich <jbeulich@novell.com>
885 * i386.h (i386_optab): Add new insns.
887 2005-07-01 Nick Clifton <nickc@redhat.com>
889 * sparc.h: Add typedefs to structure declarations.
891 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
894 * i386.h (i386_optab): Update comments for 64bit addressing on
895 mov. Allow 64bit addressing for mov and movq.
897 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
899 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
900 respectively, in various floating-point load and store patterns.
902 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
904 * hppa.h (FLAG_STRICT): Correct comment.
905 (pa_opcodes): Update load and store entries to allow both PA 1.X and
906 PA 2.0 mneumonics when equivalent. Entries with cache control
907 completers now require PA 1.1. Adjust whitespace.
909 2005-05-19 Anton Blanchard <anton@samba.org>
911 * ppc.h (PPC_OPCODE_POWER5): Define.
913 2005-05-10 Nick Clifton <nickc@redhat.com>
915 * Update the address and phone number of the FSF organization in
916 the GPL notices in the following files:
917 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
918 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
919 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
920 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
921 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
922 tic54x.h, tic80.h, v850.h, vax.h
924 2005-05-09 Jan Beulich <jbeulich@novell.com>
926 * i386.h (i386_optab): Add ht and hnt.
928 2005-04-18 Mark Kettenis <kettenis@gnu.org>
930 * i386.h: Insert hyphens into selected VIA PadLock extensions.
931 Add xcrypt-ctr. Provide aliases without hyphens.
933 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
935 Moved from ../ChangeLog
937 2005-04-12 Paul Brook <paul@codesourcery.com>
938 * m88k.h: Rename psr macros to avoid conflicts.
940 2005-03-12 Zack Weinberg <zack@codesourcery.com>
941 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
942 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
945 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
946 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
947 Remove redundant instruction types.
948 (struct argument): X_op - new field.
949 (struct cst4_entry): Remove.
950 (no_op_insn): Declare.
952 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
953 * crx.h (enum argtype): Rename types, remove unused types.
955 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
956 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
957 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
958 (enum operand_type): Rearrange operands, edit comments.
959 replace us<N> with ui<N> for unsigned immediate.
960 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
961 displacements (respectively).
962 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
963 (instruction type): Add NO_TYPE_INS.
964 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
965 (operand_entry): New field - 'flags'.
966 (operand flags): New.
968 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
969 * crx.h (operand_type): Remove redundant types i3, i4,
971 Add new unsigned immediate types us3, us4, us5, us16.
973 2005-04-12 Mark Kettenis <kettenis@gnu.org>
975 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
976 adjust them accordingly.
978 2005-04-01 Jan Beulich <jbeulich@novell.com>
980 * i386.h (i386_optab): Add rdtscp.
982 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
984 * i386.h (i386_optab): Don't allow the `l' suffix for moving
985 between memory and segment register. Allow movq for moving between
986 general-purpose register and segment register.
988 2005-02-09 Jan Beulich <jbeulich@novell.com>
991 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
992 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
995 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
997 * m68k.h (m68008, m68ec030, m68882): Remove.
999 (cpu_m68k, cpu_cf): New.
1000 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1001 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1003 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1005 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1006 * cgen.h (enum cgen_parse_operand_type): Add
1007 CGEN_PARSE_OPERAND_SYMBOLIC.
1009 2005-01-21 Fred Fish <fnf@specifixinc.com>
1011 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1012 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1013 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1015 2005-01-19 Fred Fish <fnf@specifixinc.com>
1017 * mips.h (struct mips_opcode): Add new pinfo2 member.
1018 (INSN_ALIAS): New define for opcode table entries that are
1019 specific instances of another entry, such as 'move' for an 'or'
1020 with a zero operand.
1021 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1022 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1024 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1026 * mips.h (CPU_RM9000): Define.
1027 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1029 2004-11-25 Jan Beulich <jbeulich@novell.com>
1031 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1032 to/from test registers are illegal in 64-bit mode. Add missing
1033 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1034 (previously one had to explicitly encode a rex64 prefix). Re-enable
1035 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1036 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1038 2004-11-23 Jan Beulich <jbeulich@novell.com>
1040 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1041 available only with SSE2. Change the MMX additions introduced by SSE
1042 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1043 instructions by their now designated identifier (since combining i686
1044 and 3DNow! does not really imply 3DNow!A).
1046 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1048 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1049 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1051 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1052 Vineet Sharma <vineets@noida.hcltech.com>
1054 * maxq.h: New file: Disassembly information for the maxq port.
1056 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1058 * i386.h (i386_optab): Put back "movzb".
1060 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1062 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1063 comments. Remove member cris_ver_sim. Add members
1064 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1065 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1066 (struct cris_support_reg, struct cris_cond15): New types.
1067 (cris_conds15): Declare.
1068 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1069 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1070 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1071 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1072 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1073 SIZE_FIELD_UNSIGNED.
1075 2004-11-04 Jan Beulich <jbeulich@novell.com>
1077 * i386.h (sldx_Suf): Remove.
1078 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1079 (q_FP): Define, implying no REX64.
1080 (x_FP, sl_FP): Imply FloatMF.
1081 (i386_optab): Split reg and mem forms of moving from segment registers
1082 so that the memory forms can ignore the 16-/32-bit operand size
1083 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1084 all non-floating-point instructions. Unite 32- and 64-bit forms of
1085 movsx, movzx, and movd. Adjust floating point operations for the above
1086 changes to the *FP macros. Add DefaultSize to floating point control
1087 insns operating on larger memory ranges. Remove left over comments
1088 hinting at certain insns being Intel-syntax ones where the ones
1089 actually meant are already gone.
1091 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1093 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1096 2004-09-30 Paul Brook <paul@codesourcery.com>
1098 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1099 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1101 2004-09-11 Theodore A. Roth <troth@openavr.org>
1103 * avr.h: Add support for
1104 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1106 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1108 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1110 2004-08-24 Dmitry Diky <diwil@spec.ru>
1112 * msp430.h (msp430_opc): Add new instructions.
1113 (msp430_rcodes): Declare new instructions.
1114 (msp430_hcodes): Likewise..
1116 2004-08-13 Nick Clifton <nickc@redhat.com>
1119 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1122 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1124 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1126 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1128 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1130 2004-07-21 Jan Beulich <jbeulich@novell.com>
1132 * i386.h: Adjust instruction descriptions to better match the
1135 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1137 * arm.h: Remove all old content. Replace with architecture defines
1138 from gas/config/tc-arm.c.
1140 2004-07-09 Andreas Schwab <schwab@suse.de>
1142 * m68k.h: Fix comment.
1144 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1148 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1150 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1152 2004-05-24 Peter Barada <peter@the-baradas.com>
1154 * m68k.h: Add 'size' to m68k_opcode.
1156 2004-05-05 Peter Barada <peter@the-baradas.com>
1158 * m68k.h: Switch from ColdFire chip name to core variant.
1160 2004-04-22 Peter Barada <peter@the-baradas.com>
1162 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1163 descriptions for new EMAC cases.
1164 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1165 handle Motorola MAC syntax.
1166 Allow disassembly of ColdFire V4e object files.
1168 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1170 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1172 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1174 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1176 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1178 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1180 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1182 * i386.h (i386_optab): Added xstore/xcrypt insns.
1184 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1186 * h8300.h (32bit ldc/stc): Add relaxing support.
1188 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1190 * h8300.h (BITOP): Pass MEMRELAX flag.
1192 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1194 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1197 For older changes see ChangeLog-9103
1203 version-control: never