1 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
3 * arm.h (ARM_EXT2_V8_2A): New.
6 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
8 * aarch64.h (AARCH64_FEATURE_V8_2): New.
9 (AARCH64_ARCH_V8_2): New.
11 2015-11-11 Alan Modra <amodra@gmail.com>
12 Peter Bergner <bergner@vnet.ibm.com>
14 * ppc.h (PPC_OPCODE_POWER9): New define.
15 (PPC_OPCODE_VSX3): Likewise.
17 2015-11-02 Nick Clifton <nickc@redhat.com>
19 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
21 2015-11-02 Nick Clifton <nickc@redhat.com>
23 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
25 2015-10-28 Yao Qi <yao.qi@linaro.org>
27 * aarch64.h (aarch64_decode_insn): Update declaration.
29 2015-10-07 Yao Qi <yao.qi@linaro.org>
31 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
34 2015-10-07 Yao Qi <yao.qi@linaro.org>
36 * aarch64.h [__cplusplus]: Wrap in extern "C".
38 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
39 Cupertino Miranda <cmiranda@synopsys.com>
41 * arc-func.h: New file.
44 2015-10-02 Yao Qi <yao.qi@linaro.org>
46 * aarch64.h (aarch64_zero_register_p): Move the declaration
49 2015-10-02 Yao Qi <yao.qi@linaro.org>
51 * aarch64.h (aarch64_decode_insn): Declare it.
53 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
55 * s390.h (S390_INSTR_FLAG_HTM): New flag.
56 (S390_INSTR_FLAG_VX): New flag.
57 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
59 2015-09-23 Nick Clifton <nickc@redhat.com>
61 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
64 2015-09-22 Nick Clifton <nickc@redhat.com>
66 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
68 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
70 * visium.h (gen_reg_table): Make static.
71 (fp_reg_table): Likewise.
74 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
76 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
77 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
78 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
79 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
81 2015-07-03 Alan Modra <amodra@gmail.com>
83 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
85 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
86 Cesar Philippidis <cesar@codesourcery.com>
88 * nios2.h (enum iw_format_type): Add R2 formats.
89 (enum overflow_type): Add signed_immed12_overflow and
90 enumeration_overflow for R2.
91 (struct nios2_opcode): Document new argument letters for R2.
92 (REG_3BIT, REG_LDWM, REG_POP): Define.
93 (includes): Include nios2r2.h.
94 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
95 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
96 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
97 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
98 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
99 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
101 * nios2r2.h: New file.
103 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
105 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
106 (ppc_optional_operand_value): New inline function.
108 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
110 * aarch64.h (AARCH64_V8_1): New.
112 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
114 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
115 (ARM_ARCH_V8_1A): New.
116 (ARM_ARCH_V8_1A_FP): New.
117 (ARM_ARCH_V8_1A_SIMD): New.
118 (ARM_ARCH_V8_1A_CRYPTOV1): New.
119 (ARM_FEATURE_CORE): New.
121 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
123 * arm.h (ARM_EXT2_PAN): New.
124 (ARM_FEATURE_CORE_HIGH): New.
126 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
128 * arm.h (ARM_FEATURE_ALL): New.
130 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
132 * aarch64.h (AARCH64_FEATURE_RDMA): New.
134 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
136 * aarch64.h (AARCH64_FEATURE_LOR): New.
138 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
140 * aarch64.h (AARCH64_FEATURE_PAN): New.
141 (aarch64_sys_reg_supported_p): Declare.
142 (aarch64_pstatefield_supported_p): Declare.
144 2015-04-30 DJ Delorie <dj@redhat.com>
146 * rl78.h (RL78_Dis_Isa): New.
147 (rl78_decode_opcode): Add ISA parameter.
149 2015-03-24 Terry Guo <terry.guo@arm.com>
151 * arm.h (arm_feature_set): Extended to provide more available bits.
152 (ARM_ANY): Updated to follow above new definition.
153 (ARM_CPU_HAS_FEATURE): Likewise.
154 (ARM_CPU_IS_ANY): Likewise.
155 (ARM_MERGE_FEATURE_SETS): Likewise.
156 (ARM_CLEAR_FEATURE): Likewise.
157 (ARM_FEATURE): Likewise.
158 (ARM_FEATURE_COPY): New macro.
159 (ARM_FEATURE_EQUAL): Likewise.
160 (ARM_FEATURE_ZERO): Likewise.
161 (ARM_FEATURE_CORE_EQUAL): Likewise.
162 (ARM_FEATURE_LOW): Likewise.
163 (ARM_FEATURE_CORE_LOW): Likewise.
164 (ARM_FEATURE_CORE_COPROC): Likewise.
166 2015-02-19 Pedro Alves <palves@redhat.com>
168 * cgen.h [__cplusplus]: Wrap in extern "C".
169 * msp430-decode.h [__cplusplus]: Likewise.
170 * nios2.h [__cplusplus]: Likewise.
171 * rl78.h [__cplusplus]: Likewise.
172 * rx.h [__cplusplus]: Likewise.
173 * tilegx.h [__cplusplus]: Likewise.
175 2015-01-28 James Bowman <james.bowman@ftdichip.com>
179 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
181 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
183 2015-01-01 Alan Modra <amodra@gmail.com>
185 Update year range in copyright notice of all files.
187 2014-12-27 Anthony Green <green@moxielogic.com>
189 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
190 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
192 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
194 * visium.h: New file.
196 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
198 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
199 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
200 (NIOS2_INSN_OPTARG): Renumber.
202 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
204 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
205 declaration. Fix obsolete comment.
207 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
209 * nios2.h (enum iw_format_type): New.
210 (struct nios2_opcode): Update comments. Add size and format fields.
211 (NIOS2_INSN_OPTARG): New.
212 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
213 (struct nios2_reg): Add regtype field.
214 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
215 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
216 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
217 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
218 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
219 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
220 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
221 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
222 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
223 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
224 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
225 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
226 (OP_MASK_OP, OP_SH_OP): Delete.
227 (OP_MASK_IOP, OP_SH_IOP): Delete.
228 (OP_MASK_IRD, OP_SH_IRD): Delete.
229 (OP_MASK_IRT, OP_SH_IRT): Delete.
230 (OP_MASK_IRS, OP_SH_IRS): Delete.
231 (OP_MASK_ROP, OP_SH_ROP): Delete.
232 (OP_MASK_RRD, OP_SH_RRD): Delete.
233 (OP_MASK_RRT, OP_SH_RRT): Delete.
234 (OP_MASK_RRS, OP_SH_RRS): Delete.
235 (OP_MASK_JOP, OP_SH_JOP): Delete.
236 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
237 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
238 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
239 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
240 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
241 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
242 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
243 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
244 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
245 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
246 (OP_MASK_<insn>, OP_MASK): Delete.
247 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
248 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
249 Include nios2r1.h to define new instruction opcode constants
251 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
252 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
253 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
254 (NUMOPCODES, NUMREGISTERS): Delete.
255 * nios2r1.h: New file.
257 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
259 * sparc.h (HWCAP2_VIS3B): Documentation improved.
261 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
263 * sparc.h (sparc_opcode): new field `hwcaps2'.
264 (HWCAP2_FJATHPLUS): New define.
265 (HWCAP2_VIS3B): Likewise.
266 (HWCAP2_ADP): Likewise.
267 (HWCAP2_SPARC5): Likewise.
268 (HWCAP2_MWAIT): Likewise.
269 (HWCAP2_XMPMUL): Likewise.
270 (HWCAP2_XMONT): Likewise.
271 (HWCAP2_NSEC): Likewise.
272 (HWCAP2_FJATHHPC): Likewise.
273 (HWCAP2_FJDES): Likewise.
274 (HWCAP2_FJAES): Likewise.
275 Document the new operand kind `{', corresponding to the mcdper
276 ancillary state register.
277 Document the new operand kind }, which represents frsd floating
278 point registers (double precision) which must be the same than
279 frs1 in its containing instruction.
281 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
283 * nds32.h: Add new opcode declaration.
285 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
286 Matthew Fortune <matthew.fortune@imgtec.com>
288 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
289 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
290 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
291 +I, +O, +R, +:, +\, +", +;
292 (mips_check_prev_operand): New struct.
293 (INSN2_FORBIDDEN_SLOT): New define.
294 (INSN_ISA32R6): New define.
295 (INSN_ISA64R6): New define.
296 (INSN_UPTO32R6): New define.
297 (INSN_UPTO64R6): New define.
298 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
299 (ISA_MIPS32R6): New define.
300 (ISA_MIPS64R6): New define.
301 (CPU_MIPS32R6): New define.
302 (CPU_MIPS64R6): New define.
303 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
305 2014-09-03 Jiong Wang <jiong.wang@arm.com>
307 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
308 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
309 (aarch64_insn_class): Add lse_atomic.
310 (F_LSE_SZ): New field added.
311 (opcode_has_special_coder): Recognize F_LSE_SZ.
313 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
315 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
318 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
320 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
321 (INSN_LOAD_COPROC): New define.
322 (INSN_COPROC_MOVE_DELAY): Rename to...
323 (INSN_COPROC_MOVE): New define.
325 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
326 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
327 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
328 Soundararajan <Sounderarajan.D@atmel.com>
330 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
331 (AVR_ISA_2xxxa): Define ISA without LPM.
332 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
333 Add doc for contraint used in 16 bit lds/sts.
334 Adjust ISA group for icall, ijmp, pop and push.
335 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
337 2014-05-19 Nick Clifton <nickc@redhat.com>
339 * msp430.h (struct msp430_operand_s): Add vshift field.
341 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
343 * mips.h (INSN_ISA_MASK): Updated.
344 (INSN_ISA32R3): New define.
345 (INSN_ISA32R5): New define.
346 (INSN_ISA64R3): New define.
347 (INSN_ISA64R5): New define.
348 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
349 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
350 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
352 (INSN_UPTO32R3): New define.
353 (INSN_UPTO32R5): New define.
354 (INSN_UPTO64R3): New define.
355 (INSN_UPTO64R5): New define.
356 (ISA_MIPS32R3): New define.
357 (ISA_MIPS32R5): New define.
358 (ISA_MIPS64R3): New define.
359 (ISA_MIPS64R5): New define.
360 (CPU_MIPS32R3): New define.
361 (CPU_MIPS32R5): New define.
362 (CPU_MIPS64R3): New define.
363 (CPU_MIPS64R5): New define.
365 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
367 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
369 2014-04-22 Christian Svensson <blue@cmd.nu>
373 2014-03-05 Alan Modra <amodra@gmail.com>
375 Update copyright years.
377 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
379 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
382 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
383 Wei-Cheng Wang <cole945@gmail.com>
385 * nds32.h: New file for Andes NDS32.
387 2013-12-07 Mike Frysinger <vapier@gentoo.org>
389 * bfin.h: Remove +x file mode.
391 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
393 * aarch64.h (aarch64_pstatefields): Change element type to
396 2013-11-18 Renlin Li <Renlin.Li@arm.com>
398 * arm.h (ARM_AEXT_V7VE): New define.
399 (ARM_ARCH_V7VE): New define.
400 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
402 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
406 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
408 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
409 (aarch64_sys_reg_writeonly_p): Ditto.
411 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
413 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
414 (aarch64_sys_reg_writeonly_p): Ditto.
416 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
418 * aarch64.h (aarch64_sys_reg): New typedef.
419 (aarch64_sys_regs): Change to define with the new type.
420 (aarch64_sys_reg_deprecated_p): Declare.
422 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
424 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
425 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
427 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
429 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
430 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
431 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
432 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
433 For MIPS, update extension character sequences after +.
434 (ASE_MSA): New define.
435 (ASE_MSA64): New define.
436 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
437 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
438 For microMIPS, update extension character sequences after +.
440 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
445 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
447 * mips.h: Remove references to "+I" and imm2_expr.
449 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h (M_DEXT, M_DINS): Delete.
453 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
456 (mips_optional_operand_p): New function.
458 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
459 Richard Sandiford <rdsandiford@googlemail.com>
461 * mips.h: Document new VU0 operand characters.
462 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
463 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
464 (OP_REG_R5900_ACC): New mips_reg_operand_types.
465 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
466 (mips_vu0_channel_mask): Declare.
468 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
470 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
471 (mips_int_operand_min, mips_int_operand_max): New functions.
472 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
474 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
476 * mips.h (mips_decode_reg_operand): New function.
477 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
478 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
479 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
481 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
482 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
483 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
484 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
485 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
486 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
487 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
488 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
489 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
490 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
491 macros to cover the gaps.
492 (INSN2_MOD_SP): Replace with...
493 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
494 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
495 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
496 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
497 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
500 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
502 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
503 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
504 (MIPS16_INSN_COND_BRANCH): Delete.
506 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
507 Kirill Yukhin <kirill.yukhin@intel.com>
508 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
510 * i386.h (BND_PREFIX_OPCODE): New.
512 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
514 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
515 OP_SAVE_RESTORE_LIST.
516 (decode_mips16_operand): Declare.
518 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
520 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
521 (mips_operand, mips_int_operand, mips_mapped_int_operand)
522 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
523 (mips_pcrel_operand): New structures.
524 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
525 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
526 (decode_mips_operand, decode_micromips_operand): Declare.
528 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
530 * mips.h: Document MIPS16 "I" opcode.
532 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
534 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
535 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
536 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
537 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
538 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
539 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
540 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
541 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
542 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
543 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
544 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
545 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
546 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
548 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
549 (M_USD_AB): ...these.
551 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
553 * mips.h: Remove documentation of "[" and "]". Update documentation
554 of "k" and the MDMX formats.
556 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
558 * mips.h: Update documentation of "+s" and "+S".
560 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
562 * mips.h: Document "+i".
564 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
566 * mips.h: Remove "mi" documentation. Update "mh" documentation.
567 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
569 (INSN2_WRITE_GPR_MHI): Rename to...
570 (INSN2_WRITE_GPR_MH): ...this.
572 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
574 * mips.h: Remove documentation of "+D" and "+T".
576 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
578 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
579 Use "source" rather than "destination" for microMIPS "G".
581 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
583 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
586 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
588 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
590 2013-06-17 Catherine Moore <clm@codesourcery.com>
591 Maciej W. Rozycki <macro@codesourcery.com>
592 Chao-Ying Fu <fu@mips.com>
594 * mips.h (OP_SH_EVAOFFSET): Define.
595 (OP_MASK_EVAOFFSET): Define.
596 (INSN_ASE_MASK): Delete.
598 (M_CACHEE_AB, M_CACHEE_OB): New.
599 (M_LBE_OB, M_LBE_AB): New.
600 (M_LBUE_OB, M_LBUE_AB): New.
601 (M_LHE_OB, M_LHE_AB): New.
602 (M_LHUE_OB, M_LHUE_AB): New.
603 (M_LLE_AB, M_LLE_OB): New.
604 (M_LWE_OB, M_LWE_AB): New.
605 (M_LWLE_AB, M_LWLE_OB): New.
606 (M_LWRE_AB, M_LWRE_OB): New.
607 (M_PREFE_AB, M_PREFE_OB): New.
608 (M_SCE_AB, M_SCE_OB): New.
609 (M_SBE_OB, M_SBE_AB): New.
610 (M_SHE_OB, M_SHE_AB): New.
611 (M_SWE_OB, M_SWE_AB): New.
612 (M_SWLE_AB, M_SWLE_OB): New.
613 (M_SWRE_AB, M_SWRE_OB): New.
614 (MICROMIPSOP_SH_EVAOFFSET): Define.
615 (MICROMIPSOP_MASK_EVAOFFSET): Define.
617 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
619 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
621 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
623 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
625 2013-05-09 Andrew Pinski <apinski@cavium.com>
627 * mips.h (OP_MASK_CODE10): Correct definition.
628 (OP_SH_CODE10): Likewise.
629 Add a comment that "+J" is used now for OP_*CODE10.
630 (INSN_ASE_MASK): Update.
631 (INSN_VIRT): New macro.
632 (INSN_VIRT64): New macro
634 2013-05-02 Nick Clifton <nickc@redhat.com>
636 * msp430.h: Add patterns for MSP430X instructions.
638 2013-04-06 David S. Miller <davem@davemloft.net>
640 * sparc.h (F_PREFERRED): Define.
641 (F_PREF_ALIAS): Define.
643 2013-04-03 Nick Clifton <nickc@redhat.com>
645 * v850.h (V850_INVERSE_PCREL): Define.
647 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
650 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
652 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
655 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
657 * tic6xc-opcode-table.h: Add 16-bit insns.
658 * tic6x.h: Add support for 16-bit insns.
660 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
662 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
663 and mov.b/w/l Rs,@(d:32,ERd).
665 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
668 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
669 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
670 tic6x_operand_xregpair operand coding type.
671 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
672 opcode field, usu ORXREGD1324 for the src2 operand and remove the
675 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
678 * tic6x.h (enum tic6x_coding_method): Add
679 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
680 separately the msb and lsb of a register pair. This is needed to
681 encode the opcodes in the same way as TI assembler does.
682 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
683 and rsqrdp opcodes to use the new field coding types.
685 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
687 * arm.h (CRC_EXT_ARMV8): New constant.
688 (ARCH_CRC_ARMV8): New macro.
690 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
692 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
694 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
695 Andrew Jenner <andrew@codesourcery.com>
697 Based on patches from Altera Corporation.
701 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
703 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
705 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
708 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
710 2013-01-24 Nick Clifton <nickc@redhat.com>
712 * v850.h: Add e3v5 support.
714 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
716 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
718 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
720 * ppc.h (PPC_OPCODE_POWER8): New define.
721 (PPC_OPCODE_HTM): Likewise.
723 2013-01-10 Will Newton <will.newton@imgtec.com>
727 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
729 * cr16.h (make_instruction): Rename to cr16_make_instruction.
730 (match_opcode): Rename to cr16_match_opcode.
732 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
734 * mips.h: Add support for r5900 instructions including lq and sq.
736 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
738 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
739 (make_instruction,match_opcode): Added function prototypes.
740 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
742 2012-11-23 Alan Modra <amodra@gmail.com>
744 * ppc.h (ppc_parse_cpu): Update prototype.
746 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
748 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
749 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
751 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
753 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
755 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
757 * ia64.h (ia64_opnd): Add new operand types.
759 2012-08-21 David S. Miller <davem@davemloft.net>
761 * sparc.h (F3F4): New macro.
763 2012-08-13 Ian Bolton <ian.bolton@arm.com>
764 Laurent Desnogues <laurent.desnogues@arm.com>
765 Jim MacArthur <jim.macarthur@arm.com>
766 Marcus Shawcroft <marcus.shawcroft@arm.com>
767 Nigel Stephens <nigel.stephens@arm.com>
768 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
769 Richard Earnshaw <rearnsha@arm.com>
770 Sofiane Naci <sofiane.naci@arm.com>
771 Tejas Belagod <tejas.belagod@arm.com>
772 Yufeng Zhang <yufeng.zhang@arm.com>
774 * aarch64.h: New file.
776 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
777 Maciej W. Rozycki <macro@codesourcery.com>
779 * mips.h (mips_opcode): Add the exclusions field.
780 (OPCODE_IS_MEMBER): Remove macro.
781 (cpu_is_member): New inline function.
782 (opcode_is_member): Likewise.
784 2012-07-31 Chao-Ying Fu <fu@mips.com>
785 Catherine Moore <clm@codesourcery.com>
786 Maciej W. Rozycki <macro@codesourcery.com>
788 * mips.h: Document microMIPS DSP ASE usage.
789 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
790 microMIPS DSP ASE support.
791 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
792 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
793 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
794 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
795 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
796 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
797 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
799 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
801 * mips.h: Fix a typo in description.
803 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
805 * avr.h: (AVR_ISA_XCH): New define.
806 (AVR_ISA_XMEGA): Use it.
807 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
809 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
811 * m68hc11.h: Add XGate definitions.
812 (struct m68hc11_opcode): Add xg_mask field.
814 2012-05-14 Catherine Moore <clm@codesourcery.com>
815 Maciej W. Rozycki <macro@codesourcery.com>
816 Rhonda Wittels <rhonda@codesourcery.com>
818 * ppc.h (PPC_OPCODE_VLE): New definition.
819 (PPC_OP_SA): New macro.
820 (PPC_OP_SE_VLE): New macro.
821 (PPC_OP): Use a variable shift amount.
822 (powerpc_operand): Update comments.
823 (PPC_OPSHIFT_INV): New macro.
824 (PPC_OPERAND_CR): Replace with...
825 (PPC_OPERAND_CR_BIT): ...this and
826 (PPC_OPERAND_CR_REG): ...this.
829 2012-05-03 Sean Keys <skeys@ipdatasys.com>
831 * xgate.h: Header file for XGATE assembler.
833 2012-04-27 David S. Miller <davem@davemloft.net>
835 * sparc.h: Document new arg code' )' for crypto RS3
838 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
839 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
840 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
841 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
842 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
843 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
844 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
845 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
846 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
847 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
848 HWCAP_CBCOND, HWCAP_CRC32): New defines.
850 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
852 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
854 2012-02-27 Alan Modra <amodra@gmail.com>
856 * crx.h (cst4_map): Update declaration.
858 2012-02-25 Walter Lee <walt@tilera.com>
860 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
862 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
863 TILEPRO_OPC_LW_TLS_SN.
865 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
867 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
868 (XRELEASE_PREFIX_OPCODE): Likewise.
870 2011-12-08 Andrew Pinski <apinski@cavium.com>
871 Adam Nemet <anemet@caviumnetworks.com>
873 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
874 (INSN_OCTEON2): New macro.
875 (CPU_OCTEON2): New macro.
876 (OPCODE_IS_MEMBER): Add Octeon2.
878 2011-11-29 Andrew Pinski <apinski@cavium.com>
880 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
881 (INSN_OCTEONP): New macro.
882 (CPU_OCTEONP): New macro.
883 (OPCODE_IS_MEMBER): Add Octeon+.
884 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
886 2011-11-01 DJ Delorie <dj@redhat.com>
890 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
892 * mips.h: Fix a typo in description.
894 2011-09-21 David S. Miller <davem@davemloft.net>
896 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
897 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
898 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
899 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
901 2011-08-09 Chao-ying Fu <fu@mips.com>
902 Maciej W. Rozycki <macro@codesourcery.com>
904 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
905 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
906 (INSN_ASE_MASK): Add the MCU bit.
907 (INSN_MCU): New macro.
908 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
909 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
911 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
913 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
914 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
915 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
916 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
917 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
918 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
919 (INSN2_READ_GPR_MMN): Likewise.
920 (INSN2_READ_FPR_D): Change the bit used.
921 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
922 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
923 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
924 (INSN2_COND_BRANCH): Likewise.
925 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
926 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
927 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
928 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
929 (INSN2_MOD_GPR_MN): Likewise.
931 2011-08-05 David S. Miller <davem@davemloft.net>
933 * sparc.h: Document new format codes '4', '5', and '('.
934 (OPF_LOW4, RS3): New macros.
936 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
938 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
939 order of flags documented.
941 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
943 * mips.h: Clarify the description of microMIPS instruction
945 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
947 2011-07-24 Chao-ying Fu <fu@mips.com>
948 Maciej W. Rozycki <macro@codesourcery.com>
950 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
951 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
952 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
953 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
954 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
955 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
956 (OP_MASK_RS3, OP_SH_RS3): Likewise.
957 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
958 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
959 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
960 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
961 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
962 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
963 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
964 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
965 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
966 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
967 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
968 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
969 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
970 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
971 (INSN_WRITE_GPR_S): New macro.
972 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
973 (INSN2_READ_FPR_D): Likewise.
974 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
975 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
976 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
977 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
978 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
979 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
980 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
981 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
982 (CPU_MICROMIPS): New macro.
983 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
984 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
985 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
986 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
987 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
988 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
989 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
990 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
991 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
992 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
993 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
994 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
995 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
996 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
997 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
998 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
999 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1000 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1001 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1002 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1003 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1004 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1005 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1006 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1007 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1008 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1009 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1010 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1011 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1012 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1013 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1014 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1015 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1016 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1017 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1018 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1019 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1020 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1021 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1022 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1023 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1024 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1025 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1026 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1027 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1028 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1029 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1030 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1031 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1032 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1033 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1034 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1035 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1036 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1037 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1038 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1039 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1040 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1041 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1042 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1043 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1044 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1045 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1046 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1047 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1048 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1049 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1050 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1051 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1052 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1053 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1054 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1055 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1056 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1057 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1058 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1059 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1060 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1061 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1062 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1063 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1064 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1065 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1066 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1067 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1068 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1069 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1070 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1071 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1072 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1073 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1074 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1075 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1076 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1077 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1078 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1079 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1080 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1081 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1082 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1083 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1084 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1085 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1086 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1087 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1088 (micromips_opcodes): New declaration.
1089 (bfd_micromips_num_opcodes): Likewise.
1091 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1093 * mips.h (INSN_TRAP): Rename to...
1094 (INSN_NO_DELAY_SLOT): ... this.
1095 (INSN_SYNC): Remove macro.
1097 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1099 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1100 a duplicate of AVR_ISA_SPM.
1102 2011-07-01 Nick Clifton <nickc@redhat.com>
1104 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1106 2011-06-18 Robin Getz <robin.getz@analog.com>
1108 * bfin.h (is_macmod_signed): New func
1110 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1112 * bfin.h (is_macmod_pmove): Add missing space before func args.
1113 (is_macmod_hmove): Likewise.
1115 2011-06-13 Walter Lee <walt@tilera.com>
1117 * tilegx.h: New file.
1118 * tilepro.h: New file.
1120 2011-05-31 Paul Brook <paul@codesourcery.com>
1122 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1124 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1126 * s390.h: Replace S390_OPERAND_REG_EVEN with
1127 S390_OPERAND_REG_PAIR.
1129 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1131 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1133 2011-04-18 Julian Brown <julian@codesourcery.com>
1135 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1137 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1140 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1142 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1144 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1145 New instruction set flags.
1146 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1148 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1150 * mips.h (M_PREF_AB): New enum value.
1152 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1154 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1156 (is_macmod_pmove, is_macmod_hmove): New functions.
1158 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1160 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1162 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1164 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1165 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1167 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1170 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1173 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1176 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1178 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1180 * mips.h: Update commentary after last commit.
1182 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1184 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1185 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1186 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1188 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1190 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1192 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1194 * mips.h: Fix previous commit.
1196 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1198 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1199 (INSN_LOONGSON_3A): Clear bit 31.
1201 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1204 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1205 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1206 (ARM_ARCH_V6M_ONLY): New define.
1208 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1210 * mips.h (INSN_LOONGSON_3A): Defined.
1211 (CPU_LOONGSON_3A): Defined.
1212 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1214 2010-10-09 Matt Rice <ratmice@gmail.com>
1216 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1217 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1219 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1221 * arm.h (ARM_EXT_VIRT): New define.
1222 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1223 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1226 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1228 * arm.h (ARM_AEXT_ADIV): New define.
1229 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1231 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1233 * arm.h (ARM_EXT_OS): New define.
1234 (ARM_AEXT_V6SM): Likewise.
1235 (ARM_ARCH_V6SM): Likewise.
1237 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1239 * arm.h (ARM_EXT_MP): Add.
1240 (ARM_ARCH_V7A_MP): Likewise.
1242 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1244 * bfin.h: Declare pseudoChr structs/defines.
1246 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1248 * bfin.h: Strip trailing whitespace.
1250 2010-07-29 DJ Delorie <dj@redhat.com>
1252 * rx.h (RX_Operand_Type): Add TwoReg.
1253 (RX_Opcode_ID): Remove ediv and ediv2.
1255 2010-07-27 DJ Delorie <dj@redhat.com>
1257 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1259 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1260 Ina Pandit <ina.pandit@kpitcummins.com>
1262 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1263 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1264 PROCESSOR_V850E2_ALL.
1265 Remove PROCESSOR_V850EA support.
1266 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1267 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1268 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1269 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1270 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1271 V850_OPERAND_PERCENT.
1272 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1274 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1277 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1279 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1280 (MIPS16_INSN_BRANCH): Rename to...
1281 (MIPS16_INSN_COND_BRANCH): ... this.
1283 2010-07-03 Alan Modra <amodra@gmail.com>
1285 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1286 Renumber other PPC_OPCODE defines.
1288 2010-07-03 Alan Modra <amodra@gmail.com>
1290 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1292 2010-06-29 Alan Modra <amodra@gmail.com>
1294 * maxq.h: Delete file.
1296 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1298 * ppc.h (PPC_OPCODE_E500): Define.
1300 2010-05-26 Catherine Moore <clm@codesourcery.com>
1302 * opcode/mips.h (INSN_MIPS16): Remove.
1304 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1306 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1308 2010-04-15 Nick Clifton <nickc@redhat.com>
1310 * alpha.h: Update copyright notice to use GPLv3.
1316 * convex.h: Likewise.
1323 * h8300.h: Likewise.
1330 * m68hc11.h: Likewise.
1336 * mn10200.h: Likewise.
1337 * mn10300.h: Likewise.
1338 * msp430.h: Likewise.
1340 * ns32k.h: Likewise.
1342 * pdp11.h: Likewise.
1349 * score-datadep.h: Likewise.
1350 * score-inst.h: Likewise.
1351 * sparc.h: Likewise.
1352 * spu-insns.h: Likewise.
1354 * tic30.h: Likewise.
1355 * tic4x.h: Likewise.
1356 * tic54x.h: Likewise.
1357 * tic80.h: Likewise.
1361 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1363 * tic6x-control-registers.h, tic6x-insn-formats.h,
1364 tic6x-opcode-table.h, tic6x.h: New.
1366 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1368 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1370 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1372 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1374 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1376 * ia64.h (ia64_find_opcode): Remove argument name.
1377 (ia64_find_next_opcode): Likewise.
1378 (ia64_dis_opcode): Likewise.
1379 (ia64_free_opcode): Likewise.
1380 (ia64_find_dependency): Likewise.
1382 2009-11-22 Doug Evans <dje@sebabeach.org>
1384 * cgen.h: Include bfd_stdint.h.
1385 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1387 2009-11-18 Paul Brook <paul@codesourcery.com>
1389 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1391 2009-11-17 Paul Brook <paul@codesourcery.com>
1392 Daniel Jacobowitz <dan@codesourcery.com>
1394 * arm.h (ARM_EXT_V6_DSP): Define.
1395 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1396 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1398 2009-11-04 DJ Delorie <dj@redhat.com>
1400 * rx.h (rx_decode_opcode) (mvtipl): Add.
1401 (mvtcp, mvfcp, opecp): Remove.
1403 2009-11-02 Paul Brook <paul@codesourcery.com>
1405 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1406 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1407 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1408 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1409 FPU_ARCH_NEON_VFP_V4): Define.
1411 2009-10-23 Doug Evans <dje@sebabeach.org>
1413 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1414 * cgen.h: Update. Improve multi-inclusion macro name.
1416 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1418 * ppc.h (PPC_OPCODE_476): Define.
1420 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1422 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1424 2009-09-29 DJ Delorie <dj@redhat.com>
1428 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1430 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1432 2009-09-21 Ben Elliston <bje@au.ibm.com>
1434 * ppc.h (PPC_OPCODE_PPCA2): New.
1436 2009-09-05 Martin Thuresson <martin@mtme.org>
1438 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1440 2009-08-29 Martin Thuresson <martin@mtme.org>
1442 * tic30.h (template): Rename type template to
1443 insn_template. Updated code to use new name.
1444 * tic54x.h (template): Rename type template to
1447 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1449 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1451 2009-06-11 Anthony Green <green@moxielogic.com>
1453 * moxie.h (MOXIE_F3_PCREL): Define.
1454 (moxie_form3_opc_info): Grow.
1456 2009-06-06 Anthony Green <green@moxielogic.com>
1458 * moxie.h (MOXIE_F1_M): Define.
1460 2009-04-15 Anthony Green <green@moxielogic.com>
1464 2009-04-06 DJ Delorie <dj@redhat.com>
1466 * h8300.h: Add relaxation attributes to MOVA opcodes.
1468 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1470 * ppc.h (ppc_parse_cpu): Declare.
1472 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1474 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1475 and _IMM11 for mbitclr and mbitset.
1476 * score-datadep.h: Update dependency information.
1478 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1480 * ppc.h (PPC_OPCODE_POWER7): New.
1482 2009-02-06 Doug Evans <dje@google.com>
1484 * i386.h: Add comment regarding sse* insns and prefixes.
1486 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1488 * mips.h (INSN_XLR): Define.
1489 (INSN_CHIP_MASK): Update.
1491 (OPCODE_IS_MEMBER): Update.
1492 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1494 2009-01-28 Doug Evans <dje@google.com>
1496 * opcode/i386.h: Add multiple inclusion protection.
1497 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1498 (EDI_REG_NUM): New macros.
1499 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1500 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1501 (REX_PREFIX_P): New macro.
1503 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1505 * ppc.h (struct powerpc_opcode): New field "deprecated".
1506 (PPC_OPCODE_NOPOWER4): Delete.
1508 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1510 * mips.h: Define CPU_R14000, CPU_R16000.
1511 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1513 2008-11-18 Catherine Moore <clm@codesourcery.com>
1515 * arm.h (FPU_NEON_FP16): New.
1516 (FPU_ARCH_NEON_FP16): New.
1518 2008-11-06 Chao-ying Fu <fu@mips.com>
1520 * mips.h: Doucument '1' for 5-bit sync type.
1522 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1524 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1527 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1529 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1531 2008-07-30 Michael J. Eager <eager@eagercon.com>
1533 * ppc.h (PPC_OPCODE_405): Define.
1534 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1536 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1538 * ppc.h (ppc_cpu_t): New typedef.
1539 (struct powerpc_opcode <flags>): Use it.
1540 (struct powerpc_operand <insert, extract>): Likewise.
1541 (struct powerpc_macro <flags>): Likewise.
1543 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1545 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1546 Update comment before MIPS16 field descriptors to mention MIPS16.
1547 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1549 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1550 New bit masks and shift counts for cins and exts.
1552 * mips.h: Document new field descriptors +Q.
1553 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1555 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1557 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1558 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1560 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1562 * ppc.h: (PPC_OPCODE_E500MC): New.
1564 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1566 * i386.h (MAX_OPERANDS): Set to 5.
1567 (MAX_MNEM_SIZE): Changed to 20.
1569 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1571 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1573 2008-03-09 Paul Brook <paul@codesourcery.com>
1575 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1577 2008-03-04 Paul Brook <paul@codesourcery.com>
1579 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1580 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1581 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1583 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1584 Nick Clifton <nickc@redhat.com>
1587 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1588 with a 32-bit displacement but without the top bit of the 4th byte
1591 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1593 * cr16.h (cr16_num_optab): Declared.
1595 2008-02-14 Hakan Ardo <hakan@debian.org>
1598 * avr.h (AVR_ISA_2xxe): Define.
1600 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1602 * mips.h: Update copyright.
1603 (INSN_CHIP_MASK): New macro.
1604 (INSN_OCTEON): New macro.
1605 (CPU_OCTEON): New macro.
1606 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1608 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1610 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1612 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1614 * avr.h (AVR_ISA_USB162): Add new opcode set.
1615 (AVR_ISA_AVR3): Likewise.
1617 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1619 * mips.h (INSN_LOONGSON_2E): New.
1620 (INSN_LOONGSON_2F): New.
1621 (CPU_LOONGSON_2E): New.
1622 (CPU_LOONGSON_2F): New.
1623 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1625 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1627 * mips.h (INSN_ISA*): Redefine certain values as an
1628 enumeration. Update comments.
1629 (mips_isa_table): New.
1630 (ISA_MIPS*): Redefine to match enumeration.
1631 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1634 2007-08-08 Ben Elliston <bje@au.ibm.com>
1636 * ppc.h (PPC_OPCODE_PPCPS): New.
1638 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1640 * m68k.h: Document j K & E.
1642 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1644 * cr16.h: New file for CR16 target.
1646 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1648 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1650 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1652 * m68k.h (mcfisa_c): New.
1653 (mcfusp, mcf_mask): Adjust.
1655 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1657 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1658 (num_powerpc_operands): Declare.
1659 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1660 (PPC_OPERAND_PLUS1): Define.
1662 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1664 * i386.h (REX_MODE64): Renamed to ...
1666 (REX_EXTX): Renamed to ...
1668 (REX_EXTY): Renamed to ...
1670 (REX_EXTZ): Renamed to ...
1673 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1675 * i386.h: Add entries from config/tc-i386.h and move tables
1676 to opcodes/i386-opc.h.
1678 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1680 * i386.h (FloatDR): Removed.
1681 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1683 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1685 * spu-insns.h: Add soma double-float insns.
1687 2007-02-20 Thiemo Seufer <ths@mips.com>
1688 Chao-Ying Fu <fu@mips.com>
1690 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1691 (INSN_DSPR2): Add flag for DSP R2 instructions.
1692 (M_BALIGN): New macro.
1694 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1696 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1697 and Seg3ShortFrom with Shortform.
1699 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1702 * i386.h (i386_optab): Put the real "test" before the pseudo
1705 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1707 * m68k.h (m68010up): OR fido_a.
1709 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1711 * m68k.h (fido_a): New.
1713 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1715 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1716 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1719 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1721 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1723 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1725 * score-inst.h (enum score_insn_type): Add Insn_internal.
1727 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1728 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1729 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1730 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1731 Alan Modra <amodra@bigpond.net.au>
1733 * spu-insns.h: New file.
1736 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1738 * ppc.h (PPC_OPCODE_CELL): Define.
1740 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1742 * i386.h : Modify opcode to support for the change in POPCNT opcode
1743 in amdfam10 architecture.
1745 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386.h: Replace CpuMNI with CpuSSSE3.
1749 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1750 Joseph Myers <joseph@codesourcery.com>
1751 Ian Lance Taylor <ian@wasabisystems.com>
1752 Ben Elliston <bje@wasabisystems.com>
1754 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1756 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1758 * score-datadep.h: New file.
1759 * score-inst.h: New file.
1761 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1763 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1764 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1765 movdq2q and movq2dq.
1767 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1768 Michael Meissner <michael.meissner@amd.com>
1770 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1772 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1774 * i386.h (i386_optab): Add "nop" with memory reference.
1776 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1778 * i386.h (i386_optab): Update comment for 64bit NOP.
1780 2006-06-06 Ben Elliston <bje@au.ibm.com>
1781 Anton Blanchard <anton@samba.org>
1783 * ppc.h (PPC_OPCODE_POWER6): Define.
1786 2006-06-05 Thiemo Seufer <ths@mips.com>
1788 * mips.h: Improve description of MT flags.
1790 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1792 * m68k.h (mcf_mask): Define.
1794 2006-05-05 Thiemo Seufer <ths@mips.com>
1795 David Ung <davidu@mips.com>
1797 * mips.h (enum): Add macro M_CACHE_AB.
1799 2006-05-04 Thiemo Seufer <ths@mips.com>
1800 Nigel Stephens <nigel@mips.com>
1801 David Ung <davidu@mips.com>
1803 * mips.h: Add INSN_SMARTMIPS define.
1805 2006-04-30 Thiemo Seufer <ths@mips.com>
1806 David Ung <davidu@mips.com>
1808 * mips.h: Defines udi bits and masks. Add description of
1809 characters which may appear in the args field of udi
1812 2006-04-26 Thiemo Seufer <ths@networkno.de>
1814 * mips.h: Improve comments describing the bitfield instruction
1817 2006-04-26 Julian Brown <julian@codesourcery.com>
1819 * arm.h (FPU_VFP_EXT_V3): Define constant.
1820 (FPU_NEON_EXT_V1): Likewise.
1821 (FPU_VFP_HARD): Update.
1822 (FPU_VFP_V3): Define macro.
1823 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1825 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1827 * avr.h (AVR_ISA_PWMx): New.
1829 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1831 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1832 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1833 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1834 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1835 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1837 2006-03-10 Paul Brook <paul@codesourcery.com>
1839 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1841 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1843 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1844 first. Correct mask of bb "B" opcode.
1846 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1848 * i386.h (i386_optab): Support Intel Merom New Instructions.
1850 2006-02-24 Paul Brook <paul@codesourcery.com>
1852 * arm.h: Add V7 feature bits.
1854 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1856 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1858 2006-01-31 Paul Brook <paul@codesourcery.com>
1859 Richard Earnshaw <rearnsha@arm.com>
1861 * arm.h: Use ARM_CPU_FEATURE.
1862 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1863 (arm_feature_set): Change to a structure.
1864 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1865 ARM_FEATURE): New macros.
1867 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1869 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1870 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1871 (ADD_PC_INCR_OPCODE): Don't define.
1873 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1876 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1878 2005-11-14 David Ung <davidu@mips.com>
1880 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1881 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1882 save/restore encoding of the args field.
1884 2005-10-28 Dave Brolley <brolley@redhat.com>
1886 Contribute the following changes:
1887 2005-02-16 Dave Brolley <brolley@redhat.com>
1889 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1890 cgen_isa_mask_* to cgen_bitset_*.
1893 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1895 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1896 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1897 (CGEN_CPU_TABLE): Make isas a ponter.
1899 2003-09-29 Dave Brolley <brolley@redhat.com>
1901 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1902 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1903 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1905 2002-12-13 Dave Brolley <brolley@redhat.com>
1907 * cgen.h (symcat.h): #include it.
1908 (cgen-bitset.h): #include it.
1909 (CGEN_ATTR_VALUE_TYPE): Now a union.
1910 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1911 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1912 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1913 * cgen-bitset.h: New file.
1915 2005-09-30 Catherine Moore <clm@cm00re.com>
1919 2005-10-24 Jan Beulich <jbeulich@novell.com>
1921 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1924 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1926 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1927 Add FLAG_STRICT to pa10 ftest opcode.
1929 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1931 * hppa.h (pa_opcodes): Remove lha entries.
1933 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1935 * hppa.h (FLAG_STRICT): Revise comment.
1936 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1937 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1940 2005-09-30 Catherine Moore <clm@cm00re.com>
1944 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1946 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1948 2005-09-06 Chao-ying Fu <fu@mips.com>
1950 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1951 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1953 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1954 (INSN_ASE_MASK): Update to include INSN_MT.
1955 (INSN_MT): New define for MT ASE.
1957 2005-08-25 Chao-ying Fu <fu@mips.com>
1959 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1960 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1961 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1962 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1963 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1964 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1966 (INSN_DSP): New define for DSP ASE.
1968 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1972 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1974 * ppc.h (PPC_OPCODE_E300): Define.
1976 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1978 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1980 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1983 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1986 2005-07-27 Jan Beulich <jbeulich@novell.com>
1988 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1989 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1990 Add movq-s as 64-bit variants of movd-s.
1992 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1994 * hppa.h: Fix punctuation in comment.
1996 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1997 implicit space-register addressing. Set space-register bits on opcodes
1998 using implicit space-register addressing. Add various missing pa20
1999 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2000 space-register addressing. Use "fE" instead of "fe" in various
2003 2005-07-18 Jan Beulich <jbeulich@novell.com>
2005 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2007 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2009 * i386.h (i386_optab): Support Intel VMX Instructions.
2011 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2013 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2015 2005-07-05 Jan Beulich <jbeulich@novell.com>
2017 * i386.h (i386_optab): Add new insns.
2019 2005-07-01 Nick Clifton <nickc@redhat.com>
2021 * sparc.h: Add typedefs to structure declarations.
2023 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2026 * i386.h (i386_optab): Update comments for 64bit addressing on
2027 mov. Allow 64bit addressing for mov and movq.
2029 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2031 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2032 respectively, in various floating-point load and store patterns.
2034 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2036 * hppa.h (FLAG_STRICT): Correct comment.
2037 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2038 PA 2.0 mneumonics when equivalent. Entries with cache control
2039 completers now require PA 1.1. Adjust whitespace.
2041 2005-05-19 Anton Blanchard <anton@samba.org>
2043 * ppc.h (PPC_OPCODE_POWER5): Define.
2045 2005-05-10 Nick Clifton <nickc@redhat.com>
2047 * Update the address and phone number of the FSF organization in
2048 the GPL notices in the following files:
2049 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2050 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2051 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2052 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2053 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2054 tic54x.h, tic80.h, v850.h, vax.h
2056 2005-05-09 Jan Beulich <jbeulich@novell.com>
2058 * i386.h (i386_optab): Add ht and hnt.
2060 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2062 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2063 Add xcrypt-ctr. Provide aliases without hyphens.
2065 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2067 Moved from ../ChangeLog
2069 2005-04-12 Paul Brook <paul@codesourcery.com>
2070 * m88k.h: Rename psr macros to avoid conflicts.
2072 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2073 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2074 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2075 and ARM_ARCH_V6ZKT2.
2077 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2078 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2079 Remove redundant instruction types.
2080 (struct argument): X_op - new field.
2081 (struct cst4_entry): Remove.
2082 (no_op_insn): Declare.
2084 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2085 * crx.h (enum argtype): Rename types, remove unused types.
2087 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2088 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2089 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2090 (enum operand_type): Rearrange operands, edit comments.
2091 replace us<N> with ui<N> for unsigned immediate.
2092 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2093 displacements (respectively).
2094 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2095 (instruction type): Add NO_TYPE_INS.
2096 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2097 (operand_entry): New field - 'flags'.
2098 (operand flags): New.
2100 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2101 * crx.h (operand_type): Remove redundant types i3, i4,
2103 Add new unsigned immediate types us3, us4, us5, us16.
2105 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2107 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2108 adjust them accordingly.
2110 2005-04-01 Jan Beulich <jbeulich@novell.com>
2112 * i386.h (i386_optab): Add rdtscp.
2114 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2116 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2117 between memory and segment register. Allow movq for moving between
2118 general-purpose register and segment register.
2120 2005-02-09 Jan Beulich <jbeulich@novell.com>
2123 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2124 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2127 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2129 * m68k.h (m68008, m68ec030, m68882): Remove.
2131 (cpu_m68k, cpu_cf): New.
2132 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2133 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2135 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2137 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2138 * cgen.h (enum cgen_parse_operand_type): Add
2139 CGEN_PARSE_OPERAND_SYMBOLIC.
2141 2005-01-21 Fred Fish <fnf@specifixinc.com>
2143 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2144 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2145 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2147 2005-01-19 Fred Fish <fnf@specifixinc.com>
2149 * mips.h (struct mips_opcode): Add new pinfo2 member.
2150 (INSN_ALIAS): New define for opcode table entries that are
2151 specific instances of another entry, such as 'move' for an 'or'
2152 with a zero operand.
2153 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2154 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2156 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2158 * mips.h (CPU_RM9000): Define.
2159 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2161 2004-11-25 Jan Beulich <jbeulich@novell.com>
2163 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2164 to/from test registers are illegal in 64-bit mode. Add missing
2165 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2166 (previously one had to explicitly encode a rex64 prefix). Re-enable
2167 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2168 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2170 2004-11-23 Jan Beulich <jbeulich@novell.com>
2172 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2173 available only with SSE2. Change the MMX additions introduced by SSE
2174 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2175 instructions by their now designated identifier (since combining i686
2176 and 3DNow! does not really imply 3DNow!A).
2178 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2180 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2181 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2183 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2184 Vineet Sharma <vineets@noida.hcltech.com>
2186 * maxq.h: New file: Disassembly information for the maxq port.
2188 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2190 * i386.h (i386_optab): Put back "movzb".
2192 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2194 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2195 comments. Remove member cris_ver_sim. Add members
2196 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2197 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2198 (struct cris_support_reg, struct cris_cond15): New types.
2199 (cris_conds15): Declare.
2200 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2201 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2202 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2203 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2204 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2205 SIZE_FIELD_UNSIGNED.
2207 2004-11-04 Jan Beulich <jbeulich@novell.com>
2209 * i386.h (sldx_Suf): Remove.
2210 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2211 (q_FP): Define, implying no REX64.
2212 (x_FP, sl_FP): Imply FloatMF.
2213 (i386_optab): Split reg and mem forms of moving from segment registers
2214 so that the memory forms can ignore the 16-/32-bit operand size
2215 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2216 all non-floating-point instructions. Unite 32- and 64-bit forms of
2217 movsx, movzx, and movd. Adjust floating point operations for the above
2218 changes to the *FP macros. Add DefaultSize to floating point control
2219 insns operating on larger memory ranges. Remove left over comments
2220 hinting at certain insns being Intel-syntax ones where the ones
2221 actually meant are already gone.
2223 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2225 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2228 2004-09-30 Paul Brook <paul@codesourcery.com>
2230 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2231 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2233 2004-09-11 Theodore A. Roth <troth@openavr.org>
2235 * avr.h: Add support for
2236 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2238 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2240 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2242 2004-08-24 Dmitry Diky <diwil@spec.ru>
2244 * msp430.h (msp430_opc): Add new instructions.
2245 (msp430_rcodes): Declare new instructions.
2246 (msp430_hcodes): Likewise..
2248 2004-08-13 Nick Clifton <nickc@redhat.com>
2251 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2254 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2256 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2258 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2260 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2262 2004-07-21 Jan Beulich <jbeulich@novell.com>
2264 * i386.h: Adjust instruction descriptions to better match the
2267 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2269 * arm.h: Remove all old content. Replace with architecture defines
2270 from gas/config/tc-arm.c.
2272 2004-07-09 Andreas Schwab <schwab@suse.de>
2274 * m68k.h: Fix comment.
2276 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2280 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2282 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2284 2004-05-24 Peter Barada <peter@the-baradas.com>
2286 * m68k.h: Add 'size' to m68k_opcode.
2288 2004-05-05 Peter Barada <peter@the-baradas.com>
2290 * m68k.h: Switch from ColdFire chip name to core variant.
2292 2004-04-22 Peter Barada <peter@the-baradas.com>
2294 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2295 descriptions for new EMAC cases.
2296 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2297 handle Motorola MAC syntax.
2298 Allow disassembly of ColdFire V4e object files.
2300 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2302 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2304 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2306 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2308 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2310 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2312 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2314 * i386.h (i386_optab): Added xstore/xcrypt insns.
2316 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2318 * h8300.h (32bit ldc/stc): Add relaxing support.
2320 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2322 * h8300.h (BITOP): Pass MEMRELAX flag.
2324 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2326 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2329 For older changes see ChangeLog-9103
2331 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2333 Copying and distribution of this file, with or without modification,
2334 are permitted in any medium without royalty provided the copyright
2335 notice and this notice are preserved.
2341 version-control: never
projects / deliverable / binutils-gdb.git / blob