include/opcode/ChangeLog

   1 2008-02-27  Markus Gyger  <markus+sw@gyger.org>
   2             Nick Clifton  <nickc@redhat.com>
   3
   4         PR 3134
   5         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
   6         with a 32-bit displacement but without the top bit of the 4th byte
   7         set.
   8
   9 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  10
  11         * cr16.h (cr16_num_optab): Declared.
  12
  13 2008-02-14  Hakan Ardo  <hakan@debian.org>
  14
  15         PR gas/2626
  16         * avr.h (AVR_ISA_2xxe): Define.
  17
  18 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  19
  20         * mips.h: Update copyright.
  21         (INSN_CHIP_MASK): New macro.
  22         (INSN_OCTEON): New macro.
  23         (CPU_OCTEON): New macro.
  24         (OPCODE_IS_MEMBER): Handle Octeon instructions.
  25
  26 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  27
  28         * mips.h (INSN_LOONGSON_2E): New.
  29         (INSN_LOONGSON_2F): New.
  30         (CPU_LOONGSON_2E): New.
  31         (CPU_LOONGSON_2F): New.
  32         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
  33
  34 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  35
  36         * mips.h (INSN_ISA*): Redefine certain values as an
  37         enumeration.  Update comments.
  38         (mips_isa_table): New.
  39         (ISA_MIPS*): Redefine to match enumeration.
  40         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  41         values.
  42
  43 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  44
  45         * ppc.h (PPC_OPCODE_PPCPS): New.
  46
  47 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  48
  49         * m68k.h: Document j K & E.
  50
  51 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  52
  53         * cr16.h: New file for CR16 target.
  54
  55 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  56
  57         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  58
  59 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  60
  61         * m68k.h (mcfisa_c): New.
  62         (mcfusp, mcf_mask): Adjust.
  63
  64 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  65
  66         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  67         (num_powerpc_operands): Declare.
  68         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  69         (PPC_OPERAND_PLUS1): Define.
  70
  71 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         * i386.h (REX_MODE64): Renamed to ...
  74         (REX_W): This.
  75         (REX_EXTX): Renamed to ...
  76         (REX_R): This.
  77         (REX_EXTY): Renamed to ...
  78         (REX_X): This.
  79         (REX_EXTZ): Renamed to ...
  80         (REX_B): This.
  81
  82 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386.h: Add entries from config/tc-i386.h and move tables
  85         to opcodes/i386-opc.h.
  86
  87 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  88
  89         * i386.h (FloatDR): Removed.
  90         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  91
  92 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  93
  94         * spu-insns.h: Add soma double-float insns.
  95
  96 2007-02-20  Thiemo Seufer  <ths@mips.com>
  97             Chao-Ying Fu  <fu@mips.com>
  98
  99         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 100         (INSN_DSPR2): Add flag for DSP R2 instructions.
 101         (M_BALIGN): New macro.
 102
 103 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 104
 105         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 106         and Seg3ShortFrom with Shortform.
 107
 108 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         PR gas/4027
 111         * i386.h (i386_optab): Put the real "test" before the pseudo
 112         one.
 113
 114 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 115
 116         * m68k.h (m68010up): OR fido_a.
 117
 118 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 119
 120         * m68k.h (fido_a): New.
 121
 122 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 123
 124         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 125         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 126         values.
 127
 128 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 131
 132 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 133
 134         * score-inst.h (enum score_insn_type): Add Insn_internal.
 135
 136 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 137             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 138             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 139             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 140             Alan Modra  <amodra@bigpond.net.au>
 141
 142         * spu-insns.h: New file.
 143         * spu.h: New file.
 144
 145 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 146
 147         * ppc.h (PPC_OPCODE_CELL): Define.
 148
 149 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 150
 151         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 152         in amdfam10 architecture.
 153
 154 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         * i386.h: Replace CpuMNI with CpuSSSE3.
 157
 158 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 159             Joseph Myers  <joseph@codesourcery.com>
 160             Ian Lance Taylor  <ian@wasabisystems.com>
 161             Ben Elliston  <bje@wasabisystems.com>
 162
 163         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 164
 165 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 166
 167         * score-datadep.h: New file.
 168         * score-inst.h: New file.
 169
 170 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 173         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 174         movdq2q and movq2dq.
 175
 176 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 177            Michael Meissner             <michael.meissner@amd.com>
 178
 179         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 180
 181 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 182
 183         * i386.h (i386_optab): Add "nop" with memory reference.
 184
 185 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 186
 187         * i386.h (i386_optab): Update comment for 64bit NOP.
 188
 189 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 190             Anton Blanchard  <anton@samba.org>
 191
 192         * ppc.h (PPC_OPCODE_POWER6): Define.
 193         Adjust whitespace.
 194
 195 2006-06-05  Thiemo Seufer  <ths@mips.com>
 196
 197         * mips.h: Improve description of MT flags.
 198
 199 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 200
 201         * m68k.h (mcf_mask): Define.
 202
 203 2006-05-05  Thiemo Seufer  <ths@mips.com>
 204             David Ung  <davidu@mips.com>
 205
 206         * mips.h (enum): Add macro M_CACHE_AB.
 207
 208 2006-05-04  Thiemo Seufer  <ths@mips.com>
 209             Nigel Stephens  <nigel@mips.com>
 210             David Ung  <davidu@mips.com>
 211
 212         * mips.h: Add INSN_SMARTMIPS define.
 213
 214 2006-04-30  Thiemo Seufer  <ths@mips.com>
 215             David Ung  <davidu@mips.com>
 216
 217         * mips.h: Defines udi bits and masks.  Add description of
 218         characters which may appear in the args field of udi
 219         instructions.
 220
 221 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 222
 223         * mips.h: Improve comments describing the bitfield instruction
 224         fields.
 225
 226 2006-04-26  Julian Brown  <julian@codesourcery.com>
 227
 228         * arm.h (FPU_VFP_EXT_V3): Define constant.
 229         (FPU_NEON_EXT_V1): Likewise.
 230         (FPU_VFP_HARD): Update.
 231         (FPU_VFP_V3): Define macro.
 232         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 233
 234 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 235
 236         * avr.h (AVR_ISA_PWMx): New.
 237
 238 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 239
 240         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 241         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 242         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 243         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 244         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 245
 246 2006-03-10  Paul Brook  <paul@codesourcery.com>
 247
 248         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 249
 250 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 251
 252         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 253         first.  Correct mask of bb "B" opcode.
 254
 255 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 256
 257         * i386.h (i386_optab): Support Intel Merom New Instructions.
 258
 259 2006-02-24  Paul Brook  <paul@codesourcery.com>
 260
 261         * arm.h: Add V7 feature bits.
 262
 263 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 266
 267 2006-01-31  Paul Brook  <paul@codesourcery.com>
 268         Richard Earnshaw <rearnsha@arm.com>
 269
 270         * arm.h: Use ARM_CPU_FEATURE.
 271         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 272         (arm_feature_set): Change to a structure.
 273         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 274         ARM_FEATURE): New macros.
 275
 276 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 277
 278         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 279         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 280         (ADD_PC_INCR_OPCODE): Don't define.
 281
 282 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         PR gas/1874
 285         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 286
 287 2005-11-14  David Ung  <davidu@mips.com>
 288
 289         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 290         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 291         save/restore encoding of the args field.
 292
 293 2005-10-28  Dave Brolley  <brolley@redhat.com>
 294
 295         Contribute the following changes:
 296         2005-02-16  Dave Brolley  <brolley@redhat.com>
 297
 298         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 299         cgen_isa_mask_* to cgen_bitset_*.
 300         * cgen.h: Likewise.
 301
 302         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 303
 304         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 305         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 306         (CGEN_CPU_TABLE): Make isas a ponter.
 307
 308         2003-09-29  Dave Brolley  <brolley@redhat.com>
 309
 310         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 311         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 312         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 313
 314         2002-12-13  Dave Brolley  <brolley@redhat.com>
 315
 316         * cgen.h (symcat.h): #include it.
 317         (cgen-bitset.h): #include it.
 318         (CGEN_ATTR_VALUE_TYPE): Now a union.
 319         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 320         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 321         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 322         * cgen-bitset.h: New file.
 323
 324 2005-09-30  Catherine Moore  <clm@cm00re.com>
 325
 326         * bfin.h: New file.
 327
 328 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 329
 330         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 331         indirect operands.
 332
 333 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 334
 335         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 336         Add FLAG_STRICT to pa10 ftest opcode.
 337
 338 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 339
 340         * hppa.h (pa_opcodes): Remove lha entries.
 341
 342 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 343
 344         * hppa.h (FLAG_STRICT): Revise comment.
 345         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 346         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 347         entries for "fdc".
 348
 349 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 350
 351         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 352
 353 2005-09-06  Chao-ying Fu  <fu@mips.com>
 354
 355         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 356         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 357         define.
 358         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 359         (INSN_ASE_MASK): Update to include INSN_MT.
 360         (INSN_MT): New define for MT ASE.
 361
 362 2005-08-25  Chao-ying Fu  <fu@mips.com>
 363
 364         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 365         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 366         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 367         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 368         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 369         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 370         instructions.
 371         (INSN_DSP): New define for DSP ASE.
 372
 373 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 374
 375         * a29k.h: Delete.
 376
 377 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 378
 379         * ppc.h (PPC_OPCODE_E300): Define.
 380
 381 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 382
 383         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 384
 385 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 386
 387         PR gas/336
 388         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 389         and pitlb.
 390
 391 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 392
 393         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 394         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 395         Add movq-s as 64-bit variants of movd-s.
 396
 397 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 398
 399         * hppa.h: Fix punctuation in comment.
 400
 401         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 402         implicit space-register addressing.  Set space-register bits on opcodes
 403         using implicit space-register addressing.  Add various missing pa20
 404         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 405         space-register addressing.  Use "fE" instead of "fe" in various
 406         fstw opcodes.
 407
 408 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 409
 410         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 411
 412 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 413
 414         * i386.h (i386_optab): Support Intel VMX Instructions.
 415
 416 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 417
 418         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 419
 420 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 421
 422         * i386.h (i386_optab): Add new insns.
 423
 424 2005-07-01  Nick Clifton  <nickc@redhat.com>
 425
 426         * sparc.h: Add typedefs to structure declarations.
 427
 428 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 429
 430         PR 1013
 431         * i386.h (i386_optab): Update comments for 64bit addressing on
 432         mov. Allow 64bit addressing for mov and movq.
 433
 434 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 435
 436         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 437         respectively, in various floating-point load and store patterns.
 438
 439 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 440
 441         * hppa.h (FLAG_STRICT): Correct comment.
 442         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 443         PA 2.0 mneumonics when equivalent.  Entries with cache control
 444         completers now require PA 1.1.  Adjust whitespace.
 445
 446 2005-05-19  Anton Blanchard  <anton@samba.org>
 447
 448         * ppc.h (PPC_OPCODE_POWER5): Define.
 449
 450 2005-05-10  Nick Clifton  <nickc@redhat.com>
 451
 452         * Update the address and phone number of the FSF organization in
 453         the GPL notices in the following files:
 454         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 455         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 456         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 457         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 458         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 459         tic54x.h, tic80.h, v850.h, vax.h
 460
 461 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 462
 463         * i386.h (i386_optab): Add ht and hnt.
 464
 465 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 466
 467         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 468         Add xcrypt-ctr.  Provide aliases without hyphens.
 469
 470 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         Moved from ../ChangeLog
 473
 474         2005-04-12  Paul Brook  <paul@codesourcery.com>
 475         * m88k.h: Rename psr macros to avoid conflicts.
 476
 477         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 478         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 479         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 480         and ARM_ARCH_V6ZKT2.
 481
 482         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 483         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 484         Remove redundant instruction types.
 485         (struct argument): X_op - new field.
 486         (struct cst4_entry): Remove.
 487         (no_op_insn): Declare.
 488
 489         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 490         * crx.h (enum argtype): Rename types, remove unused types.
 491
 492         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 493         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 494         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 495         (enum operand_type): Rearrange operands, edit comments.
 496         replace us<N> with ui<N> for unsigned immediate.
 497         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 498         displacements (respectively).
 499         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 500         (instruction type): Add NO_TYPE_INS.
 501         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 502         (operand_entry): New field - 'flags'.
 503         (operand flags): New.
 504
 505         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 506         * crx.h (operand_type): Remove redundant types i3, i4,
 507         i5, i8, i12.
 508         Add new unsigned immediate types us3, us4, us5, us16.
 509
 510 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 511
 512         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 513         adjust them accordingly.
 514
 515 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 516
 517         * i386.h (i386_optab): Add rdtscp.
 518
 519 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 522         between memory and segment register. Allow movq for moving between
 523         general-purpose register and segment register.
 524
 525 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 526
 527         PR gas/707
 528         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 529         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 530         fnstsw.
 531
 532 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 533
 534         * m68k.h (m68008, m68ec030, m68882): Remove.
 535         (m68k_mask): New.
 536         (cpu_m68k, cpu_cf): New.
 537         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 538         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 539
 540 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 541
 542         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 543         * cgen.h (enum cgen_parse_operand_type): Add
 544         CGEN_PARSE_OPERAND_SYMBOLIC.
 545
 546 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 547
 548         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 549         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 550         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 551
 552 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 553
 554         * mips.h (struct mips_opcode): Add new pinfo2 member.
 555         (INSN_ALIAS): New define for opcode table entries that are
 556         specific instances of another entry, such as 'move' for an 'or'
 557         with a zero operand.
 558         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 559         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 560
 561 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 562
 563         * mips.h (CPU_RM9000): Define.
 564         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 565
 566 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 567
 568         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 569         to/from test registers are illegal in 64-bit mode. Add missing
 570         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 571         (previously one had to explicitly encode a rex64 prefix). Re-enable
 572         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 573         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 574
 575 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 576
 577         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 578         available only with SSE2. Change the MMX additions introduced by SSE
 579         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 580         instructions by their now designated identifier (since combining i686
 581         and 3DNow! does not really imply 3DNow!A).
 582
 583 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 584
 585         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 586         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 587
 588 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 589             Vineet Sharma      <vineets@noida.hcltech.com>
 590
 591         * maxq.h: New file: Disassembly information for the maxq port.
 592
 593 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * i386.h (i386_optab): Put back "movzb".
 596
 597 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 598
 599         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 600         comments.  Remove member cris_ver_sim.  Add members
 601         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 602         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 603         (struct cris_support_reg, struct cris_cond15): New types.
 604         (cris_conds15): Declare.
 605         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 606         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 607         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 608         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 609         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 610         SIZE_FIELD_UNSIGNED.
 611
 612 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 613
 614         * i386.h (sldx_Suf): Remove.
 615         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 616         (q_FP): Define, implying no REX64.
 617         (x_FP, sl_FP): Imply FloatMF.
 618         (i386_optab): Split reg and mem forms of moving from segment registers
 619         so that the memory forms can ignore the 16-/32-bit operand size
 620         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 621         all non-floating-point instructions. Unite 32- and 64-bit forms of
 622         movsx, movzx, and movd. Adjust floating point operations for the above
 623         changes to the *FP macros. Add DefaultSize to floating point control
 624         insns operating on larger memory ranges. Remove left over comments
 625         hinting at certain insns being Intel-syntax ones where the ones
 626         actually meant are already gone.
 627
 628 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 629
 630         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 631         instruction type.
 632
 633 2004-09-30  Paul Brook  <paul@codesourcery.com>
 634
 635         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 636         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 637
 638 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 639
 640         * avr.h: Add support for
 641         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 642
 643 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 644
 645         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 646
 647 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 648
 649         * msp430.h (msp430_opc): Add new instructions.
 650         (msp430_rcodes): Declare new instructions.
 651         (msp430_hcodes): Likewise..
 652
 653 2004-08-13  Nick Clifton  <nickc@redhat.com>
 654
 655         PR/301
 656         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 657         processors.
 658
 659 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 660
 661         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 662
 663 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 664
 665         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 666
 667 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 668
 669         * i386.h: Adjust instruction descriptions to better match the
 670         specification.
 671
 672 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 673
 674         * arm.h: Remove all old content.  Replace with architecture defines
 675         from gas/config/tc-arm.c.
 676
 677 2004-07-09  Andreas Schwab  <schwab@suse.de>
 678
 679         * m68k.h: Fix comment.
 680
 681 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 682
 683         * crx.h: New file.
 684
 685 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 686
 687         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 688
 689 2004-05-24  Peter Barada  <peter@the-baradas.com>
 690
 691         * m68k.h: Add 'size' to m68k_opcode.
 692
 693 2004-05-05  Peter Barada  <peter@the-baradas.com>
 694
 695         * m68k.h: Switch from ColdFire chip name to core variant.
 696
 697 2004-04-22  Peter Barada  <peter@the-baradas.com>
 698
 699         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 700         descriptions for new EMAC cases.
 701         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 702         handle Motorola MAC syntax.
 703         Allow disassembly of ColdFire V4e object files.
 704
 705 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 706
 707         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 708
 709 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 710
 711         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 712
 713 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 714
 715         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 716
 717 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 718
 719         * i386.h (i386_optab): Added xstore/xcrypt insns.
 720
 721 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 722
 723         * h8300.h (32bit ldc/stc): Add relaxing support.
 724
 725 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 726
 727         * h8300.h (BITOP): Pass MEMRELAX flag.
 728
 729 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 730
 731         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 732         except for the H8S.
 733
 734 For older changes see ChangeLog-9103
 735 \f
 736 Local Variables:
 737 mode: change-log
 738 left-margin: 8
 739 fill-column: 74
 740 version-control: never
 741 End: