include/opcode/ChangeLog

   1 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   2
   3         PR gas/12198
   4         * arm.h (ARM_AEXT_V6M_ONLY): New define.
   5         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
   6         (ARM_ARCH_V6M_ONLY): New define.
   7
   8 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
   9
  10         * mips.h (INSN_LOONGSON_3A): Defined.
  11         (CPU_LOONGSON_3A): Defined.
  12         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
  13
  14 2010-10-09  Matt Rice  <ratmice@gmail.com>
  15
  16         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
  17         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
  18
  19 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  20
  21         * arm.h (ARM_EXT_VIRT): New define.
  22         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
  23         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
  24         Extensions.
  25
  26 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  27
  28         * arm.h (ARM_AEXT_ADIV): New define.
  29         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
  30
  31 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  32
  33         * arm.h (ARM_EXT_OS): New define.
  34         (ARM_AEXT_V6SM): Likewise.
  35         (ARM_ARCH_V6SM): Likewise.
  36
  37 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  38
  39         * arm.h (ARM_EXT_MP): Add.
  40         (ARM_ARCH_V7A_MP): Likewise.
  41
  42 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  43
  44         * bfin.h: Declare pseudoChr structs/defines.
  45
  46 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
  47
  48         * bfin.h: Strip trailing whitespace.
  49
  50 2010-07-29  DJ Delorie  <dj@redhat.com>
  51
  52         * rx.h (RX_Operand_Type): Add TwoReg.
  53         (RX_Opcode_ID): Remove ediv and ediv2.
  54
  55 2010-07-27  DJ Delorie  <dj@redhat.com>
  56
  57         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
  58
  59 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
  60             Ina Pandit  <ina.pandit@kpitcummins.com>
  61
  62         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
  63         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
  64         PROCESSOR_V850E2_ALL.
  65         Remove PROCESSOR_V850EA support.
  66         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
  67         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
  68         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
  69         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
  70         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
  71         V850_OPERAND_PERCENT.
  72         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
  73         V850_NOT_R0.
  74         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
  75         and V850E_PUSH_POP
  76
  77 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
  78
  79         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
  80         (MIPS16_INSN_BRANCH): Rename to...
  81         (MIPS16_INSN_COND_BRANCH): ... this.
  82
  83 2010-07-03  Alan Modra  <amodra@gmail.com>
  84
  85         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
  86         Renumber other PPC_OPCODE defines.
  87
  88 2010-07-03  Alan Modra  <amodra@gmail.com>
  89
  90         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
  91
  92 2010-06-29  Alan Modra  <amodra@gmail.com>
  93
  94         * maxq.h: Delete file.
  95
  96 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
  97
  98         * ppc.h (PPC_OPCODE_E500): Define.
  99
 100 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 101
 102         * opcode/mips.h (INSN_MIPS16): Remove.
 103
 104 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 105
 106         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 107
 108 2010-04-15  Nick Clifton  <nickc@redhat.com>
 109
 110         * alpha.h: Update copyright notice to use GPLv3.
 111         * arc.h: Likewise.
 112         * arm.h: Likewise.
 113         * avr.h: Likewise.
 114         * bfin.h: Likewise.
 115         * cgen.h: Likewise.
 116         * convex.h: Likewise.
 117         * cr16.h: Likewise.
 118         * cris.h: Likewise.
 119         * crx.h: Likewise.
 120         * d10v.h: Likewise.
 121         * d30v.h: Likewise.
 122         * dlx.h: Likewise.
 123         * h8300.h: Likewise.
 124         * hppa.h: Likewise.
 125         * i370.h: Likewise.
 126         * i386.h: Likewise.
 127         * i860.h: Likewise.
 128         * i960.h: Likewise.
 129         * ia64.h: Likewise.
 130         * m68hc11.h: Likewise.
 131         * m68k.h: Likewise.
 132         * m88k.h: Likewise.
 133         * maxq.h: Likewise.
 134         * mips.h: Likewise.
 135         * mmix.h: Likewise.
 136         * mn10200.h: Likewise.
 137         * mn10300.h: Likewise.
 138         * msp430.h: Likewise.
 139         * np1.h: Likewise.
 140         * ns32k.h: Likewise.
 141         * or32.h: Likewise.
 142         * pdp11.h: Likewise.
 143         * pj.h: Likewise.
 144         * pn.h: Likewise.
 145         * ppc.h: Likewise.
 146         * pyr.h: Likewise.
 147         * rx.h: Likewise.
 148         * s390.h: Likewise.
 149         * score-datadep.h: Likewise.
 150         * score-inst.h: Likewise.
 151         * sparc.h: Likewise.
 152         * spu-insns.h: Likewise.
 153         * spu.h: Likewise.
 154         * tic30.h: Likewise.
 155         * tic4x.h: Likewise.
 156         * tic54x.h: Likewise.
 157         * tic80.h: Likewise.
 158         * v850.h: Likewise.
 159         * vax.h: Likewise.
 160
 161 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 162
 163         * tic6x-control-registers.h, tic6x-insn-formats.h,
 164         tic6x-opcode-table.h, tic6x.h: New.
 165
 166 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 167
 168         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 169
 170 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 171
 172         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 173
 174 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         * ia64.h (ia64_find_opcode): Remove argument name.
 177         (ia64_find_next_opcode): Likewise.
 178         (ia64_dis_opcode): Likewise.
 179         (ia64_free_opcode): Likewise.
 180         (ia64_find_dependency): Likewise.
 181
 182 2009-11-22  Doug Evans  <dje@sebabeach.org>
 183
 184         * cgen.h: Include bfd_stdint.h.
 185         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 186
 187 2009-11-18  Paul Brook  <paul@codesourcery.com>
 188
 189         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 190
 191 2009-11-17  Paul Brook  <paul@codesourcery.com>
 192         Daniel Jacobowitz  <dan@codesourcery.com>
 193
 194         * arm.h (ARM_EXT_V6_DSP): Define.
 195         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 196         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 197
 198 2009-11-04  DJ Delorie  <dj@redhat.com>
 199
 200         * rx.h (rx_decode_opcode) (mvtipl): Add.
 201         (mvtcp, mvfcp, opecp): Remove.
 202
 203 2009-11-02  Paul Brook  <paul@codesourcery.com>
 204
 205         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 206         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 207         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 208         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 209         FPU_ARCH_NEON_VFP_V4): Define.
 210
 211 2009-10-23  Doug Evans  <dje@sebabeach.org>
 212
 213         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 214         * cgen.h: Update.  Improve multi-inclusion macro name.
 215
 216 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 217
 218         * ppc.h (PPC_OPCODE_476): Define.
 219
 220 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 221
 222         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 223
 224 2009-09-29  DJ Delorie  <dj@redhat.com>
 225
 226         * rx.h: New file.
 227
 228 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 229
 230         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 231
 232 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 233
 234         * ppc.h (PPC_OPCODE_PPCA2): New.
 235
 236 2009-09-05  Martin Thuresson  <martin@mtme.org>
 237
 238         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 239
 240 2009-08-29  Martin Thuresson  <martin@mtme.org>
 241
 242         * tic30.h (template): Rename type template to
 243         insn_template. Updated code to use new name.
 244         * tic54x.h (template): Rename type template to
 245         insn_template.
 246
 247 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 248
 249         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 250
 251 2009-06-11  Anthony Green  <green@moxielogic.com>
 252
 253         * moxie.h (MOXIE_F3_PCREL): Define.
 254         (moxie_form3_opc_info): Grow.
 255
 256 2009-06-06  Anthony Green  <green@moxielogic.com>
 257
 258         * moxie.h (MOXIE_F1_M): Define.
 259
 260 2009-04-15  Anthony Green  <green@moxielogic.com>
 261
 262         * moxie.h: Created.
 263
 264 2009-04-06  DJ Delorie  <dj@redhat.com>
 265
 266         * h8300.h: Add relaxation attributes to MOVA opcodes.
 267
 268 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 269
 270         * ppc.h (ppc_parse_cpu): Declare.
 271
 272 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 273
 274         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 275         and _IMM11 for mbitclr and mbitset.
 276         * score-datadep.h: Update dependency information.
 277
 278 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 279
 280         * ppc.h (PPC_OPCODE_POWER7): New.
 281
 282 2009-02-06  Doug Evans  <dje@google.com>
 283
 284         * i386.h: Add comment regarding sse* insns and prefixes.
 285
 286 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 287
 288         * mips.h (INSN_XLR): Define.
 289         (INSN_CHIP_MASK): Update.
 290         (CPU_XLR): Define.
 291         (OPCODE_IS_MEMBER): Update.
 292         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 293
 294 2009-01-28  Doug Evans  <dje@google.com>
 295
 296         * opcode/i386.h: Add multiple inclusion protection.
 297         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 298         (EDI_REG_NUM): New macros.
 299         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 300         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 301         (REX_PREFIX_P): New macro.
 302
 303 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 304
 305         * ppc.h (struct powerpc_opcode): New field "deprecated".
 306         (PPC_OPCODE_NOPOWER4): Delete.
 307
 308 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 309
 310         * mips.h: Define CPU_R14000, CPU_R16000.
 311         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 312
 313 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 314
 315         * arm.h (FPU_NEON_FP16): New.
 316         (FPU_ARCH_NEON_FP16): New.
 317
 318 2008-11-06  Chao-ying Fu  <fu@mips.com>
 319
 320         * mips.h: Doucument '1' for 5-bit sync type.
 321
 322 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 325         IA64_RS_CR.
 326
 327 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 328
 329         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 330
 331 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 332
 333         * ppc.h (PPC_OPCODE_405): Define.
 334         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 335
 336 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 337
 338         * ppc.h (ppc_cpu_t): New typedef.
 339         (struct powerpc_opcode <flags>): Use it.
 340         (struct powerpc_operand <insert, extract>): Likewise.
 341         (struct powerpc_macro <flags>): Likewise.
 342
 343 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 344
 345         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 346         Update comment before MIPS16 field descriptors to mention MIPS16.
 347         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 348         BBIT.
 349         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 350         New bit masks and shift counts for cins and exts.
 351
 352         * mips.h: Document new field descriptors +Q.
 353         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 354
 355 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 356
 357         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 358         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 359
 360 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 361
 362         * ppc.h: (PPC_OPCODE_E500MC): New.
 363
 364 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         * i386.h (MAX_OPERANDS): Set to 5.
 367         (MAX_MNEM_SIZE): Changed to 20.
 368
 369 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 370
 371         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 372
 373 2008-03-09  Paul Brook  <paul@codesourcery.com>
 374
 375         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 376
 377 2008-03-04  Paul Brook  <paul@codesourcery.com>
 378
 379         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 380         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 381         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 382
 383 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 384             Nick Clifton  <nickc@redhat.com>
 385
 386         PR 3134
 387         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 388         with a 32-bit displacement but without the top bit of the 4th byte
 389         set.
 390
 391 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 392
 393         * cr16.h (cr16_num_optab): Declared.
 394
 395 2008-02-14  Hakan Ardo  <hakan@debian.org>
 396
 397         PR gas/2626
 398         * avr.h (AVR_ISA_2xxe): Define.
 399
 400 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 401
 402         * mips.h: Update copyright.
 403         (INSN_CHIP_MASK): New macro.
 404         (INSN_OCTEON): New macro.
 405         (CPU_OCTEON): New macro.
 406         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 407
 408 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 409
 410         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 411
 412 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 413
 414         * avr.h (AVR_ISA_USB162): Add new opcode set.
 415         (AVR_ISA_AVR3): Likewise.
 416
 417 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 418
 419         * mips.h (INSN_LOONGSON_2E): New.
 420         (INSN_LOONGSON_2F): New.
 421         (CPU_LOONGSON_2E): New.
 422         (CPU_LOONGSON_2F): New.
 423         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 424
 425 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 426
 427         * mips.h (INSN_ISA*): Redefine certain values as an
 428         enumeration.  Update comments.
 429         (mips_isa_table): New.
 430         (ISA_MIPS*): Redefine to match enumeration.
 431         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 432         values.
 433
 434 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 435
 436         * ppc.h (PPC_OPCODE_PPCPS): New.
 437
 438 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 439
 440         * m68k.h: Document j K & E.
 441
 442 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 443
 444         * cr16.h: New file for CR16 target.
 445
 446 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 447
 448         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 449
 450 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 451
 452         * m68k.h (mcfisa_c): New.
 453         (mcfusp, mcf_mask): Adjust.
 454
 455 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 456
 457         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 458         (num_powerpc_operands): Declare.
 459         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 460         (PPC_OPERAND_PLUS1): Define.
 461
 462 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 463
 464         * i386.h (REX_MODE64): Renamed to ...
 465         (REX_W): This.
 466         (REX_EXTX): Renamed to ...
 467         (REX_R): This.
 468         (REX_EXTY): Renamed to ...
 469         (REX_X): This.
 470         (REX_EXTZ): Renamed to ...
 471         (REX_B): This.
 472
 473 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * i386.h: Add entries from config/tc-i386.h and move tables
 476         to opcodes/i386-opc.h.
 477
 478 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         * i386.h (FloatDR): Removed.
 481         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 482
 483 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 484
 485         * spu-insns.h: Add soma double-float insns.
 486
 487 2007-02-20  Thiemo Seufer  <ths@mips.com>
 488             Chao-Ying Fu  <fu@mips.com>
 489
 490         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 491         (INSN_DSPR2): Add flag for DSP R2 instructions.
 492         (M_BALIGN): New macro.
 493
 494 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 495
 496         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 497         and Seg3ShortFrom with Shortform.
 498
 499 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         PR gas/4027
 502         * i386.h (i386_optab): Put the real "test" before the pseudo
 503         one.
 504
 505 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 506
 507         * m68k.h (m68010up): OR fido_a.
 508
 509 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 510
 511         * m68k.h (fido_a): New.
 512
 513 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 514
 515         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 516         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 517         values.
 518
 519 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 522
 523 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 524
 525         * score-inst.h (enum score_insn_type): Add Insn_internal.
 526
 527 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 528             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 529             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 530             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 531             Alan Modra  <amodra@bigpond.net.au>
 532
 533         * spu-insns.h: New file.
 534         * spu.h: New file.
 535
 536 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 537
 538         * ppc.h (PPC_OPCODE_CELL): Define.
 539
 540 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 541
 542         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 543         in amdfam10 architecture.
 544
 545 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 546
 547         * i386.h: Replace CpuMNI with CpuSSSE3.
 548
 549 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 550             Joseph Myers  <joseph@codesourcery.com>
 551             Ian Lance Taylor  <ian@wasabisystems.com>
 552             Ben Elliston  <bje@wasabisystems.com>
 553
 554         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 555
 556 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 557
 558         * score-datadep.h: New file.
 559         * score-inst.h: New file.
 560
 561 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 564         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 565         movdq2q and movq2dq.
 566
 567 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 568            Michael Meissner             <michael.meissner@amd.com>
 569
 570         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 571
 572 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         * i386.h (i386_optab): Add "nop" with memory reference.
 575
 576 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         * i386.h (i386_optab): Update comment for 64bit NOP.
 579
 580 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 581             Anton Blanchard  <anton@samba.org>
 582
 583         * ppc.h (PPC_OPCODE_POWER6): Define.
 584         Adjust whitespace.
 585
 586 2006-06-05  Thiemo Seufer  <ths@mips.com>
 587
 588         * mips.h: Improve description of MT flags.
 589
 590 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 591
 592         * m68k.h (mcf_mask): Define.
 593
 594 2006-05-05  Thiemo Seufer  <ths@mips.com>
 595             David Ung  <davidu@mips.com>
 596
 597         * mips.h (enum): Add macro M_CACHE_AB.
 598
 599 2006-05-04  Thiemo Seufer  <ths@mips.com>
 600             Nigel Stephens  <nigel@mips.com>
 601             David Ung  <davidu@mips.com>
 602
 603         * mips.h: Add INSN_SMARTMIPS define.
 604
 605 2006-04-30  Thiemo Seufer  <ths@mips.com>
 606             David Ung  <davidu@mips.com>
 607
 608         * mips.h: Defines udi bits and masks.  Add description of
 609         characters which may appear in the args field of udi
 610         instructions.
 611
 612 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 613
 614         * mips.h: Improve comments describing the bitfield instruction
 615         fields.
 616
 617 2006-04-26  Julian Brown  <julian@codesourcery.com>
 618
 619         * arm.h (FPU_VFP_EXT_V3): Define constant.
 620         (FPU_NEON_EXT_V1): Likewise.
 621         (FPU_VFP_HARD): Update.
 622         (FPU_VFP_V3): Define macro.
 623         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 624
 625 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 626
 627         * avr.h (AVR_ISA_PWMx): New.
 628
 629 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 630
 631         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 632         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 633         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 634         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 635         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 636
 637 2006-03-10  Paul Brook  <paul@codesourcery.com>
 638
 639         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 640
 641 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 642
 643         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 644         first.  Correct mask of bb "B" opcode.
 645
 646 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 647
 648         * i386.h (i386_optab): Support Intel Merom New Instructions.
 649
 650 2006-02-24  Paul Brook  <paul@codesourcery.com>
 651
 652         * arm.h: Add V7 feature bits.
 653
 654 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 657
 658 2006-01-31  Paul Brook  <paul@codesourcery.com>
 659         Richard Earnshaw <rearnsha@arm.com>
 660
 661         * arm.h: Use ARM_CPU_FEATURE.
 662         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 663         (arm_feature_set): Change to a structure.
 664         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 665         ARM_FEATURE): New macros.
 666
 667 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 668
 669         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 670         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 671         (ADD_PC_INCR_OPCODE): Don't define.
 672
 673 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         PR gas/1874
 676         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 677
 678 2005-11-14  David Ung  <davidu@mips.com>
 679
 680         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 681         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 682         save/restore encoding of the args field.
 683
 684 2005-10-28  Dave Brolley  <brolley@redhat.com>
 685
 686         Contribute the following changes:
 687         2005-02-16  Dave Brolley  <brolley@redhat.com>
 688
 689         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 690         cgen_isa_mask_* to cgen_bitset_*.
 691         * cgen.h: Likewise.
 692
 693         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 694
 695         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 696         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 697         (CGEN_CPU_TABLE): Make isas a ponter.
 698
 699         2003-09-29  Dave Brolley  <brolley@redhat.com>
 700
 701         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 702         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 703         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 704
 705         2002-12-13  Dave Brolley  <brolley@redhat.com>
 706
 707         * cgen.h (symcat.h): #include it.
 708         (cgen-bitset.h): #include it.
 709         (CGEN_ATTR_VALUE_TYPE): Now a union.
 710         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 711         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 712         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 713         * cgen-bitset.h: New file.
 714
 715 2005-09-30  Catherine Moore  <clm@cm00re.com>
 716
 717         * bfin.h: New file.
 718
 719 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 720
 721         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 722         indirect operands.
 723
 724 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 725
 726         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 727         Add FLAG_STRICT to pa10 ftest opcode.
 728
 729 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 730
 731         * hppa.h (pa_opcodes): Remove lha entries.
 732
 733 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 734
 735         * hppa.h (FLAG_STRICT): Revise comment.
 736         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 737         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 738         entries for "fdc".
 739
 740 2005-09-30  Catherine Moore  <clm@cm00re.com>
 741
 742         * bfin.h: New file.
 743
 744 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 745
 746         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 747
 748 2005-09-06  Chao-ying Fu  <fu@mips.com>
 749
 750         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 751         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 752         define.
 753         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 754         (INSN_ASE_MASK): Update to include INSN_MT.
 755         (INSN_MT): New define for MT ASE.
 756
 757 2005-08-25  Chao-ying Fu  <fu@mips.com>
 758
 759         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 760         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 761         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 762         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 763         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 764         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 765         instructions.
 766         (INSN_DSP): New define for DSP ASE.
 767
 768 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 769
 770         * a29k.h: Delete.
 771
 772 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 773
 774         * ppc.h (PPC_OPCODE_E300): Define.
 775
 776 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 777
 778         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 779
 780 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 781
 782         PR gas/336
 783         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 784         and pitlb.
 785
 786 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 787
 788         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 789         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 790         Add movq-s as 64-bit variants of movd-s.
 791
 792 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 793
 794         * hppa.h: Fix punctuation in comment.
 795
 796         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 797         implicit space-register addressing.  Set space-register bits on opcodes
 798         using implicit space-register addressing.  Add various missing pa20
 799         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 800         space-register addressing.  Use "fE" instead of "fe" in various
 801         fstw opcodes.
 802
 803 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 804
 805         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 806
 807 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 808
 809         * i386.h (i386_optab): Support Intel VMX Instructions.
 810
 811 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 812
 813         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 814
 815 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 816
 817         * i386.h (i386_optab): Add new insns.
 818
 819 2005-07-01  Nick Clifton  <nickc@redhat.com>
 820
 821         * sparc.h: Add typedefs to structure declarations.
 822
 823 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 824
 825         PR 1013
 826         * i386.h (i386_optab): Update comments for 64bit addressing on
 827         mov. Allow 64bit addressing for mov and movq.
 828
 829 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 830
 831         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 832         respectively, in various floating-point load and store patterns.
 833
 834 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 835
 836         * hppa.h (FLAG_STRICT): Correct comment.
 837         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 838         PA 2.0 mneumonics when equivalent.  Entries with cache control
 839         completers now require PA 1.1.  Adjust whitespace.
 840
 841 2005-05-19  Anton Blanchard  <anton@samba.org>
 842
 843         * ppc.h (PPC_OPCODE_POWER5): Define.
 844
 845 2005-05-10  Nick Clifton  <nickc@redhat.com>
 846
 847         * Update the address and phone number of the FSF organization in
 848         the GPL notices in the following files:
 849         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 850         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 851         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 852         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 853         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 854         tic54x.h, tic80.h, v850.h, vax.h
 855
 856 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 857
 858         * i386.h (i386_optab): Add ht and hnt.
 859
 860 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 861
 862         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 863         Add xcrypt-ctr.  Provide aliases without hyphens.
 864
 865 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         Moved from ../ChangeLog
 868
 869         2005-04-12  Paul Brook  <paul@codesourcery.com>
 870         * m88k.h: Rename psr macros to avoid conflicts.
 871
 872         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 873         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 874         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 875         and ARM_ARCH_V6ZKT2.
 876
 877         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 878         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 879         Remove redundant instruction types.
 880         (struct argument): X_op - new field.
 881         (struct cst4_entry): Remove.
 882         (no_op_insn): Declare.
 883
 884         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 885         * crx.h (enum argtype): Rename types, remove unused types.
 886
 887         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 888         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 889         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 890         (enum operand_type): Rearrange operands, edit comments.
 891         replace us<N> with ui<N> for unsigned immediate.
 892         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 893         displacements (respectively).
 894         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 895         (instruction type): Add NO_TYPE_INS.
 896         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 897         (operand_entry): New field - 'flags'.
 898         (operand flags): New.
 899
 900         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 901         * crx.h (operand_type): Remove redundant types i3, i4,
 902         i5, i8, i12.
 903         Add new unsigned immediate types us3, us4, us5, us16.
 904
 905 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 906
 907         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 908         adjust them accordingly.
 909
 910 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 911
 912         * i386.h (i386_optab): Add rdtscp.
 913
 914 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 917         between memory and segment register. Allow movq for moving between
 918         general-purpose register and segment register.
 919
 920 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 921
 922         PR gas/707
 923         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 924         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 925         fnstsw.
 926
 927 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 928
 929         * m68k.h (m68008, m68ec030, m68882): Remove.
 930         (m68k_mask): New.
 931         (cpu_m68k, cpu_cf): New.
 932         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 933         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 934
 935 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 936
 937         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 938         * cgen.h (enum cgen_parse_operand_type): Add
 939         CGEN_PARSE_OPERAND_SYMBOLIC.
 940
 941 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 942
 943         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 944         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 945         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 946
 947 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 948
 949         * mips.h (struct mips_opcode): Add new pinfo2 member.
 950         (INSN_ALIAS): New define for opcode table entries that are
 951         specific instances of another entry, such as 'move' for an 'or'
 952         with a zero operand.
 953         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 954         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 955
 956 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 957
 958         * mips.h (CPU_RM9000): Define.
 959         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 960
 961 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 962
 963         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 964         to/from test registers are illegal in 64-bit mode. Add missing
 965         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 966         (previously one had to explicitly encode a rex64 prefix). Re-enable
 967         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 968         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 969
 970 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 971
 972         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 973         available only with SSE2. Change the MMX additions introduced by SSE
 974         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 975         instructions by their now designated identifier (since combining i686
 976         and 3DNow! does not really imply 3DNow!A).
 977
 978 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 979
 980         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 981         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 982
 983 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 984             Vineet Sharma      <vineets@noida.hcltech.com>
 985
 986         * maxq.h: New file: Disassembly information for the maxq port.
 987
 988 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * i386.h (i386_optab): Put back "movzb".
 991
 992 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 993
 994         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 995         comments.  Remove member cris_ver_sim.  Add members
 996         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 997         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 998         (struct cris_support_reg, struct cris_cond15): New types.
 999         (cris_conds15): Declare.
1000         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1001         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1002         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1003         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1004         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1005         SIZE_FIELD_UNSIGNED.
1006
1007 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1008
1009         * i386.h (sldx_Suf): Remove.
1010         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1011         (q_FP): Define, implying no REX64.
1012         (x_FP, sl_FP): Imply FloatMF.
1013         (i386_optab): Split reg and mem forms of moving from segment registers
1014         so that the memory forms can ignore the 16-/32-bit operand size
1015         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1016         all non-floating-point instructions. Unite 32- and 64-bit forms of
1017         movsx, movzx, and movd. Adjust floating point operations for the above
1018         changes to the *FP macros. Add DefaultSize to floating point control
1019         insns operating on larger memory ranges. Remove left over comments
1020         hinting at certain insns being Intel-syntax ones where the ones
1021         actually meant are already gone.
1022
1023 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1024
1025         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1026         instruction type.
1027
1028 2004-09-30  Paul Brook  <paul@codesourcery.com>
1029
1030         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1031         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1032
1033 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1034
1035         * avr.h: Add support for
1036         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1037
1038 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1039
1040         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1041
1042 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1043
1044         * msp430.h (msp430_opc): Add new instructions.
1045         (msp430_rcodes): Declare new instructions.
1046         (msp430_hcodes): Likewise..
1047
1048 2004-08-13  Nick Clifton  <nickc@redhat.com>
1049
1050         PR/301
1051         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1052         processors.
1053
1054 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1055
1056         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1057
1058 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1059
1060         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1061
1062 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1063
1064         * i386.h: Adjust instruction descriptions to better match the
1065         specification.
1066
1067 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1068
1069         * arm.h: Remove all old content.  Replace with architecture defines
1070         from gas/config/tc-arm.c.
1071
1072 2004-07-09  Andreas Schwab  <schwab@suse.de>
1073
1074         * m68k.h: Fix comment.
1075
1076 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1077
1078         * crx.h: New file.
1079
1080 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1081
1082         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1083
1084 2004-05-24  Peter Barada  <peter@the-baradas.com>
1085
1086         * m68k.h: Add 'size' to m68k_opcode.
1087
1088 2004-05-05  Peter Barada  <peter@the-baradas.com>
1089
1090         * m68k.h: Switch from ColdFire chip name to core variant.
1091
1092 2004-04-22  Peter Barada  <peter@the-baradas.com>
1093
1094         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1095         descriptions for new EMAC cases.
1096         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1097         handle Motorola MAC syntax.
1098         Allow disassembly of ColdFire V4e object files.
1099
1100 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1101
1102         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1103
1104 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1105
1106         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1107
1108 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1109
1110         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1111
1112 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1113
1114         * i386.h (i386_optab): Added xstore/xcrypt insns.
1115
1116 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1117
1118         * h8300.h (32bit ldc/stc): Add relaxing support.
1119
1120 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1121
1122         * h8300.h (BITOP): Pass MEMRELAX flag.
1123
1124 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1125
1126         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1127         except for the H8S.
1128
1129 For older changes see ChangeLog-9103
1130 \f
1131 Local Variables:
1132 mode: change-log
1133 left-margin: 8
1134 fill-column: 74
1135 version-control: never
1136 End: