1 2005-09-30 Catherine Moore <clm@cm00re.com>
5 2005-10-24 Jan Beulich <jbeulich@novell.com>
7 * ia64.h (enum ia64_opnd): Move memory operand out of set of
10 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
12 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
13 Add FLAG_STRICT to pa10 ftest opcode.
15 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
17 * hppa.h (pa_opcodes): Remove lha entries.
19 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
21 * hppa.h (FLAG_STRICT): Revise comment.
22 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
23 before corresponding pa11 opcodes. Add strict pa10 register-immediate
26 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
28 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
30 2005-09-06 Chao-ying Fu <fu@mips.com>
32 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
33 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
35 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
36 (INSN_ASE_MASK): Update to include INSN_MT.
37 (INSN_MT): New define for MT ASE.
39 2005-08-25 Chao-ying Fu <fu@mips.com>
41 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
42 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
43 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
44 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
45 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
46 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
48 (INSN_DSP): New define for DSP ASE.
50 2005-08-18 Alan Modra <amodra@bigpond.net.au>
54 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
56 * ppc.h (PPC_OPCODE_E300): Define.
58 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
60 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
62 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
65 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
68 2005-07-27 Jan Beulich <jbeulich@novell.com>
70 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
71 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
72 Add movq-s as 64-bit variants of movd-s.
74 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
76 * hppa.h: Fix punctuation in comment.
78 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
79 implicit space-register addressing. Set space-register bits on opcodes
80 using implicit space-register addressing. Add various missing pa20
81 long-immediate opcodes. Remove various opcodes using implicit 3-bit
82 space-register addressing. Use "fE" instead of "fe" in various
85 2005-07-18 Jan Beulich <jbeulich@novell.com>
87 * i386.h (i386_optab): Operands of aam and aad are unsigned.
89 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
91 * i386.h (i386_optab): Support Intel VMX Instructions.
93 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
95 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
97 2005-07-05 Jan Beulich <jbeulich@novell.com>
99 * i386.h (i386_optab): Add new insns.
101 2005-07-01 Nick Clifton <nickc@redhat.com>
103 * sparc.h: Add typedefs to structure declarations.
105 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
108 * i386.h (i386_optab): Update comments for 64bit addressing on
109 mov. Allow 64bit addressing for mov and movq.
111 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
113 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
114 respectively, in various floating-point load and store patterns.
116 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
118 * hppa.h (FLAG_STRICT): Correct comment.
119 (pa_opcodes): Update load and store entries to allow both PA 1.X and
120 PA 2.0 mneumonics when equivalent. Entries with cache control
121 completers now require PA 1.1. Adjust whitespace.
123 2005-05-19 Anton Blanchard <anton@samba.org>
125 * ppc.h (PPC_OPCODE_POWER5): Define.
127 2005-05-10 Nick Clifton <nickc@redhat.com>
129 * Update the address and phone number of the FSF organization in
130 the GPL notices in the following files:
131 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
132 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
133 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
134 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
135 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
136 tic54x.h, tic80.h, v850.h, vax.h
138 2005-05-09 Jan Beulich <jbeulich@novell.com>
140 * i386.h (i386_optab): Add ht and hnt.
142 2005-04-18 Mark Kettenis <kettenis@gnu.org>
144 * i386.h: Insert hyphens into selected VIA PadLock extensions.
145 Add xcrypt-ctr. Provide aliases without hyphens.
147 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
149 Moved from ../ChangeLog
151 2005-04-12 Paul Brook <paul@codesourcery.com>
152 * m88k.h: Rename psr macros to avoid conflicts.
154 2005-03-12 Zack Weinberg <zack@codesourcery.com>
155 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
156 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
159 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
160 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
161 Remove redundant instruction types.
162 (struct argument): X_op - new field.
163 (struct cst4_entry): Remove.
164 (no_op_insn): Declare.
166 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
167 * crx.h (enum argtype): Rename types, remove unused types.
169 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
170 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
171 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
172 (enum operand_type): Rearrange operands, edit comments.
173 replace us<N> with ui<N> for unsigned immediate.
174 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
175 displacements (respectively).
176 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
177 (instruction type): Add NO_TYPE_INS.
178 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
179 (operand_entry): New field - 'flags'.
180 (operand flags): New.
182 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
183 * crx.h (operand_type): Remove redundant types i3, i4,
185 Add new unsigned immediate types us3, us4, us5, us16.
187 2005-04-12 Mark Kettenis <kettenis@gnu.org>
189 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
190 adjust them accordingly.
192 2005-04-01 Jan Beulich <jbeulich@novell.com>
194 * i386.h (i386_optab): Add rdtscp.
196 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
198 * i386.h (i386_optab): Don't allow the `l' suffix for moving
199 between memory and segment register. Allow movq for moving between
200 general-purpose register and segment register.
202 2005-02-09 Jan Beulich <jbeulich@novell.com>
205 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
206 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
209 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
211 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
212 * cgen.h (enum cgen_parse_operand_type): Add
213 CGEN_PARSE_OPERAND_SYMBOLIC.
215 2005-01-21 Fred Fish <fnf@specifixinc.com>
217 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
218 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
219 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
221 2005-01-19 Fred Fish <fnf@specifixinc.com>
223 * mips.h (struct mips_opcode): Add new pinfo2 member.
224 (INSN_ALIAS): New define for opcode table entries that are
225 specific instances of another entry, such as 'move' for an 'or'
227 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
228 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
230 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
232 * mips.h (CPU_RM9000): Define.
233 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
235 2004-11-25 Jan Beulich <jbeulich@novell.com>
237 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
238 to/from test registers are illegal in 64-bit mode. Add missing
239 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
240 (previously one had to explicitly encode a rex64 prefix). Re-enable
241 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
242 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
244 2004-11-23 Jan Beulich <jbeulich@novell.com>
246 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
247 available only with SSE2. Change the MMX additions introduced by SSE
248 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
249 instructions by their now designated identifier (since combining i686
250 and 3DNow! does not really imply 3DNow!A).
252 2004-11-19 Alan Modra <amodra@bigpond.net.au>
254 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
255 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
257 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
258 Vineet Sharma <vineets@noida.hcltech.com>
260 * maxq.h: New file: Disassembly information for the maxq port.
262 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
264 * i386.h (i386_optab): Put back "movzb".
266 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
268 * cris.h (enum cris_insn_version_usage): Tweak formatting and
269 comments. Remove member cris_ver_sim. Add members
270 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
271 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
272 (struct cris_support_reg, struct cris_cond15): New types.
273 (cris_conds15): Declare.
274 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
275 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
276 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
277 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
278 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
281 2004-11-04 Jan Beulich <jbeulich@novell.com>
283 * i386.h (sldx_Suf): Remove.
284 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
285 (q_FP): Define, implying no REX64.
286 (x_FP, sl_FP): Imply FloatMF.
287 (i386_optab): Split reg and mem forms of moving from segment registers
288 so that the memory forms can ignore the 16-/32-bit operand size
289 distinction. Adjust a few others for Intel mode. Remove *FP uses from
290 all non-floating-point instructions. Unite 32- and 64-bit forms of
291 movsx, movzx, and movd. Adjust floating point operations for the above
292 changes to the *FP macros. Add DefaultSize to floating point control
293 insns operating on larger memory ranges. Remove left over comments
294 hinting at certain insns being Intel-syntax ones where the ones
295 actually meant are already gone.
297 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
299 * crx.h: Add COPS_REG_INS - Coprocessor Special register
302 2004-09-30 Paul Brook <paul@codesourcery.com>
304 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
305 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
307 2004-09-11 Theodore A. Roth <troth@openavr.org>
309 * avr.h: Add support for
310 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
312 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
314 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
316 2004-08-24 Dmitry Diky <diwil@spec.ru>
318 * msp430.h (msp430_opc): Add new instructions.
319 (msp430_rcodes): Declare new instructions.
320 (msp430_hcodes): Likewise..
322 2004-08-13 Nick Clifton <nickc@redhat.com>
325 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
328 2004-08-30 Michal Ludvig <mludvig@suse.cz>
330 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
332 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
334 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
336 2004-07-21 Jan Beulich <jbeulich@novell.com>
338 * i386.h: Adjust instruction descriptions to better match the
341 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
343 * arm.h: Remove all old content. Replace with architecture defines
344 from gas/config/tc-arm.c.
346 2004-07-09 Andreas Schwab <schwab@suse.de>
348 * m68k.h: Fix comment.
350 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
354 2004-06-24 Alan Modra <amodra@bigpond.net.au>
356 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
358 2004-05-24 Peter Barada <peter@the-baradas.com>
360 * m68k.h: Add 'size' to m68k_opcode.
362 2004-05-05 Peter Barada <peter@the-baradas.com>
364 * m68k.h: Switch from ColdFire chip name to core variant.
366 2004-04-22 Peter Barada <peter@the-baradas.com>
368 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
369 descriptions for new EMAC cases.
370 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
371 handle Motorola MAC syntax.
372 Allow disassembly of ColdFire V4e object files.
374 2004-03-16 Alan Modra <amodra@bigpond.net.au>
376 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
378 2004-03-12 Jakub Jelinek <jakub@redhat.com>
380 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
382 2004-03-12 Michal Ludvig <mludvig@suse.cz>
384 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
386 2004-03-12 Michal Ludvig <mludvig@suse.cz>
388 * i386.h (i386_optab): Added xstore/xcrypt insns.
390 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
392 * h8300.h (32bit ldc/stc): Add relaxing support.
394 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
396 * h8300.h (BITOP): Pass MEMRELAX flag.
398 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
400 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
403 For older changes see ChangeLog-9103
409 version-control: never