include/opcode/ChangeLog

   1 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
   2
   3         * score-datadep.h: New file.
   4         * score-inst.h: New file.
   5
   6 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
   9         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  10         movdq2q and movq2dq.
  11
  12 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  13            Michael Meissner             <michael.meissner@amd.com>
  14
  15         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  16
  17 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386.h (i386_optab): Add "nop" with memory reference.
  20
  21 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386.h (i386_optab): Update comment for 64bit NOP.
  24
  25 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  26             Anton Blanchard  <anton@samba.org>
  27
  28         * ppc.h (PPC_OPCODE_POWER6): Define.
  29         Adjust whitespace.
  30
  31 2006-06-05  Thiemo Seufer  <ths@mips.com>
  32
  33         * mips.h: Improve description of MT flags.
  34
  35 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  36
  37         * m68k.h (mcf_mask): Define.
  38
  39 2006-05-05  Thiemo Seufer  <ths@mips.com>
  40             David Ung  <davidu@mips.com>
  41
  42         * mips.h (enum): Add macro M_CACHE_AB.
  43
  44 2006-05-04  Thiemo Seufer  <ths@mips.com>
  45             Nigel Stephens  <nigel@mips.com>
  46             David Ung  <davidu@mips.com>
  47
  48         * mips.h: Add INSN_SMARTMIPS define.
  49
  50 2006-04-30  Thiemo Seufer  <ths@mips.com>
  51             David Ung  <davidu@mips.com>
  52
  53         * mips.h: Defines udi bits and masks.  Add description of
  54         characters which may appear in the args field of udi
  55         instructions.
  56
  57 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  58
  59         * mips.h: Improve comments describing the bitfield instruction
  60         fields.
  61
  62 2006-04-26  Julian Brown  <julian@codesourcery.com>
  63
  64         * arm.h (FPU_VFP_EXT_V3): Define constant.
  65         (FPU_NEON_EXT_V1): Likewise.
  66         (FPU_VFP_HARD): Update.
  67         (FPU_VFP_V3): Define macro.
  68         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  69
  70 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  71
  72         * avr.h (AVR_ISA_PWMx): New.
  73
  74 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  75
  76         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  77         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  78         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  79         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  80         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  81
  82 2006-03-10  Paul Brook  <paul@codesourcery.com>
  83
  84         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  85
  86 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  87
  88         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  89         first.  Correct mask of bb "B" opcode.
  90
  91 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  92
  93         * i386.h (i386_optab): Support Intel Merom New Instructions.
  94
  95 2006-02-24  Paul Brook  <paul@codesourcery.com>
  96
  97         * arm.h: Add V7 feature bits.
  98
  99 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 102
 103 2006-01-31  Paul Brook  <paul@codesourcery.com>
 104         Richard Earnshaw <rearnsha@arm.com>
 105
 106         * arm.h: Use ARM_CPU_FEATURE.
 107         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 108         (arm_feature_set): Change to a structure.
 109         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 110         ARM_FEATURE): New macros.
 111
 112 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 113
 114         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 115         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 116         (ADD_PC_INCR_OPCODE): Don't define.
 117
 118 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR gas/1874
 121         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 122
 123 2005-11-14  David Ung  <davidu@mips.com>
 124
 125         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 126         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 127         save/restore encoding of the args field.
 128
 129 2005-10-28  Dave Brolley  <brolley@redhat.com>
 130
 131         Contribute the following changes:
 132         2005-02-16  Dave Brolley  <brolley@redhat.com>
 133
 134         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 135         cgen_isa_mask_* to cgen_bitset_*.
 136         * cgen.h: Likewise.
 137
 138         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 139
 140         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 141         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 142         (CGEN_CPU_TABLE): Make isas a ponter.
 143
 144         2003-09-29  Dave Brolley  <brolley@redhat.com>
 145
 146         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 147         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 148         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 149
 150         2002-12-13  Dave Brolley  <brolley@redhat.com>
 151
 152         * cgen.h (symcat.h): #include it.
 153         (cgen-bitset.h): #include it.
 154         (CGEN_ATTR_VALUE_TYPE): Now a union.
 155         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 156         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 157         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 158         * cgen-bitset.h: New file.
 159
 160 2005-09-30  Catherine Moore  <clm@cm00re.com>
 161
 162         * bfin.h: New file.
 163
 164 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 165
 166         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 167         indirect operands.
 168
 169 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 170
 171         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 172         Add FLAG_STRICT to pa10 ftest opcode.
 173
 174 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 175
 176         * hppa.h (pa_opcodes): Remove lha entries.
 177
 178 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 179
 180         * hppa.h (FLAG_STRICT): Revise comment.
 181         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 182         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 183         entries for "fdc".
 184
 185 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 186
 187         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 188
 189 2005-09-06  Chao-ying Fu  <fu@mips.com>
 190
 191         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 192         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 193         define.
 194         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 195         (INSN_ASE_MASK): Update to include INSN_MT.
 196         (INSN_MT): New define for MT ASE.
 197
 198 2005-08-25  Chao-ying Fu  <fu@mips.com>
 199
 200         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 201         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 202         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 203         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 204         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 205         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 206         instructions.
 207         (INSN_DSP): New define for DSP ASE.
 208
 209 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 210
 211         * a29k.h: Delete.
 212
 213 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 214
 215         * ppc.h (PPC_OPCODE_E300): Define.
 216
 217 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 218
 219         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 220
 221 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 222
 223         PR gas/336
 224         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 225         and pitlb.
 226
 227 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 228
 229         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 230         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 231         Add movq-s as 64-bit variants of movd-s.
 232
 233 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 234
 235         * hppa.h: Fix punctuation in comment.
 236
 237         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 238         implicit space-register addressing.  Set space-register bits on opcodes
 239         using implicit space-register addressing.  Add various missing pa20
 240         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 241         space-register addressing.  Use "fE" instead of "fe" in various
 242         fstw opcodes.
 243
 244 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 245
 246         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 247
 248 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 249
 250         * i386.h (i386_optab): Support Intel VMX Instructions.
 251
 252 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 253
 254         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 255
 256 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 257
 258         * i386.h (i386_optab): Add new insns.
 259
 260 2005-07-01  Nick Clifton  <nickc@redhat.com>
 261
 262         * sparc.h: Add typedefs to structure declarations.
 263
 264 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         PR 1013
 267         * i386.h (i386_optab): Update comments for 64bit addressing on
 268         mov. Allow 64bit addressing for mov and movq.
 269
 270 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 271
 272         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 273         respectively, in various floating-point load and store patterns.
 274
 275 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 276
 277         * hppa.h (FLAG_STRICT): Correct comment.
 278         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 279         PA 2.0 mneumonics when equivalent.  Entries with cache control
 280         completers now require PA 1.1.  Adjust whitespace.
 281
 282 2005-05-19  Anton Blanchard  <anton@samba.org>
 283
 284         * ppc.h (PPC_OPCODE_POWER5): Define.
 285
 286 2005-05-10  Nick Clifton  <nickc@redhat.com>
 287
 288         * Update the address and phone number of the FSF organization in
 289         the GPL notices in the following files:
 290         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 291         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 292         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 293         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 294         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 295         tic54x.h, tic80.h, v850.h, vax.h
 296
 297 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 298
 299         * i386.h (i386_optab): Add ht and hnt.
 300
 301 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 302
 303         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 304         Add xcrypt-ctr.  Provide aliases without hyphens.
 305
 306 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 307
 308         Moved from ../ChangeLog
 309
 310         2005-04-12  Paul Brook  <paul@codesourcery.com>
 311         * m88k.h: Rename psr macros to avoid conflicts.
 312
 313         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 314         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 315         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 316         and ARM_ARCH_V6ZKT2.
 317
 318         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 319         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 320         Remove redundant instruction types.
 321         (struct argument): X_op - new field.
 322         (struct cst4_entry): Remove.
 323         (no_op_insn): Declare.
 324
 325         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 326         * crx.h (enum argtype): Rename types, remove unused types.
 327
 328         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 329         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 330         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 331         (enum operand_type): Rearrange operands, edit comments.
 332         replace us<N> with ui<N> for unsigned immediate.
 333         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 334         displacements (respectively).
 335         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 336         (instruction type): Add NO_TYPE_INS.
 337         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 338         (operand_entry): New field - 'flags'.
 339         (operand flags): New.
 340
 341         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 342         * crx.h (operand_type): Remove redundant types i3, i4,
 343         i5, i8, i12.
 344         Add new unsigned immediate types us3, us4, us5, us16.
 345
 346 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 347
 348         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 349         adjust them accordingly.
 350
 351 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 352
 353         * i386.h (i386_optab): Add rdtscp.
 354
 355 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 358         between memory and segment register. Allow movq for moving between
 359         general-purpose register and segment register.
 360
 361 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 362
 363         PR gas/707
 364         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 365         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 366         fnstsw.
 367
 368 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 369
 370         * m68k.h (m68008, m68ec030, m68882): Remove.
 371         (m68k_mask): New.
 372         (cpu_m68k, cpu_cf): New.
 373         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 374         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 375
 376 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 377
 378         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 379         * cgen.h (enum cgen_parse_operand_type): Add
 380         CGEN_PARSE_OPERAND_SYMBOLIC.
 381
 382 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 383
 384         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 385         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 386         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 387
 388 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 389
 390         * mips.h (struct mips_opcode): Add new pinfo2 member.
 391         (INSN_ALIAS): New define for opcode table entries that are
 392         specific instances of another entry, such as 'move' for an 'or'
 393         with a zero operand.
 394         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 395         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 396
 397 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 398
 399         * mips.h (CPU_RM9000): Define.
 400         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 401
 402 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 403
 404         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 405         to/from test registers are illegal in 64-bit mode. Add missing
 406         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 407         (previously one had to explicitly encode a rex64 prefix). Re-enable
 408         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 409         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 410
 411 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 412
 413         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 414         available only with SSE2. Change the MMX additions introduced by SSE
 415         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 416         instructions by their now designated identifier (since combining i686
 417         and 3DNow! does not really imply 3DNow!A).
 418
 419 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 420
 421         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 422         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 423
 424 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 425             Vineet Sharma      <vineets@noida.hcltech.com>
 426
 427         * maxq.h: New file: Disassembly information for the maxq port.
 428
 429 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         * i386.h (i386_optab): Put back "movzb".
 432
 433 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 434
 435         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 436         comments.  Remove member cris_ver_sim.  Add members
 437         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 438         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 439         (struct cris_support_reg, struct cris_cond15): New types.
 440         (cris_conds15): Declare.
 441         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 442         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 443         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 444         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 445         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 446         SIZE_FIELD_UNSIGNED.
 447
 448 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 449
 450         * i386.h (sldx_Suf): Remove.
 451         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 452         (q_FP): Define, implying no REX64.
 453         (x_FP, sl_FP): Imply FloatMF.
 454         (i386_optab): Split reg and mem forms of moving from segment registers
 455         so that the memory forms can ignore the 16-/32-bit operand size
 456         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 457         all non-floating-point instructions. Unite 32- and 64-bit forms of
 458         movsx, movzx, and movd. Adjust floating point operations for the above
 459         changes to the *FP macros. Add DefaultSize to floating point control
 460         insns operating on larger memory ranges. Remove left over comments
 461         hinting at certain insns being Intel-syntax ones where the ones
 462         actually meant are already gone.
 463
 464 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 465
 466         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 467         instruction type.
 468
 469 2004-09-30  Paul Brook  <paul@codesourcery.com>
 470
 471         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 472         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 473
 474 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 475
 476         * avr.h: Add support for
 477         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 478
 479 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 480
 481         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 482
 483 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 484
 485         * msp430.h (msp430_opc): Add new instructions.
 486         (msp430_rcodes): Declare new instructions.
 487         (msp430_hcodes): Likewise..
 488
 489 2004-08-13  Nick Clifton  <nickc@redhat.com>
 490
 491         PR/301
 492         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 493         processors.
 494
 495 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 496
 497         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 498
 499 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 502
 503 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 504
 505         * i386.h: Adjust instruction descriptions to better match the
 506         specification.
 507
 508 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 509
 510         * arm.h: Remove all old content.  Replace with architecture defines
 511         from gas/config/tc-arm.c.
 512
 513 2004-07-09  Andreas Schwab  <schwab@suse.de>
 514
 515         * m68k.h: Fix comment.
 516
 517 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 518
 519         * crx.h: New file.
 520
 521 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 522
 523         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 524
 525 2004-05-24  Peter Barada  <peter@the-baradas.com>
 526
 527         * m68k.h: Add 'size' to m68k_opcode.
 528
 529 2004-05-05  Peter Barada  <peter@the-baradas.com>
 530
 531         * m68k.h: Switch from ColdFire chip name to core variant.
 532
 533 2004-04-22  Peter Barada  <peter@the-baradas.com>
 534
 535         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 536         descriptions for new EMAC cases.
 537         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 538         handle Motorola MAC syntax.
 539         Allow disassembly of ColdFire V4e object files.
 540
 541 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 544
 545 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 546
 547         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 548
 549 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 550
 551         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 552
 553 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 554
 555         * i386.h (i386_optab): Added xstore/xcrypt insns.
 556
 557 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 558
 559         * h8300.h (32bit ldc/stc): Add relaxing support.
 560
 561 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 562
 563         * h8300.h (BITOP): Pass MEMRELAX flag.
 564
 565 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 566
 567         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 568         except for the H8S.
 569
 570 For older changes see ChangeLog-9103
 571 \f
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