1 2010-09-21 Mike Frysinger <vapier@gentoo.org>
3 * bfin.h: Strip trailing whitespace.
5 2010-07-29 DJ Delorie <dj@redhat.com>
7 * rx.h (RX_Operand_Type): Add TwoReg.
8 (RX_Opcode_ID): Remove ediv and ediv2.
10 2010-07-27 DJ Delorie <dj@redhat.com>
12 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
14 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
15 Ina Pandit <ina.pandit@kpitcummins.com>
17 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
18 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
20 Remove PROCESSOR_V850EA support.
21 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
22 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
23 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
24 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
25 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
27 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
29 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
32 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
34 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
35 (MIPS16_INSN_BRANCH): Rename to...
36 (MIPS16_INSN_COND_BRANCH): ... this.
38 2010-07-03 Alan Modra <amodra@gmail.com>
40 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
41 Renumber other PPC_OPCODE defines.
43 2010-07-03 Alan Modra <amodra@gmail.com>
45 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
47 2010-06-29 Alan Modra <amodra@gmail.com>
49 * maxq.h: Delete file.
51 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
53 * ppc.h (PPC_OPCODE_E500): Define.
55 2010-05-26 Catherine Moore <clm@codesourcery.com>
57 * opcode/mips.h (INSN_MIPS16): Remove.
59 2010-04-21 Joseph Myers <joseph@codesourcery.com>
61 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
63 2010-04-15 Nick Clifton <nickc@redhat.com>
65 * alpha.h: Update copyright notice to use GPLv3.
85 * m68hc11.h: Likewise.
91 * mn10200.h: Likewise.
92 * mn10300.h: Likewise.
104 * score-datadep.h: Likewise.
105 * score-inst.h: Likewise.
107 * spu-insns.h: Likewise.
111 * tic54x.h: Likewise.
116 2010-03-25 Joseph Myers <joseph@codesourcery.com>
118 * tic6x-control-registers.h, tic6x-insn-formats.h,
119 tic6x-opcode-table.h, tic6x.h: New.
121 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
123 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
125 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
127 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
129 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
131 * ia64.h (ia64_find_opcode): Remove argument name.
132 (ia64_find_next_opcode): Likewise.
133 (ia64_dis_opcode): Likewise.
134 (ia64_free_opcode): Likewise.
135 (ia64_find_dependency): Likewise.
137 2009-11-22 Doug Evans <dje@sebabeach.org>
139 * cgen.h: Include bfd_stdint.h.
140 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
142 2009-11-18 Paul Brook <paul@codesourcery.com>
144 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
146 2009-11-17 Paul Brook <paul@codesourcery.com>
147 Daniel Jacobowitz <dan@codesourcery.com>
149 * arm.h (ARM_EXT_V6_DSP): Define.
150 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
151 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
153 2009-11-04 DJ Delorie <dj@redhat.com>
155 * rx.h (rx_decode_opcode) (mvtipl): Add.
156 (mvtcp, mvfcp, opecp): Remove.
158 2009-11-02 Paul Brook <paul@codesourcery.com>
160 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
161 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
162 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
163 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
164 FPU_ARCH_NEON_VFP_V4): Define.
166 2009-10-23 Doug Evans <dje@sebabeach.org>
168 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
169 * cgen.h: Update. Improve multi-inclusion macro name.
171 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
173 * ppc.h (PPC_OPCODE_476): Define.
175 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
177 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
179 2009-09-29 DJ Delorie <dj@redhat.com>
183 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
185 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
187 2009-09-21 Ben Elliston <bje@au.ibm.com>
189 * ppc.h (PPC_OPCODE_PPCA2): New.
191 2009-09-05 Martin Thuresson <martin@mtme.org>
193 * ia64.h (struct ia64_operand): Renamed member class to op_class.
195 2009-08-29 Martin Thuresson <martin@mtme.org>
197 * tic30.h (template): Rename type template to
198 insn_template. Updated code to use new name.
199 * tic54x.h (template): Rename type template to
202 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
204 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
206 2009-06-11 Anthony Green <green@moxielogic.com>
208 * moxie.h (MOXIE_F3_PCREL): Define.
209 (moxie_form3_opc_info): Grow.
211 2009-06-06 Anthony Green <green@moxielogic.com>
213 * moxie.h (MOXIE_F1_M): Define.
215 2009-04-15 Anthony Green <green@moxielogic.com>
219 2009-04-06 DJ Delorie <dj@redhat.com>
221 * h8300.h: Add relaxation attributes to MOVA opcodes.
223 2009-03-10 Alan Modra <amodra@bigpond.net.au>
225 * ppc.h (ppc_parse_cpu): Declare.
227 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
229 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
230 and _IMM11 for mbitclr and mbitset.
231 * score-datadep.h: Update dependency information.
233 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
235 * ppc.h (PPC_OPCODE_POWER7): New.
237 2009-02-06 Doug Evans <dje@google.com>
239 * i386.h: Add comment regarding sse* insns and prefixes.
241 2009-02-03 Sandip Matte <sandip@rmicorp.com>
243 * mips.h (INSN_XLR): Define.
244 (INSN_CHIP_MASK): Update.
246 (OPCODE_IS_MEMBER): Update.
247 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
249 2009-01-28 Doug Evans <dje@google.com>
251 * opcode/i386.h: Add multiple inclusion protection.
252 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
253 (EDI_REG_NUM): New macros.
254 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
255 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
256 (REX_PREFIX_P): New macro.
258 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
260 * ppc.h (struct powerpc_opcode): New field "deprecated".
261 (PPC_OPCODE_NOPOWER4): Delete.
263 2008-11-28 Joshua Kinard <kumba@gentoo.org>
265 * mips.h: Define CPU_R14000, CPU_R16000.
266 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
268 2008-11-18 Catherine Moore <clm@codesourcery.com>
270 * arm.h (FPU_NEON_FP16): New.
271 (FPU_ARCH_NEON_FP16): New.
273 2008-11-06 Chao-ying Fu <fu@mips.com>
275 * mips.h: Doucument '1' for 5-bit sync type.
277 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
279 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
282 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
284 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
286 2008-07-30 Michael J. Eager <eager@eagercon.com>
288 * ppc.h (PPC_OPCODE_405): Define.
289 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
291 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
293 * ppc.h (ppc_cpu_t): New typedef.
294 (struct powerpc_opcode <flags>): Use it.
295 (struct powerpc_operand <insert, extract>): Likewise.
296 (struct powerpc_macro <flags>): Likewise.
298 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
300 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
301 Update comment before MIPS16 field descriptors to mention MIPS16.
302 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
304 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
305 New bit masks and shift counts for cins and exts.
307 * mips.h: Document new field descriptors +Q.
308 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
310 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
312 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
313 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
315 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
317 * ppc.h: (PPC_OPCODE_E500MC): New.
319 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
321 * i386.h (MAX_OPERANDS): Set to 5.
322 (MAX_MNEM_SIZE): Changed to 20.
324 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
326 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
328 2008-03-09 Paul Brook <paul@codesourcery.com>
330 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
332 2008-03-04 Paul Brook <paul@codesourcery.com>
334 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
335 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
336 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
338 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
339 Nick Clifton <nickc@redhat.com>
342 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
343 with a 32-bit displacement but without the top bit of the 4th byte
346 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
348 * cr16.h (cr16_num_optab): Declared.
350 2008-02-14 Hakan Ardo <hakan@debian.org>
353 * avr.h (AVR_ISA_2xxe): Define.
355 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
357 * mips.h: Update copyright.
358 (INSN_CHIP_MASK): New macro.
359 (INSN_OCTEON): New macro.
360 (CPU_OCTEON): New macro.
361 (OPCODE_IS_MEMBER): Handle Octeon instructions.
363 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
365 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
367 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
369 * avr.h (AVR_ISA_USB162): Add new opcode set.
370 (AVR_ISA_AVR3): Likewise.
372 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
374 * mips.h (INSN_LOONGSON_2E): New.
375 (INSN_LOONGSON_2F): New.
376 (CPU_LOONGSON_2E): New.
377 (CPU_LOONGSON_2F): New.
378 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
380 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
382 * mips.h (INSN_ISA*): Redefine certain values as an
383 enumeration. Update comments.
384 (mips_isa_table): New.
385 (ISA_MIPS*): Redefine to match enumeration.
386 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
389 2007-08-08 Ben Elliston <bje@au.ibm.com>
391 * ppc.h (PPC_OPCODE_PPCPS): New.
393 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
395 * m68k.h: Document j K & E.
397 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
399 * cr16.h: New file for CR16 target.
401 2007-05-02 Alan Modra <amodra@bigpond.net.au>
403 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
405 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
407 * m68k.h (mcfisa_c): New.
408 (mcfusp, mcf_mask): Adjust.
410 2007-04-20 Alan Modra <amodra@bigpond.net.au>
412 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
413 (num_powerpc_operands): Declare.
414 (PPC_OPERAND_SIGNED et al): Redefine as hex.
415 (PPC_OPERAND_PLUS1): Define.
417 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
419 * i386.h (REX_MODE64): Renamed to ...
421 (REX_EXTX): Renamed to ...
423 (REX_EXTY): Renamed to ...
425 (REX_EXTZ): Renamed to ...
428 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
430 * i386.h: Add entries from config/tc-i386.h and move tables
431 to opcodes/i386-opc.h.
433 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
435 * i386.h (FloatDR): Removed.
436 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
438 2007-03-01 Alan Modra <amodra@bigpond.net.au>
440 * spu-insns.h: Add soma double-float insns.
442 2007-02-20 Thiemo Seufer <ths@mips.com>
443 Chao-Ying Fu <fu@mips.com>
445 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
446 (INSN_DSPR2): Add flag for DSP R2 instructions.
447 (M_BALIGN): New macro.
449 2007-02-14 Alan Modra <amodra@bigpond.net.au>
451 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
452 and Seg3ShortFrom with Shortform.
454 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
457 * i386.h (i386_optab): Put the real "test" before the pseudo
460 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
462 * m68k.h (m68010up): OR fido_a.
464 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
466 * m68k.h (fido_a): New.
468 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
470 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
471 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
474 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
476 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
478 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
480 * score-inst.h (enum score_insn_type): Add Insn_internal.
482 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
483 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
484 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
485 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
486 Alan Modra <amodra@bigpond.net.au>
488 * spu-insns.h: New file.
491 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
493 * ppc.h (PPC_OPCODE_CELL): Define.
495 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
497 * i386.h : Modify opcode to support for the change in POPCNT opcode
498 in amdfam10 architecture.
500 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
502 * i386.h: Replace CpuMNI with CpuSSSE3.
504 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
505 Joseph Myers <joseph@codesourcery.com>
506 Ian Lance Taylor <ian@wasabisystems.com>
507 Ben Elliston <bje@wasabisystems.com>
509 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
511 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
513 * score-datadep.h: New file.
514 * score-inst.h: New file.
516 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
518 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
519 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
522 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
523 Michael Meissner <michael.meissner@amd.com>
525 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
527 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
529 * i386.h (i386_optab): Add "nop" with memory reference.
531 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
533 * i386.h (i386_optab): Update comment for 64bit NOP.
535 2006-06-06 Ben Elliston <bje@au.ibm.com>
536 Anton Blanchard <anton@samba.org>
538 * ppc.h (PPC_OPCODE_POWER6): Define.
541 2006-06-05 Thiemo Seufer <ths@mips.com>
543 * mips.h: Improve description of MT flags.
545 2006-05-25 Richard Sandiford <richard@codesourcery.com>
547 * m68k.h (mcf_mask): Define.
549 2006-05-05 Thiemo Seufer <ths@mips.com>
550 David Ung <davidu@mips.com>
552 * mips.h (enum): Add macro M_CACHE_AB.
554 2006-05-04 Thiemo Seufer <ths@mips.com>
555 Nigel Stephens <nigel@mips.com>
556 David Ung <davidu@mips.com>
558 * mips.h: Add INSN_SMARTMIPS define.
560 2006-04-30 Thiemo Seufer <ths@mips.com>
561 David Ung <davidu@mips.com>
563 * mips.h: Defines udi bits and masks. Add description of
564 characters which may appear in the args field of udi
567 2006-04-26 Thiemo Seufer <ths@networkno.de>
569 * mips.h: Improve comments describing the bitfield instruction
572 2006-04-26 Julian Brown <julian@codesourcery.com>
574 * arm.h (FPU_VFP_EXT_V3): Define constant.
575 (FPU_NEON_EXT_V1): Likewise.
576 (FPU_VFP_HARD): Update.
577 (FPU_VFP_V3): Define macro.
578 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
580 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
582 * avr.h (AVR_ISA_PWMx): New.
584 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
586 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
587 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
588 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
589 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
590 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
592 2006-03-10 Paul Brook <paul@codesourcery.com>
594 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
596 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
598 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
599 first. Correct mask of bb "B" opcode.
601 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
603 * i386.h (i386_optab): Support Intel Merom New Instructions.
605 2006-02-24 Paul Brook <paul@codesourcery.com>
607 * arm.h: Add V7 feature bits.
609 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
611 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
613 2006-01-31 Paul Brook <paul@codesourcery.com>
614 Richard Earnshaw <rearnsha@arm.com>
616 * arm.h: Use ARM_CPU_FEATURE.
617 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
618 (arm_feature_set): Change to a structure.
619 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
620 ARM_FEATURE): New macros.
622 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
624 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
625 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
626 (ADD_PC_INCR_OPCODE): Don't define.
628 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
631 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
633 2005-11-14 David Ung <davidu@mips.com>
635 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
636 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
637 save/restore encoding of the args field.
639 2005-10-28 Dave Brolley <brolley@redhat.com>
641 Contribute the following changes:
642 2005-02-16 Dave Brolley <brolley@redhat.com>
644 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
645 cgen_isa_mask_* to cgen_bitset_*.
648 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
650 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
651 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
652 (CGEN_CPU_TABLE): Make isas a ponter.
654 2003-09-29 Dave Brolley <brolley@redhat.com>
656 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
657 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
658 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
660 2002-12-13 Dave Brolley <brolley@redhat.com>
662 * cgen.h (symcat.h): #include it.
663 (cgen-bitset.h): #include it.
664 (CGEN_ATTR_VALUE_TYPE): Now a union.
665 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
666 (CGEN_ATTR_ENTRY): 'value' now unsigned.
667 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
668 * cgen-bitset.h: New file.
670 2005-09-30 Catherine Moore <clm@cm00re.com>
674 2005-10-24 Jan Beulich <jbeulich@novell.com>
676 * ia64.h (enum ia64_opnd): Move memory operand out of set of
679 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
681 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
682 Add FLAG_STRICT to pa10 ftest opcode.
684 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
686 * hppa.h (pa_opcodes): Remove lha entries.
688 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
690 * hppa.h (FLAG_STRICT): Revise comment.
691 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
692 before corresponding pa11 opcodes. Add strict pa10 register-immediate
695 2005-09-30 Catherine Moore <clm@cm00re.com>
699 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
701 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
703 2005-09-06 Chao-ying Fu <fu@mips.com>
705 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
706 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
708 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
709 (INSN_ASE_MASK): Update to include INSN_MT.
710 (INSN_MT): New define for MT ASE.
712 2005-08-25 Chao-ying Fu <fu@mips.com>
714 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
715 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
716 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
717 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
718 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
719 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
721 (INSN_DSP): New define for DSP ASE.
723 2005-08-18 Alan Modra <amodra@bigpond.net.au>
727 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
729 * ppc.h (PPC_OPCODE_E300): Define.
731 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
733 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
735 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
738 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
741 2005-07-27 Jan Beulich <jbeulich@novell.com>
743 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
744 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
745 Add movq-s as 64-bit variants of movd-s.
747 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
749 * hppa.h: Fix punctuation in comment.
751 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
752 implicit space-register addressing. Set space-register bits on opcodes
753 using implicit space-register addressing. Add various missing pa20
754 long-immediate opcodes. Remove various opcodes using implicit 3-bit
755 space-register addressing. Use "fE" instead of "fe" in various
758 2005-07-18 Jan Beulich <jbeulich@novell.com>
760 * i386.h (i386_optab): Operands of aam and aad are unsigned.
762 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
764 * i386.h (i386_optab): Support Intel VMX Instructions.
766 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
768 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
770 2005-07-05 Jan Beulich <jbeulich@novell.com>
772 * i386.h (i386_optab): Add new insns.
774 2005-07-01 Nick Clifton <nickc@redhat.com>
776 * sparc.h: Add typedefs to structure declarations.
778 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
781 * i386.h (i386_optab): Update comments for 64bit addressing on
782 mov. Allow 64bit addressing for mov and movq.
784 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
786 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
787 respectively, in various floating-point load and store patterns.
789 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
791 * hppa.h (FLAG_STRICT): Correct comment.
792 (pa_opcodes): Update load and store entries to allow both PA 1.X and
793 PA 2.0 mneumonics when equivalent. Entries with cache control
794 completers now require PA 1.1. Adjust whitespace.
796 2005-05-19 Anton Blanchard <anton@samba.org>
798 * ppc.h (PPC_OPCODE_POWER5): Define.
800 2005-05-10 Nick Clifton <nickc@redhat.com>
802 * Update the address and phone number of the FSF organization in
803 the GPL notices in the following files:
804 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
805 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
806 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
807 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
808 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
809 tic54x.h, tic80.h, v850.h, vax.h
811 2005-05-09 Jan Beulich <jbeulich@novell.com>
813 * i386.h (i386_optab): Add ht and hnt.
815 2005-04-18 Mark Kettenis <kettenis@gnu.org>
817 * i386.h: Insert hyphens into selected VIA PadLock extensions.
818 Add xcrypt-ctr. Provide aliases without hyphens.
820 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
822 Moved from ../ChangeLog
824 2005-04-12 Paul Brook <paul@codesourcery.com>
825 * m88k.h: Rename psr macros to avoid conflicts.
827 2005-03-12 Zack Weinberg <zack@codesourcery.com>
828 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
829 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
832 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
833 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
834 Remove redundant instruction types.
835 (struct argument): X_op - new field.
836 (struct cst4_entry): Remove.
837 (no_op_insn): Declare.
839 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
840 * crx.h (enum argtype): Rename types, remove unused types.
842 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
843 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
844 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
845 (enum operand_type): Rearrange operands, edit comments.
846 replace us<N> with ui<N> for unsigned immediate.
847 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
848 displacements (respectively).
849 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
850 (instruction type): Add NO_TYPE_INS.
851 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
852 (operand_entry): New field - 'flags'.
853 (operand flags): New.
855 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
856 * crx.h (operand_type): Remove redundant types i3, i4,
858 Add new unsigned immediate types us3, us4, us5, us16.
860 2005-04-12 Mark Kettenis <kettenis@gnu.org>
862 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
863 adjust them accordingly.
865 2005-04-01 Jan Beulich <jbeulich@novell.com>
867 * i386.h (i386_optab): Add rdtscp.
869 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
871 * i386.h (i386_optab): Don't allow the `l' suffix for moving
872 between memory and segment register. Allow movq for moving between
873 general-purpose register and segment register.
875 2005-02-09 Jan Beulich <jbeulich@novell.com>
878 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
879 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
882 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
884 * m68k.h (m68008, m68ec030, m68882): Remove.
886 (cpu_m68k, cpu_cf): New.
887 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
888 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
890 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
892 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
893 * cgen.h (enum cgen_parse_operand_type): Add
894 CGEN_PARSE_OPERAND_SYMBOLIC.
896 2005-01-21 Fred Fish <fnf@specifixinc.com>
898 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
899 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
900 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
902 2005-01-19 Fred Fish <fnf@specifixinc.com>
904 * mips.h (struct mips_opcode): Add new pinfo2 member.
905 (INSN_ALIAS): New define for opcode table entries that are
906 specific instances of another entry, such as 'move' for an 'or'
908 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
909 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
911 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
913 * mips.h (CPU_RM9000): Define.
914 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
916 2004-11-25 Jan Beulich <jbeulich@novell.com>
918 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
919 to/from test registers are illegal in 64-bit mode. Add missing
920 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
921 (previously one had to explicitly encode a rex64 prefix). Re-enable
922 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
923 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
925 2004-11-23 Jan Beulich <jbeulich@novell.com>
927 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
928 available only with SSE2. Change the MMX additions introduced by SSE
929 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
930 instructions by their now designated identifier (since combining i686
931 and 3DNow! does not really imply 3DNow!A).
933 2004-11-19 Alan Modra <amodra@bigpond.net.au>
935 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
936 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
938 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
939 Vineet Sharma <vineets@noida.hcltech.com>
941 * maxq.h: New file: Disassembly information for the maxq port.
943 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
945 * i386.h (i386_optab): Put back "movzb".
947 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
949 * cris.h (enum cris_insn_version_usage): Tweak formatting and
950 comments. Remove member cris_ver_sim. Add members
951 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
952 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
953 (struct cris_support_reg, struct cris_cond15): New types.
954 (cris_conds15): Declare.
955 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
956 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
957 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
958 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
959 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
962 2004-11-04 Jan Beulich <jbeulich@novell.com>
964 * i386.h (sldx_Suf): Remove.
965 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
966 (q_FP): Define, implying no REX64.
967 (x_FP, sl_FP): Imply FloatMF.
968 (i386_optab): Split reg and mem forms of moving from segment registers
969 so that the memory forms can ignore the 16-/32-bit operand size
970 distinction. Adjust a few others for Intel mode. Remove *FP uses from
971 all non-floating-point instructions. Unite 32- and 64-bit forms of
972 movsx, movzx, and movd. Adjust floating point operations for the above
973 changes to the *FP macros. Add DefaultSize to floating point control
974 insns operating on larger memory ranges. Remove left over comments
975 hinting at certain insns being Intel-syntax ones where the ones
976 actually meant are already gone.
978 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
980 * crx.h: Add COPS_REG_INS - Coprocessor Special register
983 2004-09-30 Paul Brook <paul@codesourcery.com>
985 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
986 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
988 2004-09-11 Theodore A. Roth <troth@openavr.org>
990 * avr.h: Add support for
991 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
993 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
995 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
997 2004-08-24 Dmitry Diky <diwil@spec.ru>
999 * msp430.h (msp430_opc): Add new instructions.
1000 (msp430_rcodes): Declare new instructions.
1001 (msp430_hcodes): Likewise..
1003 2004-08-13 Nick Clifton <nickc@redhat.com>
1006 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1009 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1011 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1013 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1015 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1017 2004-07-21 Jan Beulich <jbeulich@novell.com>
1019 * i386.h: Adjust instruction descriptions to better match the
1022 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1024 * arm.h: Remove all old content. Replace with architecture defines
1025 from gas/config/tc-arm.c.
1027 2004-07-09 Andreas Schwab <schwab@suse.de>
1029 * m68k.h: Fix comment.
1031 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1035 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1037 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1039 2004-05-24 Peter Barada <peter@the-baradas.com>
1041 * m68k.h: Add 'size' to m68k_opcode.
1043 2004-05-05 Peter Barada <peter@the-baradas.com>
1045 * m68k.h: Switch from ColdFire chip name to core variant.
1047 2004-04-22 Peter Barada <peter@the-baradas.com>
1049 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1050 descriptions for new EMAC cases.
1051 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1052 handle Motorola MAC syntax.
1053 Allow disassembly of ColdFire V4e object files.
1055 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1057 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1059 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1061 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1063 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1065 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1067 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1069 * i386.h (i386_optab): Added xstore/xcrypt insns.
1071 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1073 * h8300.h (32bit ldc/stc): Add relaxing support.
1075 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1077 * h8300.h (BITOP): Pass MEMRELAX flag.
1079 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1081 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1084 For older changes see ChangeLog-9103
1090 version-control: never