include/opcode/ChangeLog

   1 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/4027
   4         * i386.h (i386_optab): Put the real "test" before the pseudo
   5         one.
   6
   7 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
   8
   9         * m68k.h (m68010up): OR fido_a.
  10
  11 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  12
  13         * m68k.h (fido_a): New.
  14
  15 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  16
  17         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  18         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  19         values.
  20
  21 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  24
  25 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  26
  27         * score-inst.h (enum score_insn_type): Add Insn_internal.
  28
  29 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  30             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  31             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  32             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  33             Alan Modra  <amodra@bigpond.net.au>
  34
  35         * spu-insns.h: New file.
  36         * spu.h: New file.
  37
  38 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  39
  40         * ppc.h (PPC_OPCODE_CELL): Define.
  41
  42 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  43
  44         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  45         in amdfam10 architecture.
  46
  47 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * i386.h: Replace CpuMNI with CpuSSSE3.
  50
  51 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  52             Joseph Myers  <joseph@codesourcery.com>
  53             Ian Lance Taylor  <ian@wasabisystems.com>
  54             Ben Elliston  <bje@wasabisystems.com>
  55
  56         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  57
  58 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  59
  60         * score-datadep.h: New file.
  61         * score-inst.h: New file.
  62
  63 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  66         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  67         movdq2q and movq2dq.
  68
  69 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  70            Michael Meissner             <michael.meissner@amd.com>
  71
  72         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  73
  74 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * i386.h (i386_optab): Add "nop" with memory reference.
  77
  78 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  79
  80         * i386.h (i386_optab): Update comment for 64bit NOP.
  81
  82 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  83             Anton Blanchard  <anton@samba.org>
  84
  85         * ppc.h (PPC_OPCODE_POWER6): Define.
  86         Adjust whitespace.
  87
  88 2006-06-05  Thiemo Seufer  <ths@mips.com>
  89
  90         * mips.h: Improve description of MT flags.
  91
  92 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  93
  94         * m68k.h (mcf_mask): Define.
  95
  96 2006-05-05  Thiemo Seufer  <ths@mips.com>
  97             David Ung  <davidu@mips.com>
  98
  99         * mips.h (enum): Add macro M_CACHE_AB.
 100
 101 2006-05-04  Thiemo Seufer  <ths@mips.com>
 102             Nigel Stephens  <nigel@mips.com>
 103             David Ung  <davidu@mips.com>
 104
 105         * mips.h: Add INSN_SMARTMIPS define.
 106
 107 2006-04-30  Thiemo Seufer  <ths@mips.com>
 108             David Ung  <davidu@mips.com>
 109
 110         * mips.h: Defines udi bits and masks.  Add description of
 111         characters which may appear in the args field of udi
 112         instructions.
 113
 114 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 115
 116         * mips.h: Improve comments describing the bitfield instruction
 117         fields.
 118
 119 2006-04-26  Julian Brown  <julian@codesourcery.com>
 120
 121         * arm.h (FPU_VFP_EXT_V3): Define constant.
 122         (FPU_NEON_EXT_V1): Likewise.
 123         (FPU_VFP_HARD): Update.
 124         (FPU_VFP_V3): Define macro.
 125         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 126
 127 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 128
 129         * avr.h (AVR_ISA_PWMx): New.
 130
 131 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 132
 133         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 134         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 135         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 136         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 137         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 138
 139 2006-03-10  Paul Brook  <paul@codesourcery.com>
 140
 141         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 142
 143 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 144
 145         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 146         first.  Correct mask of bb "B" opcode.
 147
 148 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 149
 150         * i386.h (i386_optab): Support Intel Merom New Instructions.
 151
 152 2006-02-24  Paul Brook  <paul@codesourcery.com>
 153
 154         * arm.h: Add V7 feature bits.
 155
 156 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 159
 160 2006-01-31  Paul Brook  <paul@codesourcery.com>
 161         Richard Earnshaw <rearnsha@arm.com>
 162
 163         * arm.h: Use ARM_CPU_FEATURE.
 164         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 165         (arm_feature_set): Change to a structure.
 166         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 167         ARM_FEATURE): New macros.
 168
 169 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 170
 171         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 172         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 173         (ADD_PC_INCR_OPCODE): Don't define.
 174
 175 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         PR gas/1874
 178         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 179
 180 2005-11-14  David Ung  <davidu@mips.com>
 181
 182         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 183         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 184         save/restore encoding of the args field.
 185
 186 2005-10-28  Dave Brolley  <brolley@redhat.com>
 187
 188         Contribute the following changes:
 189         2005-02-16  Dave Brolley  <brolley@redhat.com>
 190
 191         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 192         cgen_isa_mask_* to cgen_bitset_*.
 193         * cgen.h: Likewise.
 194
 195         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 196
 197         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 198         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 199         (CGEN_CPU_TABLE): Make isas a ponter.
 200
 201         2003-09-29  Dave Brolley  <brolley@redhat.com>
 202
 203         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 204         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 205         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 206
 207         2002-12-13  Dave Brolley  <brolley@redhat.com>
 208
 209         * cgen.h (symcat.h): #include it.
 210         (cgen-bitset.h): #include it.
 211         (CGEN_ATTR_VALUE_TYPE): Now a union.
 212         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 213         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 214         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 215         * cgen-bitset.h: New file.
 216
 217 2005-09-30  Catherine Moore  <clm@cm00re.com>
 218
 219         * bfin.h: New file.
 220
 221 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 222
 223         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 224         indirect operands.
 225
 226 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 227
 228         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 229         Add FLAG_STRICT to pa10 ftest opcode.
 230
 231 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 232
 233         * hppa.h (pa_opcodes): Remove lha entries.
 234
 235 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 236
 237         * hppa.h (FLAG_STRICT): Revise comment.
 238         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 239         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 240         entries for "fdc".
 241
 242 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 243
 244         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 245
 246 2005-09-06  Chao-ying Fu  <fu@mips.com>
 247
 248         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 249         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 250         define.
 251         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 252         (INSN_ASE_MASK): Update to include INSN_MT.
 253         (INSN_MT): New define for MT ASE.
 254
 255 2005-08-25  Chao-ying Fu  <fu@mips.com>
 256
 257         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 258         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 259         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 260         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 261         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 262         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 263         instructions.
 264         (INSN_DSP): New define for DSP ASE.
 265
 266 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 267
 268         * a29k.h: Delete.
 269
 270 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 271
 272         * ppc.h (PPC_OPCODE_E300): Define.
 273
 274 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 275
 276         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 277
 278 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 279
 280         PR gas/336
 281         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 282         and pitlb.
 283
 284 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 285
 286         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 287         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 288         Add movq-s as 64-bit variants of movd-s.
 289
 290 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 291
 292         * hppa.h: Fix punctuation in comment.
 293
 294         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 295         implicit space-register addressing.  Set space-register bits on opcodes
 296         using implicit space-register addressing.  Add various missing pa20
 297         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 298         space-register addressing.  Use "fE" instead of "fe" in various
 299         fstw opcodes.
 300
 301 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 302
 303         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 304
 305 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 306
 307         * i386.h (i386_optab): Support Intel VMX Instructions.
 308
 309 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 310
 311         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 312
 313 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 314
 315         * i386.h (i386_optab): Add new insns.
 316
 317 2005-07-01  Nick Clifton  <nickc@redhat.com>
 318
 319         * sparc.h: Add typedefs to structure declarations.
 320
 321 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         PR 1013
 324         * i386.h (i386_optab): Update comments for 64bit addressing on
 325         mov. Allow 64bit addressing for mov and movq.
 326
 327 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 328
 329         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 330         respectively, in various floating-point load and store patterns.
 331
 332 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 333
 334         * hppa.h (FLAG_STRICT): Correct comment.
 335         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 336         PA 2.0 mneumonics when equivalent.  Entries with cache control
 337         completers now require PA 1.1.  Adjust whitespace.
 338
 339 2005-05-19  Anton Blanchard  <anton@samba.org>
 340
 341         * ppc.h (PPC_OPCODE_POWER5): Define.
 342
 343 2005-05-10  Nick Clifton  <nickc@redhat.com>
 344
 345         * Update the address and phone number of the FSF organization in
 346         the GPL notices in the following files:
 347         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 348         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 349         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 350         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 351         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 352         tic54x.h, tic80.h, v850.h, vax.h
 353
 354 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 355
 356         * i386.h (i386_optab): Add ht and hnt.
 357
 358 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 359
 360         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 361         Add xcrypt-ctr.  Provide aliases without hyphens.
 362
 363 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         Moved from ../ChangeLog
 366
 367         2005-04-12  Paul Brook  <paul@codesourcery.com>
 368         * m88k.h: Rename psr macros to avoid conflicts.
 369
 370         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 371         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 372         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 373         and ARM_ARCH_V6ZKT2.
 374
 375         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 376         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 377         Remove redundant instruction types.
 378         (struct argument): X_op - new field.
 379         (struct cst4_entry): Remove.
 380         (no_op_insn): Declare.
 381
 382         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 383         * crx.h (enum argtype): Rename types, remove unused types.
 384
 385         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 386         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 387         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 388         (enum operand_type): Rearrange operands, edit comments.
 389         replace us<N> with ui<N> for unsigned immediate.
 390         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 391         displacements (respectively).
 392         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 393         (instruction type): Add NO_TYPE_INS.
 394         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 395         (operand_entry): New field - 'flags'.
 396         (operand flags): New.
 397
 398         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 399         * crx.h (operand_type): Remove redundant types i3, i4,
 400         i5, i8, i12.
 401         Add new unsigned immediate types us3, us4, us5, us16.
 402
 403 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 404
 405         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 406         adjust them accordingly.
 407
 408 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 409
 410         * i386.h (i386_optab): Add rdtscp.
 411
 412 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 415         between memory and segment register. Allow movq for moving between
 416         general-purpose register and segment register.
 417
 418 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 419
 420         PR gas/707
 421         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 422         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 423         fnstsw.
 424
 425 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 426
 427         * m68k.h (m68008, m68ec030, m68882): Remove.
 428         (m68k_mask): New.
 429         (cpu_m68k, cpu_cf): New.
 430         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 431         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 432
 433 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 434
 435         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 436         * cgen.h (enum cgen_parse_operand_type): Add
 437         CGEN_PARSE_OPERAND_SYMBOLIC.
 438
 439 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 440
 441         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 442         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 443         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 444
 445 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 446
 447         * mips.h (struct mips_opcode): Add new pinfo2 member.
 448         (INSN_ALIAS): New define for opcode table entries that are
 449         specific instances of another entry, such as 'move' for an 'or'
 450         with a zero operand.
 451         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 452         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 453
 454 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 455
 456         * mips.h (CPU_RM9000): Define.
 457         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 458
 459 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 460
 461         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 462         to/from test registers are illegal in 64-bit mode. Add missing
 463         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 464         (previously one had to explicitly encode a rex64 prefix). Re-enable
 465         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 466         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 467
 468 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 469
 470         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 471         available only with SSE2. Change the MMX additions introduced by SSE
 472         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 473         instructions by their now designated identifier (since combining i686
 474         and 3DNow! does not really imply 3DNow!A).
 475
 476 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 477
 478         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 479         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 480
 481 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 482             Vineet Sharma      <vineets@noida.hcltech.com>
 483
 484         * maxq.h: New file: Disassembly information for the maxq port.
 485
 486 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386.h (i386_optab): Put back "movzb".
 489
 490 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 491
 492         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 493         comments.  Remove member cris_ver_sim.  Add members
 494         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 495         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 496         (struct cris_support_reg, struct cris_cond15): New types.
 497         (cris_conds15): Declare.
 498         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 499         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 500         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 501         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 502         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 503         SIZE_FIELD_UNSIGNED.
 504
 505 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 506
 507         * i386.h (sldx_Suf): Remove.
 508         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 509         (q_FP): Define, implying no REX64.
 510         (x_FP, sl_FP): Imply FloatMF.
 511         (i386_optab): Split reg and mem forms of moving from segment registers
 512         so that the memory forms can ignore the 16-/32-bit operand size
 513         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 514         all non-floating-point instructions. Unite 32- and 64-bit forms of
 515         movsx, movzx, and movd. Adjust floating point operations for the above
 516         changes to the *FP macros. Add DefaultSize to floating point control
 517         insns operating on larger memory ranges. Remove left over comments
 518         hinting at certain insns being Intel-syntax ones where the ones
 519         actually meant are already gone.
 520
 521 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 522
 523         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 524         instruction type.
 525
 526 2004-09-30  Paul Brook  <paul@codesourcery.com>
 527
 528         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 529         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 530
 531 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 532
 533         * avr.h: Add support for
 534         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 535
 536 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 537
 538         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 539
 540 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 541
 542         * msp430.h (msp430_opc): Add new instructions.
 543         (msp430_rcodes): Declare new instructions.
 544         (msp430_hcodes): Likewise..
 545
 546 2004-08-13  Nick Clifton  <nickc@redhat.com>
 547
 548         PR/301
 549         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 550         processors.
 551
 552 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 553
 554         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 555
 556 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 557
 558         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 559
 560 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 561
 562         * i386.h: Adjust instruction descriptions to better match the
 563         specification.
 564
 565 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 566
 567         * arm.h: Remove all old content.  Replace with architecture defines
 568         from gas/config/tc-arm.c.
 569
 570 2004-07-09  Andreas Schwab  <schwab@suse.de>
 571
 572         * m68k.h: Fix comment.
 573
 574 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 575
 576         * crx.h: New file.
 577
 578 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 579
 580         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 581
 582 2004-05-24  Peter Barada  <peter@the-baradas.com>
 583
 584         * m68k.h: Add 'size' to m68k_opcode.
 585
 586 2004-05-05  Peter Barada  <peter@the-baradas.com>
 587
 588         * m68k.h: Switch from ColdFire chip name to core variant.
 589
 590 2004-04-22  Peter Barada  <peter@the-baradas.com>
 591
 592         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 593         descriptions for new EMAC cases.
 594         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 595         handle Motorola MAC syntax.
 596         Allow disassembly of ColdFire V4e object files.
 597
 598 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 599
 600         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 601
 602 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 603
 604         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 605
 606 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 607
 608         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 609
 610 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 611
 612         * i386.h (i386_optab): Added xstore/xcrypt insns.
 613
 614 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 615
 616         * h8300.h (32bit ldc/stc): Add relaxing support.
 617
 618 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 619
 620         * h8300.h (BITOP): Pass MEMRELAX flag.
 621
 622 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 623
 624         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 625         except for the H8S.
 626
 627 For older changes see ChangeLog-9103
 628 \f
 629 Local Variables:
 630 mode: change-log
 631 left-margin: 8
 632 fill-column: 74
 633 version-control: never
 634 End: