include/opcode/ChangeLog

   1 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * ppc.h (struct powerpc_opcode): New field "deprecated".
   4         (PPC_OPCODE_NOPOWER4): Delete.
   5
   6 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
   7
   8         * mips.h: Define CPU_R14000, CPU_R16000.
   9         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  10
  11 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  12
  13         * arm.h (FPU_NEON_FP16): New.
  14         (FPU_ARCH_NEON_FP16): New.
  15
  16 2008-11-06  Chao-ying Fu  <fu@mips.com>
  17
  18         * mips.h: Doucument '1' for 5-bit sync type.
  19
  20 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  23         IA64_RS_CR.
  24
  25 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  26
  27         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  28
  29 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  30
  31         * ppc.h (PPC_OPCODE_405): Define.
  32         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  33
  34 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  35
  36         * ppc.h (ppc_cpu_t): New typedef.
  37         (struct powerpc_opcode <flags>): Use it.
  38         (struct powerpc_operand <insert, extract>): Likewise.
  39         (struct powerpc_macro <flags>): Likewise.
  40
  41 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  42
  43         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  44         Update comment before MIPS16 field descriptors to mention MIPS16.
  45         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  46         BBIT.
  47         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  48         New bit masks and shift counts for cins and exts.
  49
  50         * mips.h: Document new field descriptors +Q.
  51         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  52
  53 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  54
  55         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  56         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  57
  58 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  59
  60         * ppc.h: (PPC_OPCODE_E500MC): New.
  61
  62 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         * i386.h (MAX_OPERANDS): Set to 5.
  65         (MAX_MNEM_SIZE): Changed to 20.
  66
  67 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  68
  69         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  70
  71 2008-03-09  Paul Brook  <paul@codesourcery.com>
  72
  73         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  74
  75 2008-03-04  Paul Brook  <paul@codesourcery.com>
  76
  77         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  78         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
  79         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  80
  81 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  82             Nick Clifton  <nickc@redhat.com>
  83
  84         PR 3134
  85         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
  86         with a 32-bit displacement but without the top bit of the 4th byte
  87         set.
  88
  89 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  90
  91         * cr16.h (cr16_num_optab): Declared.
  92
  93 2008-02-14  Hakan Ardo  <hakan@debian.org>
  94
  95         PR gas/2626
  96         * avr.h (AVR_ISA_2xxe): Define.
  97
  98 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  99
 100         * mips.h: Update copyright.
 101         (INSN_CHIP_MASK): New macro.
 102         (INSN_OCTEON): New macro.
 103         (CPU_OCTEON): New macro.
 104         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 105
 106 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 107
 108         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 109
 110 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 111
 112         * avr.h (AVR_ISA_USB162): Add new opcode set.
 113         (AVR_ISA_AVR3): Likewise.
 114
 115 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 116
 117         * mips.h (INSN_LOONGSON_2E): New.
 118         (INSN_LOONGSON_2F): New.
 119         (CPU_LOONGSON_2E): New.
 120         (CPU_LOONGSON_2F): New.
 121         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 122
 123 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 124
 125         * mips.h (INSN_ISA*): Redefine certain values as an
 126         enumeration.  Update comments.
 127         (mips_isa_table): New.
 128         (ISA_MIPS*): Redefine to match enumeration.
 129         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 130         values.
 131
 132 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 133
 134         * ppc.h (PPC_OPCODE_PPCPS): New.
 135
 136 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 137
 138         * m68k.h: Document j K & E.
 139
 140 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 141
 142         * cr16.h: New file for CR16 target.
 143
 144 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 145
 146         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 147
 148 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 149
 150         * m68k.h (mcfisa_c): New.
 151         (mcfusp, mcf_mask): Adjust.
 152
 153 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 154
 155         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 156         (num_powerpc_operands): Declare.
 157         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 158         (PPC_OPERAND_PLUS1): Define.
 159
 160 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386.h (REX_MODE64): Renamed to ...
 163         (REX_W): This.
 164         (REX_EXTX): Renamed to ...
 165         (REX_R): This.
 166         (REX_EXTY): Renamed to ...
 167         (REX_X): This.
 168         (REX_EXTZ): Renamed to ...
 169         (REX_B): This.
 170
 171 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         * i386.h: Add entries from config/tc-i386.h and move tables
 174         to opcodes/i386-opc.h.
 175
 176 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * i386.h (FloatDR): Removed.
 179         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 180
 181 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 182
 183         * spu-insns.h: Add soma double-float insns.
 184
 185 2007-02-20  Thiemo Seufer  <ths@mips.com>
 186             Chao-Ying Fu  <fu@mips.com>
 187
 188         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 189         (INSN_DSPR2): Add flag for DSP R2 instructions.
 190         (M_BALIGN): New macro.
 191
 192 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 193
 194         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 195         and Seg3ShortFrom with Shortform.
 196
 197 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         PR gas/4027
 200         * i386.h (i386_optab): Put the real "test" before the pseudo
 201         one.
 202
 203 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 204
 205         * m68k.h (m68010up): OR fido_a.
 206
 207 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 208
 209         * m68k.h (fido_a): New.
 210
 211 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 212
 213         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 214         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 215         values.
 216
 217 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 218
 219         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 220
 221 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 222
 223         * score-inst.h (enum score_insn_type): Add Insn_internal.
 224
 225 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 226             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 227             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 228             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 229             Alan Modra  <amodra@bigpond.net.au>
 230
 231         * spu-insns.h: New file.
 232         * spu.h: New file.
 233
 234 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 235
 236         * ppc.h (PPC_OPCODE_CELL): Define.
 237
 238 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 239
 240         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 241         in amdfam10 architecture.
 242
 243 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * i386.h: Replace CpuMNI with CpuSSSE3.
 246
 247 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 248             Joseph Myers  <joseph@codesourcery.com>
 249             Ian Lance Taylor  <ian@wasabisystems.com>
 250             Ben Elliston  <bje@wasabisystems.com>
 251
 252         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 253
 254 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 255
 256         * score-datadep.h: New file.
 257         * score-inst.h: New file.
 258
 259 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 262         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 263         movdq2q and movq2dq.
 264
 265 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 266            Michael Meissner             <michael.meissner@amd.com>
 267
 268         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 269
 270 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         * i386.h (i386_optab): Add "nop" with memory reference.
 273
 274 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         * i386.h (i386_optab): Update comment for 64bit NOP.
 277
 278 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 279             Anton Blanchard  <anton@samba.org>
 280
 281         * ppc.h (PPC_OPCODE_POWER6): Define.
 282         Adjust whitespace.
 283
 284 2006-06-05  Thiemo Seufer  <ths@mips.com>
 285
 286         * mips.h: Improve description of MT flags.
 287
 288 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 289
 290         * m68k.h (mcf_mask): Define.
 291
 292 2006-05-05  Thiemo Seufer  <ths@mips.com>
 293             David Ung  <davidu@mips.com>
 294
 295         * mips.h (enum): Add macro M_CACHE_AB.
 296
 297 2006-05-04  Thiemo Seufer  <ths@mips.com>
 298             Nigel Stephens  <nigel@mips.com>
 299             David Ung  <davidu@mips.com>
 300
 301         * mips.h: Add INSN_SMARTMIPS define.
 302
 303 2006-04-30  Thiemo Seufer  <ths@mips.com>
 304             David Ung  <davidu@mips.com>
 305
 306         * mips.h: Defines udi bits and masks.  Add description of
 307         characters which may appear in the args field of udi
 308         instructions.
 309
 310 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 311
 312         * mips.h: Improve comments describing the bitfield instruction
 313         fields.
 314
 315 2006-04-26  Julian Brown  <julian@codesourcery.com>
 316
 317         * arm.h (FPU_VFP_EXT_V3): Define constant.
 318         (FPU_NEON_EXT_V1): Likewise.
 319         (FPU_VFP_HARD): Update.
 320         (FPU_VFP_V3): Define macro.
 321         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 322
 323 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 324
 325         * avr.h (AVR_ISA_PWMx): New.
 326
 327 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 328
 329         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 330         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 331         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 332         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 333         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 334
 335 2006-03-10  Paul Brook  <paul@codesourcery.com>
 336
 337         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 338
 339 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 340
 341         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 342         first.  Correct mask of bb "B" opcode.
 343
 344 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 345
 346         * i386.h (i386_optab): Support Intel Merom New Instructions.
 347
 348 2006-02-24  Paul Brook  <paul@codesourcery.com>
 349
 350         * arm.h: Add V7 feature bits.
 351
 352 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 353
 354         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 355
 356 2006-01-31  Paul Brook  <paul@codesourcery.com>
 357         Richard Earnshaw <rearnsha@arm.com>
 358
 359         * arm.h: Use ARM_CPU_FEATURE.
 360         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 361         (arm_feature_set): Change to a structure.
 362         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 363         ARM_FEATURE): New macros.
 364
 365 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 366
 367         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 368         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 369         (ADD_PC_INCR_OPCODE): Don't define.
 370
 371 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         PR gas/1874
 374         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 375
 376 2005-11-14  David Ung  <davidu@mips.com>
 377
 378         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 379         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 380         save/restore encoding of the args field.
 381
 382 2005-10-28  Dave Brolley  <brolley@redhat.com>
 383
 384         Contribute the following changes:
 385         2005-02-16  Dave Brolley  <brolley@redhat.com>
 386
 387         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 388         cgen_isa_mask_* to cgen_bitset_*.
 389         * cgen.h: Likewise.
 390
 391         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 392
 393         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 394         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 395         (CGEN_CPU_TABLE): Make isas a ponter.
 396
 397         2003-09-29  Dave Brolley  <brolley@redhat.com>
 398
 399         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 400         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 401         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 402
 403         2002-12-13  Dave Brolley  <brolley@redhat.com>
 404
 405         * cgen.h (symcat.h): #include it.
 406         (cgen-bitset.h): #include it.
 407         (CGEN_ATTR_VALUE_TYPE): Now a union.
 408         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 409         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 410         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 411         * cgen-bitset.h: New file.
 412
 413 2005-09-30  Catherine Moore  <clm@cm00re.com>
 414
 415         * bfin.h: New file.
 416
 417 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 418
 419         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 420         indirect operands.
 421
 422 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 425         Add FLAG_STRICT to pa10 ftest opcode.
 426
 427 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 428
 429         * hppa.h (pa_opcodes): Remove lha entries.
 430
 431 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 432
 433         * hppa.h (FLAG_STRICT): Revise comment.
 434         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 435         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 436         entries for "fdc".
 437
 438 2005-09-30  Catherine Moore  <clm@cm00re.com>
 439
 440         * bfin.h: New file.
 441
 442 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 443
 444         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 445
 446 2005-09-06  Chao-ying Fu  <fu@mips.com>
 447
 448         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 449         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 450         define.
 451         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 452         (INSN_ASE_MASK): Update to include INSN_MT.
 453         (INSN_MT): New define for MT ASE.
 454
 455 2005-08-25  Chao-ying Fu  <fu@mips.com>
 456
 457         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 458         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 459         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 460         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 461         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 462         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 463         instructions.
 464         (INSN_DSP): New define for DSP ASE.
 465
 466 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 467
 468         * a29k.h: Delete.
 469
 470 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 471
 472         * ppc.h (PPC_OPCODE_E300): Define.
 473
 474 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 475
 476         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 477
 478 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 479
 480         PR gas/336
 481         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 482         and pitlb.
 483
 484 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 485
 486         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 487         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 488         Add movq-s as 64-bit variants of movd-s.
 489
 490 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 491
 492         * hppa.h: Fix punctuation in comment.
 493
 494         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 495         implicit space-register addressing.  Set space-register bits on opcodes
 496         using implicit space-register addressing.  Add various missing pa20
 497         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 498         space-register addressing.  Use "fE" instead of "fe" in various
 499         fstw opcodes.
 500
 501 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 502
 503         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 504
 505 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 506
 507         * i386.h (i386_optab): Support Intel VMX Instructions.
 508
 509 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 510
 511         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 512
 513 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 514
 515         * i386.h (i386_optab): Add new insns.
 516
 517 2005-07-01  Nick Clifton  <nickc@redhat.com>
 518
 519         * sparc.h: Add typedefs to structure declarations.
 520
 521 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         PR 1013
 524         * i386.h (i386_optab): Update comments for 64bit addressing on
 525         mov. Allow 64bit addressing for mov and movq.
 526
 527 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 528
 529         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 530         respectively, in various floating-point load and store patterns.
 531
 532 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 533
 534         * hppa.h (FLAG_STRICT): Correct comment.
 535         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 536         PA 2.0 mneumonics when equivalent.  Entries with cache control
 537         completers now require PA 1.1.  Adjust whitespace.
 538
 539 2005-05-19  Anton Blanchard  <anton@samba.org>
 540
 541         * ppc.h (PPC_OPCODE_POWER5): Define.
 542
 543 2005-05-10  Nick Clifton  <nickc@redhat.com>
 544
 545         * Update the address and phone number of the FSF organization in
 546         the GPL notices in the following files:
 547         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 548         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 549         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 550         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 551         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 552         tic54x.h, tic80.h, v850.h, vax.h
 553
 554 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 555
 556         * i386.h (i386_optab): Add ht and hnt.
 557
 558 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 559
 560         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 561         Add xcrypt-ctr.  Provide aliases without hyphens.
 562
 563 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         Moved from ../ChangeLog
 566
 567         2005-04-12  Paul Brook  <paul@codesourcery.com>
 568         * m88k.h: Rename psr macros to avoid conflicts.
 569
 570         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 571         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 572         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 573         and ARM_ARCH_V6ZKT2.
 574
 575         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 576         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 577         Remove redundant instruction types.
 578         (struct argument): X_op - new field.
 579         (struct cst4_entry): Remove.
 580         (no_op_insn): Declare.
 581
 582         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 583         * crx.h (enum argtype): Rename types, remove unused types.
 584
 585         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 586         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 587         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 588         (enum operand_type): Rearrange operands, edit comments.
 589         replace us<N> with ui<N> for unsigned immediate.
 590         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 591         displacements (respectively).
 592         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 593         (instruction type): Add NO_TYPE_INS.
 594         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 595         (operand_entry): New field - 'flags'.
 596         (operand flags): New.
 597
 598         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 599         * crx.h (operand_type): Remove redundant types i3, i4,
 600         i5, i8, i12.
 601         Add new unsigned immediate types us3, us4, us5, us16.
 602
 603 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 604
 605         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 606         adjust them accordingly.
 607
 608 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 609
 610         * i386.h (i386_optab): Add rdtscp.
 611
 612 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 615         between memory and segment register. Allow movq for moving between
 616         general-purpose register and segment register.
 617
 618 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 619
 620         PR gas/707
 621         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 622         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 623         fnstsw.
 624
 625 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 626
 627         * m68k.h (m68008, m68ec030, m68882): Remove.
 628         (m68k_mask): New.
 629         (cpu_m68k, cpu_cf): New.
 630         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 631         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 632
 633 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 634
 635         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 636         * cgen.h (enum cgen_parse_operand_type): Add
 637         CGEN_PARSE_OPERAND_SYMBOLIC.
 638
 639 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 640
 641         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 642         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 643         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 644
 645 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 646
 647         * mips.h (struct mips_opcode): Add new pinfo2 member.
 648         (INSN_ALIAS): New define for opcode table entries that are
 649         specific instances of another entry, such as 'move' for an 'or'
 650         with a zero operand.
 651         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 652         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 653
 654 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 655
 656         * mips.h (CPU_RM9000): Define.
 657         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 658
 659 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 660
 661         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 662         to/from test registers are illegal in 64-bit mode. Add missing
 663         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 664         (previously one had to explicitly encode a rex64 prefix). Re-enable
 665         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 666         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 667
 668 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 669
 670         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 671         available only with SSE2. Change the MMX additions introduced by SSE
 672         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 673         instructions by their now designated identifier (since combining i686
 674         and 3DNow! does not really imply 3DNow!A).
 675
 676 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 677
 678         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 679         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 680
 681 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 682             Vineet Sharma      <vineets@noida.hcltech.com>
 683
 684         * maxq.h: New file: Disassembly information for the maxq port.
 685
 686 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386.h (i386_optab): Put back "movzb".
 689
 690 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 691
 692         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 693         comments.  Remove member cris_ver_sim.  Add members
 694         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 695         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 696         (struct cris_support_reg, struct cris_cond15): New types.
 697         (cris_conds15): Declare.
 698         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 699         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 700         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 701         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 702         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 703         SIZE_FIELD_UNSIGNED.
 704
 705 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 706
 707         * i386.h (sldx_Suf): Remove.
 708         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 709         (q_FP): Define, implying no REX64.
 710         (x_FP, sl_FP): Imply FloatMF.
 711         (i386_optab): Split reg and mem forms of moving from segment registers
 712         so that the memory forms can ignore the 16-/32-bit operand size
 713         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 714         all non-floating-point instructions. Unite 32- and 64-bit forms of
 715         movsx, movzx, and movd. Adjust floating point operations for the above
 716         changes to the *FP macros. Add DefaultSize to floating point control
 717         insns operating on larger memory ranges. Remove left over comments
 718         hinting at certain insns being Intel-syntax ones where the ones
 719         actually meant are already gone.
 720
 721 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 722
 723         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 724         instruction type.
 725
 726 2004-09-30  Paul Brook  <paul@codesourcery.com>
 727
 728         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 729         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 730
 731 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 732
 733         * avr.h: Add support for
 734         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 735
 736 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 737
 738         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 739
 740 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 741
 742         * msp430.h (msp430_opc): Add new instructions.
 743         (msp430_rcodes): Declare new instructions.
 744         (msp430_hcodes): Likewise..
 745
 746 2004-08-13  Nick Clifton  <nickc@redhat.com>
 747
 748         PR/301
 749         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 750         processors.
 751
 752 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 753
 754         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 755
 756 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 759
 760 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 761
 762         * i386.h: Adjust instruction descriptions to better match the
 763         specification.
 764
 765 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 766
 767         * arm.h: Remove all old content.  Replace with architecture defines
 768         from gas/config/tc-arm.c.
 769
 770 2004-07-09  Andreas Schwab  <schwab@suse.de>
 771
 772         * m68k.h: Fix comment.
 773
 774 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 775
 776         * crx.h: New file.
 777
 778 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 779
 780         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 781
 782 2004-05-24  Peter Barada  <peter@the-baradas.com>
 783
 784         * m68k.h: Add 'size' to m68k_opcode.
 785
 786 2004-05-05  Peter Barada  <peter@the-baradas.com>
 787
 788         * m68k.h: Switch from ColdFire chip name to core variant.
 789
 790 2004-04-22  Peter Barada  <peter@the-baradas.com>
 791
 792         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 793         descriptions for new EMAC cases.
 794         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 795         handle Motorola MAC syntax.
 796         Allow disassembly of ColdFire V4e object files.
 797
 798 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 799
 800         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 801
 802 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 803
 804         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 805
 806 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 807
 808         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 809
 810 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 811
 812         * i386.h (i386_optab): Added xstore/xcrypt insns.
 813
 814 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 815
 816         * h8300.h (32bit ldc/stc): Add relaxing support.
 817
 818 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 819
 820         * h8300.h (BITOP): Pass MEMRELAX flag.
 821
 822 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 823
 824         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 825         except for the H8S.
 826
 827 For older changes see ChangeLog-9103
 828 \f
 829 Local Variables:
 830 mode: change-log
 831 left-margin: 8
 832 fill-column: 74
 833 version-control: never
 834 End: