include/opcode/ChangeLog

   1 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
   2             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
   3             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
   4             Soundararajan  <Sounderarajan.D@atmel.com>
   5
   6         * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
   7         (AVR_ISA_2xxxa): Define ISA without LPM.
   8         (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
   9         Add doc for contraint used in 16 bit lds/sts.
  10         Adjust ISA group for icall, ijmp, pop and push.
  11         Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
  12
  13 2014-05-19  Nick Clifton  <nickc@redhat.com>
  14
  15         * msp430.h (struct msp430_operand_s): Add vshift field.
  16
  17 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
  18
  19         * mips.h (INSN_ISA_MASK): Updated.
  20         (INSN_ISA32R3): New define.
  21         (INSN_ISA32R5): New define.
  22         (INSN_ISA64R3): New define.
  23         (INSN_ISA64R5): New define.
  24         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
  25         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
  26         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
  27         mips64r5.
  28         (INSN_UPTO32R3): New define.
  29         (INSN_UPTO32R5): New define.
  30         (INSN_UPTO64R3): New define.
  31         (INSN_UPTO64R5): New define.
  32         (ISA_MIPS32R3): New define.
  33         (ISA_MIPS32R5): New define.
  34         (ISA_MIPS64R3): New define.
  35         (ISA_MIPS64R5): New define.
  36         (CPU_MIPS32R3): New define.
  37         (CPU_MIPS32R5): New define.
  38         (CPU_MIPS64R3): New define.
  39         (CPU_MIPS64R5): New define.
  40
  41 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
  42
  43         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
  44
  45 2014-04-22  Christian Svensson  <blue@cmd.nu>
  46
  47         * or32.h: Delete.
  48
  49 2014-03-05  Alan Modra  <amodra@gmail.com>
  50
  51         Update copyright years.
  52
  53 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  54
  55         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
  56         microMIPS.
  57
  58 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  59             Wei-Cheng Wang  <cole945@gmail.com>
  60
  61         * nds32.h: New file for Andes NDS32.
  62
  63 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
  64
  65         * bfin.h: Remove +x file mode.
  66
  67 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  68
  69         * aarch64.h (aarch64_pstatefields): Change element type to
  70         aarch64_sys_reg.
  71
  72 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  73
  74         * arm.h (ARM_AEXT_V7VE): New define.
  75         (ARM_ARCH_V7VE): New define.
  76         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  77
  78 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  79
  80         Revert
  81
  82         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  83
  84         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  85         (aarch64_sys_reg_writeonly_p): Ditto.
  86
  87 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  88
  89         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  90         (aarch64_sys_reg_writeonly_p): Ditto.
  91
  92 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  93
  94         * aarch64.h (aarch64_sys_reg): New typedef.
  95         (aarch64_sys_regs): Change to define with the new type.
  96         (aarch64_sys_reg_deprecated_p): Declare.
  97
  98 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  99
 100         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
 101         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
 102
 103 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 104
 105         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
 106         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
 107         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 108         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 109         For MIPS, update extension character sequences after +.
 110         (ASE_MSA): New define.
 111         (ASE_MSA64): New define.
 112         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 113         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 114         For microMIPS, update extension character sequences after +.
 115
 116 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 117
 118         PR binutils/15834
 119         * i960.h: Fix typos.
 120
 121 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 122
 123         * mips.h: Remove references to "+I" and imm2_expr.
 124
 125 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 126
 127         * mips.h (M_DEXT, M_DINS): Delete.
 128
 129 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 130
 131         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 132         (mips_optional_operand_p): New function.
 133
 134 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 135             Richard Sandiford  <rdsandiford@googlemail.com>
 136
 137         * mips.h: Document new VU0 operand characters.
 138         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 139         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 140         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 141         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 142         (mips_vu0_channel_mask): Declare.
 143
 144 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 145
 146         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 147         (mips_int_operand_min, mips_int_operand_max): New functions.
 148         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 149
 150 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 151
 152         * mips.h (mips_decode_reg_operand): New function.
 153         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 154         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 155         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 156         New macros.
 157         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 158         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 159         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 160         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 161         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 162         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 163         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 164         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 165         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 166         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 167         macros to cover the gaps.
 168         (INSN2_MOD_SP): Replace with...
 169         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 170         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 171         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 172         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 173         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 174         Delete.
 175
 176 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 177
 178         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 179         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 180         (MIPS16_INSN_COND_BRANCH): Delete.
 181
 182 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 183             Kirill Yukhin  <kirill.yukhin@intel.com>
 184             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 185
 186         * i386.h (BND_PREFIX_OPCODE): New.
 187
 188 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 189
 190         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 191         OP_SAVE_RESTORE_LIST.
 192         (decode_mips16_operand): Declare.
 193
 194 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 195
 196         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 197         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 198         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 199         (mips_pcrel_operand): New structures.
 200         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 201         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 202         (decode_mips_operand, decode_micromips_operand): Declare.
 203
 204 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 205
 206         * mips.h: Document MIPS16 "I" opcode.
 207
 208 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 209
 210         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 211         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 212         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 213         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 214         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 215         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 216         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 217         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 218         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 219         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 220         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 221         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 222         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 223         Rename to...
 224         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 225         (M_USD_AB): ...these.
 226
 227 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 228
 229         * mips.h: Remove documentation of "[" and "]".  Update documentation
 230         of "k" and the MDMX formats.
 231
 232 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 233
 234         * mips.h: Update documentation of "+s" and "+S".
 235
 236 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 237
 238         * mips.h: Document "+i".
 239
 240 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 241
 242         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 243         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 244         Delete.
 245         (INSN2_WRITE_GPR_MHI): Rename to...
 246         (INSN2_WRITE_GPR_MH): ...this.
 247
 248 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 249
 250         * mips.h: Remove documentation of "+D" and "+T".
 251
 252 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 253
 254         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 255         Use "source" rather than "destination" for microMIPS "G".
 256
 257 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 258
 259         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 260         values.
 261
 262 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 263
 264         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 265
 266 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 267             Maciej W. Rozycki  <macro@codesourcery.com>
 268             Chao-Ying Fu  <fu@mips.com>
 269
 270         * mips.h (OP_SH_EVAOFFSET): Define.
 271         (OP_MASK_EVAOFFSET): Define.
 272         (INSN_ASE_MASK): Delete.
 273         (ASE_EVA): Define.
 274         (M_CACHEE_AB, M_CACHEE_OB): New.
 275         (M_LBE_OB, M_LBE_AB): New.
 276         (M_LBUE_OB, M_LBUE_AB): New.
 277         (M_LHE_OB, M_LHE_AB): New.
 278         (M_LHUE_OB, M_LHUE_AB): New.
 279         (M_LLE_AB, M_LLE_OB): New.
 280         (M_LWE_OB, M_LWE_AB): New.
 281         (M_LWLE_AB, M_LWLE_OB): New.
 282         (M_LWRE_AB, M_LWRE_OB): New.
 283         (M_PREFE_AB, M_PREFE_OB): New.
 284         (M_SCE_AB, M_SCE_OB): New.
 285         (M_SBE_OB, M_SBE_AB): New.
 286         (M_SHE_OB, M_SHE_AB): New.
 287         (M_SWE_OB, M_SWE_AB): New.
 288         (M_SWLE_AB, M_SWLE_OB): New.
 289         (M_SWRE_AB, M_SWRE_OB): New.
 290         (MICROMIPSOP_SH_EVAOFFSET): Define.
 291         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 292
 293 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 294
 295         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 296
 297 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 298
 299         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 300
 301 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 302
 303         * mips.h (OP_MASK_CODE10): Correct definition.
 304         (OP_SH_CODE10): Likewise.
 305         Add a comment that "+J" is used now for OP_*CODE10.
 306         (INSN_ASE_MASK): Update.
 307         (INSN_VIRT): New macro.
 308         (INSN_VIRT64): New macro
 309
 310 2013-05-02  Nick Clifton  <nickc@redhat.com>
 311
 312         * msp430.h: Add patterns for MSP430X instructions.
 313
 314 2013-04-06  David S. Miller  <davem@davemloft.net>
 315
 316         * sparc.h (F_PREFERRED): Define.
 317         (F_PREF_ALIAS): Define.
 318
 319 2013-04-03  Nick Clifton  <nickc@redhat.com>
 320
 321         * v850.h (V850_INVERSE_PCREL): Define.
 322
 323 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 324
 325         PR binutils/15068
 326         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 327
 328 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 329
 330         PR binutils/15068
 331         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 332         Add 16-bit opcodes.
 333         * tic6xc-opcode-table.h: Add 16-bit insns.
 334         * tic6x.h: Add support for 16-bit insns.
 335
 336 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 337
 338         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 339         and mov.b/w/l Rs,@(d:32,ERd).
 340
 341 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 342
 343         PR gas/15082
 344         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 345         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 346         tic6x_operand_xregpair operand coding type.
 347         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 348         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 349         TIC6X_FLAG_NO_CROSS.
 350
 351 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 352
 353         PR gas/15095
 354         * tic6x.h (enum tic6x_coding_method): Add
 355         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 356         separately the msb and lsb of a register pair.  This is needed to
 357         encode the opcodes in the same way as TI assembler does.
 358         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 359         and rsqrdp opcodes to use the new field coding types.
 360
 361 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 362
 363         * arm.h (CRC_EXT_ARMV8): New constant.
 364         (ARCH_CRC_ARMV8): New macro.
 365
 366 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 367
 368         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 369
 370 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 371             Andrew Jenner <andrew@codesourcery.com>
 372
 373         Based on patches from Altera Corporation.
 374
 375         * nios2.h: New file.
 376
 377 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 378
 379         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 380
 381 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 382
 383         PR gas/15069
 384         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 385
 386 2013-01-24  Nick Clifton  <nickc@redhat.com>
 387
 388         * v850.h: Add e3v5 support.
 389
 390 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 391
 392         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 393
 394 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 395
 396         * ppc.h (PPC_OPCODE_POWER8): New define.
 397         (PPC_OPCODE_HTM): Likewise.
 398
 399 2013-01-10  Will Newton <will.newton@imgtec.com>
 400
 401         * metag.h: New file.
 402
 403 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 404
 405         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 406         (match_opcode): Rename to cr16_match_opcode.
 407
 408 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 409
 410         * mips.h: Add support for r5900 instructions including lq and sq.
 411
 412 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 413
 414         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 415         (make_instruction,match_opcode): Added function prototypes.
 416         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 417
 418 2012-11-23  Alan Modra  <amodra@gmail.com>
 419
 420         * ppc.h (ppc_parse_cpu): Update prototype.
 421
 422 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 425         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 426
 427 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 428
 429         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 430
 431 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 432
 433         * ia64.h (ia64_opnd): Add new operand types.
 434
 435 2012-08-21  David S. Miller  <davem@davemloft.net>
 436
 437         * sparc.h (F3F4): New macro.
 438
 439 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 440             Laurent Desnogues  <laurent.desnogues@arm.com>
 441             Jim MacArthur  <jim.macarthur@arm.com>
 442             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 443             Nigel Stephens  <nigel.stephens@arm.com>
 444             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 445             Richard Earnshaw  <rearnsha@arm.com>
 446             Sofiane Naci  <sofiane.naci@arm.com>
 447             Tejas Belagod  <tejas.belagod@arm.com>
 448             Yufeng Zhang  <yufeng.zhang@arm.com>
 449
 450         * aarch64.h: New file.
 451
 452 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 453             Maciej W. Rozycki  <macro@codesourcery.com>
 454
 455         * mips.h (mips_opcode): Add the exclusions field.
 456         (OPCODE_IS_MEMBER): Remove macro.
 457         (cpu_is_member): New inline function.
 458         (opcode_is_member): Likewise.
 459
 460 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 461             Catherine Moore  <clm@codesourcery.com>
 462             Maciej W. Rozycki  <macro@codesourcery.com>
 463
 464         * mips.h: Document microMIPS DSP ASE usage.
 465         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 466         microMIPS DSP ASE support.
 467         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 468         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 469         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 470         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 471         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 472         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 473         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 474
 475 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 476
 477         * mips.h: Fix a typo in description.
 478
 479 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 480
 481         * avr.h: (AVR_ISA_XCH): New define.
 482         (AVR_ISA_XMEGA): Use it.
 483         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 484
 485 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 486
 487         * m68hc11.h: Add XGate definitions.
 488         (struct m68hc11_opcode): Add xg_mask field.
 489
 490 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 491             Maciej W. Rozycki  <macro@codesourcery.com>
 492             Rhonda Wittels  <rhonda@codesourcery.com>
 493
 494         * ppc.h (PPC_OPCODE_VLE): New definition.
 495         (PPC_OP_SA): New macro.
 496         (PPC_OP_SE_VLE): New macro.
 497         (PPC_OP): Use a variable shift amount.
 498         (powerpc_operand): Update comments.
 499         (PPC_OPSHIFT_INV): New macro.
 500         (PPC_OPERAND_CR): Replace with...
 501         (PPC_OPERAND_CR_BIT): ...this and
 502         (PPC_OPERAND_CR_REG): ...this.
 503
 504
 505 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 506
 507         * xgate.h: Header file for XGATE assembler.
 508
 509 2012-04-27  David S. Miller  <davem@davemloft.net>
 510
 511         * sparc.h: Document new arg code' )' for crypto RS3
 512         immediates.
 513
 514         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 515         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 516         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 517         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 518         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 519         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 520         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 521         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 522         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 523         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 524         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 525
 526 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 527
 528         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 529
 530 2012-02-27  Alan Modra  <amodra@gmail.com>
 531
 532         * crx.h (cst4_map): Update declaration.
 533
 534 2012-02-25  Walter Lee  <walt@tilera.com>
 535
 536         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 537         TILEGX_OPC_LD_TLS.
 538         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 539         TILEPRO_OPC_LW_TLS_SN.
 540
 541 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 542
 543         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 544         (XRELEASE_PREFIX_OPCODE): Likewise.
 545
 546 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 547             Adam Nemet  <anemet@caviumnetworks.com>
 548
 549         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 550         (INSN_OCTEON2): New macro.
 551         (CPU_OCTEON2): New macro.
 552         (OPCODE_IS_MEMBER): Add Octeon2.
 553
 554 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 555
 556         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 557         (INSN_OCTEONP): New macro.
 558         (CPU_OCTEONP): New macro.
 559         (OPCODE_IS_MEMBER): Add Octeon+.
 560         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 561
 562 2011-11-01  DJ Delorie  <dj@redhat.com>
 563
 564         * rl78.h: New file.
 565
 566 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 567
 568         * mips.h: Fix a typo in description.
 569
 570 2011-09-21  David S. Miller  <davem@davemloft.net>
 571
 572         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 573         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 574         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 575         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 576
 577 2011-08-09  Chao-ying Fu  <fu@mips.com>
 578             Maciej W. Rozycki  <macro@codesourcery.com>
 579
 580         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 581         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 582         (INSN_ASE_MASK): Add the MCU bit.
 583         (INSN_MCU): New macro.
 584         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 585         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 586
 587 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 588
 589         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 590         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 591         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 592         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 593         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 594         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 595         (INSN2_READ_GPR_MMN): Likewise.
 596         (INSN2_READ_FPR_D): Change the bit used.
 597         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 598         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 599         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 600         (INSN2_COND_BRANCH): Likewise.
 601         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 602         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 603         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 604         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 605         (INSN2_MOD_GPR_MN): Likewise.
 606
 607 2011-08-05  David S. Miller  <davem@davemloft.net>
 608
 609         * sparc.h: Document new format codes '4', '5', and '('.
 610         (OPF_LOW4, RS3): New macros.
 611
 612 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 613
 614         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 615         order of flags documented.
 616
 617 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 618
 619         * mips.h: Clarify the description of microMIPS instruction
 620         manipulation macros.
 621         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 622
 623 2011-07-24  Chao-ying Fu  <fu@mips.com>
 624             Maciej W. Rozycki  <macro@codesourcery.com>
 625
 626         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 627         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 628         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 629         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 630         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 631         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 632         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 633         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 634         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 635         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 636         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 637         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 638         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 639         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 640         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 641         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 642         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 643         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 644         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 645         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 646         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 647         (INSN_WRITE_GPR_S): New macro.
 648         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 649         (INSN2_READ_FPR_D): Likewise.
 650         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 651         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 652         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 653         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 654         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 655         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 656         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 657         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 658         (CPU_MICROMIPS): New macro.
 659         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 660         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 661         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 662         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 663         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 664         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 665         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 666         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 667         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 668         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 669         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 670         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 671         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 672         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 673         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 674         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 675         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 676         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 677         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 678         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 679         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 680         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 681         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 682         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 683         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 684         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 685         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 686         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 687         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 688         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 689         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 690         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 691         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 692         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 693         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 694         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 695         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 696         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 697         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 698         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 699         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 700         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 701         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 702         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 703         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 704         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 705         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 706         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 707         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 708         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 709         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 710         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 711         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 712         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 713         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 714         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 715         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 716         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 717         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 718         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 719         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 720         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 721         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 722         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 723         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 724         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 725         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 726         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 727         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 728         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 729         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 730         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 731         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 732         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 733         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 734         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 735         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 736         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 737         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 738         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 739         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 740         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 741         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 742         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 743         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 744         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 745         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 746         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 747         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 748         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 749         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 750         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 751         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 752         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 753         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 754         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 755         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 756         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 757         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 758         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 759         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 760         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 761         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 762         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 763         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 764         (micromips_opcodes): New declaration.
 765         (bfd_micromips_num_opcodes): Likewise.
 766
 767 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 768
 769         * mips.h (INSN_TRAP): Rename to...
 770         (INSN_NO_DELAY_SLOT): ... this.
 771         (INSN_SYNC): Remove macro.
 772
 773 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 774
 775         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 776         a duplicate of AVR_ISA_SPM.
 777
 778 2011-07-01  Nick Clifton  <nickc@redhat.com>
 779
 780         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 781
 782 2011-06-18  Robin Getz  <robin.getz@analog.com>
 783
 784         * bfin.h (is_macmod_signed): New func
 785
 786 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 787
 788         * bfin.h (is_macmod_pmove): Add missing space before func args.
 789         (is_macmod_hmove): Likewise.
 790
 791 2011-06-13  Walter Lee  <walt@tilera.com>
 792
 793         * tilegx.h: New file.
 794         * tilepro.h: New file.
 795
 796 2011-05-31  Paul Brook  <paul@codesourcery.com>
 797
 798         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 799
 800 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 801
 802         * s390.h: Replace S390_OPERAND_REG_EVEN with
 803         S390_OPERAND_REG_PAIR.
 804
 805 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 806
 807         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 808
 809 2011-04-18  Julian Brown  <julian@codesourcery.com>
 810
 811         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 812
 813 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 814
 815         PR gas/12296
 816         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 817
 818 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 819
 820         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 821         New instruction set flags.
 822         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 823
 824 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 825
 826         * mips.h (M_PREF_AB): New enum value.
 827
 828 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 829
 830         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 831         M_IU): Define.
 832         (is_macmod_pmove, is_macmod_hmove): New functions.
 833
 834 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 835
 836         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 837
 838 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 839
 840         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 841         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 842
 843 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 844
 845         PR gas/11395
 846         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 847         "bb" entries.
 848
 849 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 850
 851         PR gas/11395
 852         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 853
 854 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 855
 856         * mips.h: Update commentary after last commit.
 857
 858 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 859
 860         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 861         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 862         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 863
 864 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 865
 866         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 867
 868 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 869
 870         * mips.h: Fix previous commit.
 871
 872 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 873
 874         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 875         (INSN_LOONGSON_3A): Clear bit 31.
 876
 877 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 878
 879         PR gas/12198
 880         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 881         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 882         (ARM_ARCH_V6M_ONLY): New define.
 883
 884 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 885
 886         * mips.h (INSN_LOONGSON_3A): Defined.
 887         (CPU_LOONGSON_3A): Defined.
 888         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 889
 890 2010-10-09  Matt Rice  <ratmice@gmail.com>
 891
 892         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 893         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 894
 895 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 896
 897         * arm.h (ARM_EXT_VIRT): New define.
 898         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 899         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 900         Extensions.
 901
 902 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 903
 904         * arm.h (ARM_AEXT_ADIV): New define.
 905         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 906
 907 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 908
 909         * arm.h (ARM_EXT_OS): New define.
 910         (ARM_AEXT_V6SM): Likewise.
 911         (ARM_ARCH_V6SM): Likewise.
 912
 913 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 914
 915         * arm.h (ARM_EXT_MP): Add.
 916         (ARM_ARCH_V7A_MP): Likewise.
 917
 918 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 919
 920         * bfin.h: Declare pseudoChr structs/defines.
 921
 922 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 923
 924         * bfin.h: Strip trailing whitespace.
 925
 926 2010-07-29  DJ Delorie  <dj@redhat.com>
 927
 928         * rx.h (RX_Operand_Type): Add TwoReg.
 929         (RX_Opcode_ID): Remove ediv and ediv2.
 930
 931 2010-07-27  DJ Delorie  <dj@redhat.com>
 932
 933         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 934
 935 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 936             Ina Pandit  <ina.pandit@kpitcummins.com>
 937
 938         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 939         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 940         PROCESSOR_V850E2_ALL.
 941         Remove PROCESSOR_V850EA support.
 942         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 943         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 944         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 945         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 946         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 947         V850_OPERAND_PERCENT.
 948         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 949         V850_NOT_R0.
 950         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 951         and V850E_PUSH_POP
 952
 953 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 954
 955         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 956         (MIPS16_INSN_BRANCH): Rename to...
 957         (MIPS16_INSN_COND_BRANCH): ... this.
 958
 959 2010-07-03  Alan Modra  <amodra@gmail.com>
 960
 961         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 962         Renumber other PPC_OPCODE defines.
 963
 964 2010-07-03  Alan Modra  <amodra@gmail.com>
 965
 966         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 967
 968 2010-06-29  Alan Modra  <amodra@gmail.com>
 969
 970         * maxq.h: Delete file.
 971
 972 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 973
 974         * ppc.h (PPC_OPCODE_E500): Define.
 975
 976 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 977
 978         * opcode/mips.h (INSN_MIPS16): Remove.
 979
 980 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 981
 982         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 983
 984 2010-04-15  Nick Clifton  <nickc@redhat.com>
 985
 986         * alpha.h: Update copyright notice to use GPLv3.
 987         * arc.h: Likewise.
 988         * arm.h: Likewise.
 989         * avr.h: Likewise.
 990         * bfin.h: Likewise.
 991         * cgen.h: Likewise.
 992         * convex.h: Likewise.
 993         * cr16.h: Likewise.
 994         * cris.h: Likewise.
 995         * crx.h: Likewise.
 996         * d10v.h: Likewise.
 997         * d30v.h: Likewise.
 998         * dlx.h: Likewise.
 999         * h8300.h: Likewise.
1000         * hppa.h: Likewise.
1001         * i370.h: Likewise.
1002         * i386.h: Likewise.
1003         * i860.h: Likewise.
1004         * i960.h: Likewise.
1005         * ia64.h: Likewise.
1006         * m68hc11.h: Likewise.
1007         * m68k.h: Likewise.
1008         * m88k.h: Likewise.
1009         * maxq.h: Likewise.
1010         * mips.h: Likewise.
1011         * mmix.h: Likewise.
1012         * mn10200.h: Likewise.
1013         * mn10300.h: Likewise.
1014         * msp430.h: Likewise.
1015         * np1.h: Likewise.
1016         * ns32k.h: Likewise.
1017         * or32.h: Likewise.
1018         * pdp11.h: Likewise.
1019         * pj.h: Likewise.
1020         * pn.h: Likewise.
1021         * ppc.h: Likewise.
1022         * pyr.h: Likewise.
1023         * rx.h: Likewise.
1024         * s390.h: Likewise.
1025         * score-datadep.h: Likewise.
1026         * score-inst.h: Likewise.
1027         * sparc.h: Likewise.
1028         * spu-insns.h: Likewise.
1029         * spu.h: Likewise.
1030         * tic30.h: Likewise.
1031         * tic4x.h: Likewise.
1032         * tic54x.h: Likewise.
1033         * tic80.h: Likewise.
1034         * v850.h: Likewise.
1035         * vax.h: Likewise.
1036
1037 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1038
1039         * tic6x-control-registers.h, tic6x-insn-formats.h,
1040         tic6x-opcode-table.h, tic6x.h: New.
1041
1042 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1043
1044         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1045
1046 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1047
1048         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1049
1050 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1051
1052         * ia64.h (ia64_find_opcode): Remove argument name.
1053         (ia64_find_next_opcode): Likewise.
1054         (ia64_dis_opcode): Likewise.
1055         (ia64_free_opcode): Likewise.
1056         (ia64_find_dependency): Likewise.
1057
1058 2009-11-22  Doug Evans  <dje@sebabeach.org>
1059
1060         * cgen.h: Include bfd_stdint.h.
1061         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1062
1063 2009-11-18  Paul Brook  <paul@codesourcery.com>
1064
1065         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1066
1067 2009-11-17  Paul Brook  <paul@codesourcery.com>
1068         Daniel Jacobowitz  <dan@codesourcery.com>
1069
1070         * arm.h (ARM_EXT_V6_DSP): Define.
1071         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1072         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1073
1074 2009-11-04  DJ Delorie  <dj@redhat.com>
1075
1076         * rx.h (rx_decode_opcode) (mvtipl): Add.
1077         (mvtcp, mvfcp, opecp): Remove.
1078
1079 2009-11-02  Paul Brook  <paul@codesourcery.com>
1080
1081         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1082         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1083         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1084         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1085         FPU_ARCH_NEON_VFP_V4): Define.
1086
1087 2009-10-23  Doug Evans  <dje@sebabeach.org>
1088
1089         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1090         * cgen.h: Update.  Improve multi-inclusion macro name.
1091
1092 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1093
1094         * ppc.h (PPC_OPCODE_476): Define.
1095
1096 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1097
1098         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1099
1100 2009-09-29  DJ Delorie  <dj@redhat.com>
1101
1102         * rx.h: New file.
1103
1104 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1105
1106         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1107
1108 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1109
1110         * ppc.h (PPC_OPCODE_PPCA2): New.
1111
1112 2009-09-05  Martin Thuresson  <martin@mtme.org>
1113
1114         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1115
1116 2009-08-29  Martin Thuresson  <martin@mtme.org>
1117
1118         * tic30.h (template): Rename type template to
1119         insn_template. Updated code to use new name.
1120         * tic54x.h (template): Rename type template to
1121         insn_template.
1122
1123 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1124
1125         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1126
1127 2009-06-11  Anthony Green  <green@moxielogic.com>
1128
1129         * moxie.h (MOXIE_F3_PCREL): Define.
1130         (moxie_form3_opc_info): Grow.
1131
1132 2009-06-06  Anthony Green  <green@moxielogic.com>
1133
1134         * moxie.h (MOXIE_F1_M): Define.
1135
1136 2009-04-15  Anthony Green  <green@moxielogic.com>
1137
1138         * moxie.h: Created.
1139
1140 2009-04-06  DJ Delorie  <dj@redhat.com>
1141
1142         * h8300.h: Add relaxation attributes to MOVA opcodes.
1143
1144 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1145
1146         * ppc.h (ppc_parse_cpu): Declare.
1147
1148 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1149
1150         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1151         and _IMM11 for mbitclr and mbitset.
1152         * score-datadep.h: Update dependency information.
1153
1154 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1155
1156         * ppc.h (PPC_OPCODE_POWER7): New.
1157
1158 2009-02-06  Doug Evans  <dje@google.com>
1159
1160         * i386.h: Add comment regarding sse* insns and prefixes.
1161
1162 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1163
1164         * mips.h (INSN_XLR): Define.
1165         (INSN_CHIP_MASK): Update.
1166         (CPU_XLR): Define.
1167         (OPCODE_IS_MEMBER): Update.
1168         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1169
1170 2009-01-28  Doug Evans  <dje@google.com>
1171
1172         * opcode/i386.h: Add multiple inclusion protection.
1173         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1174         (EDI_REG_NUM): New macros.
1175         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1176         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1177         (REX_PREFIX_P): New macro.
1178
1179 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1180
1181         * ppc.h (struct powerpc_opcode): New field "deprecated".
1182         (PPC_OPCODE_NOPOWER4): Delete.
1183
1184 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1185
1186         * mips.h: Define CPU_R14000, CPU_R16000.
1187         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1188
1189 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1190
1191         * arm.h (FPU_NEON_FP16): New.
1192         (FPU_ARCH_NEON_FP16): New.
1193
1194 2008-11-06  Chao-ying Fu  <fu@mips.com>
1195
1196         * mips.h: Doucument '1' for 5-bit sync type.
1197
1198 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1199
1200         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1201         IA64_RS_CR.
1202
1203 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1204
1205         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1206
1207 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1208
1209         * ppc.h (PPC_OPCODE_405): Define.
1210         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1211
1212 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1213
1214         * ppc.h (ppc_cpu_t): New typedef.
1215         (struct powerpc_opcode <flags>): Use it.
1216         (struct powerpc_operand <insert, extract>): Likewise.
1217         (struct powerpc_macro <flags>): Likewise.
1218
1219 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1220
1221         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1222         Update comment before MIPS16 field descriptors to mention MIPS16.
1223         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1224         BBIT.
1225         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1226         New bit masks and shift counts for cins and exts.
1227
1228         * mips.h: Document new field descriptors +Q.
1229         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1230
1231 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1232
1233         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1234         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1235
1236 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1237
1238         * ppc.h: (PPC_OPCODE_E500MC): New.
1239
1240 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1241
1242         * i386.h (MAX_OPERANDS): Set to 5.
1243         (MAX_MNEM_SIZE): Changed to 20.
1244
1245 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1246
1247         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1248
1249 2008-03-09  Paul Brook  <paul@codesourcery.com>
1250
1251         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1252
1253 2008-03-04  Paul Brook  <paul@codesourcery.com>
1254
1255         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1256         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1257         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1258
1259 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1260             Nick Clifton  <nickc@redhat.com>
1261
1262         PR 3134
1263         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1264         with a 32-bit displacement but without the top bit of the 4th byte
1265         set.
1266
1267 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1268
1269         * cr16.h (cr16_num_optab): Declared.
1270
1271 2008-02-14  Hakan Ardo  <hakan@debian.org>
1272
1273         PR gas/2626
1274         * avr.h (AVR_ISA_2xxe): Define.
1275
1276 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1277
1278         * mips.h: Update copyright.
1279         (INSN_CHIP_MASK): New macro.
1280         (INSN_OCTEON): New macro.
1281         (CPU_OCTEON): New macro.
1282         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1283
1284 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1285
1286         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1287
1288 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1289
1290         * avr.h (AVR_ISA_USB162): Add new opcode set.
1291         (AVR_ISA_AVR3): Likewise.
1292
1293 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1294
1295         * mips.h (INSN_LOONGSON_2E): New.
1296         (INSN_LOONGSON_2F): New.
1297         (CPU_LOONGSON_2E): New.
1298         (CPU_LOONGSON_2F): New.
1299         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1300
1301 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1302
1303         * mips.h (INSN_ISA*): Redefine certain values as an
1304         enumeration.  Update comments.
1305         (mips_isa_table): New.
1306         (ISA_MIPS*): Redefine to match enumeration.
1307         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1308         values.
1309
1310 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1311
1312         * ppc.h (PPC_OPCODE_PPCPS): New.
1313
1314 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1315
1316         * m68k.h: Document j K & E.
1317
1318 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1319
1320         * cr16.h: New file for CR16 target.
1321
1322 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1323
1324         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1325
1326 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1327
1328         * m68k.h (mcfisa_c): New.
1329         (mcfusp, mcf_mask): Adjust.
1330
1331 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1332
1333         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1334         (num_powerpc_operands): Declare.
1335         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1336         (PPC_OPERAND_PLUS1): Define.
1337
1338 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1339
1340         * i386.h (REX_MODE64): Renamed to ...
1341         (REX_W): This.
1342         (REX_EXTX): Renamed to ...
1343         (REX_R): This.
1344         (REX_EXTY): Renamed to ...
1345         (REX_X): This.
1346         (REX_EXTZ): Renamed to ...
1347         (REX_B): This.
1348
1349 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1350
1351         * i386.h: Add entries from config/tc-i386.h and move tables
1352         to opcodes/i386-opc.h.
1353
1354 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1355
1356         * i386.h (FloatDR): Removed.
1357         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1358
1359 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1360
1361         * spu-insns.h: Add soma double-float insns.
1362
1363 2007-02-20  Thiemo Seufer  <ths@mips.com>
1364             Chao-Ying Fu  <fu@mips.com>
1365
1366         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1367         (INSN_DSPR2): Add flag for DSP R2 instructions.
1368         (M_BALIGN): New macro.
1369
1370 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1371
1372         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1373         and Seg3ShortFrom with Shortform.
1374
1375 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1376
1377         PR gas/4027
1378         * i386.h (i386_optab): Put the real "test" before the pseudo
1379         one.
1380
1381 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1382
1383         * m68k.h (m68010up): OR fido_a.
1384
1385 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1386
1387         * m68k.h (fido_a): New.
1388
1389 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1390
1391         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1392         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1393         values.
1394
1395 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1396
1397         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1398
1399 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1400
1401         * score-inst.h (enum score_insn_type): Add Insn_internal.
1402
1403 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1404             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1405             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1406             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1407             Alan Modra  <amodra@bigpond.net.au>
1408
1409         * spu-insns.h: New file.
1410         * spu.h: New file.
1411
1412 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1413
1414         * ppc.h (PPC_OPCODE_CELL): Define.
1415
1416 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1417
1418         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1419         in amdfam10 architecture.
1420
1421 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1422
1423         * i386.h: Replace CpuMNI with CpuSSSE3.
1424
1425 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1426             Joseph Myers  <joseph@codesourcery.com>
1427             Ian Lance Taylor  <ian@wasabisystems.com>
1428             Ben Elliston  <bje@wasabisystems.com>
1429
1430         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1431
1432 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1433
1434         * score-datadep.h: New file.
1435         * score-inst.h: New file.
1436
1437 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1438
1439         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1440         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1441         movdq2q and movq2dq.
1442
1443 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1444            Michael Meissner             <michael.meissner@amd.com>
1445
1446         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1447
1448 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1449
1450         * i386.h (i386_optab): Add "nop" with memory reference.
1451
1452 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1453
1454         * i386.h (i386_optab): Update comment for 64bit NOP.
1455
1456 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1457             Anton Blanchard  <anton@samba.org>
1458
1459         * ppc.h (PPC_OPCODE_POWER6): Define.
1460         Adjust whitespace.
1461
1462 2006-06-05  Thiemo Seufer  <ths@mips.com>
1463
1464         * mips.h: Improve description of MT flags.
1465
1466 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1467
1468         * m68k.h (mcf_mask): Define.
1469
1470 2006-05-05  Thiemo Seufer  <ths@mips.com>
1471             David Ung  <davidu@mips.com>
1472
1473         * mips.h (enum): Add macro M_CACHE_AB.
1474
1475 2006-05-04  Thiemo Seufer  <ths@mips.com>
1476             Nigel Stephens  <nigel@mips.com>
1477             David Ung  <davidu@mips.com>
1478
1479         * mips.h: Add INSN_SMARTMIPS define.
1480
1481 2006-04-30  Thiemo Seufer  <ths@mips.com>
1482             David Ung  <davidu@mips.com>
1483
1484         * mips.h: Defines udi bits and masks.  Add description of
1485         characters which may appear in the args field of udi
1486         instructions.
1487
1488 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1489
1490         * mips.h: Improve comments describing the bitfield instruction
1491         fields.
1492
1493 2006-04-26  Julian Brown  <julian@codesourcery.com>
1494
1495         * arm.h (FPU_VFP_EXT_V3): Define constant.
1496         (FPU_NEON_EXT_V1): Likewise.
1497         (FPU_VFP_HARD): Update.
1498         (FPU_VFP_V3): Define macro.
1499         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1500
1501 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1502
1503         * avr.h (AVR_ISA_PWMx): New.
1504
1505 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1506
1507         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1508         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1509         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1510         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1511         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1512
1513 2006-03-10  Paul Brook  <paul@codesourcery.com>
1514
1515         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1516
1517 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1518
1519         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1520         first.  Correct mask of bb "B" opcode.
1521
1522 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1523
1524         * i386.h (i386_optab): Support Intel Merom New Instructions.
1525
1526 2006-02-24  Paul Brook  <paul@codesourcery.com>
1527
1528         * arm.h: Add V7 feature bits.
1529
1530 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1531
1532         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1533
1534 2006-01-31  Paul Brook  <paul@codesourcery.com>
1535         Richard Earnshaw <rearnsha@arm.com>
1536
1537         * arm.h: Use ARM_CPU_FEATURE.
1538         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1539         (arm_feature_set): Change to a structure.
1540         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1541         ARM_FEATURE): New macros.
1542
1543 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1544
1545         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1546         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1547         (ADD_PC_INCR_OPCODE): Don't define.
1548
1549 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1550
1551         PR gas/1874
1552         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1553
1554 2005-11-14  David Ung  <davidu@mips.com>
1555
1556         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1557         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1558         save/restore encoding of the args field.
1559
1560 2005-10-28  Dave Brolley  <brolley@redhat.com>
1561
1562         Contribute the following changes:
1563         2005-02-16  Dave Brolley  <brolley@redhat.com>
1564
1565         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1566         cgen_isa_mask_* to cgen_bitset_*.
1567         * cgen.h: Likewise.
1568
1569         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1570
1571         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1572         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1573         (CGEN_CPU_TABLE): Make isas a ponter.
1574
1575         2003-09-29  Dave Brolley  <brolley@redhat.com>
1576
1577         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1578         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1579         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1580
1581         2002-12-13  Dave Brolley  <brolley@redhat.com>
1582
1583         * cgen.h (symcat.h): #include it.
1584         (cgen-bitset.h): #include it.
1585         (CGEN_ATTR_VALUE_TYPE): Now a union.
1586         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1587         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1588         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1589         * cgen-bitset.h: New file.
1590
1591 2005-09-30  Catherine Moore  <clm@cm00re.com>
1592
1593         * bfin.h: New file.
1594
1595 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1596
1597         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1598         indirect operands.
1599
1600 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1601
1602         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1603         Add FLAG_STRICT to pa10 ftest opcode.
1604
1605 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1606
1607         * hppa.h (pa_opcodes): Remove lha entries.
1608
1609 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1610
1611         * hppa.h (FLAG_STRICT): Revise comment.
1612         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1613         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1614         entries for "fdc".
1615
1616 2005-09-30  Catherine Moore  <clm@cm00re.com>
1617
1618         * bfin.h: New file.
1619
1620 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1621
1622         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1623
1624 2005-09-06  Chao-ying Fu  <fu@mips.com>
1625
1626         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1627         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1628         define.
1629         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1630         (INSN_ASE_MASK): Update to include INSN_MT.
1631         (INSN_MT): New define for MT ASE.
1632
1633 2005-08-25  Chao-ying Fu  <fu@mips.com>
1634
1635         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1636         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1637         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1638         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1639         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1640         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1641         instructions.
1642         (INSN_DSP): New define for DSP ASE.
1643
1644 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1645
1646         * a29k.h: Delete.
1647
1648 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1649
1650         * ppc.h (PPC_OPCODE_E300): Define.
1651
1652 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1653
1654         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1655
1656 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1657
1658         PR gas/336
1659         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1660         and pitlb.
1661
1662 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1663
1664         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1665         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1666         Add movq-s as 64-bit variants of movd-s.
1667
1668 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1669
1670         * hppa.h: Fix punctuation in comment.
1671
1672         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1673         implicit space-register addressing.  Set space-register bits on opcodes
1674         using implicit space-register addressing.  Add various missing pa20
1675         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1676         space-register addressing.  Use "fE" instead of "fe" in various
1677         fstw opcodes.
1678
1679 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1680
1681         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1682
1683 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1684
1685         * i386.h (i386_optab): Support Intel VMX Instructions.
1686
1687 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1688
1689         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1690
1691 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1692
1693         * i386.h (i386_optab): Add new insns.
1694
1695 2005-07-01  Nick Clifton  <nickc@redhat.com>
1696
1697         * sparc.h: Add typedefs to structure declarations.
1698
1699 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1700
1701         PR 1013
1702         * i386.h (i386_optab): Update comments for 64bit addressing on
1703         mov. Allow 64bit addressing for mov and movq.
1704
1705 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1706
1707         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1708         respectively, in various floating-point load and store patterns.
1709
1710 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1711
1712         * hppa.h (FLAG_STRICT): Correct comment.
1713         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1714         PA 2.0 mneumonics when equivalent.  Entries with cache control
1715         completers now require PA 1.1.  Adjust whitespace.
1716
1717 2005-05-19  Anton Blanchard  <anton@samba.org>
1718
1719         * ppc.h (PPC_OPCODE_POWER5): Define.
1720
1721 2005-05-10  Nick Clifton  <nickc@redhat.com>
1722
1723         * Update the address and phone number of the FSF organization in
1724         the GPL notices in the following files:
1725         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1726         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1727         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1728         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1729         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1730         tic54x.h, tic80.h, v850.h, vax.h
1731
1732 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1733
1734         * i386.h (i386_optab): Add ht and hnt.
1735
1736 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1737
1738         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1739         Add xcrypt-ctr.  Provide aliases without hyphens.
1740
1741 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1742
1743         Moved from ../ChangeLog
1744
1745         2005-04-12  Paul Brook  <paul@codesourcery.com>
1746         * m88k.h: Rename psr macros to avoid conflicts.
1747
1748         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1749         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1750         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1751         and ARM_ARCH_V6ZKT2.
1752
1753         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1754         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1755         Remove redundant instruction types.
1756         (struct argument): X_op - new field.
1757         (struct cst4_entry): Remove.
1758         (no_op_insn): Declare.
1759
1760         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1761         * crx.h (enum argtype): Rename types, remove unused types.
1762
1763         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1764         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1765         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1766         (enum operand_type): Rearrange operands, edit comments.
1767         replace us<N> with ui<N> for unsigned immediate.
1768         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1769         displacements (respectively).
1770         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1771         (instruction type): Add NO_TYPE_INS.
1772         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1773         (operand_entry): New field - 'flags'.
1774         (operand flags): New.
1775
1776         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1777         * crx.h (operand_type): Remove redundant types i3, i4,
1778         i5, i8, i12.
1779         Add new unsigned immediate types us3, us4, us5, us16.
1780
1781 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1782
1783         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1784         adjust them accordingly.
1785
1786 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1787
1788         * i386.h (i386_optab): Add rdtscp.
1789
1790 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1791
1792         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1793         between memory and segment register. Allow movq for moving between
1794         general-purpose register and segment register.
1795
1796 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1797
1798         PR gas/707
1799         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1800         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1801         fnstsw.
1802
1803 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1804
1805         * m68k.h (m68008, m68ec030, m68882): Remove.
1806         (m68k_mask): New.
1807         (cpu_m68k, cpu_cf): New.
1808         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1809         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1810
1811 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1812
1813         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1814         * cgen.h (enum cgen_parse_operand_type): Add
1815         CGEN_PARSE_OPERAND_SYMBOLIC.
1816
1817 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1818
1819         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1820         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1821         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1822
1823 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1824
1825         * mips.h (struct mips_opcode): Add new pinfo2 member.
1826         (INSN_ALIAS): New define for opcode table entries that are
1827         specific instances of another entry, such as 'move' for an 'or'
1828         with a zero operand.
1829         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1830         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1831
1832 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1833
1834         * mips.h (CPU_RM9000): Define.
1835         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1836
1837 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1838
1839         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1840         to/from test registers are illegal in 64-bit mode. Add missing
1841         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1842         (previously one had to explicitly encode a rex64 prefix). Re-enable
1843         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1844         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1845
1846 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1847
1848         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1849         available only with SSE2. Change the MMX additions introduced by SSE
1850         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1851         instructions by their now designated identifier (since combining i686
1852         and 3DNow! does not really imply 3DNow!A).
1853
1854 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1855
1856         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1857         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1858
1859 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1860             Vineet Sharma      <vineets@noida.hcltech.com>
1861
1862         * maxq.h: New file: Disassembly information for the maxq port.
1863
1864 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1865
1866         * i386.h (i386_optab): Put back "movzb".
1867
1868 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1869
1870         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1871         comments.  Remove member cris_ver_sim.  Add members
1872         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1873         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1874         (struct cris_support_reg, struct cris_cond15): New types.
1875         (cris_conds15): Declare.
1876         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1877         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1878         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1879         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1880         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1881         SIZE_FIELD_UNSIGNED.
1882
1883 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1884
1885         * i386.h (sldx_Suf): Remove.
1886         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1887         (q_FP): Define, implying no REX64.
1888         (x_FP, sl_FP): Imply FloatMF.
1889         (i386_optab): Split reg and mem forms of moving from segment registers
1890         so that the memory forms can ignore the 16-/32-bit operand size
1891         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1892         all non-floating-point instructions. Unite 32- and 64-bit forms of
1893         movsx, movzx, and movd. Adjust floating point operations for the above
1894         changes to the *FP macros. Add DefaultSize to floating point control
1895         insns operating on larger memory ranges. Remove left over comments
1896         hinting at certain insns being Intel-syntax ones where the ones
1897         actually meant are already gone.
1898
1899 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1900
1901         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1902         instruction type.
1903
1904 2004-09-30  Paul Brook  <paul@codesourcery.com>
1905
1906         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1907         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1908
1909 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1910
1911         * avr.h: Add support for
1912         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1913
1914 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1915
1916         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1917
1918 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1919
1920         * msp430.h (msp430_opc): Add new instructions.
1921         (msp430_rcodes): Declare new instructions.
1922         (msp430_hcodes): Likewise..
1923
1924 2004-08-13  Nick Clifton  <nickc@redhat.com>
1925
1926         PR/301
1927         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1928         processors.
1929
1930 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1931
1932         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1933
1934 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1935
1936         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1937
1938 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1939
1940         * i386.h: Adjust instruction descriptions to better match the
1941         specification.
1942
1943 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1944
1945         * arm.h: Remove all old content.  Replace with architecture defines
1946         from gas/config/tc-arm.c.
1947
1948 2004-07-09  Andreas Schwab  <schwab@suse.de>
1949
1950         * m68k.h: Fix comment.
1951
1952 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1953
1954         * crx.h: New file.
1955
1956 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1957
1958         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1959
1960 2004-05-24  Peter Barada  <peter@the-baradas.com>
1961
1962         * m68k.h: Add 'size' to m68k_opcode.
1963
1964 2004-05-05  Peter Barada  <peter@the-baradas.com>
1965
1966         * m68k.h: Switch from ColdFire chip name to core variant.
1967
1968 2004-04-22  Peter Barada  <peter@the-baradas.com>
1969
1970         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1971         descriptions for new EMAC cases.
1972         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1973         handle Motorola MAC syntax.
1974         Allow disassembly of ColdFire V4e object files.
1975
1976 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1977
1978         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1979
1980 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1981
1982         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1983
1984 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1985
1986         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1987
1988 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1989
1990         * i386.h (i386_optab): Added xstore/xcrypt insns.
1991
1992 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1993
1994         * h8300.h (32bit ldc/stc): Add relaxing support.
1995
1996 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1997
1998         * h8300.h (BITOP): Pass MEMRELAX flag.
1999
2000 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2001
2002         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2003         except for the H8S.
2004
2005 For older changes see ChangeLog-9103
2006 \f
2007 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2008
2009 Copying and distribution of this file, with or without modification,
2010 are permitted in any medium without royalty provided the copyright
2011 notice and this notice are preserved.
2012
2013 Local Variables:
2014 mode: change-log
2015 left-margin: 8
2016 fill-column: 74
2017 version-control: never
2018 End: