1 2006-04-26 Thiemo Seufer <ths@networkno.de>
3 * mips.h: Improve comments describing the bitfield instruction
6 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
8 * avr.h (AVR_ISA_PWMx): New.
10 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
12 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
13 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
14 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
15 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
16 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
18 2006-03-10 Paul Brook <paul@codesourcery.com>
20 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
22 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
24 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
25 first. Correct mask of bb "B" opcode.
27 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
29 * i386.h (i386_optab): Support Intel Merom New Instructions.
31 2006-02-24 Paul Brook <paul@codesourcery.com>
33 * arm.h: Add V7 feature bits.
35 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
37 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
39 2006-01-31 Paul Brook <paul@codesourcery.com>
40 Richard Earnshaw <rearnsha@arm.com>
42 * arm.h: Use ARM_CPU_FEATURE.
43 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
44 (arm_feature_set): Change to a structure.
45 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
46 ARM_FEATURE): New macros.
48 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
50 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
51 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
52 (ADD_PC_INCR_OPCODE): Don't define.
54 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
57 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
59 2005-11-14 David Ung <davidu@mips.com>
61 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
62 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
63 save/restore encoding of the args field.
65 2005-10-28 Dave Brolley <brolley@redhat.com>
67 Contribute the following changes:
68 2005-02-16 Dave Brolley <brolley@redhat.com>
70 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
71 cgen_isa_mask_* to cgen_bitset_*.
74 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
76 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
77 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
78 (CGEN_CPU_TABLE): Make isas a ponter.
80 2003-09-29 Dave Brolley <brolley@redhat.com>
82 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
83 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
84 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
86 2002-12-13 Dave Brolley <brolley@redhat.com>
88 * cgen.h (symcat.h): #include it.
89 (cgen-bitset.h): #include it.
90 (CGEN_ATTR_VALUE_TYPE): Now a union.
91 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
92 (CGEN_ATTR_ENTRY): 'value' now unsigned.
93 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
94 * cgen-bitset.h: New file.
96 2005-09-30 Catherine Moore <clm@cm00re.com>
100 2005-10-24 Jan Beulich <jbeulich@novell.com>
102 * ia64.h (enum ia64_opnd): Move memory operand out of set of
105 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
107 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
108 Add FLAG_STRICT to pa10 ftest opcode.
110 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
112 * hppa.h (pa_opcodes): Remove lha entries.
114 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
116 * hppa.h (FLAG_STRICT): Revise comment.
117 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
118 before corresponding pa11 opcodes. Add strict pa10 register-immediate
121 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
123 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
125 2005-09-06 Chao-ying Fu <fu@mips.com>
127 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
128 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
130 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
131 (INSN_ASE_MASK): Update to include INSN_MT.
132 (INSN_MT): New define for MT ASE.
134 2005-08-25 Chao-ying Fu <fu@mips.com>
136 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
137 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
138 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
139 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
140 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
141 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
143 (INSN_DSP): New define for DSP ASE.
145 2005-08-18 Alan Modra <amodra@bigpond.net.au>
149 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
151 * ppc.h (PPC_OPCODE_E300): Define.
153 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
155 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
157 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
160 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
163 2005-07-27 Jan Beulich <jbeulich@novell.com>
165 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
166 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
167 Add movq-s as 64-bit variants of movd-s.
169 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
171 * hppa.h: Fix punctuation in comment.
173 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
174 implicit space-register addressing. Set space-register bits on opcodes
175 using implicit space-register addressing. Add various missing pa20
176 long-immediate opcodes. Remove various opcodes using implicit 3-bit
177 space-register addressing. Use "fE" instead of "fe" in various
180 2005-07-18 Jan Beulich <jbeulich@novell.com>
182 * i386.h (i386_optab): Operands of aam and aad are unsigned.
184 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
186 * i386.h (i386_optab): Support Intel VMX Instructions.
188 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
190 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
192 2005-07-05 Jan Beulich <jbeulich@novell.com>
194 * i386.h (i386_optab): Add new insns.
196 2005-07-01 Nick Clifton <nickc@redhat.com>
198 * sparc.h: Add typedefs to structure declarations.
200 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
203 * i386.h (i386_optab): Update comments for 64bit addressing on
204 mov. Allow 64bit addressing for mov and movq.
206 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
208 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
209 respectively, in various floating-point load and store patterns.
211 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
213 * hppa.h (FLAG_STRICT): Correct comment.
214 (pa_opcodes): Update load and store entries to allow both PA 1.X and
215 PA 2.0 mneumonics when equivalent. Entries with cache control
216 completers now require PA 1.1. Adjust whitespace.
218 2005-05-19 Anton Blanchard <anton@samba.org>
220 * ppc.h (PPC_OPCODE_POWER5): Define.
222 2005-05-10 Nick Clifton <nickc@redhat.com>
224 * Update the address and phone number of the FSF organization in
225 the GPL notices in the following files:
226 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
227 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
228 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
229 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
230 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
231 tic54x.h, tic80.h, v850.h, vax.h
233 2005-05-09 Jan Beulich <jbeulich@novell.com>
235 * i386.h (i386_optab): Add ht and hnt.
237 2005-04-18 Mark Kettenis <kettenis@gnu.org>
239 * i386.h: Insert hyphens into selected VIA PadLock extensions.
240 Add xcrypt-ctr. Provide aliases without hyphens.
242 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
244 Moved from ../ChangeLog
246 2005-04-12 Paul Brook <paul@codesourcery.com>
247 * m88k.h: Rename psr macros to avoid conflicts.
249 2005-03-12 Zack Weinberg <zack@codesourcery.com>
250 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
251 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
254 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
255 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
256 Remove redundant instruction types.
257 (struct argument): X_op - new field.
258 (struct cst4_entry): Remove.
259 (no_op_insn): Declare.
261 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
262 * crx.h (enum argtype): Rename types, remove unused types.
264 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
265 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
266 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
267 (enum operand_type): Rearrange operands, edit comments.
268 replace us<N> with ui<N> for unsigned immediate.
269 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
270 displacements (respectively).
271 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
272 (instruction type): Add NO_TYPE_INS.
273 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
274 (operand_entry): New field - 'flags'.
275 (operand flags): New.
277 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
278 * crx.h (operand_type): Remove redundant types i3, i4,
280 Add new unsigned immediate types us3, us4, us5, us16.
282 2005-04-12 Mark Kettenis <kettenis@gnu.org>
284 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
285 adjust them accordingly.
287 2005-04-01 Jan Beulich <jbeulich@novell.com>
289 * i386.h (i386_optab): Add rdtscp.
291 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
293 * i386.h (i386_optab): Don't allow the `l' suffix for moving
294 between memory and segment register. Allow movq for moving between
295 general-purpose register and segment register.
297 2005-02-09 Jan Beulich <jbeulich@novell.com>
300 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
301 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
304 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
306 * m68k.h (m68008, m68ec030, m68882): Remove.
308 (cpu_m68k, cpu_cf): New.
309 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
310 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
312 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
314 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
315 * cgen.h (enum cgen_parse_operand_type): Add
316 CGEN_PARSE_OPERAND_SYMBOLIC.
318 2005-01-21 Fred Fish <fnf@specifixinc.com>
320 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
321 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
322 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
324 2005-01-19 Fred Fish <fnf@specifixinc.com>
326 * mips.h (struct mips_opcode): Add new pinfo2 member.
327 (INSN_ALIAS): New define for opcode table entries that are
328 specific instances of another entry, such as 'move' for an 'or'
330 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
331 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
333 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
335 * mips.h (CPU_RM9000): Define.
336 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
338 2004-11-25 Jan Beulich <jbeulich@novell.com>
340 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
341 to/from test registers are illegal in 64-bit mode. Add missing
342 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
343 (previously one had to explicitly encode a rex64 prefix). Re-enable
344 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
345 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
347 2004-11-23 Jan Beulich <jbeulich@novell.com>
349 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
350 available only with SSE2. Change the MMX additions introduced by SSE
351 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
352 instructions by their now designated identifier (since combining i686
353 and 3DNow! does not really imply 3DNow!A).
355 2004-11-19 Alan Modra <amodra@bigpond.net.au>
357 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
358 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
360 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
361 Vineet Sharma <vineets@noida.hcltech.com>
363 * maxq.h: New file: Disassembly information for the maxq port.
365 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
367 * i386.h (i386_optab): Put back "movzb".
369 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
371 * cris.h (enum cris_insn_version_usage): Tweak formatting and
372 comments. Remove member cris_ver_sim. Add members
373 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
374 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
375 (struct cris_support_reg, struct cris_cond15): New types.
376 (cris_conds15): Declare.
377 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
378 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
379 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
380 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
381 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
384 2004-11-04 Jan Beulich <jbeulich@novell.com>
386 * i386.h (sldx_Suf): Remove.
387 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
388 (q_FP): Define, implying no REX64.
389 (x_FP, sl_FP): Imply FloatMF.
390 (i386_optab): Split reg and mem forms of moving from segment registers
391 so that the memory forms can ignore the 16-/32-bit operand size
392 distinction. Adjust a few others for Intel mode. Remove *FP uses from
393 all non-floating-point instructions. Unite 32- and 64-bit forms of
394 movsx, movzx, and movd. Adjust floating point operations for the above
395 changes to the *FP macros. Add DefaultSize to floating point control
396 insns operating on larger memory ranges. Remove left over comments
397 hinting at certain insns being Intel-syntax ones where the ones
398 actually meant are already gone.
400 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
402 * crx.h: Add COPS_REG_INS - Coprocessor Special register
405 2004-09-30 Paul Brook <paul@codesourcery.com>
407 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
408 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
410 2004-09-11 Theodore A. Roth <troth@openavr.org>
412 * avr.h: Add support for
413 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
415 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
417 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
419 2004-08-24 Dmitry Diky <diwil@spec.ru>
421 * msp430.h (msp430_opc): Add new instructions.
422 (msp430_rcodes): Declare new instructions.
423 (msp430_hcodes): Likewise..
425 2004-08-13 Nick Clifton <nickc@redhat.com>
428 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
431 2004-08-30 Michal Ludvig <mludvig@suse.cz>
433 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
435 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
437 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
439 2004-07-21 Jan Beulich <jbeulich@novell.com>
441 * i386.h: Adjust instruction descriptions to better match the
444 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
446 * arm.h: Remove all old content. Replace with architecture defines
447 from gas/config/tc-arm.c.
449 2004-07-09 Andreas Schwab <schwab@suse.de>
451 * m68k.h: Fix comment.
453 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
457 2004-06-24 Alan Modra <amodra@bigpond.net.au>
459 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
461 2004-05-24 Peter Barada <peter@the-baradas.com>
463 * m68k.h: Add 'size' to m68k_opcode.
465 2004-05-05 Peter Barada <peter@the-baradas.com>
467 * m68k.h: Switch from ColdFire chip name to core variant.
469 2004-04-22 Peter Barada <peter@the-baradas.com>
471 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
472 descriptions for new EMAC cases.
473 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
474 handle Motorola MAC syntax.
475 Allow disassembly of ColdFire V4e object files.
477 2004-03-16 Alan Modra <amodra@bigpond.net.au>
479 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
481 2004-03-12 Jakub Jelinek <jakub@redhat.com>
483 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
485 2004-03-12 Michal Ludvig <mludvig@suse.cz>
487 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
489 2004-03-12 Michal Ludvig <mludvig@suse.cz>
491 * i386.h (i386_optab): Added xstore/xcrypt insns.
493 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
495 * h8300.h (32bit ldc/stc): Add relaxing support.
497 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
499 * h8300.h (BITOP): Pass MEMRELAX flag.
501 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
503 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
506 For older changes see ChangeLog-9103
512 version-control: never