include/opcode/ChangeLog

   1 2009-11-18  Paul Brook  <paul@codesourcery.com>
   2
   3         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
   4
   5 2009-11-17  Paul Brook  <paul@codesourcery.com>
   6         Daniel Jacobowitz  <dan@codesourcery.com>
   7
   8         * arm.h (ARM_EXT_V6_DSP): Define.
   9         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
  10         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
  11
  12 2009-11-04  DJ Delorie  <dj@redhat.com>
  13
  14         * rx.h (rx_decode_opcode) (mvtipl): Add.
  15         (mvtcp, mvfcp, opecp): Remove.
  16
  17 2009-11-02  Paul Brook  <paul@codesourcery.com>
  18
  19         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
  20         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
  21         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
  22         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
  23         FPU_ARCH_NEON_VFP_V4): Define.
  24
  25 2009-10-23  Doug Evans  <dje@sebabeach.org>
  26
  27         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
  28         * cgen.h: Update.  Improve multi-inclusion macro name.
  29
  30 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
  31
  32         * ppc.h (PPC_OPCODE_476): Define.
  33
  34 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
  35
  36         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
  37
  38 2009-09-29  DJ Delorie  <dj@redhat.com>
  39
  40         * rx.h: New file.
  41
  42 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  43
  44         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  45
  46 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  47
  48         * ppc.h (PPC_OPCODE_PPCA2): New.
  49
  50 2009-09-05  Martin Thuresson  <martin@mtme.org>
  51
  52         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  53
  54 2009-08-29  Martin Thuresson  <martin@mtme.org>
  55
  56         * tic30.h (template): Rename type template to
  57         insn_template. Updated code to use new name.
  58         * tic54x.h (template): Rename type template to
  59         insn_template.
  60
  61 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  62
  63         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  64
  65 2009-06-11  Anthony Green  <green@moxielogic.com>
  66
  67         * moxie.h (MOXIE_F3_PCREL): Define.
  68         (moxie_form3_opc_info): Grow.
  69
  70 2009-06-06  Anthony Green  <green@moxielogic.com>
  71
  72         * moxie.h (MOXIE_F1_M): Define.
  73
  74 2009-04-15  Anthony Green  <green@moxielogic.com>
  75
  76         * moxie.h: Created.
  77
  78 2009-04-06  DJ Delorie  <dj@redhat.com>
  79
  80         * h8300.h: Add relaxation attributes to MOVA opcodes.
  81
  82 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  83
  84         * ppc.h (ppc_parse_cpu): Declare.
  85
  86 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  87
  88         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  89         and _IMM11 for mbitclr and mbitset.
  90         * score-datadep.h: Update dependency information.
  91
  92 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  93
  94         * ppc.h (PPC_OPCODE_POWER7): New.
  95
  96 2009-02-06  Doug Evans  <dje@google.com>
  97
  98         * i386.h: Add comment regarding sse* insns and prefixes.
  99
 100 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 101
 102         * mips.h (INSN_XLR): Define.
 103         (INSN_CHIP_MASK): Update.
 104         (CPU_XLR): Define.
 105         (OPCODE_IS_MEMBER): Update.
 106         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 107
 108 2009-01-28  Doug Evans  <dje@google.com>
 109
 110         * opcode/i386.h: Add multiple inclusion protection.
 111         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 112         (EDI_REG_NUM): New macros.
 113         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 114         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 115         (REX_PREFIX_P): New macro.
 116
 117 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 118
 119         * ppc.h (struct powerpc_opcode): New field "deprecated".
 120         (PPC_OPCODE_NOPOWER4): Delete.
 121
 122 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 123
 124         * mips.h: Define CPU_R14000, CPU_R16000.
 125         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 126
 127 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 128
 129         * arm.h (FPU_NEON_FP16): New.
 130         (FPU_ARCH_NEON_FP16): New.
 131
 132 2008-11-06  Chao-ying Fu  <fu@mips.com>
 133
 134         * mips.h: Doucument '1' for 5-bit sync type.
 135
 136 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 139         IA64_RS_CR.
 140
 141 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 142
 143         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 144
 145 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 146
 147         * ppc.h (PPC_OPCODE_405): Define.
 148         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 149
 150 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 151
 152         * ppc.h (ppc_cpu_t): New typedef.
 153         (struct powerpc_opcode <flags>): Use it.
 154         (struct powerpc_operand <insert, extract>): Likewise.
 155         (struct powerpc_macro <flags>): Likewise.
 156
 157 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 158
 159         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 160         Update comment before MIPS16 field descriptors to mention MIPS16.
 161         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 162         BBIT.
 163         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 164         New bit masks and shift counts for cins and exts.
 165
 166         * mips.h: Document new field descriptors +Q.
 167         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 168
 169 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 170
 171         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 172         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 173
 174 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 175
 176         * ppc.h: (PPC_OPCODE_E500MC): New.
 177
 178 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 179
 180         * i386.h (MAX_OPERANDS): Set to 5.
 181         (MAX_MNEM_SIZE): Changed to 20.
 182
 183 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 184
 185         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 186
 187 2008-03-09  Paul Brook  <paul@codesourcery.com>
 188
 189         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 190
 191 2008-03-04  Paul Brook  <paul@codesourcery.com>
 192
 193         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 194         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 195         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 196
 197 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 198             Nick Clifton  <nickc@redhat.com>
 199
 200         PR 3134
 201         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 202         with a 32-bit displacement but without the top bit of the 4th byte
 203         set.
 204
 205 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 206
 207         * cr16.h (cr16_num_optab): Declared.
 208
 209 2008-02-14  Hakan Ardo  <hakan@debian.org>
 210
 211         PR gas/2626
 212         * avr.h (AVR_ISA_2xxe): Define.
 213
 214 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 215
 216         * mips.h: Update copyright.
 217         (INSN_CHIP_MASK): New macro.
 218         (INSN_OCTEON): New macro.
 219         (CPU_OCTEON): New macro.
 220         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 221
 222 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 223
 224         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 225
 226 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 227
 228         * avr.h (AVR_ISA_USB162): Add new opcode set.
 229         (AVR_ISA_AVR3): Likewise.
 230
 231 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 232
 233         * mips.h (INSN_LOONGSON_2E): New.
 234         (INSN_LOONGSON_2F): New.
 235         (CPU_LOONGSON_2E): New.
 236         (CPU_LOONGSON_2F): New.
 237         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 238
 239 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 240
 241         * mips.h (INSN_ISA*): Redefine certain values as an
 242         enumeration.  Update comments.
 243         (mips_isa_table): New.
 244         (ISA_MIPS*): Redefine to match enumeration.
 245         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 246         values.
 247
 248 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 249
 250         * ppc.h (PPC_OPCODE_PPCPS): New.
 251
 252 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 253
 254         * m68k.h: Document j K & E.
 255
 256 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 257
 258         * cr16.h: New file for CR16 target.
 259
 260 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 261
 262         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 263
 264 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 265
 266         * m68k.h (mcfisa_c): New.
 267         (mcfusp, mcf_mask): Adjust.
 268
 269 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 270
 271         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 272         (num_powerpc_operands): Declare.
 273         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 274         (PPC_OPERAND_PLUS1): Define.
 275
 276 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         * i386.h (REX_MODE64): Renamed to ...
 279         (REX_W): This.
 280         (REX_EXTX): Renamed to ...
 281         (REX_R): This.
 282         (REX_EXTY): Renamed to ...
 283         (REX_X): This.
 284         (REX_EXTZ): Renamed to ...
 285         (REX_B): This.
 286
 287 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 288
 289         * i386.h: Add entries from config/tc-i386.h and move tables
 290         to opcodes/i386-opc.h.
 291
 292 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386.h (FloatDR): Removed.
 295         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 296
 297 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 298
 299         * spu-insns.h: Add soma double-float insns.
 300
 301 2007-02-20  Thiemo Seufer  <ths@mips.com>
 302             Chao-Ying Fu  <fu@mips.com>
 303
 304         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 305         (INSN_DSPR2): Add flag for DSP R2 instructions.
 306         (M_BALIGN): New macro.
 307
 308 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 309
 310         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 311         and Seg3ShortFrom with Shortform.
 312
 313 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         PR gas/4027
 316         * i386.h (i386_optab): Put the real "test" before the pseudo
 317         one.
 318
 319 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 320
 321         * m68k.h (m68010up): OR fido_a.
 322
 323 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 324
 325         * m68k.h (fido_a): New.
 326
 327 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 328
 329         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 330         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 331         values.
 332
 333 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 336
 337 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 338
 339         * score-inst.h (enum score_insn_type): Add Insn_internal.
 340
 341 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 342             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 343             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 344             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 345             Alan Modra  <amodra@bigpond.net.au>
 346
 347         * spu-insns.h: New file.
 348         * spu.h: New file.
 349
 350 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 351
 352         * ppc.h (PPC_OPCODE_CELL): Define.
 353
 354 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 355
 356         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 357         in amdfam10 architecture.
 358
 359 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 360
 361         * i386.h: Replace CpuMNI with CpuSSSE3.
 362
 363 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 364             Joseph Myers  <joseph@codesourcery.com>
 365             Ian Lance Taylor  <ian@wasabisystems.com>
 366             Ben Elliston  <bje@wasabisystems.com>
 367
 368         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 369
 370 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 371
 372         * score-datadep.h: New file.
 373         * score-inst.h: New file.
 374
 375 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 376
 377         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 378         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 379         movdq2q and movq2dq.
 380
 381 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 382            Michael Meissner             <michael.meissner@amd.com>
 383
 384         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 385
 386 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         * i386.h (i386_optab): Add "nop" with memory reference.
 389
 390 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         * i386.h (i386_optab): Update comment for 64bit NOP.
 393
 394 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 395             Anton Blanchard  <anton@samba.org>
 396
 397         * ppc.h (PPC_OPCODE_POWER6): Define.
 398         Adjust whitespace.
 399
 400 2006-06-05  Thiemo Seufer  <ths@mips.com>
 401
 402         * mips.h: Improve description of MT flags.
 403
 404 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 405
 406         * m68k.h (mcf_mask): Define.
 407
 408 2006-05-05  Thiemo Seufer  <ths@mips.com>
 409             David Ung  <davidu@mips.com>
 410
 411         * mips.h (enum): Add macro M_CACHE_AB.
 412
 413 2006-05-04  Thiemo Seufer  <ths@mips.com>
 414             Nigel Stephens  <nigel@mips.com>
 415             David Ung  <davidu@mips.com>
 416
 417         * mips.h: Add INSN_SMARTMIPS define.
 418
 419 2006-04-30  Thiemo Seufer  <ths@mips.com>
 420             David Ung  <davidu@mips.com>
 421
 422         * mips.h: Defines udi bits and masks.  Add description of
 423         characters which may appear in the args field of udi
 424         instructions.
 425
 426 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 427
 428         * mips.h: Improve comments describing the bitfield instruction
 429         fields.
 430
 431 2006-04-26  Julian Brown  <julian@codesourcery.com>
 432
 433         * arm.h (FPU_VFP_EXT_V3): Define constant.
 434         (FPU_NEON_EXT_V1): Likewise.
 435         (FPU_VFP_HARD): Update.
 436         (FPU_VFP_V3): Define macro.
 437         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 438
 439 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 440
 441         * avr.h (AVR_ISA_PWMx): New.
 442
 443 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 444
 445         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 446         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 447         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 448         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 449         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 450
 451 2006-03-10  Paul Brook  <paul@codesourcery.com>
 452
 453         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 454
 455 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 456
 457         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 458         first.  Correct mask of bb "B" opcode.
 459
 460 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 461
 462         * i386.h (i386_optab): Support Intel Merom New Instructions.
 463
 464 2006-02-24  Paul Brook  <paul@codesourcery.com>
 465
 466         * arm.h: Add V7 feature bits.
 467
 468 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 469
 470         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 471
 472 2006-01-31  Paul Brook  <paul@codesourcery.com>
 473         Richard Earnshaw <rearnsha@arm.com>
 474
 475         * arm.h: Use ARM_CPU_FEATURE.
 476         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 477         (arm_feature_set): Change to a structure.
 478         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 479         ARM_FEATURE): New macros.
 480
 481 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 482
 483         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 484         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 485         (ADD_PC_INCR_OPCODE): Don't define.
 486
 487 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 488
 489         PR gas/1874
 490         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 491
 492 2005-11-14  David Ung  <davidu@mips.com>
 493
 494         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 495         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 496         save/restore encoding of the args field.
 497
 498 2005-10-28  Dave Brolley  <brolley@redhat.com>
 499
 500         Contribute the following changes:
 501         2005-02-16  Dave Brolley  <brolley@redhat.com>
 502
 503         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 504         cgen_isa_mask_* to cgen_bitset_*.
 505         * cgen.h: Likewise.
 506
 507         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 508
 509         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 510         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 511         (CGEN_CPU_TABLE): Make isas a ponter.
 512
 513         2003-09-29  Dave Brolley  <brolley@redhat.com>
 514
 515         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 516         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 517         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 518
 519         2002-12-13  Dave Brolley  <brolley@redhat.com>
 520
 521         * cgen.h (symcat.h): #include it.
 522         (cgen-bitset.h): #include it.
 523         (CGEN_ATTR_VALUE_TYPE): Now a union.
 524         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 525         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 526         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 527         * cgen-bitset.h: New file.
 528
 529 2005-09-30  Catherine Moore  <clm@cm00re.com>
 530
 531         * bfin.h: New file.
 532
 533 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 534
 535         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 536         indirect operands.
 537
 538 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 539
 540         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 541         Add FLAG_STRICT to pa10 ftest opcode.
 542
 543 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 544
 545         * hppa.h (pa_opcodes): Remove lha entries.
 546
 547 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 548
 549         * hppa.h (FLAG_STRICT): Revise comment.
 550         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 551         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 552         entries for "fdc".
 553
 554 2005-09-30  Catherine Moore  <clm@cm00re.com>
 555
 556         * bfin.h: New file.
 557
 558 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 559
 560         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 561
 562 2005-09-06  Chao-ying Fu  <fu@mips.com>
 563
 564         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 565         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 566         define.
 567         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 568         (INSN_ASE_MASK): Update to include INSN_MT.
 569         (INSN_MT): New define for MT ASE.
 570
 571 2005-08-25  Chao-ying Fu  <fu@mips.com>
 572
 573         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 574         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 575         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 576         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 577         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 578         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 579         instructions.
 580         (INSN_DSP): New define for DSP ASE.
 581
 582 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 583
 584         * a29k.h: Delete.
 585
 586 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 587
 588         * ppc.h (PPC_OPCODE_E300): Define.
 589
 590 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 591
 592         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 593
 594 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 595
 596         PR gas/336
 597         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 598         and pitlb.
 599
 600 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 601
 602         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 603         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 604         Add movq-s as 64-bit variants of movd-s.
 605
 606 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 607
 608         * hppa.h: Fix punctuation in comment.
 609
 610         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 611         implicit space-register addressing.  Set space-register bits on opcodes
 612         using implicit space-register addressing.  Add various missing pa20
 613         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 614         space-register addressing.  Use "fE" instead of "fe" in various
 615         fstw opcodes.
 616
 617 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 618
 619         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 620
 621 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 622
 623         * i386.h (i386_optab): Support Intel VMX Instructions.
 624
 625 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 626
 627         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 628
 629 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 630
 631         * i386.h (i386_optab): Add new insns.
 632
 633 2005-07-01  Nick Clifton  <nickc@redhat.com>
 634
 635         * sparc.h: Add typedefs to structure declarations.
 636
 637 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         PR 1013
 640         * i386.h (i386_optab): Update comments for 64bit addressing on
 641         mov. Allow 64bit addressing for mov and movq.
 642
 643 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 644
 645         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 646         respectively, in various floating-point load and store patterns.
 647
 648 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 649
 650         * hppa.h (FLAG_STRICT): Correct comment.
 651         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 652         PA 2.0 mneumonics when equivalent.  Entries with cache control
 653         completers now require PA 1.1.  Adjust whitespace.
 654
 655 2005-05-19  Anton Blanchard  <anton@samba.org>
 656
 657         * ppc.h (PPC_OPCODE_POWER5): Define.
 658
 659 2005-05-10  Nick Clifton  <nickc@redhat.com>
 660
 661         * Update the address and phone number of the FSF organization in
 662         the GPL notices in the following files:
 663         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 664         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 665         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 666         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 667         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 668         tic54x.h, tic80.h, v850.h, vax.h
 669
 670 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 671
 672         * i386.h (i386_optab): Add ht and hnt.
 673
 674 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 675
 676         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 677         Add xcrypt-ctr.  Provide aliases without hyphens.
 678
 679 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         Moved from ../ChangeLog
 682
 683         2005-04-12  Paul Brook  <paul@codesourcery.com>
 684         * m88k.h: Rename psr macros to avoid conflicts.
 685
 686         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 687         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 688         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 689         and ARM_ARCH_V6ZKT2.
 690
 691         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 692         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 693         Remove redundant instruction types.
 694         (struct argument): X_op - new field.
 695         (struct cst4_entry): Remove.
 696         (no_op_insn): Declare.
 697
 698         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 699         * crx.h (enum argtype): Rename types, remove unused types.
 700
 701         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 702         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 703         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 704         (enum operand_type): Rearrange operands, edit comments.
 705         replace us<N> with ui<N> for unsigned immediate.
 706         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 707         displacements (respectively).
 708         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 709         (instruction type): Add NO_TYPE_INS.
 710         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 711         (operand_entry): New field - 'flags'.
 712         (operand flags): New.
 713
 714         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 715         * crx.h (operand_type): Remove redundant types i3, i4,
 716         i5, i8, i12.
 717         Add new unsigned immediate types us3, us4, us5, us16.
 718
 719 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 720
 721         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 722         adjust them accordingly.
 723
 724 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 725
 726         * i386.h (i386_optab): Add rdtscp.
 727
 728 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 731         between memory and segment register. Allow movq for moving between
 732         general-purpose register and segment register.
 733
 734 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 735
 736         PR gas/707
 737         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 738         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 739         fnstsw.
 740
 741 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 742
 743         * m68k.h (m68008, m68ec030, m68882): Remove.
 744         (m68k_mask): New.
 745         (cpu_m68k, cpu_cf): New.
 746         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 747         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 748
 749 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 750
 751         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 752         * cgen.h (enum cgen_parse_operand_type): Add
 753         CGEN_PARSE_OPERAND_SYMBOLIC.
 754
 755 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 756
 757         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 758         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 759         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 760
 761 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 762
 763         * mips.h (struct mips_opcode): Add new pinfo2 member.
 764         (INSN_ALIAS): New define for opcode table entries that are
 765         specific instances of another entry, such as 'move' for an 'or'
 766         with a zero operand.
 767         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 768         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 769
 770 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 771
 772         * mips.h (CPU_RM9000): Define.
 773         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 774
 775 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 776
 777         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 778         to/from test registers are illegal in 64-bit mode. Add missing
 779         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 780         (previously one had to explicitly encode a rex64 prefix). Re-enable
 781         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 782         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 783
 784 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 785
 786         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 787         available only with SSE2. Change the MMX additions introduced by SSE
 788         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 789         instructions by their now designated identifier (since combining i686
 790         and 3DNow! does not really imply 3DNow!A).
 791
 792 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 793
 794         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 795         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 796
 797 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 798             Vineet Sharma      <vineets@noida.hcltech.com>
 799
 800         * maxq.h: New file: Disassembly information for the maxq port.
 801
 802 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 803
 804         * i386.h (i386_optab): Put back "movzb".
 805
 806 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 807
 808         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 809         comments.  Remove member cris_ver_sim.  Add members
 810         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 811         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 812         (struct cris_support_reg, struct cris_cond15): New types.
 813         (cris_conds15): Declare.
 814         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 815         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 816         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 817         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 818         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 819         SIZE_FIELD_UNSIGNED.
 820
 821 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 822
 823         * i386.h (sldx_Suf): Remove.
 824         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 825         (q_FP): Define, implying no REX64.
 826         (x_FP, sl_FP): Imply FloatMF.
 827         (i386_optab): Split reg and mem forms of moving from segment registers
 828         so that the memory forms can ignore the 16-/32-bit operand size
 829         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 830         all non-floating-point instructions. Unite 32- and 64-bit forms of
 831         movsx, movzx, and movd. Adjust floating point operations for the above
 832         changes to the *FP macros. Add DefaultSize to floating point control
 833         insns operating on larger memory ranges. Remove left over comments
 834         hinting at certain insns being Intel-syntax ones where the ones
 835         actually meant are already gone.
 836
 837 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 838
 839         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 840         instruction type.
 841
 842 2004-09-30  Paul Brook  <paul@codesourcery.com>
 843
 844         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 845         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 846
 847 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 848
 849         * avr.h: Add support for
 850         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 851
 852 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 853
 854         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 855
 856 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 857
 858         * msp430.h (msp430_opc): Add new instructions.
 859         (msp430_rcodes): Declare new instructions.
 860         (msp430_hcodes): Likewise..
 861
 862 2004-08-13  Nick Clifton  <nickc@redhat.com>
 863
 864         PR/301
 865         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 866         processors.
 867
 868 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 869
 870         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 871
 872 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 875
 876 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 877
 878         * i386.h: Adjust instruction descriptions to better match the
 879         specification.
 880
 881 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 882
 883         * arm.h: Remove all old content.  Replace with architecture defines
 884         from gas/config/tc-arm.c.
 885
 886 2004-07-09  Andreas Schwab  <schwab@suse.de>
 887
 888         * m68k.h: Fix comment.
 889
 890 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 891
 892         * crx.h: New file.
 893
 894 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 895
 896         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 897
 898 2004-05-24  Peter Barada  <peter@the-baradas.com>
 899
 900         * m68k.h: Add 'size' to m68k_opcode.
 901
 902 2004-05-05  Peter Barada  <peter@the-baradas.com>
 903
 904         * m68k.h: Switch from ColdFire chip name to core variant.
 905
 906 2004-04-22  Peter Barada  <peter@the-baradas.com>
 907
 908         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 909         descriptions for new EMAC cases.
 910         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 911         handle Motorola MAC syntax.
 912         Allow disassembly of ColdFire V4e object files.
 913
 914 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 915
 916         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 917
 918 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 919
 920         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 921
 922 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 923
 924         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 925
 926 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 927
 928         * i386.h (i386_optab): Added xstore/xcrypt insns.
 929
 930 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 931
 932         * h8300.h (32bit ldc/stc): Add relaxing support.
 933
 934 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 935
 936         * h8300.h (BITOP): Pass MEMRELAX flag.
 937
 938 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 939
 940         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 941         except for the H8S.
 942
 943 For older changes see ChangeLog-9103
 944 \f
 945 Local Variables:
 946 mode: change-log
 947 left-margin: 8
 948 fill-column: 74
 949 version-control: never
 950 End: