include/opcode/ChangeLog

   1 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
   4         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
   5         movdq2q and movq2dq.
   6
   7 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
   8            Michael Meissner             <michael.meissner@amd.com>
   9
  10         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  11
  12 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * i386.h (i386_optab): Add "nop" with memory reference.
  15
  16 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386.h (i386_optab): Update comment for 64bit NOP.
  19
  20 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  21             Anton Blanchard  <anton@samba.org>
  22
  23         * ppc.h (PPC_OPCODE_POWER6): Define.
  24         Adjust whitespace.
  25
  26 2006-06-05  Thiemo Seufer  <ths@mips.com>
  27
  28         * mips.h: Improve description of MT flags.
  29
  30 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  31
  32         * m68k.h (mcf_mask): Define.
  33
  34 2006-05-05  Thiemo Seufer  <ths@mips.com>
  35             David Ung  <davidu@mips.com>
  36
  37         * mips.h (enum): Add macro M_CACHE_AB.
  38
  39 2006-05-04  Thiemo Seufer  <ths@mips.com>
  40             Nigel Stephens  <nigel@mips.com>
  41             David Ung  <davidu@mips.com>
  42
  43         * mips.h: Add INSN_SMARTMIPS define.
  44
  45 2006-04-30  Thiemo Seufer  <ths@mips.com>
  46             David Ung  <davidu@mips.com>
  47
  48         * mips.h: Defines udi bits and masks.  Add description of
  49         characters which may appear in the args field of udi
  50         instructions.
  51
  52 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  53
  54         * mips.h: Improve comments describing the bitfield instruction
  55         fields.
  56
  57 2006-04-26  Julian Brown  <julian@codesourcery.com>
  58
  59         * arm.h (FPU_VFP_EXT_V3): Define constant.
  60         (FPU_NEON_EXT_V1): Likewise.
  61         (FPU_VFP_HARD): Update.
  62         (FPU_VFP_V3): Define macro.
  63         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  64
  65 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  66
  67         * avr.h (AVR_ISA_PWMx): New.
  68
  69 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  70
  71         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  72         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  73         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  74         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  75         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  76
  77 2006-03-10  Paul Brook  <paul@codesourcery.com>
  78
  79         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  80
  81 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  82
  83         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  84         first.  Correct mask of bb "B" opcode.
  85
  86 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  87
  88         * i386.h (i386_optab): Support Intel Merom New Instructions.
  89
  90 2006-02-24  Paul Brook  <paul@codesourcery.com>
  91
  92         * arm.h: Add V7 feature bits.
  93
  94 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  97
  98 2006-01-31  Paul Brook  <paul@codesourcery.com>
  99         Richard Earnshaw <rearnsha@arm.com>
 100
 101         * arm.h: Use ARM_CPU_FEATURE.
 102         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 103         (arm_feature_set): Change to a structure.
 104         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 105         ARM_FEATURE): New macros.
 106
 107 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 108
 109         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 110         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 111         (ADD_PC_INCR_OPCODE): Don't define.
 112
 113 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         PR gas/1874
 116         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 117
 118 2005-11-14  David Ung  <davidu@mips.com>
 119
 120         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 121         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 122         save/restore encoding of the args field.
 123
 124 2005-10-28  Dave Brolley  <brolley@redhat.com>
 125
 126         Contribute the following changes:
 127         2005-02-16  Dave Brolley  <brolley@redhat.com>
 128
 129         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 130         cgen_isa_mask_* to cgen_bitset_*.
 131         * cgen.h: Likewise.
 132
 133         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 134
 135         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 136         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 137         (CGEN_CPU_TABLE): Make isas a ponter.
 138
 139         2003-09-29  Dave Brolley  <brolley@redhat.com>
 140
 141         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 142         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 143         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 144
 145         2002-12-13  Dave Brolley  <brolley@redhat.com>
 146
 147         * cgen.h (symcat.h): #include it.
 148         (cgen-bitset.h): #include it.
 149         (CGEN_ATTR_VALUE_TYPE): Now a union.
 150         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 151         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 152         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 153         * cgen-bitset.h: New file.
 154
 155 2005-09-30  Catherine Moore  <clm@cm00re.com>
 156
 157         * bfin.h: New file.
 158
 159 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 160
 161         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 162         indirect operands.
 163
 164 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 165
 166         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 167         Add FLAG_STRICT to pa10 ftest opcode.
 168
 169 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 170
 171         * hppa.h (pa_opcodes): Remove lha entries.
 172
 173 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 174
 175         * hppa.h (FLAG_STRICT): Revise comment.
 176         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 177         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 178         entries for "fdc".
 179
 180 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 181
 182         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 183
 184 2005-09-06  Chao-ying Fu  <fu@mips.com>
 185
 186         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 187         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 188         define.
 189         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 190         (INSN_ASE_MASK): Update to include INSN_MT.
 191         (INSN_MT): New define for MT ASE.
 192
 193 2005-08-25  Chao-ying Fu  <fu@mips.com>
 194
 195         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 196         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 197         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 198         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 199         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 200         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 201         instructions.
 202         (INSN_DSP): New define for DSP ASE.
 203
 204 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 205
 206         * a29k.h: Delete.
 207
 208 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 209
 210         * ppc.h (PPC_OPCODE_E300): Define.
 211
 212 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 213
 214         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 215
 216 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 217
 218         PR gas/336
 219         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 220         and pitlb.
 221
 222 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 223
 224         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 225         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 226         Add movq-s as 64-bit variants of movd-s.
 227
 228 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 229
 230         * hppa.h: Fix punctuation in comment.
 231
 232         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 233         implicit space-register addressing.  Set space-register bits on opcodes
 234         using implicit space-register addressing.  Add various missing pa20
 235         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 236         space-register addressing.  Use "fE" instead of "fe" in various
 237         fstw opcodes.
 238
 239 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 240
 241         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 242
 243 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 244
 245         * i386.h (i386_optab): Support Intel VMX Instructions.
 246
 247 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 248
 249         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 250
 251 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 252
 253         * i386.h (i386_optab): Add new insns.
 254
 255 2005-07-01  Nick Clifton  <nickc@redhat.com>
 256
 257         * sparc.h: Add typedefs to structure declarations.
 258
 259 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         PR 1013
 262         * i386.h (i386_optab): Update comments for 64bit addressing on
 263         mov. Allow 64bit addressing for mov and movq.
 264
 265 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 266
 267         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 268         respectively, in various floating-point load and store patterns.
 269
 270 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 271
 272         * hppa.h (FLAG_STRICT): Correct comment.
 273         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 274         PA 2.0 mneumonics when equivalent.  Entries with cache control
 275         completers now require PA 1.1.  Adjust whitespace.
 276
 277 2005-05-19  Anton Blanchard  <anton@samba.org>
 278
 279         * ppc.h (PPC_OPCODE_POWER5): Define.
 280
 281 2005-05-10  Nick Clifton  <nickc@redhat.com>
 282
 283         * Update the address and phone number of the FSF organization in
 284         the GPL notices in the following files:
 285         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 286         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 287         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 288         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 289         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 290         tic54x.h, tic80.h, v850.h, vax.h
 291
 292 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 293
 294         * i386.h (i386_optab): Add ht and hnt.
 295
 296 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 297
 298         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 299         Add xcrypt-ctr.  Provide aliases without hyphens.
 300
 301 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         Moved from ../ChangeLog
 304
 305         2005-04-12  Paul Brook  <paul@codesourcery.com>
 306         * m88k.h: Rename psr macros to avoid conflicts.
 307
 308         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 309         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 310         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 311         and ARM_ARCH_V6ZKT2.
 312
 313         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 314         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 315         Remove redundant instruction types.
 316         (struct argument): X_op - new field.
 317         (struct cst4_entry): Remove.
 318         (no_op_insn): Declare.
 319
 320         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 321         * crx.h (enum argtype): Rename types, remove unused types.
 322
 323         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 324         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 325         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 326         (enum operand_type): Rearrange operands, edit comments.
 327         replace us<N> with ui<N> for unsigned immediate.
 328         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 329         displacements (respectively).
 330         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 331         (instruction type): Add NO_TYPE_INS.
 332         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 333         (operand_entry): New field - 'flags'.
 334         (operand flags): New.
 335
 336         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 337         * crx.h (operand_type): Remove redundant types i3, i4,
 338         i5, i8, i12.
 339         Add new unsigned immediate types us3, us4, us5, us16.
 340
 341 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 342
 343         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 344         adjust them accordingly.
 345
 346 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 347
 348         * i386.h (i386_optab): Add rdtscp.
 349
 350 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 353         between memory and segment register. Allow movq for moving between
 354         general-purpose register and segment register.
 355
 356 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 357
 358         PR gas/707
 359         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 360         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 361         fnstsw.
 362
 363 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 364
 365         * m68k.h (m68008, m68ec030, m68882): Remove.
 366         (m68k_mask): New.
 367         (cpu_m68k, cpu_cf): New.
 368         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 369         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 370
 371 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 372
 373         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 374         * cgen.h (enum cgen_parse_operand_type): Add
 375         CGEN_PARSE_OPERAND_SYMBOLIC.
 376
 377 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 378
 379         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 380         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 381         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 382
 383 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 384
 385         * mips.h (struct mips_opcode): Add new pinfo2 member.
 386         (INSN_ALIAS): New define for opcode table entries that are
 387         specific instances of another entry, such as 'move' for an 'or'
 388         with a zero operand.
 389         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 390         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 391
 392 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 393
 394         * mips.h (CPU_RM9000): Define.
 395         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 396
 397 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 398
 399         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 400         to/from test registers are illegal in 64-bit mode. Add missing
 401         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 402         (previously one had to explicitly encode a rex64 prefix). Re-enable
 403         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 404         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 405
 406 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 407
 408         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 409         available only with SSE2. Change the MMX additions introduced by SSE
 410         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 411         instructions by their now designated identifier (since combining i686
 412         and 3DNow! does not really imply 3DNow!A).
 413
 414 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 415
 416         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 417         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 418
 419 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 420             Vineet Sharma      <vineets@noida.hcltech.com>
 421
 422         * maxq.h: New file: Disassembly information for the maxq port.
 423
 424 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386.h (i386_optab): Put back "movzb".
 427
 428 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 429
 430         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 431         comments.  Remove member cris_ver_sim.  Add members
 432         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 433         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 434         (struct cris_support_reg, struct cris_cond15): New types.
 435         (cris_conds15): Declare.
 436         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 437         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 438         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 439         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 440         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 441         SIZE_FIELD_UNSIGNED.
 442
 443 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 444
 445         * i386.h (sldx_Suf): Remove.
 446         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 447         (q_FP): Define, implying no REX64.
 448         (x_FP, sl_FP): Imply FloatMF.
 449         (i386_optab): Split reg and mem forms of moving from segment registers
 450         so that the memory forms can ignore the 16-/32-bit operand size
 451         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 452         all non-floating-point instructions. Unite 32- and 64-bit forms of
 453         movsx, movzx, and movd. Adjust floating point operations for the above
 454         changes to the *FP macros. Add DefaultSize to floating point control
 455         insns operating on larger memory ranges. Remove left over comments
 456         hinting at certain insns being Intel-syntax ones where the ones
 457         actually meant are already gone.
 458
 459 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 460
 461         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 462         instruction type.
 463
 464 2004-09-30  Paul Brook  <paul@codesourcery.com>
 465
 466         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 467         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 468
 469 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 470
 471         * avr.h: Add support for
 472         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 473
 474 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 475
 476         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 477
 478 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 479
 480         * msp430.h (msp430_opc): Add new instructions.
 481         (msp430_rcodes): Declare new instructions.
 482         (msp430_hcodes): Likewise..
 483
 484 2004-08-13  Nick Clifton  <nickc@redhat.com>
 485
 486         PR/301
 487         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 488         processors.
 489
 490 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 491
 492         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 493
 494 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 497
 498 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 499
 500         * i386.h: Adjust instruction descriptions to better match the
 501         specification.
 502
 503 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 504
 505         * arm.h: Remove all old content.  Replace with architecture defines
 506         from gas/config/tc-arm.c.
 507
 508 2004-07-09  Andreas Schwab  <schwab@suse.de>
 509
 510         * m68k.h: Fix comment.
 511
 512 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 513
 514         * crx.h: New file.
 515
 516 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 517
 518         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 519
 520 2004-05-24  Peter Barada  <peter@the-baradas.com>
 521
 522         * m68k.h: Add 'size' to m68k_opcode.
 523
 524 2004-05-05  Peter Barada  <peter@the-baradas.com>
 525
 526         * m68k.h: Switch from ColdFire chip name to core variant.
 527
 528 2004-04-22  Peter Barada  <peter@the-baradas.com>
 529
 530         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 531         descriptions for new EMAC cases.
 532         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 533         handle Motorola MAC syntax.
 534         Allow disassembly of ColdFire V4e object files.
 535
 536 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 537
 538         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 539
 540 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 541
 542         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 543
 544 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 545
 546         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 547
 548 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 549
 550         * i386.h (i386_optab): Added xstore/xcrypt insns.
 551
 552 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 553
 554         * h8300.h (32bit ldc/stc): Add relaxing support.
 555
 556 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 557
 558         * h8300.h (BITOP): Pass MEMRELAX flag.
 559
 560 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 561
 562         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 563         except for the H8S.
 564
 565 For older changes see ChangeLog-9103
 566 \f
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 568 mode: change-log
 569 left-margin: 8
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