include/opcode/ChangeLog

   1 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
   2
   3         PR gas/12296
   4         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
   5
   6 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
   7
   8         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
   9         New instruction set flags.
  10         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
  11
  12 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
  13
  14         * mips.h (M_PREF_AB): New enum value.
  15
  16 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
  17
  18         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
  19         M_IU): Define.
  20         (is_macmod_pmove, is_macmod_hmove): New functions.
  21
  22 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
  23
  24         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
  25
  26 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
  27
  28         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
  29         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
  30
  31 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  32
  33         PR gas/11395
  34         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
  35         "bb" entries.
  36
  37 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  38
  39         PR gas/11395
  40         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
  41
  42 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
  43
  44         * mips.h: Update commentary after last commit.
  45
  46 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
  47
  48         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
  49         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
  50         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
  51
  52 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
  53
  54         * mips.h: Fix previous commit.
  55
  56 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
  57
  58         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
  59         (INSN_LOONGSON_3A): Clear bit 31.
  60
  61 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  62
  63         PR gas/12198
  64         * arm.h (ARM_AEXT_V6M_ONLY): New define.
  65         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
  66         (ARM_ARCH_V6M_ONLY): New define.
  67
  68 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
  69
  70         * mips.h (INSN_LOONGSON_3A): Defined.
  71         (CPU_LOONGSON_3A): Defined.
  72         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
  73
  74 2010-10-09  Matt Rice  <ratmice@gmail.com>
  75
  76         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
  77         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
  78
  79 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  80
  81         * arm.h (ARM_EXT_VIRT): New define.
  82         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
  83         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
  84         Extensions.
  85
  86 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  87
  88         * arm.h (ARM_AEXT_ADIV): New define.
  89         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
  90
  91 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  92
  93         * arm.h (ARM_EXT_OS): New define.
  94         (ARM_AEXT_V6SM): Likewise.
  95         (ARM_ARCH_V6SM): Likewise.
  96
  97 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  98
  99         * arm.h (ARM_EXT_MP): Add.
 100         (ARM_ARCH_V7A_MP): Likewise.
 101
 102 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 103
 104         * bfin.h: Declare pseudoChr structs/defines.
 105
 106 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 107
 108         * bfin.h: Strip trailing whitespace.
 109
 110 2010-07-29  DJ Delorie  <dj@redhat.com>
 111
 112         * rx.h (RX_Operand_Type): Add TwoReg.
 113         (RX_Opcode_ID): Remove ediv and ediv2.
 114
 115 2010-07-27  DJ Delorie  <dj@redhat.com>
 116
 117         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 118
 119 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 120             Ina Pandit  <ina.pandit@kpitcummins.com>
 121
 122         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 123         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 124         PROCESSOR_V850E2_ALL.
 125         Remove PROCESSOR_V850EA support.
 126         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 127         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 128         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 129         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 130         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 131         V850_OPERAND_PERCENT.
 132         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 133         V850_NOT_R0.
 134         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 135         and V850E_PUSH_POP
 136
 137 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 138
 139         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 140         (MIPS16_INSN_BRANCH): Rename to...
 141         (MIPS16_INSN_COND_BRANCH): ... this.
 142
 143 2010-07-03  Alan Modra  <amodra@gmail.com>
 144
 145         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 146         Renumber other PPC_OPCODE defines.
 147
 148 2010-07-03  Alan Modra  <amodra@gmail.com>
 149
 150         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 151
 152 2010-06-29  Alan Modra  <amodra@gmail.com>
 153
 154         * maxq.h: Delete file.
 155
 156 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 157
 158         * ppc.h (PPC_OPCODE_E500): Define.
 159
 160 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 161
 162         * opcode/mips.h (INSN_MIPS16): Remove.
 163
 164 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 165
 166         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 167
 168 2010-04-15  Nick Clifton  <nickc@redhat.com>
 169
 170         * alpha.h: Update copyright notice to use GPLv3.
 171         * arc.h: Likewise.
 172         * arm.h: Likewise.
 173         * avr.h: Likewise.
 174         * bfin.h: Likewise.
 175         * cgen.h: Likewise.
 176         * convex.h: Likewise.
 177         * cr16.h: Likewise.
 178         * cris.h: Likewise.
 179         * crx.h: Likewise.
 180         * d10v.h: Likewise.
 181         * d30v.h: Likewise.
 182         * dlx.h: Likewise.
 183         * h8300.h: Likewise.
 184         * hppa.h: Likewise.
 185         * i370.h: Likewise.
 186         * i386.h: Likewise.
 187         * i860.h: Likewise.
 188         * i960.h: Likewise.
 189         * ia64.h: Likewise.
 190         * m68hc11.h: Likewise.
 191         * m68k.h: Likewise.
 192         * m88k.h: Likewise.
 193         * maxq.h: Likewise.
 194         * mips.h: Likewise.
 195         * mmix.h: Likewise.
 196         * mn10200.h: Likewise.
 197         * mn10300.h: Likewise.
 198         * msp430.h: Likewise.
 199         * np1.h: Likewise.
 200         * ns32k.h: Likewise.
 201         * or32.h: Likewise.
 202         * pdp11.h: Likewise.
 203         * pj.h: Likewise.
 204         * pn.h: Likewise.
 205         * ppc.h: Likewise.
 206         * pyr.h: Likewise.
 207         * rx.h: Likewise.
 208         * s390.h: Likewise.
 209         * score-datadep.h: Likewise.
 210         * score-inst.h: Likewise.
 211         * sparc.h: Likewise.
 212         * spu-insns.h: Likewise.
 213         * spu.h: Likewise.
 214         * tic30.h: Likewise.
 215         * tic4x.h: Likewise.
 216         * tic54x.h: Likewise.
 217         * tic80.h: Likewise.
 218         * v850.h: Likewise.
 219         * vax.h: Likewise.
 220
 221 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 222
 223         * tic6x-control-registers.h, tic6x-insn-formats.h,
 224         tic6x-opcode-table.h, tic6x.h: New.
 225
 226 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 227
 228         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 229
 230 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 231
 232         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 233
 234 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * ia64.h (ia64_find_opcode): Remove argument name.
 237         (ia64_find_next_opcode): Likewise.
 238         (ia64_dis_opcode): Likewise.
 239         (ia64_free_opcode): Likewise.
 240         (ia64_find_dependency): Likewise.
 241
 242 2009-11-22  Doug Evans  <dje@sebabeach.org>
 243
 244         * cgen.h: Include bfd_stdint.h.
 245         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 246
 247 2009-11-18  Paul Brook  <paul@codesourcery.com>
 248
 249         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 250
 251 2009-11-17  Paul Brook  <paul@codesourcery.com>
 252         Daniel Jacobowitz  <dan@codesourcery.com>
 253
 254         * arm.h (ARM_EXT_V6_DSP): Define.
 255         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 256         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 257
 258 2009-11-04  DJ Delorie  <dj@redhat.com>
 259
 260         * rx.h (rx_decode_opcode) (mvtipl): Add.
 261         (mvtcp, mvfcp, opecp): Remove.
 262
 263 2009-11-02  Paul Brook  <paul@codesourcery.com>
 264
 265         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 266         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 267         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 268         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 269         FPU_ARCH_NEON_VFP_V4): Define.
 270
 271 2009-10-23  Doug Evans  <dje@sebabeach.org>
 272
 273         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 274         * cgen.h: Update.  Improve multi-inclusion macro name.
 275
 276 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 277
 278         * ppc.h (PPC_OPCODE_476): Define.
 279
 280 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 281
 282         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 283
 284 2009-09-29  DJ Delorie  <dj@redhat.com>
 285
 286         * rx.h: New file.
 287
 288 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 289
 290         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 291
 292 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 293
 294         * ppc.h (PPC_OPCODE_PPCA2): New.
 295
 296 2009-09-05  Martin Thuresson  <martin@mtme.org>
 297
 298         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 299
 300 2009-08-29  Martin Thuresson  <martin@mtme.org>
 301
 302         * tic30.h (template): Rename type template to
 303         insn_template. Updated code to use new name.
 304         * tic54x.h (template): Rename type template to
 305         insn_template.
 306
 307 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 308
 309         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 310
 311 2009-06-11  Anthony Green  <green@moxielogic.com>
 312
 313         * moxie.h (MOXIE_F3_PCREL): Define.
 314         (moxie_form3_opc_info): Grow.
 315
 316 2009-06-06  Anthony Green  <green@moxielogic.com>
 317
 318         * moxie.h (MOXIE_F1_M): Define.
 319
 320 2009-04-15  Anthony Green  <green@moxielogic.com>
 321
 322         * moxie.h: Created.
 323
 324 2009-04-06  DJ Delorie  <dj@redhat.com>
 325
 326         * h8300.h: Add relaxation attributes to MOVA opcodes.
 327
 328 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 329
 330         * ppc.h (ppc_parse_cpu): Declare.
 331
 332 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 333
 334         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 335         and _IMM11 for mbitclr and mbitset.
 336         * score-datadep.h: Update dependency information.
 337
 338 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 339
 340         * ppc.h (PPC_OPCODE_POWER7): New.
 341
 342 2009-02-06  Doug Evans  <dje@google.com>
 343
 344         * i386.h: Add comment regarding sse* insns and prefixes.
 345
 346 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 347
 348         * mips.h (INSN_XLR): Define.
 349         (INSN_CHIP_MASK): Update.
 350         (CPU_XLR): Define.
 351         (OPCODE_IS_MEMBER): Update.
 352         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 353
 354 2009-01-28  Doug Evans  <dje@google.com>
 355
 356         * opcode/i386.h: Add multiple inclusion protection.
 357         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 358         (EDI_REG_NUM): New macros.
 359         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 360         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 361         (REX_PREFIX_P): New macro.
 362
 363 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 364
 365         * ppc.h (struct powerpc_opcode): New field "deprecated".
 366         (PPC_OPCODE_NOPOWER4): Delete.
 367
 368 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 369
 370         * mips.h: Define CPU_R14000, CPU_R16000.
 371         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 372
 373 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 374
 375         * arm.h (FPU_NEON_FP16): New.
 376         (FPU_ARCH_NEON_FP16): New.
 377
 378 2008-11-06  Chao-ying Fu  <fu@mips.com>
 379
 380         * mips.h: Doucument '1' for 5-bit sync type.
 381
 382 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 385         IA64_RS_CR.
 386
 387 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 388
 389         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 390
 391 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 392
 393         * ppc.h (PPC_OPCODE_405): Define.
 394         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 395
 396 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 397
 398         * ppc.h (ppc_cpu_t): New typedef.
 399         (struct powerpc_opcode <flags>): Use it.
 400         (struct powerpc_operand <insert, extract>): Likewise.
 401         (struct powerpc_macro <flags>): Likewise.
 402
 403 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 404
 405         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 406         Update comment before MIPS16 field descriptors to mention MIPS16.
 407         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 408         BBIT.
 409         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 410         New bit masks and shift counts for cins and exts.
 411
 412         * mips.h: Document new field descriptors +Q.
 413         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 414
 415 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 416
 417         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 418         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 419
 420 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 421
 422         * ppc.h: (PPC_OPCODE_E500MC): New.
 423
 424 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386.h (MAX_OPERANDS): Set to 5.
 427         (MAX_MNEM_SIZE): Changed to 20.
 428
 429 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 430
 431         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 432
 433 2008-03-09  Paul Brook  <paul@codesourcery.com>
 434
 435         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 436
 437 2008-03-04  Paul Brook  <paul@codesourcery.com>
 438
 439         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 440         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 441         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 442
 443 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 444             Nick Clifton  <nickc@redhat.com>
 445
 446         PR 3134
 447         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 448         with a 32-bit displacement but without the top bit of the 4th byte
 449         set.
 450
 451 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 452
 453         * cr16.h (cr16_num_optab): Declared.
 454
 455 2008-02-14  Hakan Ardo  <hakan@debian.org>
 456
 457         PR gas/2626
 458         * avr.h (AVR_ISA_2xxe): Define.
 459
 460 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 461
 462         * mips.h: Update copyright.
 463         (INSN_CHIP_MASK): New macro.
 464         (INSN_OCTEON): New macro.
 465         (CPU_OCTEON): New macro.
 466         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 467
 468 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 469
 470         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 471
 472 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 473
 474         * avr.h (AVR_ISA_USB162): Add new opcode set.
 475         (AVR_ISA_AVR3): Likewise.
 476
 477 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 478
 479         * mips.h (INSN_LOONGSON_2E): New.
 480         (INSN_LOONGSON_2F): New.
 481         (CPU_LOONGSON_2E): New.
 482         (CPU_LOONGSON_2F): New.
 483         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 484
 485 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 486
 487         * mips.h (INSN_ISA*): Redefine certain values as an
 488         enumeration.  Update comments.
 489         (mips_isa_table): New.
 490         (ISA_MIPS*): Redefine to match enumeration.
 491         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 492         values.
 493
 494 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 495
 496         * ppc.h (PPC_OPCODE_PPCPS): New.
 497
 498 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 499
 500         * m68k.h: Document j K & E.
 501
 502 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 503
 504         * cr16.h: New file for CR16 target.
 505
 506 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 507
 508         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 509
 510 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 511
 512         * m68k.h (mcfisa_c): New.
 513         (mcfusp, mcf_mask): Adjust.
 514
 515 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 516
 517         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 518         (num_powerpc_operands): Declare.
 519         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 520         (PPC_OPERAND_PLUS1): Define.
 521
 522 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         * i386.h (REX_MODE64): Renamed to ...
 525         (REX_W): This.
 526         (REX_EXTX): Renamed to ...
 527         (REX_R): This.
 528         (REX_EXTY): Renamed to ...
 529         (REX_X): This.
 530         (REX_EXTZ): Renamed to ...
 531         (REX_B): This.
 532
 533 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 534
 535         * i386.h: Add entries from config/tc-i386.h and move tables
 536         to opcodes/i386-opc.h.
 537
 538 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         * i386.h (FloatDR): Removed.
 541         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 542
 543 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 544
 545         * spu-insns.h: Add soma double-float insns.
 546
 547 2007-02-20  Thiemo Seufer  <ths@mips.com>
 548             Chao-Ying Fu  <fu@mips.com>
 549
 550         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 551         (INSN_DSPR2): Add flag for DSP R2 instructions.
 552         (M_BALIGN): New macro.
 553
 554 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 555
 556         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 557         and Seg3ShortFrom with Shortform.
 558
 559 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         PR gas/4027
 562         * i386.h (i386_optab): Put the real "test" before the pseudo
 563         one.
 564
 565 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 566
 567         * m68k.h (m68010up): OR fido_a.
 568
 569 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 570
 571         * m68k.h (fido_a): New.
 572
 573 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 574
 575         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 576         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 577         values.
 578
 579 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 582
 583 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 584
 585         * score-inst.h (enum score_insn_type): Add Insn_internal.
 586
 587 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 588             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 589             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 590             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 591             Alan Modra  <amodra@bigpond.net.au>
 592
 593         * spu-insns.h: New file.
 594         * spu.h: New file.
 595
 596 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 597
 598         * ppc.h (PPC_OPCODE_CELL): Define.
 599
 600 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 601
 602         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 603         in amdfam10 architecture.
 604
 605 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         * i386.h: Replace CpuMNI with CpuSSSE3.
 608
 609 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 610             Joseph Myers  <joseph@codesourcery.com>
 611             Ian Lance Taylor  <ian@wasabisystems.com>
 612             Ben Elliston  <bje@wasabisystems.com>
 613
 614         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 615
 616 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 617
 618         * score-datadep.h: New file.
 619         * score-inst.h: New file.
 620
 621 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 624         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 625         movdq2q and movq2dq.
 626
 627 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 628            Michael Meissner             <michael.meissner@amd.com>
 629
 630         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 631
 632 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         * i386.h (i386_optab): Add "nop" with memory reference.
 635
 636 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 637
 638         * i386.h (i386_optab): Update comment for 64bit NOP.
 639
 640 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 641             Anton Blanchard  <anton@samba.org>
 642
 643         * ppc.h (PPC_OPCODE_POWER6): Define.
 644         Adjust whitespace.
 645
 646 2006-06-05  Thiemo Seufer  <ths@mips.com>
 647
 648         * mips.h: Improve description of MT flags.
 649
 650 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 651
 652         * m68k.h (mcf_mask): Define.
 653
 654 2006-05-05  Thiemo Seufer  <ths@mips.com>
 655             David Ung  <davidu@mips.com>
 656
 657         * mips.h (enum): Add macro M_CACHE_AB.
 658
 659 2006-05-04  Thiemo Seufer  <ths@mips.com>
 660             Nigel Stephens  <nigel@mips.com>
 661             David Ung  <davidu@mips.com>
 662
 663         * mips.h: Add INSN_SMARTMIPS define.
 664
 665 2006-04-30  Thiemo Seufer  <ths@mips.com>
 666             David Ung  <davidu@mips.com>
 667
 668         * mips.h: Defines udi bits and masks.  Add description of
 669         characters which may appear in the args field of udi
 670         instructions.
 671
 672 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 673
 674         * mips.h: Improve comments describing the bitfield instruction
 675         fields.
 676
 677 2006-04-26  Julian Brown  <julian@codesourcery.com>
 678
 679         * arm.h (FPU_VFP_EXT_V3): Define constant.
 680         (FPU_NEON_EXT_V1): Likewise.
 681         (FPU_VFP_HARD): Update.
 682         (FPU_VFP_V3): Define macro.
 683         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 684
 685 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 686
 687         * avr.h (AVR_ISA_PWMx): New.
 688
 689 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 690
 691         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 692         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 693         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 694         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 695         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 696
 697 2006-03-10  Paul Brook  <paul@codesourcery.com>
 698
 699         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 700
 701 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 702
 703         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 704         first.  Correct mask of bb "B" opcode.
 705
 706 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 707
 708         * i386.h (i386_optab): Support Intel Merom New Instructions.
 709
 710 2006-02-24  Paul Brook  <paul@codesourcery.com>
 711
 712         * arm.h: Add V7 feature bits.
 713
 714 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 717
 718 2006-01-31  Paul Brook  <paul@codesourcery.com>
 719         Richard Earnshaw <rearnsha@arm.com>
 720
 721         * arm.h: Use ARM_CPU_FEATURE.
 722         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 723         (arm_feature_set): Change to a structure.
 724         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 725         ARM_FEATURE): New macros.
 726
 727 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 728
 729         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 730         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 731         (ADD_PC_INCR_OPCODE): Don't define.
 732
 733 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 734
 735         PR gas/1874
 736         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 737
 738 2005-11-14  David Ung  <davidu@mips.com>
 739
 740         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 741         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 742         save/restore encoding of the args field.
 743
 744 2005-10-28  Dave Brolley  <brolley@redhat.com>
 745
 746         Contribute the following changes:
 747         2005-02-16  Dave Brolley  <brolley@redhat.com>
 748
 749         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 750         cgen_isa_mask_* to cgen_bitset_*.
 751         * cgen.h: Likewise.
 752
 753         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 754
 755         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 756         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 757         (CGEN_CPU_TABLE): Make isas a ponter.
 758
 759         2003-09-29  Dave Brolley  <brolley@redhat.com>
 760
 761         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 762         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 763         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 764
 765         2002-12-13  Dave Brolley  <brolley@redhat.com>
 766
 767         * cgen.h (symcat.h): #include it.
 768         (cgen-bitset.h): #include it.
 769         (CGEN_ATTR_VALUE_TYPE): Now a union.
 770         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 771         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 772         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 773         * cgen-bitset.h: New file.
 774
 775 2005-09-30  Catherine Moore  <clm@cm00re.com>
 776
 777         * bfin.h: New file.
 778
 779 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 780
 781         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 782         indirect operands.
 783
 784 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 785
 786         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 787         Add FLAG_STRICT to pa10 ftest opcode.
 788
 789 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 790
 791         * hppa.h (pa_opcodes): Remove lha entries.
 792
 793 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 794
 795         * hppa.h (FLAG_STRICT): Revise comment.
 796         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 797         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 798         entries for "fdc".
 799
 800 2005-09-30  Catherine Moore  <clm@cm00re.com>
 801
 802         * bfin.h: New file.
 803
 804 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 805
 806         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 807
 808 2005-09-06  Chao-ying Fu  <fu@mips.com>
 809
 810         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 811         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 812         define.
 813         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 814         (INSN_ASE_MASK): Update to include INSN_MT.
 815         (INSN_MT): New define for MT ASE.
 816
 817 2005-08-25  Chao-ying Fu  <fu@mips.com>
 818
 819         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 820         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 821         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 822         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 823         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 824         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 825         instructions.
 826         (INSN_DSP): New define for DSP ASE.
 827
 828 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 829
 830         * a29k.h: Delete.
 831
 832 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 833
 834         * ppc.h (PPC_OPCODE_E300): Define.
 835
 836 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 837
 838         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 839
 840 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 841
 842         PR gas/336
 843         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 844         and pitlb.
 845
 846 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 847
 848         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 849         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 850         Add movq-s as 64-bit variants of movd-s.
 851
 852 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 853
 854         * hppa.h: Fix punctuation in comment.
 855
 856         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 857         implicit space-register addressing.  Set space-register bits on opcodes
 858         using implicit space-register addressing.  Add various missing pa20
 859         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 860         space-register addressing.  Use "fE" instead of "fe" in various
 861         fstw opcodes.
 862
 863 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 864
 865         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 866
 867 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 868
 869         * i386.h (i386_optab): Support Intel VMX Instructions.
 870
 871 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 872
 873         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 874
 875 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 876
 877         * i386.h (i386_optab): Add new insns.
 878
 879 2005-07-01  Nick Clifton  <nickc@redhat.com>
 880
 881         * sparc.h: Add typedefs to structure declarations.
 882
 883 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         PR 1013
 886         * i386.h (i386_optab): Update comments for 64bit addressing on
 887         mov. Allow 64bit addressing for mov and movq.
 888
 889 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 890
 891         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 892         respectively, in various floating-point load and store patterns.
 893
 894 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 895
 896         * hppa.h (FLAG_STRICT): Correct comment.
 897         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 898         PA 2.0 mneumonics when equivalent.  Entries with cache control
 899         completers now require PA 1.1.  Adjust whitespace.
 900
 901 2005-05-19  Anton Blanchard  <anton@samba.org>
 902
 903         * ppc.h (PPC_OPCODE_POWER5): Define.
 904
 905 2005-05-10  Nick Clifton  <nickc@redhat.com>
 906
 907         * Update the address and phone number of the FSF organization in
 908         the GPL notices in the following files:
 909         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 910         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 911         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 912         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 913         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 914         tic54x.h, tic80.h, v850.h, vax.h
 915
 916 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 917
 918         * i386.h (i386_optab): Add ht and hnt.
 919
 920 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 921
 922         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 923         Add xcrypt-ctr.  Provide aliases without hyphens.
 924
 925 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         Moved from ../ChangeLog
 928
 929         2005-04-12  Paul Brook  <paul@codesourcery.com>
 930         * m88k.h: Rename psr macros to avoid conflicts.
 931
 932         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 933         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 934         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 935         and ARM_ARCH_V6ZKT2.
 936
 937         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 938         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 939         Remove redundant instruction types.
 940         (struct argument): X_op - new field.
 941         (struct cst4_entry): Remove.
 942         (no_op_insn): Declare.
 943
 944         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 945         * crx.h (enum argtype): Rename types, remove unused types.
 946
 947         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 948         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 949         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 950         (enum operand_type): Rearrange operands, edit comments.
 951         replace us<N> with ui<N> for unsigned immediate.
 952         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 953         displacements (respectively).
 954         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 955         (instruction type): Add NO_TYPE_INS.
 956         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 957         (operand_entry): New field - 'flags'.
 958         (operand flags): New.
 959
 960         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 961         * crx.h (operand_type): Remove redundant types i3, i4,
 962         i5, i8, i12.
 963         Add new unsigned immediate types us3, us4, us5, us16.
 964
 965 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 966
 967         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 968         adjust them accordingly.
 969
 970 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 971
 972         * i386.h (i386_optab): Add rdtscp.
 973
 974 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 975
 976         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 977         between memory and segment register. Allow movq for moving between
 978         general-purpose register and segment register.
 979
 980 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 981
 982         PR gas/707
 983         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 984         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 985         fnstsw.
 986
 987 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 988
 989         * m68k.h (m68008, m68ec030, m68882): Remove.
 990         (m68k_mask): New.
 991         (cpu_m68k, cpu_cf): New.
 992         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 993         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 994
 995 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 996
 997         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 998         * cgen.h (enum cgen_parse_operand_type): Add
 999         CGEN_PARSE_OPERAND_SYMBOLIC.
1000
1001 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1002
1003         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1004         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1005         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1006
1007 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1008
1009         * mips.h (struct mips_opcode): Add new pinfo2 member.
1010         (INSN_ALIAS): New define for opcode table entries that are
1011         specific instances of another entry, such as 'move' for an 'or'
1012         with a zero operand.
1013         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1014         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1015
1016 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1017
1018         * mips.h (CPU_RM9000): Define.
1019         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1020
1021 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1022
1023         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1024         to/from test registers are illegal in 64-bit mode. Add missing
1025         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1026         (previously one had to explicitly encode a rex64 prefix). Re-enable
1027         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1028         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1029
1030 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1031
1032         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1033         available only with SSE2. Change the MMX additions introduced by SSE
1034         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1035         instructions by their now designated identifier (since combining i686
1036         and 3DNow! does not really imply 3DNow!A).
1037
1038 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1039
1040         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1041         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1042
1043 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1044             Vineet Sharma      <vineets@noida.hcltech.com>
1045
1046         * maxq.h: New file: Disassembly information for the maxq port.
1047
1048 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1049
1050         * i386.h (i386_optab): Put back "movzb".
1051
1052 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1053
1054         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1055         comments.  Remove member cris_ver_sim.  Add members
1056         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1057         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1058         (struct cris_support_reg, struct cris_cond15): New types.
1059         (cris_conds15): Declare.
1060         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1061         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1062         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1063         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1064         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1065         SIZE_FIELD_UNSIGNED.
1066
1067 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1068
1069         * i386.h (sldx_Suf): Remove.
1070         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1071         (q_FP): Define, implying no REX64.
1072         (x_FP, sl_FP): Imply FloatMF.
1073         (i386_optab): Split reg and mem forms of moving from segment registers
1074         so that the memory forms can ignore the 16-/32-bit operand size
1075         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1076         all non-floating-point instructions. Unite 32- and 64-bit forms of
1077         movsx, movzx, and movd. Adjust floating point operations for the above
1078         changes to the *FP macros. Add DefaultSize to floating point control
1079         insns operating on larger memory ranges. Remove left over comments
1080         hinting at certain insns being Intel-syntax ones where the ones
1081         actually meant are already gone.
1082
1083 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1084
1085         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1086         instruction type.
1087
1088 2004-09-30  Paul Brook  <paul@codesourcery.com>
1089
1090         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1091         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1092
1093 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1094
1095         * avr.h: Add support for
1096         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1097
1098 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1099
1100         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1101
1102 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1103
1104         * msp430.h (msp430_opc): Add new instructions.
1105         (msp430_rcodes): Declare new instructions.
1106         (msp430_hcodes): Likewise..
1107
1108 2004-08-13  Nick Clifton  <nickc@redhat.com>
1109
1110         PR/301
1111         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1112         processors.
1113
1114 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1115
1116         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1117
1118 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1121
1122 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1123
1124         * i386.h: Adjust instruction descriptions to better match the
1125         specification.
1126
1127 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1128
1129         * arm.h: Remove all old content.  Replace with architecture defines
1130         from gas/config/tc-arm.c.
1131
1132 2004-07-09  Andreas Schwab  <schwab@suse.de>
1133
1134         * m68k.h: Fix comment.
1135
1136 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1137
1138         * crx.h: New file.
1139
1140 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1141
1142         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1143
1144 2004-05-24  Peter Barada  <peter@the-baradas.com>
1145
1146         * m68k.h: Add 'size' to m68k_opcode.
1147
1148 2004-05-05  Peter Barada  <peter@the-baradas.com>
1149
1150         * m68k.h: Switch from ColdFire chip name to core variant.
1151
1152 2004-04-22  Peter Barada  <peter@the-baradas.com>
1153
1154         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1155         descriptions for new EMAC cases.
1156         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1157         handle Motorola MAC syntax.
1158         Allow disassembly of ColdFire V4e object files.
1159
1160 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1161
1162         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1163
1164 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1165
1166         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1167
1168 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1169
1170         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1171
1172 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1173
1174         * i386.h (i386_optab): Added xstore/xcrypt insns.
1175
1176 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1177
1178         * h8300.h (32bit ldc/stc): Add relaxing support.
1179
1180 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1181
1182         * h8300.h (BITOP): Pass MEMRELAX flag.
1183
1184 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1185
1186         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1187         except for the H8S.
1188
1189 For older changes see ChangeLog-9103
1190 \f
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1192 mode: change-log
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