1 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
3 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
4 a duplicate of AVR_ISA_SPM.
6 2011-07-01 Nick Clifton <nickc@redhat.com>
8 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
10 2011-06-18 Robin Getz <robin.getz@analog.com>
12 * bfin.h (is_macmod_signed): New func
14 2011-06-18 Mike Frysinger <vapier@gentoo.org>
16 * bfin.h (is_macmod_pmove): Add missing space before func args.
17 (is_macmod_hmove): Likewise.
19 2011-06-13 Walter Lee <walt@tilera.com>
22 * tilepro.h: New file.
24 2011-05-31 Paul Brook <paul@codesourcery.com>
26 * arm.h (ARM_ARCH_V7R_IDIV): Define.
28 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
30 * s390.h: Replace S390_OPERAND_REG_EVEN with
31 S390_OPERAND_REG_PAIR.
33 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
35 * s390.h: Add S390_OPCODE_REG_EVEN flag.
37 2011-04-18 Julian Brown <julian@codesourcery.com>
39 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
41 2011-04-11 Dan McDonald <dan@wellkeeper.com>
44 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
46 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
48 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
49 New instruction set flags.
50 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
52 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
54 * mips.h (M_PREF_AB): New enum value.
56 2011-02-12 Mike Frysinger <vapier@gentoo.org>
58 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
60 (is_macmod_pmove, is_macmod_hmove): New functions.
62 2011-02-11 Mike Frysinger <vapier@gentoo.org>
64 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
66 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
68 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
69 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
71 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
74 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
77 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
80 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
82 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
84 * mips.h: Update commentary after last commit.
86 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
88 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
89 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
90 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
92 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
94 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
96 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
98 * mips.h: Fix previous commit.
100 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
102 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
103 (INSN_LOONGSON_3A): Clear bit 31.
105 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
108 * arm.h (ARM_AEXT_V6M_ONLY): New define.
109 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
110 (ARM_ARCH_V6M_ONLY): New define.
112 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
114 * mips.h (INSN_LOONGSON_3A): Defined.
115 (CPU_LOONGSON_3A): Defined.
116 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
118 2010-10-09 Matt Rice <ratmice@gmail.com>
120 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
121 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
123 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
125 * arm.h (ARM_EXT_VIRT): New define.
126 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
127 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
130 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
132 * arm.h (ARM_AEXT_ADIV): New define.
133 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
135 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
137 * arm.h (ARM_EXT_OS): New define.
138 (ARM_AEXT_V6SM): Likewise.
139 (ARM_ARCH_V6SM): Likewise.
141 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
143 * arm.h (ARM_EXT_MP): Add.
144 (ARM_ARCH_V7A_MP): Likewise.
146 2010-09-22 Mike Frysinger <vapier@gentoo.org>
148 * bfin.h: Declare pseudoChr structs/defines.
150 2010-09-21 Mike Frysinger <vapier@gentoo.org>
152 * bfin.h: Strip trailing whitespace.
154 2010-07-29 DJ Delorie <dj@redhat.com>
156 * rx.h (RX_Operand_Type): Add TwoReg.
157 (RX_Opcode_ID): Remove ediv and ediv2.
159 2010-07-27 DJ Delorie <dj@redhat.com>
161 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
163 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
164 Ina Pandit <ina.pandit@kpitcummins.com>
166 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
167 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
168 PROCESSOR_V850E2_ALL.
169 Remove PROCESSOR_V850EA support.
170 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
171 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
172 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
173 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
174 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
175 V850_OPERAND_PERCENT.
176 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
178 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
181 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
183 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
184 (MIPS16_INSN_BRANCH): Rename to...
185 (MIPS16_INSN_COND_BRANCH): ... this.
187 2010-07-03 Alan Modra <amodra@gmail.com>
189 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
190 Renumber other PPC_OPCODE defines.
192 2010-07-03 Alan Modra <amodra@gmail.com>
194 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
196 2010-06-29 Alan Modra <amodra@gmail.com>
198 * maxq.h: Delete file.
200 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
202 * ppc.h (PPC_OPCODE_E500): Define.
204 2010-05-26 Catherine Moore <clm@codesourcery.com>
206 * opcode/mips.h (INSN_MIPS16): Remove.
208 2010-04-21 Joseph Myers <joseph@codesourcery.com>
210 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
212 2010-04-15 Nick Clifton <nickc@redhat.com>
214 * alpha.h: Update copyright notice to use GPLv3.
220 * convex.h: Likewise.
234 * m68hc11.h: Likewise.
240 * mn10200.h: Likewise.
241 * mn10300.h: Likewise.
242 * msp430.h: Likewise.
253 * score-datadep.h: Likewise.
254 * score-inst.h: Likewise.
256 * spu-insns.h: Likewise.
260 * tic54x.h: Likewise.
265 2010-03-25 Joseph Myers <joseph@codesourcery.com>
267 * tic6x-control-registers.h, tic6x-insn-formats.h,
268 tic6x-opcode-table.h, tic6x.h: New.
270 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
272 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
274 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
276 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
278 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
280 * ia64.h (ia64_find_opcode): Remove argument name.
281 (ia64_find_next_opcode): Likewise.
282 (ia64_dis_opcode): Likewise.
283 (ia64_free_opcode): Likewise.
284 (ia64_find_dependency): Likewise.
286 2009-11-22 Doug Evans <dje@sebabeach.org>
288 * cgen.h: Include bfd_stdint.h.
289 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
291 2009-11-18 Paul Brook <paul@codesourcery.com>
293 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
295 2009-11-17 Paul Brook <paul@codesourcery.com>
296 Daniel Jacobowitz <dan@codesourcery.com>
298 * arm.h (ARM_EXT_V6_DSP): Define.
299 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
300 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
302 2009-11-04 DJ Delorie <dj@redhat.com>
304 * rx.h (rx_decode_opcode) (mvtipl): Add.
305 (mvtcp, mvfcp, opecp): Remove.
307 2009-11-02 Paul Brook <paul@codesourcery.com>
309 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
310 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
311 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
312 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
313 FPU_ARCH_NEON_VFP_V4): Define.
315 2009-10-23 Doug Evans <dje@sebabeach.org>
317 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
318 * cgen.h: Update. Improve multi-inclusion macro name.
320 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
322 * ppc.h (PPC_OPCODE_476): Define.
324 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
326 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
328 2009-09-29 DJ Delorie <dj@redhat.com>
332 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
334 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
336 2009-09-21 Ben Elliston <bje@au.ibm.com>
338 * ppc.h (PPC_OPCODE_PPCA2): New.
340 2009-09-05 Martin Thuresson <martin@mtme.org>
342 * ia64.h (struct ia64_operand): Renamed member class to op_class.
344 2009-08-29 Martin Thuresson <martin@mtme.org>
346 * tic30.h (template): Rename type template to
347 insn_template. Updated code to use new name.
348 * tic54x.h (template): Rename type template to
351 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
353 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
355 2009-06-11 Anthony Green <green@moxielogic.com>
357 * moxie.h (MOXIE_F3_PCREL): Define.
358 (moxie_form3_opc_info): Grow.
360 2009-06-06 Anthony Green <green@moxielogic.com>
362 * moxie.h (MOXIE_F1_M): Define.
364 2009-04-15 Anthony Green <green@moxielogic.com>
368 2009-04-06 DJ Delorie <dj@redhat.com>
370 * h8300.h: Add relaxation attributes to MOVA opcodes.
372 2009-03-10 Alan Modra <amodra@bigpond.net.au>
374 * ppc.h (ppc_parse_cpu): Declare.
376 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
378 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
379 and _IMM11 for mbitclr and mbitset.
380 * score-datadep.h: Update dependency information.
382 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
384 * ppc.h (PPC_OPCODE_POWER7): New.
386 2009-02-06 Doug Evans <dje@google.com>
388 * i386.h: Add comment regarding sse* insns and prefixes.
390 2009-02-03 Sandip Matte <sandip@rmicorp.com>
392 * mips.h (INSN_XLR): Define.
393 (INSN_CHIP_MASK): Update.
395 (OPCODE_IS_MEMBER): Update.
396 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
398 2009-01-28 Doug Evans <dje@google.com>
400 * opcode/i386.h: Add multiple inclusion protection.
401 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
402 (EDI_REG_NUM): New macros.
403 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
404 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
405 (REX_PREFIX_P): New macro.
407 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
409 * ppc.h (struct powerpc_opcode): New field "deprecated".
410 (PPC_OPCODE_NOPOWER4): Delete.
412 2008-11-28 Joshua Kinard <kumba@gentoo.org>
414 * mips.h: Define CPU_R14000, CPU_R16000.
415 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
417 2008-11-18 Catherine Moore <clm@codesourcery.com>
419 * arm.h (FPU_NEON_FP16): New.
420 (FPU_ARCH_NEON_FP16): New.
422 2008-11-06 Chao-ying Fu <fu@mips.com>
424 * mips.h: Doucument '1' for 5-bit sync type.
426 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
428 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
431 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
433 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
435 2008-07-30 Michael J. Eager <eager@eagercon.com>
437 * ppc.h (PPC_OPCODE_405): Define.
438 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
440 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
442 * ppc.h (ppc_cpu_t): New typedef.
443 (struct powerpc_opcode <flags>): Use it.
444 (struct powerpc_operand <insert, extract>): Likewise.
445 (struct powerpc_macro <flags>): Likewise.
447 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
449 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
450 Update comment before MIPS16 field descriptors to mention MIPS16.
451 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
453 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
454 New bit masks and shift counts for cins and exts.
456 * mips.h: Document new field descriptors +Q.
457 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
459 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
461 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
462 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
464 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
466 * ppc.h: (PPC_OPCODE_E500MC): New.
468 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
470 * i386.h (MAX_OPERANDS): Set to 5.
471 (MAX_MNEM_SIZE): Changed to 20.
473 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
475 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
477 2008-03-09 Paul Brook <paul@codesourcery.com>
479 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
481 2008-03-04 Paul Brook <paul@codesourcery.com>
483 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
484 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
485 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
487 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
488 Nick Clifton <nickc@redhat.com>
491 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
492 with a 32-bit displacement but without the top bit of the 4th byte
495 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
497 * cr16.h (cr16_num_optab): Declared.
499 2008-02-14 Hakan Ardo <hakan@debian.org>
502 * avr.h (AVR_ISA_2xxe): Define.
504 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
506 * mips.h: Update copyright.
507 (INSN_CHIP_MASK): New macro.
508 (INSN_OCTEON): New macro.
509 (CPU_OCTEON): New macro.
510 (OPCODE_IS_MEMBER): Handle Octeon instructions.
512 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
514 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
516 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
518 * avr.h (AVR_ISA_USB162): Add new opcode set.
519 (AVR_ISA_AVR3): Likewise.
521 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
523 * mips.h (INSN_LOONGSON_2E): New.
524 (INSN_LOONGSON_2F): New.
525 (CPU_LOONGSON_2E): New.
526 (CPU_LOONGSON_2F): New.
527 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
529 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
531 * mips.h (INSN_ISA*): Redefine certain values as an
532 enumeration. Update comments.
533 (mips_isa_table): New.
534 (ISA_MIPS*): Redefine to match enumeration.
535 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
538 2007-08-08 Ben Elliston <bje@au.ibm.com>
540 * ppc.h (PPC_OPCODE_PPCPS): New.
542 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
544 * m68k.h: Document j K & E.
546 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
548 * cr16.h: New file for CR16 target.
550 2007-05-02 Alan Modra <amodra@bigpond.net.au>
552 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
554 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
556 * m68k.h (mcfisa_c): New.
557 (mcfusp, mcf_mask): Adjust.
559 2007-04-20 Alan Modra <amodra@bigpond.net.au>
561 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
562 (num_powerpc_operands): Declare.
563 (PPC_OPERAND_SIGNED et al): Redefine as hex.
564 (PPC_OPERAND_PLUS1): Define.
566 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
568 * i386.h (REX_MODE64): Renamed to ...
570 (REX_EXTX): Renamed to ...
572 (REX_EXTY): Renamed to ...
574 (REX_EXTZ): Renamed to ...
577 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
579 * i386.h: Add entries from config/tc-i386.h and move tables
580 to opcodes/i386-opc.h.
582 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
584 * i386.h (FloatDR): Removed.
585 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
587 2007-03-01 Alan Modra <amodra@bigpond.net.au>
589 * spu-insns.h: Add soma double-float insns.
591 2007-02-20 Thiemo Seufer <ths@mips.com>
592 Chao-Ying Fu <fu@mips.com>
594 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
595 (INSN_DSPR2): Add flag for DSP R2 instructions.
596 (M_BALIGN): New macro.
598 2007-02-14 Alan Modra <amodra@bigpond.net.au>
600 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
601 and Seg3ShortFrom with Shortform.
603 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
606 * i386.h (i386_optab): Put the real "test" before the pseudo
609 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
611 * m68k.h (m68010up): OR fido_a.
613 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
615 * m68k.h (fido_a): New.
617 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
619 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
620 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
623 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
625 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
627 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
629 * score-inst.h (enum score_insn_type): Add Insn_internal.
631 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
632 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
633 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
634 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
635 Alan Modra <amodra@bigpond.net.au>
637 * spu-insns.h: New file.
640 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
642 * ppc.h (PPC_OPCODE_CELL): Define.
644 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
646 * i386.h : Modify opcode to support for the change in POPCNT opcode
647 in amdfam10 architecture.
649 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
651 * i386.h: Replace CpuMNI with CpuSSSE3.
653 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
654 Joseph Myers <joseph@codesourcery.com>
655 Ian Lance Taylor <ian@wasabisystems.com>
656 Ben Elliston <bje@wasabisystems.com>
658 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
660 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
662 * score-datadep.h: New file.
663 * score-inst.h: New file.
665 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
667 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
668 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
671 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
672 Michael Meissner <michael.meissner@amd.com>
674 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
676 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
678 * i386.h (i386_optab): Add "nop" with memory reference.
680 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
682 * i386.h (i386_optab): Update comment for 64bit NOP.
684 2006-06-06 Ben Elliston <bje@au.ibm.com>
685 Anton Blanchard <anton@samba.org>
687 * ppc.h (PPC_OPCODE_POWER6): Define.
690 2006-06-05 Thiemo Seufer <ths@mips.com>
692 * mips.h: Improve description of MT flags.
694 2006-05-25 Richard Sandiford <richard@codesourcery.com>
696 * m68k.h (mcf_mask): Define.
698 2006-05-05 Thiemo Seufer <ths@mips.com>
699 David Ung <davidu@mips.com>
701 * mips.h (enum): Add macro M_CACHE_AB.
703 2006-05-04 Thiemo Seufer <ths@mips.com>
704 Nigel Stephens <nigel@mips.com>
705 David Ung <davidu@mips.com>
707 * mips.h: Add INSN_SMARTMIPS define.
709 2006-04-30 Thiemo Seufer <ths@mips.com>
710 David Ung <davidu@mips.com>
712 * mips.h: Defines udi bits and masks. Add description of
713 characters which may appear in the args field of udi
716 2006-04-26 Thiemo Seufer <ths@networkno.de>
718 * mips.h: Improve comments describing the bitfield instruction
721 2006-04-26 Julian Brown <julian@codesourcery.com>
723 * arm.h (FPU_VFP_EXT_V3): Define constant.
724 (FPU_NEON_EXT_V1): Likewise.
725 (FPU_VFP_HARD): Update.
726 (FPU_VFP_V3): Define macro.
727 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
729 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
731 * avr.h (AVR_ISA_PWMx): New.
733 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
735 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
736 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
737 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
738 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
739 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
741 2006-03-10 Paul Brook <paul@codesourcery.com>
743 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
745 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
747 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
748 first. Correct mask of bb "B" opcode.
750 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
752 * i386.h (i386_optab): Support Intel Merom New Instructions.
754 2006-02-24 Paul Brook <paul@codesourcery.com>
756 * arm.h: Add V7 feature bits.
758 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
760 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
762 2006-01-31 Paul Brook <paul@codesourcery.com>
763 Richard Earnshaw <rearnsha@arm.com>
765 * arm.h: Use ARM_CPU_FEATURE.
766 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
767 (arm_feature_set): Change to a structure.
768 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
769 ARM_FEATURE): New macros.
771 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
773 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
774 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
775 (ADD_PC_INCR_OPCODE): Don't define.
777 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
780 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
782 2005-11-14 David Ung <davidu@mips.com>
784 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
785 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
786 save/restore encoding of the args field.
788 2005-10-28 Dave Brolley <brolley@redhat.com>
790 Contribute the following changes:
791 2005-02-16 Dave Brolley <brolley@redhat.com>
793 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
794 cgen_isa_mask_* to cgen_bitset_*.
797 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
799 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
800 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
801 (CGEN_CPU_TABLE): Make isas a ponter.
803 2003-09-29 Dave Brolley <brolley@redhat.com>
805 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
806 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
807 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
809 2002-12-13 Dave Brolley <brolley@redhat.com>
811 * cgen.h (symcat.h): #include it.
812 (cgen-bitset.h): #include it.
813 (CGEN_ATTR_VALUE_TYPE): Now a union.
814 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
815 (CGEN_ATTR_ENTRY): 'value' now unsigned.
816 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
817 * cgen-bitset.h: New file.
819 2005-09-30 Catherine Moore <clm@cm00re.com>
823 2005-10-24 Jan Beulich <jbeulich@novell.com>
825 * ia64.h (enum ia64_opnd): Move memory operand out of set of
828 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
830 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
831 Add FLAG_STRICT to pa10 ftest opcode.
833 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
835 * hppa.h (pa_opcodes): Remove lha entries.
837 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
839 * hppa.h (FLAG_STRICT): Revise comment.
840 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
841 before corresponding pa11 opcodes. Add strict pa10 register-immediate
844 2005-09-30 Catherine Moore <clm@cm00re.com>
848 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
850 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
852 2005-09-06 Chao-ying Fu <fu@mips.com>
854 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
855 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
857 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
858 (INSN_ASE_MASK): Update to include INSN_MT.
859 (INSN_MT): New define for MT ASE.
861 2005-08-25 Chao-ying Fu <fu@mips.com>
863 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
864 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
865 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
866 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
867 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
868 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
870 (INSN_DSP): New define for DSP ASE.
872 2005-08-18 Alan Modra <amodra@bigpond.net.au>
876 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
878 * ppc.h (PPC_OPCODE_E300): Define.
880 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
882 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
884 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
887 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
890 2005-07-27 Jan Beulich <jbeulich@novell.com>
892 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
893 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
894 Add movq-s as 64-bit variants of movd-s.
896 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
898 * hppa.h: Fix punctuation in comment.
900 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
901 implicit space-register addressing. Set space-register bits on opcodes
902 using implicit space-register addressing. Add various missing pa20
903 long-immediate opcodes. Remove various opcodes using implicit 3-bit
904 space-register addressing. Use "fE" instead of "fe" in various
907 2005-07-18 Jan Beulich <jbeulich@novell.com>
909 * i386.h (i386_optab): Operands of aam and aad are unsigned.
911 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
913 * i386.h (i386_optab): Support Intel VMX Instructions.
915 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
917 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
919 2005-07-05 Jan Beulich <jbeulich@novell.com>
921 * i386.h (i386_optab): Add new insns.
923 2005-07-01 Nick Clifton <nickc@redhat.com>
925 * sparc.h: Add typedefs to structure declarations.
927 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
930 * i386.h (i386_optab): Update comments for 64bit addressing on
931 mov. Allow 64bit addressing for mov and movq.
933 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
935 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
936 respectively, in various floating-point load and store patterns.
938 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
940 * hppa.h (FLAG_STRICT): Correct comment.
941 (pa_opcodes): Update load and store entries to allow both PA 1.X and
942 PA 2.0 mneumonics when equivalent. Entries with cache control
943 completers now require PA 1.1. Adjust whitespace.
945 2005-05-19 Anton Blanchard <anton@samba.org>
947 * ppc.h (PPC_OPCODE_POWER5): Define.
949 2005-05-10 Nick Clifton <nickc@redhat.com>
951 * Update the address and phone number of the FSF organization in
952 the GPL notices in the following files:
953 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
954 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
955 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
956 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
957 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
958 tic54x.h, tic80.h, v850.h, vax.h
960 2005-05-09 Jan Beulich <jbeulich@novell.com>
962 * i386.h (i386_optab): Add ht and hnt.
964 2005-04-18 Mark Kettenis <kettenis@gnu.org>
966 * i386.h: Insert hyphens into selected VIA PadLock extensions.
967 Add xcrypt-ctr. Provide aliases without hyphens.
969 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
971 Moved from ../ChangeLog
973 2005-04-12 Paul Brook <paul@codesourcery.com>
974 * m88k.h: Rename psr macros to avoid conflicts.
976 2005-03-12 Zack Weinberg <zack@codesourcery.com>
977 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
978 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
981 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
982 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
983 Remove redundant instruction types.
984 (struct argument): X_op - new field.
985 (struct cst4_entry): Remove.
986 (no_op_insn): Declare.
988 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
989 * crx.h (enum argtype): Rename types, remove unused types.
991 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
992 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
993 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
994 (enum operand_type): Rearrange operands, edit comments.
995 replace us<N> with ui<N> for unsigned immediate.
996 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
997 displacements (respectively).
998 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
999 (instruction type): Add NO_TYPE_INS.
1000 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1001 (operand_entry): New field - 'flags'.
1002 (operand flags): New.
1004 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1005 * crx.h (operand_type): Remove redundant types i3, i4,
1007 Add new unsigned immediate types us3, us4, us5, us16.
1009 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1011 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1012 adjust them accordingly.
1014 2005-04-01 Jan Beulich <jbeulich@novell.com>
1016 * i386.h (i386_optab): Add rdtscp.
1018 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1020 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1021 between memory and segment register. Allow movq for moving between
1022 general-purpose register and segment register.
1024 2005-02-09 Jan Beulich <jbeulich@novell.com>
1027 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1028 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1031 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1033 * m68k.h (m68008, m68ec030, m68882): Remove.
1035 (cpu_m68k, cpu_cf): New.
1036 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1037 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1039 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1041 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1042 * cgen.h (enum cgen_parse_operand_type): Add
1043 CGEN_PARSE_OPERAND_SYMBOLIC.
1045 2005-01-21 Fred Fish <fnf@specifixinc.com>
1047 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1048 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1049 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1051 2005-01-19 Fred Fish <fnf@specifixinc.com>
1053 * mips.h (struct mips_opcode): Add new pinfo2 member.
1054 (INSN_ALIAS): New define for opcode table entries that are
1055 specific instances of another entry, such as 'move' for an 'or'
1056 with a zero operand.
1057 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1058 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1060 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1062 * mips.h (CPU_RM9000): Define.
1063 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1065 2004-11-25 Jan Beulich <jbeulich@novell.com>
1067 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1068 to/from test registers are illegal in 64-bit mode. Add missing
1069 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1070 (previously one had to explicitly encode a rex64 prefix). Re-enable
1071 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1072 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1074 2004-11-23 Jan Beulich <jbeulich@novell.com>
1076 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1077 available only with SSE2. Change the MMX additions introduced by SSE
1078 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1079 instructions by their now designated identifier (since combining i686
1080 and 3DNow! does not really imply 3DNow!A).
1082 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1084 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1085 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1087 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1088 Vineet Sharma <vineets@noida.hcltech.com>
1090 * maxq.h: New file: Disassembly information for the maxq port.
1092 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1094 * i386.h (i386_optab): Put back "movzb".
1096 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1098 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1099 comments. Remove member cris_ver_sim. Add members
1100 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1101 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1102 (struct cris_support_reg, struct cris_cond15): New types.
1103 (cris_conds15): Declare.
1104 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1105 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1106 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1107 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1108 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1109 SIZE_FIELD_UNSIGNED.
1111 2004-11-04 Jan Beulich <jbeulich@novell.com>
1113 * i386.h (sldx_Suf): Remove.
1114 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1115 (q_FP): Define, implying no REX64.
1116 (x_FP, sl_FP): Imply FloatMF.
1117 (i386_optab): Split reg and mem forms of moving from segment registers
1118 so that the memory forms can ignore the 16-/32-bit operand size
1119 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1120 all non-floating-point instructions. Unite 32- and 64-bit forms of
1121 movsx, movzx, and movd. Adjust floating point operations for the above
1122 changes to the *FP macros. Add DefaultSize to floating point control
1123 insns operating on larger memory ranges. Remove left over comments
1124 hinting at certain insns being Intel-syntax ones where the ones
1125 actually meant are already gone.
1127 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1129 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1132 2004-09-30 Paul Brook <paul@codesourcery.com>
1134 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1135 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1137 2004-09-11 Theodore A. Roth <troth@openavr.org>
1139 * avr.h: Add support for
1140 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1142 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1144 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1146 2004-08-24 Dmitry Diky <diwil@spec.ru>
1148 * msp430.h (msp430_opc): Add new instructions.
1149 (msp430_rcodes): Declare new instructions.
1150 (msp430_hcodes): Likewise..
1152 2004-08-13 Nick Clifton <nickc@redhat.com>
1155 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1158 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1160 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1162 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1164 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1166 2004-07-21 Jan Beulich <jbeulich@novell.com>
1168 * i386.h: Adjust instruction descriptions to better match the
1171 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1173 * arm.h: Remove all old content. Replace with architecture defines
1174 from gas/config/tc-arm.c.
1176 2004-07-09 Andreas Schwab <schwab@suse.de>
1178 * m68k.h: Fix comment.
1180 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1184 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1186 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1188 2004-05-24 Peter Barada <peter@the-baradas.com>
1190 * m68k.h: Add 'size' to m68k_opcode.
1192 2004-05-05 Peter Barada <peter@the-baradas.com>
1194 * m68k.h: Switch from ColdFire chip name to core variant.
1196 2004-04-22 Peter Barada <peter@the-baradas.com>
1198 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1199 descriptions for new EMAC cases.
1200 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1201 handle Motorola MAC syntax.
1202 Allow disassembly of ColdFire V4e object files.
1204 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1206 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1208 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1210 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1212 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1214 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1216 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1218 * i386.h (i386_optab): Added xstore/xcrypt insns.
1220 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1222 * h8300.h (32bit ldc/stc): Add relaxing support.
1224 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1226 * h8300.h (BITOP): Pass MEMRELAX flag.
1228 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1230 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1233 For older changes see ChangeLog-9103
1239 version-control: never