include/opcode/ChangeLog

   1 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
   2
   3         * mips.h (M_PREF_AB): New enum value.
   4
   5 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
   8         M_IU): Define.
   9         (is_macmod_pmove, is_macmod_hmove): New functions.
  10
  11 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
  14
  15 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
  16
  17         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
  18         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
  19
  20 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  21
  22         PR gas/11395
  23         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
  24         "bb" entries.
  25
  26 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  27
  28         PR gas/11395
  29         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
  30
  31 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
  32
  33         * mips.h: Update commentary after last commit.
  34
  35 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
  36
  37         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
  38         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
  39         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
  40
  41 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
  42
  43         * mips.h: Fix previous commit.
  44
  45 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
  46
  47         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
  48         (INSN_LOONGSON_3A): Clear bit 31.
  49
  50 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  51
  52         PR gas/12198
  53         * arm.h (ARM_AEXT_V6M_ONLY): New define.
  54         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
  55         (ARM_ARCH_V6M_ONLY): New define.
  56
  57 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
  58
  59         * mips.h (INSN_LOONGSON_3A): Defined.
  60         (CPU_LOONGSON_3A): Defined.
  61         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
  62
  63 2010-10-09  Matt Rice  <ratmice@gmail.com>
  64
  65         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
  66         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
  67
  68 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  69
  70         * arm.h (ARM_EXT_VIRT): New define.
  71         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
  72         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
  73         Extensions.
  74
  75 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  76
  77         * arm.h (ARM_AEXT_ADIV): New define.
  78         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
  79
  80 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  81
  82         * arm.h (ARM_EXT_OS): New define.
  83         (ARM_AEXT_V6SM): Likewise.
  84         (ARM_ARCH_V6SM): Likewise.
  85
  86 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  87
  88         * arm.h (ARM_EXT_MP): Add.
  89         (ARM_ARCH_V7A_MP): Likewise.
  90
  91 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * bfin.h: Declare pseudoChr structs/defines.
  94
  95 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
  96
  97         * bfin.h: Strip trailing whitespace.
  98
  99 2010-07-29  DJ Delorie  <dj@redhat.com>
 100
 101         * rx.h (RX_Operand_Type): Add TwoReg.
 102         (RX_Opcode_ID): Remove ediv and ediv2.
 103
 104 2010-07-27  DJ Delorie  <dj@redhat.com>
 105
 106         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 107
 108 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 109             Ina Pandit  <ina.pandit@kpitcummins.com>
 110
 111         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 112         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 113         PROCESSOR_V850E2_ALL.
 114         Remove PROCESSOR_V850EA support.
 115         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 116         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 117         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 118         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 119         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 120         V850_OPERAND_PERCENT.
 121         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 122         V850_NOT_R0.
 123         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 124         and V850E_PUSH_POP
 125
 126 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 127
 128         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 129         (MIPS16_INSN_BRANCH): Rename to...
 130         (MIPS16_INSN_COND_BRANCH): ... this.
 131
 132 2010-07-03  Alan Modra  <amodra@gmail.com>
 133
 134         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 135         Renumber other PPC_OPCODE defines.
 136
 137 2010-07-03  Alan Modra  <amodra@gmail.com>
 138
 139         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 140
 141 2010-06-29  Alan Modra  <amodra@gmail.com>
 142
 143         * maxq.h: Delete file.
 144
 145 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 146
 147         * ppc.h (PPC_OPCODE_E500): Define.
 148
 149 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 150
 151         * opcode/mips.h (INSN_MIPS16): Remove.
 152
 153 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 154
 155         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 156
 157 2010-04-15  Nick Clifton  <nickc@redhat.com>
 158
 159         * alpha.h: Update copyright notice to use GPLv3.
 160         * arc.h: Likewise.
 161         * arm.h: Likewise.
 162         * avr.h: Likewise.
 163         * bfin.h: Likewise.
 164         * cgen.h: Likewise.
 165         * convex.h: Likewise.
 166         * cr16.h: Likewise.
 167         * cris.h: Likewise.
 168         * crx.h: Likewise.
 169         * d10v.h: Likewise.
 170         * d30v.h: Likewise.
 171         * dlx.h: Likewise.
 172         * h8300.h: Likewise.
 173         * hppa.h: Likewise.
 174         * i370.h: Likewise.
 175         * i386.h: Likewise.
 176         * i860.h: Likewise.
 177         * i960.h: Likewise.
 178         * ia64.h: Likewise.
 179         * m68hc11.h: Likewise.
 180         * m68k.h: Likewise.
 181         * m88k.h: Likewise.
 182         * maxq.h: Likewise.
 183         * mips.h: Likewise.
 184         * mmix.h: Likewise.
 185         * mn10200.h: Likewise.
 186         * mn10300.h: Likewise.
 187         * msp430.h: Likewise.
 188         * np1.h: Likewise.
 189         * ns32k.h: Likewise.
 190         * or32.h: Likewise.
 191         * pdp11.h: Likewise.
 192         * pj.h: Likewise.
 193         * pn.h: Likewise.
 194         * ppc.h: Likewise.
 195         * pyr.h: Likewise.
 196         * rx.h: Likewise.
 197         * s390.h: Likewise.
 198         * score-datadep.h: Likewise.
 199         * score-inst.h: Likewise.
 200         * sparc.h: Likewise.
 201         * spu-insns.h: Likewise.
 202         * spu.h: Likewise.
 203         * tic30.h: Likewise.
 204         * tic4x.h: Likewise.
 205         * tic54x.h: Likewise.
 206         * tic80.h: Likewise.
 207         * v850.h: Likewise.
 208         * vax.h: Likewise.
 209
 210 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 211
 212         * tic6x-control-registers.h, tic6x-insn-formats.h,
 213         tic6x-opcode-table.h, tic6x.h: New.
 214
 215 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 216
 217         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 218
 219 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 220
 221         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 222
 223 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * ia64.h (ia64_find_opcode): Remove argument name.
 226         (ia64_find_next_opcode): Likewise.
 227         (ia64_dis_opcode): Likewise.
 228         (ia64_free_opcode): Likewise.
 229         (ia64_find_dependency): Likewise.
 230
 231 2009-11-22  Doug Evans  <dje@sebabeach.org>
 232
 233         * cgen.h: Include bfd_stdint.h.
 234         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 235
 236 2009-11-18  Paul Brook  <paul@codesourcery.com>
 237
 238         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 239
 240 2009-11-17  Paul Brook  <paul@codesourcery.com>
 241         Daniel Jacobowitz  <dan@codesourcery.com>
 242
 243         * arm.h (ARM_EXT_V6_DSP): Define.
 244         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 245         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 246
 247 2009-11-04  DJ Delorie  <dj@redhat.com>
 248
 249         * rx.h (rx_decode_opcode) (mvtipl): Add.
 250         (mvtcp, mvfcp, opecp): Remove.
 251
 252 2009-11-02  Paul Brook  <paul@codesourcery.com>
 253
 254         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 255         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 256         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 257         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 258         FPU_ARCH_NEON_VFP_V4): Define.
 259
 260 2009-10-23  Doug Evans  <dje@sebabeach.org>
 261
 262         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 263         * cgen.h: Update.  Improve multi-inclusion macro name.
 264
 265 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 266
 267         * ppc.h (PPC_OPCODE_476): Define.
 268
 269 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 270
 271         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 272
 273 2009-09-29  DJ Delorie  <dj@redhat.com>
 274
 275         * rx.h: New file.
 276
 277 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 278
 279         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 280
 281 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 282
 283         * ppc.h (PPC_OPCODE_PPCA2): New.
 284
 285 2009-09-05  Martin Thuresson  <martin@mtme.org>
 286
 287         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 288
 289 2009-08-29  Martin Thuresson  <martin@mtme.org>
 290
 291         * tic30.h (template): Rename type template to
 292         insn_template. Updated code to use new name.
 293         * tic54x.h (template): Rename type template to
 294         insn_template.
 295
 296 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 297
 298         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 299
 300 2009-06-11  Anthony Green  <green@moxielogic.com>
 301
 302         * moxie.h (MOXIE_F3_PCREL): Define.
 303         (moxie_form3_opc_info): Grow.
 304
 305 2009-06-06  Anthony Green  <green@moxielogic.com>
 306
 307         * moxie.h (MOXIE_F1_M): Define.
 308
 309 2009-04-15  Anthony Green  <green@moxielogic.com>
 310
 311         * moxie.h: Created.
 312
 313 2009-04-06  DJ Delorie  <dj@redhat.com>
 314
 315         * h8300.h: Add relaxation attributes to MOVA opcodes.
 316
 317 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 318
 319         * ppc.h (ppc_parse_cpu): Declare.
 320
 321 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 322
 323         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 324         and _IMM11 for mbitclr and mbitset.
 325         * score-datadep.h: Update dependency information.
 326
 327 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 328
 329         * ppc.h (PPC_OPCODE_POWER7): New.
 330
 331 2009-02-06  Doug Evans  <dje@google.com>
 332
 333         * i386.h: Add comment regarding sse* insns and prefixes.
 334
 335 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 336
 337         * mips.h (INSN_XLR): Define.
 338         (INSN_CHIP_MASK): Update.
 339         (CPU_XLR): Define.
 340         (OPCODE_IS_MEMBER): Update.
 341         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 342
 343 2009-01-28  Doug Evans  <dje@google.com>
 344
 345         * opcode/i386.h: Add multiple inclusion protection.
 346         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 347         (EDI_REG_NUM): New macros.
 348         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 349         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 350         (REX_PREFIX_P): New macro.
 351
 352 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 353
 354         * ppc.h (struct powerpc_opcode): New field "deprecated".
 355         (PPC_OPCODE_NOPOWER4): Delete.
 356
 357 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 358
 359         * mips.h: Define CPU_R14000, CPU_R16000.
 360         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 361
 362 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 363
 364         * arm.h (FPU_NEON_FP16): New.
 365         (FPU_ARCH_NEON_FP16): New.
 366
 367 2008-11-06  Chao-ying Fu  <fu@mips.com>
 368
 369         * mips.h: Doucument '1' for 5-bit sync type.
 370
 371 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 374         IA64_RS_CR.
 375
 376 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 377
 378         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 379
 380 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 381
 382         * ppc.h (PPC_OPCODE_405): Define.
 383         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 384
 385 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 386
 387         * ppc.h (ppc_cpu_t): New typedef.
 388         (struct powerpc_opcode <flags>): Use it.
 389         (struct powerpc_operand <insert, extract>): Likewise.
 390         (struct powerpc_macro <flags>): Likewise.
 391
 392 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 393
 394         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 395         Update comment before MIPS16 field descriptors to mention MIPS16.
 396         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 397         BBIT.
 398         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 399         New bit masks and shift counts for cins and exts.
 400
 401         * mips.h: Document new field descriptors +Q.
 402         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 403
 404 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 405
 406         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 407         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 408
 409 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 410
 411         * ppc.h: (PPC_OPCODE_E500MC): New.
 412
 413 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386.h (MAX_OPERANDS): Set to 5.
 416         (MAX_MNEM_SIZE): Changed to 20.
 417
 418 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 419
 420         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 421
 422 2008-03-09  Paul Brook  <paul@codesourcery.com>
 423
 424         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 425
 426 2008-03-04  Paul Brook  <paul@codesourcery.com>
 427
 428         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 429         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 430         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 431
 432 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 433             Nick Clifton  <nickc@redhat.com>
 434
 435         PR 3134
 436         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 437         with a 32-bit displacement but without the top bit of the 4th byte
 438         set.
 439
 440 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 441
 442         * cr16.h (cr16_num_optab): Declared.
 443
 444 2008-02-14  Hakan Ardo  <hakan@debian.org>
 445
 446         PR gas/2626
 447         * avr.h (AVR_ISA_2xxe): Define.
 448
 449 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 450
 451         * mips.h: Update copyright.
 452         (INSN_CHIP_MASK): New macro.
 453         (INSN_OCTEON): New macro.
 454         (CPU_OCTEON): New macro.
 455         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 456
 457 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 458
 459         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 460
 461 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 462
 463         * avr.h (AVR_ISA_USB162): Add new opcode set.
 464         (AVR_ISA_AVR3): Likewise.
 465
 466 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 467
 468         * mips.h (INSN_LOONGSON_2E): New.
 469         (INSN_LOONGSON_2F): New.
 470         (CPU_LOONGSON_2E): New.
 471         (CPU_LOONGSON_2F): New.
 472         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 473
 474 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 475
 476         * mips.h (INSN_ISA*): Redefine certain values as an
 477         enumeration.  Update comments.
 478         (mips_isa_table): New.
 479         (ISA_MIPS*): Redefine to match enumeration.
 480         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 481         values.
 482
 483 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 484
 485         * ppc.h (PPC_OPCODE_PPCPS): New.
 486
 487 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 488
 489         * m68k.h: Document j K & E.
 490
 491 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 492
 493         * cr16.h: New file for CR16 target.
 494
 495 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 496
 497         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 498
 499 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 500
 501         * m68k.h (mcfisa_c): New.
 502         (mcfusp, mcf_mask): Adjust.
 503
 504 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 505
 506         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 507         (num_powerpc_operands): Declare.
 508         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 509         (PPC_OPERAND_PLUS1): Define.
 510
 511 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         * i386.h (REX_MODE64): Renamed to ...
 514         (REX_W): This.
 515         (REX_EXTX): Renamed to ...
 516         (REX_R): This.
 517         (REX_EXTY): Renamed to ...
 518         (REX_X): This.
 519         (REX_EXTZ): Renamed to ...
 520         (REX_B): This.
 521
 522 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         * i386.h: Add entries from config/tc-i386.h and move tables
 525         to opcodes/i386-opc.h.
 526
 527 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * i386.h (FloatDR): Removed.
 530         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 531
 532 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 533
 534         * spu-insns.h: Add soma double-float insns.
 535
 536 2007-02-20  Thiemo Seufer  <ths@mips.com>
 537             Chao-Ying Fu  <fu@mips.com>
 538
 539         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 540         (INSN_DSPR2): Add flag for DSP R2 instructions.
 541         (M_BALIGN): New macro.
 542
 543 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 544
 545         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 546         and Seg3ShortFrom with Shortform.
 547
 548 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         PR gas/4027
 551         * i386.h (i386_optab): Put the real "test" before the pseudo
 552         one.
 553
 554 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 555
 556         * m68k.h (m68010up): OR fido_a.
 557
 558 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 559
 560         * m68k.h (fido_a): New.
 561
 562 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 563
 564         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 565         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 566         values.
 567
 568 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 571
 572 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 573
 574         * score-inst.h (enum score_insn_type): Add Insn_internal.
 575
 576 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 577             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 578             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 579             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 580             Alan Modra  <amodra@bigpond.net.au>
 581
 582         * spu-insns.h: New file.
 583         * spu.h: New file.
 584
 585 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 586
 587         * ppc.h (PPC_OPCODE_CELL): Define.
 588
 589 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 590
 591         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 592         in amdfam10 architecture.
 593
 594 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386.h: Replace CpuMNI with CpuSSSE3.
 597
 598 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 599             Joseph Myers  <joseph@codesourcery.com>
 600             Ian Lance Taylor  <ian@wasabisystems.com>
 601             Ben Elliston  <bje@wasabisystems.com>
 602
 603         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 604
 605 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 606
 607         * score-datadep.h: New file.
 608         * score-inst.h: New file.
 609
 610 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 613         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 614         movdq2q and movq2dq.
 615
 616 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 617            Michael Meissner             <michael.meissner@amd.com>
 618
 619         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 620
 621 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * i386.h (i386_optab): Add "nop" with memory reference.
 624
 625 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         * i386.h (i386_optab): Update comment for 64bit NOP.
 628
 629 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 630             Anton Blanchard  <anton@samba.org>
 631
 632         * ppc.h (PPC_OPCODE_POWER6): Define.
 633         Adjust whitespace.
 634
 635 2006-06-05  Thiemo Seufer  <ths@mips.com>
 636
 637         * mips.h: Improve description of MT flags.
 638
 639 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 640
 641         * m68k.h (mcf_mask): Define.
 642
 643 2006-05-05  Thiemo Seufer  <ths@mips.com>
 644             David Ung  <davidu@mips.com>
 645
 646         * mips.h (enum): Add macro M_CACHE_AB.
 647
 648 2006-05-04  Thiemo Seufer  <ths@mips.com>
 649             Nigel Stephens  <nigel@mips.com>
 650             David Ung  <davidu@mips.com>
 651
 652         * mips.h: Add INSN_SMARTMIPS define.
 653
 654 2006-04-30  Thiemo Seufer  <ths@mips.com>
 655             David Ung  <davidu@mips.com>
 656
 657         * mips.h: Defines udi bits and masks.  Add description of
 658         characters which may appear in the args field of udi
 659         instructions.
 660
 661 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 662
 663         * mips.h: Improve comments describing the bitfield instruction
 664         fields.
 665
 666 2006-04-26  Julian Brown  <julian@codesourcery.com>
 667
 668         * arm.h (FPU_VFP_EXT_V3): Define constant.
 669         (FPU_NEON_EXT_V1): Likewise.
 670         (FPU_VFP_HARD): Update.
 671         (FPU_VFP_V3): Define macro.
 672         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 673
 674 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 675
 676         * avr.h (AVR_ISA_PWMx): New.
 677
 678 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 679
 680         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 681         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 682         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 683         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 684         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 685
 686 2006-03-10  Paul Brook  <paul@codesourcery.com>
 687
 688         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 689
 690 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 691
 692         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 693         first.  Correct mask of bb "B" opcode.
 694
 695 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 696
 697         * i386.h (i386_optab): Support Intel Merom New Instructions.
 698
 699 2006-02-24  Paul Brook  <paul@codesourcery.com>
 700
 701         * arm.h: Add V7 feature bits.
 702
 703 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 706
 707 2006-01-31  Paul Brook  <paul@codesourcery.com>
 708         Richard Earnshaw <rearnsha@arm.com>
 709
 710         * arm.h: Use ARM_CPU_FEATURE.
 711         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 712         (arm_feature_set): Change to a structure.
 713         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 714         ARM_FEATURE): New macros.
 715
 716 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 717
 718         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 719         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 720         (ADD_PC_INCR_OPCODE): Don't define.
 721
 722 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 723
 724         PR gas/1874
 725         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 726
 727 2005-11-14  David Ung  <davidu@mips.com>
 728
 729         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 730         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 731         save/restore encoding of the args field.
 732
 733 2005-10-28  Dave Brolley  <brolley@redhat.com>
 734
 735         Contribute the following changes:
 736         2005-02-16  Dave Brolley  <brolley@redhat.com>
 737
 738         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 739         cgen_isa_mask_* to cgen_bitset_*.
 740         * cgen.h: Likewise.
 741
 742         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 743
 744         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 745         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 746         (CGEN_CPU_TABLE): Make isas a ponter.
 747
 748         2003-09-29  Dave Brolley  <brolley@redhat.com>
 749
 750         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 751         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 752         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 753
 754         2002-12-13  Dave Brolley  <brolley@redhat.com>
 755
 756         * cgen.h (symcat.h): #include it.
 757         (cgen-bitset.h): #include it.
 758         (CGEN_ATTR_VALUE_TYPE): Now a union.
 759         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 760         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 761         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 762         * cgen-bitset.h: New file.
 763
 764 2005-09-30  Catherine Moore  <clm@cm00re.com>
 765
 766         * bfin.h: New file.
 767
 768 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 769
 770         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 771         indirect operands.
 772
 773 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 774
 775         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 776         Add FLAG_STRICT to pa10 ftest opcode.
 777
 778 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 779
 780         * hppa.h (pa_opcodes): Remove lha entries.
 781
 782 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 783
 784         * hppa.h (FLAG_STRICT): Revise comment.
 785         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 786         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 787         entries for "fdc".
 788
 789 2005-09-30  Catherine Moore  <clm@cm00re.com>
 790
 791         * bfin.h: New file.
 792
 793 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 794
 795         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 796
 797 2005-09-06  Chao-ying Fu  <fu@mips.com>
 798
 799         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 800         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 801         define.
 802         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 803         (INSN_ASE_MASK): Update to include INSN_MT.
 804         (INSN_MT): New define for MT ASE.
 805
 806 2005-08-25  Chao-ying Fu  <fu@mips.com>
 807
 808         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 809         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 810         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 811         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 812         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 813         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 814         instructions.
 815         (INSN_DSP): New define for DSP ASE.
 816
 817 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 818
 819         * a29k.h: Delete.
 820
 821 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 822
 823         * ppc.h (PPC_OPCODE_E300): Define.
 824
 825 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 826
 827         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 828
 829 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 830
 831         PR gas/336
 832         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 833         and pitlb.
 834
 835 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 836
 837         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 838         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 839         Add movq-s as 64-bit variants of movd-s.
 840
 841 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 842
 843         * hppa.h: Fix punctuation in comment.
 844
 845         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 846         implicit space-register addressing.  Set space-register bits on opcodes
 847         using implicit space-register addressing.  Add various missing pa20
 848         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 849         space-register addressing.  Use "fE" instead of "fe" in various
 850         fstw opcodes.
 851
 852 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 853
 854         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 855
 856 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 857
 858         * i386.h (i386_optab): Support Intel VMX Instructions.
 859
 860 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 861
 862         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 863
 864 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 865
 866         * i386.h (i386_optab): Add new insns.
 867
 868 2005-07-01  Nick Clifton  <nickc@redhat.com>
 869
 870         * sparc.h: Add typedefs to structure declarations.
 871
 872 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         PR 1013
 875         * i386.h (i386_optab): Update comments for 64bit addressing on
 876         mov. Allow 64bit addressing for mov and movq.
 877
 878 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 879
 880         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 881         respectively, in various floating-point load and store patterns.
 882
 883 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 884
 885         * hppa.h (FLAG_STRICT): Correct comment.
 886         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 887         PA 2.0 mneumonics when equivalent.  Entries with cache control
 888         completers now require PA 1.1.  Adjust whitespace.
 889
 890 2005-05-19  Anton Blanchard  <anton@samba.org>
 891
 892         * ppc.h (PPC_OPCODE_POWER5): Define.
 893
 894 2005-05-10  Nick Clifton  <nickc@redhat.com>
 895
 896         * Update the address and phone number of the FSF organization in
 897         the GPL notices in the following files:
 898         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 899         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 900         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 901         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 902         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 903         tic54x.h, tic80.h, v850.h, vax.h
 904
 905 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 906
 907         * i386.h (i386_optab): Add ht and hnt.
 908
 909 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 910
 911         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 912         Add xcrypt-ctr.  Provide aliases without hyphens.
 913
 914 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         Moved from ../ChangeLog
 917
 918         2005-04-12  Paul Brook  <paul@codesourcery.com>
 919         * m88k.h: Rename psr macros to avoid conflicts.
 920
 921         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 922         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 923         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 924         and ARM_ARCH_V6ZKT2.
 925
 926         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 927         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 928         Remove redundant instruction types.
 929         (struct argument): X_op - new field.
 930         (struct cst4_entry): Remove.
 931         (no_op_insn): Declare.
 932
 933         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 934         * crx.h (enum argtype): Rename types, remove unused types.
 935
 936         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 937         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 938         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 939         (enum operand_type): Rearrange operands, edit comments.
 940         replace us<N> with ui<N> for unsigned immediate.
 941         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 942         displacements (respectively).
 943         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 944         (instruction type): Add NO_TYPE_INS.
 945         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 946         (operand_entry): New field - 'flags'.
 947         (operand flags): New.
 948
 949         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 950         * crx.h (operand_type): Remove redundant types i3, i4,
 951         i5, i8, i12.
 952         Add new unsigned immediate types us3, us4, us5, us16.
 953
 954 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 955
 956         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 957         adjust them accordingly.
 958
 959 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 960
 961         * i386.h (i386_optab): Add rdtscp.
 962
 963 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 964
 965         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 966         between memory and segment register. Allow movq for moving between
 967         general-purpose register and segment register.
 968
 969 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 970
 971         PR gas/707
 972         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 973         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 974         fnstsw.
 975
 976 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 977
 978         * m68k.h (m68008, m68ec030, m68882): Remove.
 979         (m68k_mask): New.
 980         (cpu_m68k, cpu_cf): New.
 981         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 982         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 983
 984 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 985
 986         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 987         * cgen.h (enum cgen_parse_operand_type): Add
 988         CGEN_PARSE_OPERAND_SYMBOLIC.
 989
 990 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 991
 992         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 993         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 994         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 995
 996 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 997
 998         * mips.h (struct mips_opcode): Add new pinfo2 member.
 999         (INSN_ALIAS): New define for opcode table entries that are
1000         specific instances of another entry, such as 'move' for an 'or'
1001         with a zero operand.
1002         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1003         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1004
1005 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1006
1007         * mips.h (CPU_RM9000): Define.
1008         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1009
1010 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1011
1012         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1013         to/from test registers are illegal in 64-bit mode. Add missing
1014         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1015         (previously one had to explicitly encode a rex64 prefix). Re-enable
1016         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1017         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1018
1019 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1020
1021         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1022         available only with SSE2. Change the MMX additions introduced by SSE
1023         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1024         instructions by their now designated identifier (since combining i686
1025         and 3DNow! does not really imply 3DNow!A).
1026
1027 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1028
1029         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1030         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1031
1032 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1033             Vineet Sharma      <vineets@noida.hcltech.com>
1034
1035         * maxq.h: New file: Disassembly information for the maxq port.
1036
1037 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1038
1039         * i386.h (i386_optab): Put back "movzb".
1040
1041 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1042
1043         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1044         comments.  Remove member cris_ver_sim.  Add members
1045         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1046         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1047         (struct cris_support_reg, struct cris_cond15): New types.
1048         (cris_conds15): Declare.
1049         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1050         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1051         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1052         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1053         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1054         SIZE_FIELD_UNSIGNED.
1055
1056 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1057
1058         * i386.h (sldx_Suf): Remove.
1059         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1060         (q_FP): Define, implying no REX64.
1061         (x_FP, sl_FP): Imply FloatMF.
1062         (i386_optab): Split reg and mem forms of moving from segment registers
1063         so that the memory forms can ignore the 16-/32-bit operand size
1064         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1065         all non-floating-point instructions. Unite 32- and 64-bit forms of
1066         movsx, movzx, and movd. Adjust floating point operations for the above
1067         changes to the *FP macros. Add DefaultSize to floating point control
1068         insns operating on larger memory ranges. Remove left over comments
1069         hinting at certain insns being Intel-syntax ones where the ones
1070         actually meant are already gone.
1071
1072 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1073
1074         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1075         instruction type.
1076
1077 2004-09-30  Paul Brook  <paul@codesourcery.com>
1078
1079         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1080         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1081
1082 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1083
1084         * avr.h: Add support for
1085         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1086
1087 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1088
1089         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1090
1091 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1092
1093         * msp430.h (msp430_opc): Add new instructions.
1094         (msp430_rcodes): Declare new instructions.
1095         (msp430_hcodes): Likewise..
1096
1097 2004-08-13  Nick Clifton  <nickc@redhat.com>
1098
1099         PR/301
1100         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1101         processors.
1102
1103 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1104
1105         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1106
1107 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1108
1109         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1110
1111 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1112
1113         * i386.h: Adjust instruction descriptions to better match the
1114         specification.
1115
1116 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1117
1118         * arm.h: Remove all old content.  Replace with architecture defines
1119         from gas/config/tc-arm.c.
1120
1121 2004-07-09  Andreas Schwab  <schwab@suse.de>
1122
1123         * m68k.h: Fix comment.
1124
1125 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1126
1127         * crx.h: New file.
1128
1129 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1130
1131         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1132
1133 2004-05-24  Peter Barada  <peter@the-baradas.com>
1134
1135         * m68k.h: Add 'size' to m68k_opcode.
1136
1137 2004-05-05  Peter Barada  <peter@the-baradas.com>
1138
1139         * m68k.h: Switch from ColdFire chip name to core variant.
1140
1141 2004-04-22  Peter Barada  <peter@the-baradas.com>
1142
1143         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1144         descriptions for new EMAC cases.
1145         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1146         handle Motorola MAC syntax.
1147         Allow disassembly of ColdFire V4e object files.
1148
1149 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1150
1151         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1152
1153 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1154
1155         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1156
1157 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1158
1159         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1160
1161 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1162
1163         * i386.h (i386_optab): Added xstore/xcrypt insns.
1164
1165 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1166
1167         * h8300.h (32bit ldc/stc): Add relaxing support.
1168
1169 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1170
1171         * h8300.h (BITOP): Pass MEMRELAX flag.
1172
1173 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1174
1175         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1176         except for the H8S.
1177
1178 For older changes see ChangeLog-9103
1179 \f
1180 Local Variables:
1181 mode: change-log
1182 left-margin: 8
1183 fill-column: 74
1184 version-control: never
1185 End: