1 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
4 * tic6x.h (enum tic6x_coding_method): Add
5 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
6 separately the msb and lsb of a register pair. This is needed to
7 encode the opcodes in the same way as TI assembler does.
8 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
9 and rsqrdp opcodes to use the new field coding types.
11 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
13 * arm.h (CRC_EXT_ARMV8): New constant.
14 (ARCH_CRC_ARMV8): New macro.
16 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
18 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
20 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
21 Andrew Jenner <andrew@codesourcery.com>
23 Based on patches from Altera Corporation.
27 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
29 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
31 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
34 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
36 2013-01-24 Nick Clifton <nickc@redhat.com>
38 * v850.h: Add e3v5 support.
40 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
42 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
44 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
46 * ppc.h (PPC_OPCODE_POWER8): New define.
47 (PPC_OPCODE_HTM): Likewise.
49 2013-01-10 Will Newton <will.newton@imgtec.com>
53 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
55 * cr16.h (make_instruction): Rename to cr16_make_instruction.
56 (match_opcode): Rename to cr16_match_opcode.
58 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
60 * mips.h: Add support for r5900 instructions including lq and sq.
62 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
64 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
65 (make_instruction,match_opcode): Added function prototypes.
66 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
68 2012-11-23 Alan Modra <amodra@gmail.com>
70 * ppc.h (ppc_parse_cpu): Update prototype.
72 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
74 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
75 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
77 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
79 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
81 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
83 * ia64.h (ia64_opnd): Add new operand types.
85 2012-08-21 David S. Miller <davem@davemloft.net>
87 * sparc.h (F3F4): New macro.
89 2012-08-13 Ian Bolton <ian.bolton@arm.com>
90 Laurent Desnogues <laurent.desnogues@arm.com>
91 Jim MacArthur <jim.macarthur@arm.com>
92 Marcus Shawcroft <marcus.shawcroft@arm.com>
93 Nigel Stephens <nigel.stephens@arm.com>
94 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
95 Richard Earnshaw <rearnsha@arm.com>
96 Sofiane Naci <sofiane.naci@arm.com>
97 Tejas Belagod <tejas.belagod@arm.com>
98 Yufeng Zhang <yufeng.zhang@arm.com>
100 * aarch64.h: New file.
102 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
103 Maciej W. Rozycki <macro@codesourcery.com>
105 * mips.h (mips_opcode): Add the exclusions field.
106 (OPCODE_IS_MEMBER): Remove macro.
107 (cpu_is_member): New inline function.
108 (opcode_is_member): Likewise.
110 2012-07-31 Chao-Ying Fu <fu@mips.com>
111 Catherine Moore <clm@codesourcery.com>
112 Maciej W. Rozycki <macro@codesourcery.com>
114 * mips.h: Document microMIPS DSP ASE usage.
115 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
116 microMIPS DSP ASE support.
117 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
118 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
119 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
120 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
121 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
122 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
123 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
125 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
127 * mips.h: Fix a typo in description.
129 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
131 * avr.h: (AVR_ISA_XCH): New define.
132 (AVR_ISA_XMEGA): Use it.
133 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
135 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
137 * m68hc11.h: Add XGate definitions.
138 (struct m68hc11_opcode): Add xg_mask field.
140 2012-05-14 Catherine Moore <clm@codesourcery.com>
141 Maciej W. Rozycki <macro@codesourcery.com>
142 Rhonda Wittels <rhonda@codesourcery.com>
144 * ppc.h (PPC_OPCODE_VLE): New definition.
145 (PPC_OP_SA): New macro.
146 (PPC_OP_SE_VLE): New macro.
147 (PPC_OP): Use a variable shift amount.
148 (powerpc_operand): Update comments.
149 (PPC_OPSHIFT_INV): New macro.
150 (PPC_OPERAND_CR): Replace with...
151 (PPC_OPERAND_CR_BIT): ...this and
152 (PPC_OPERAND_CR_REG): ...this.
155 2012-05-03 Sean Keys <skeys@ipdatasys.com>
157 * xgate.h: Header file for XGATE assembler.
159 2012-04-27 David S. Miller <davem@davemloft.net>
161 * sparc.h: Document new arg code' )' for crypto RS3
164 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
165 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
166 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
167 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
168 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
169 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
170 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
171 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
172 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
173 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
174 HWCAP_CBCOND, HWCAP_CRC32): New defines.
176 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
178 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
180 2012-02-27 Alan Modra <amodra@gmail.com>
182 * crx.h (cst4_map): Update declaration.
184 2012-02-25 Walter Lee <walt@tilera.com>
186 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
188 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
189 TILEPRO_OPC_LW_TLS_SN.
191 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
193 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
194 (XRELEASE_PREFIX_OPCODE): Likewise.
196 2011-12-08 Andrew Pinski <apinski@cavium.com>
197 Adam Nemet <anemet@caviumnetworks.com>
199 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
200 (INSN_OCTEON2): New macro.
201 (CPU_OCTEON2): New macro.
202 (OPCODE_IS_MEMBER): Add Octeon2.
204 2011-11-29 Andrew Pinski <apinski@cavium.com>
206 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
207 (INSN_OCTEONP): New macro.
208 (CPU_OCTEONP): New macro.
209 (OPCODE_IS_MEMBER): Add Octeon+.
210 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
212 2011-11-01 DJ Delorie <dj@redhat.com>
216 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
218 * mips.h: Fix a typo in description.
220 2011-09-21 David S. Miller <davem@davemloft.net>
222 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
223 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
224 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
225 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
227 2011-08-09 Chao-ying Fu <fu@mips.com>
228 Maciej W. Rozycki <macro@codesourcery.com>
230 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
231 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
232 (INSN_ASE_MASK): Add the MCU bit.
233 (INSN_MCU): New macro.
234 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
235 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
237 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
239 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
240 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
241 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
242 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
243 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
244 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
245 (INSN2_READ_GPR_MMN): Likewise.
246 (INSN2_READ_FPR_D): Change the bit used.
247 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
248 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
249 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
250 (INSN2_COND_BRANCH): Likewise.
251 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
252 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
253 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
254 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
255 (INSN2_MOD_GPR_MN): Likewise.
257 2011-08-05 David S. Miller <davem@davemloft.net>
259 * sparc.h: Document new format codes '4', '5', and '('.
260 (OPF_LOW4, RS3): New macros.
262 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
264 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
265 order of flags documented.
267 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
269 * mips.h: Clarify the description of microMIPS instruction
271 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
273 2011-07-24 Chao-ying Fu <fu@mips.com>
274 Maciej W. Rozycki <macro@codesourcery.com>
276 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
277 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
278 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
279 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
280 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
281 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
282 (OP_MASK_RS3, OP_SH_RS3): Likewise.
283 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
284 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
285 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
286 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
287 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
288 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
289 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
290 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
291 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
292 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
293 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
294 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
295 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
296 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
297 (INSN_WRITE_GPR_S): New macro.
298 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
299 (INSN2_READ_FPR_D): Likewise.
300 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
301 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
302 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
303 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
304 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
305 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
306 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
307 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
308 (CPU_MICROMIPS): New macro.
309 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
310 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
311 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
312 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
313 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
314 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
315 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
316 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
317 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
318 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
319 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
320 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
321 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
322 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
323 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
324 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
325 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
326 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
327 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
328 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
329 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
330 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
331 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
332 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
333 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
334 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
335 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
336 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
337 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
338 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
339 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
340 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
341 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
342 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
343 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
344 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
345 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
346 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
347 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
348 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
349 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
350 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
351 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
352 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
353 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
354 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
355 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
356 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
357 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
358 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
359 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
360 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
361 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
362 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
363 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
364 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
365 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
366 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
367 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
368 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
369 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
370 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
371 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
372 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
373 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
374 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
375 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
376 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
377 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
378 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
379 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
380 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
381 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
382 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
383 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
384 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
385 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
386 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
387 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
388 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
389 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
390 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
391 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
392 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
393 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
394 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
395 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
396 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
397 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
398 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
399 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
400 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
401 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
402 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
403 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
404 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
405 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
406 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
407 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
408 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
409 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
410 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
411 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
412 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
413 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
414 (micromips_opcodes): New declaration.
415 (bfd_micromips_num_opcodes): Likewise.
417 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
419 * mips.h (INSN_TRAP): Rename to...
420 (INSN_NO_DELAY_SLOT): ... this.
421 (INSN_SYNC): Remove macro.
423 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
425 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
426 a duplicate of AVR_ISA_SPM.
428 2011-07-01 Nick Clifton <nickc@redhat.com>
430 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
432 2011-06-18 Robin Getz <robin.getz@analog.com>
434 * bfin.h (is_macmod_signed): New func
436 2011-06-18 Mike Frysinger <vapier@gentoo.org>
438 * bfin.h (is_macmod_pmove): Add missing space before func args.
439 (is_macmod_hmove): Likewise.
441 2011-06-13 Walter Lee <walt@tilera.com>
443 * tilegx.h: New file.
444 * tilepro.h: New file.
446 2011-05-31 Paul Brook <paul@codesourcery.com>
448 * arm.h (ARM_ARCH_V7R_IDIV): Define.
450 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
452 * s390.h: Replace S390_OPERAND_REG_EVEN with
453 S390_OPERAND_REG_PAIR.
455 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
457 * s390.h: Add S390_OPCODE_REG_EVEN flag.
459 2011-04-18 Julian Brown <julian@codesourcery.com>
461 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
463 2011-04-11 Dan McDonald <dan@wellkeeper.com>
466 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
468 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
470 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
471 New instruction set flags.
472 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
474 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
476 * mips.h (M_PREF_AB): New enum value.
478 2011-02-12 Mike Frysinger <vapier@gentoo.org>
480 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
482 (is_macmod_pmove, is_macmod_hmove): New functions.
484 2011-02-11 Mike Frysinger <vapier@gentoo.org>
486 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
488 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
490 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
491 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
493 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
496 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
499 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
502 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
504 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
506 * mips.h: Update commentary after last commit.
508 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
510 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
511 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
512 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
514 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
516 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
518 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
520 * mips.h: Fix previous commit.
522 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
524 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
525 (INSN_LOONGSON_3A): Clear bit 31.
527 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
530 * arm.h (ARM_AEXT_V6M_ONLY): New define.
531 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
532 (ARM_ARCH_V6M_ONLY): New define.
534 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
536 * mips.h (INSN_LOONGSON_3A): Defined.
537 (CPU_LOONGSON_3A): Defined.
538 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
540 2010-10-09 Matt Rice <ratmice@gmail.com>
542 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
543 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
545 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
547 * arm.h (ARM_EXT_VIRT): New define.
548 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
549 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
552 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
554 * arm.h (ARM_AEXT_ADIV): New define.
555 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
557 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
559 * arm.h (ARM_EXT_OS): New define.
560 (ARM_AEXT_V6SM): Likewise.
561 (ARM_ARCH_V6SM): Likewise.
563 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
565 * arm.h (ARM_EXT_MP): Add.
566 (ARM_ARCH_V7A_MP): Likewise.
568 2010-09-22 Mike Frysinger <vapier@gentoo.org>
570 * bfin.h: Declare pseudoChr structs/defines.
572 2010-09-21 Mike Frysinger <vapier@gentoo.org>
574 * bfin.h: Strip trailing whitespace.
576 2010-07-29 DJ Delorie <dj@redhat.com>
578 * rx.h (RX_Operand_Type): Add TwoReg.
579 (RX_Opcode_ID): Remove ediv and ediv2.
581 2010-07-27 DJ Delorie <dj@redhat.com>
583 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
585 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
586 Ina Pandit <ina.pandit@kpitcummins.com>
588 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
589 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
590 PROCESSOR_V850E2_ALL.
591 Remove PROCESSOR_V850EA support.
592 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
593 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
594 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
595 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
596 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
597 V850_OPERAND_PERCENT.
598 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
600 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
603 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
605 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
606 (MIPS16_INSN_BRANCH): Rename to...
607 (MIPS16_INSN_COND_BRANCH): ... this.
609 2010-07-03 Alan Modra <amodra@gmail.com>
611 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
612 Renumber other PPC_OPCODE defines.
614 2010-07-03 Alan Modra <amodra@gmail.com>
616 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
618 2010-06-29 Alan Modra <amodra@gmail.com>
620 * maxq.h: Delete file.
622 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
624 * ppc.h (PPC_OPCODE_E500): Define.
626 2010-05-26 Catherine Moore <clm@codesourcery.com>
628 * opcode/mips.h (INSN_MIPS16): Remove.
630 2010-04-21 Joseph Myers <joseph@codesourcery.com>
632 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
634 2010-04-15 Nick Clifton <nickc@redhat.com>
636 * alpha.h: Update copyright notice to use GPLv3.
642 * convex.h: Likewise.
656 * m68hc11.h: Likewise.
662 * mn10200.h: Likewise.
663 * mn10300.h: Likewise.
664 * msp430.h: Likewise.
675 * score-datadep.h: Likewise.
676 * score-inst.h: Likewise.
678 * spu-insns.h: Likewise.
682 * tic54x.h: Likewise.
687 2010-03-25 Joseph Myers <joseph@codesourcery.com>
689 * tic6x-control-registers.h, tic6x-insn-formats.h,
690 tic6x-opcode-table.h, tic6x.h: New.
692 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
694 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
696 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
698 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
700 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
702 * ia64.h (ia64_find_opcode): Remove argument name.
703 (ia64_find_next_opcode): Likewise.
704 (ia64_dis_opcode): Likewise.
705 (ia64_free_opcode): Likewise.
706 (ia64_find_dependency): Likewise.
708 2009-11-22 Doug Evans <dje@sebabeach.org>
710 * cgen.h: Include bfd_stdint.h.
711 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
713 2009-11-18 Paul Brook <paul@codesourcery.com>
715 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
717 2009-11-17 Paul Brook <paul@codesourcery.com>
718 Daniel Jacobowitz <dan@codesourcery.com>
720 * arm.h (ARM_EXT_V6_DSP): Define.
721 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
722 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
724 2009-11-04 DJ Delorie <dj@redhat.com>
726 * rx.h (rx_decode_opcode) (mvtipl): Add.
727 (mvtcp, mvfcp, opecp): Remove.
729 2009-11-02 Paul Brook <paul@codesourcery.com>
731 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
732 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
733 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
734 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
735 FPU_ARCH_NEON_VFP_V4): Define.
737 2009-10-23 Doug Evans <dje@sebabeach.org>
739 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
740 * cgen.h: Update. Improve multi-inclusion macro name.
742 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
744 * ppc.h (PPC_OPCODE_476): Define.
746 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
748 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
750 2009-09-29 DJ Delorie <dj@redhat.com>
754 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
756 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
758 2009-09-21 Ben Elliston <bje@au.ibm.com>
760 * ppc.h (PPC_OPCODE_PPCA2): New.
762 2009-09-05 Martin Thuresson <martin@mtme.org>
764 * ia64.h (struct ia64_operand): Renamed member class to op_class.
766 2009-08-29 Martin Thuresson <martin@mtme.org>
768 * tic30.h (template): Rename type template to
769 insn_template. Updated code to use new name.
770 * tic54x.h (template): Rename type template to
773 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
775 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
777 2009-06-11 Anthony Green <green@moxielogic.com>
779 * moxie.h (MOXIE_F3_PCREL): Define.
780 (moxie_form3_opc_info): Grow.
782 2009-06-06 Anthony Green <green@moxielogic.com>
784 * moxie.h (MOXIE_F1_M): Define.
786 2009-04-15 Anthony Green <green@moxielogic.com>
790 2009-04-06 DJ Delorie <dj@redhat.com>
792 * h8300.h: Add relaxation attributes to MOVA opcodes.
794 2009-03-10 Alan Modra <amodra@bigpond.net.au>
796 * ppc.h (ppc_parse_cpu): Declare.
798 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
800 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
801 and _IMM11 for mbitclr and mbitset.
802 * score-datadep.h: Update dependency information.
804 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
806 * ppc.h (PPC_OPCODE_POWER7): New.
808 2009-02-06 Doug Evans <dje@google.com>
810 * i386.h: Add comment regarding sse* insns and prefixes.
812 2009-02-03 Sandip Matte <sandip@rmicorp.com>
814 * mips.h (INSN_XLR): Define.
815 (INSN_CHIP_MASK): Update.
817 (OPCODE_IS_MEMBER): Update.
818 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
820 2009-01-28 Doug Evans <dje@google.com>
822 * opcode/i386.h: Add multiple inclusion protection.
823 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
824 (EDI_REG_NUM): New macros.
825 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
826 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
827 (REX_PREFIX_P): New macro.
829 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
831 * ppc.h (struct powerpc_opcode): New field "deprecated".
832 (PPC_OPCODE_NOPOWER4): Delete.
834 2008-11-28 Joshua Kinard <kumba@gentoo.org>
836 * mips.h: Define CPU_R14000, CPU_R16000.
837 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
839 2008-11-18 Catherine Moore <clm@codesourcery.com>
841 * arm.h (FPU_NEON_FP16): New.
842 (FPU_ARCH_NEON_FP16): New.
844 2008-11-06 Chao-ying Fu <fu@mips.com>
846 * mips.h: Doucument '1' for 5-bit sync type.
848 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
850 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
853 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
855 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
857 2008-07-30 Michael J. Eager <eager@eagercon.com>
859 * ppc.h (PPC_OPCODE_405): Define.
860 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
862 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
864 * ppc.h (ppc_cpu_t): New typedef.
865 (struct powerpc_opcode <flags>): Use it.
866 (struct powerpc_operand <insert, extract>): Likewise.
867 (struct powerpc_macro <flags>): Likewise.
869 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
871 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
872 Update comment before MIPS16 field descriptors to mention MIPS16.
873 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
875 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
876 New bit masks and shift counts for cins and exts.
878 * mips.h: Document new field descriptors +Q.
879 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
881 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
883 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
884 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
886 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
888 * ppc.h: (PPC_OPCODE_E500MC): New.
890 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
892 * i386.h (MAX_OPERANDS): Set to 5.
893 (MAX_MNEM_SIZE): Changed to 20.
895 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
897 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
899 2008-03-09 Paul Brook <paul@codesourcery.com>
901 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
903 2008-03-04 Paul Brook <paul@codesourcery.com>
905 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
906 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
907 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
909 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
910 Nick Clifton <nickc@redhat.com>
913 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
914 with a 32-bit displacement but without the top bit of the 4th byte
917 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
919 * cr16.h (cr16_num_optab): Declared.
921 2008-02-14 Hakan Ardo <hakan@debian.org>
924 * avr.h (AVR_ISA_2xxe): Define.
926 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
928 * mips.h: Update copyright.
929 (INSN_CHIP_MASK): New macro.
930 (INSN_OCTEON): New macro.
931 (CPU_OCTEON): New macro.
932 (OPCODE_IS_MEMBER): Handle Octeon instructions.
934 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
936 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
938 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
940 * avr.h (AVR_ISA_USB162): Add new opcode set.
941 (AVR_ISA_AVR3): Likewise.
943 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
945 * mips.h (INSN_LOONGSON_2E): New.
946 (INSN_LOONGSON_2F): New.
947 (CPU_LOONGSON_2E): New.
948 (CPU_LOONGSON_2F): New.
949 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
951 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
953 * mips.h (INSN_ISA*): Redefine certain values as an
954 enumeration. Update comments.
955 (mips_isa_table): New.
956 (ISA_MIPS*): Redefine to match enumeration.
957 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
960 2007-08-08 Ben Elliston <bje@au.ibm.com>
962 * ppc.h (PPC_OPCODE_PPCPS): New.
964 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
966 * m68k.h: Document j K & E.
968 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
970 * cr16.h: New file for CR16 target.
972 2007-05-02 Alan Modra <amodra@bigpond.net.au>
974 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
976 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
978 * m68k.h (mcfisa_c): New.
979 (mcfusp, mcf_mask): Adjust.
981 2007-04-20 Alan Modra <amodra@bigpond.net.au>
983 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
984 (num_powerpc_operands): Declare.
985 (PPC_OPERAND_SIGNED et al): Redefine as hex.
986 (PPC_OPERAND_PLUS1): Define.
988 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
990 * i386.h (REX_MODE64): Renamed to ...
992 (REX_EXTX): Renamed to ...
994 (REX_EXTY): Renamed to ...
996 (REX_EXTZ): Renamed to ...
999 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386.h: Add entries from config/tc-i386.h and move tables
1002 to opcodes/i386-opc.h.
1004 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1006 * i386.h (FloatDR): Removed.
1007 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1009 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1011 * spu-insns.h: Add soma double-float insns.
1013 2007-02-20 Thiemo Seufer <ths@mips.com>
1014 Chao-Ying Fu <fu@mips.com>
1016 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1017 (INSN_DSPR2): Add flag for DSP R2 instructions.
1018 (M_BALIGN): New macro.
1020 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1022 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1023 and Seg3ShortFrom with Shortform.
1025 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1028 * i386.h (i386_optab): Put the real "test" before the pseudo
1031 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1033 * m68k.h (m68010up): OR fido_a.
1035 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1037 * m68k.h (fido_a): New.
1039 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1041 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1042 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1045 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1049 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1051 * score-inst.h (enum score_insn_type): Add Insn_internal.
1053 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1054 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1055 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1056 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1057 Alan Modra <amodra@bigpond.net.au>
1059 * spu-insns.h: New file.
1062 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1064 * ppc.h (PPC_OPCODE_CELL): Define.
1066 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1068 * i386.h : Modify opcode to support for the change in POPCNT opcode
1069 in amdfam10 architecture.
1071 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1073 * i386.h: Replace CpuMNI with CpuSSSE3.
1075 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1076 Joseph Myers <joseph@codesourcery.com>
1077 Ian Lance Taylor <ian@wasabisystems.com>
1078 Ben Elliston <bje@wasabisystems.com>
1080 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1082 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1084 * score-datadep.h: New file.
1085 * score-inst.h: New file.
1087 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1089 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1090 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1091 movdq2q and movq2dq.
1093 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1094 Michael Meissner <michael.meissner@amd.com>
1096 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1098 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1100 * i386.h (i386_optab): Add "nop" with memory reference.
1102 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1104 * i386.h (i386_optab): Update comment for 64bit NOP.
1106 2006-06-06 Ben Elliston <bje@au.ibm.com>
1107 Anton Blanchard <anton@samba.org>
1109 * ppc.h (PPC_OPCODE_POWER6): Define.
1112 2006-06-05 Thiemo Seufer <ths@mips.com>
1114 * mips.h: Improve description of MT flags.
1116 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1118 * m68k.h (mcf_mask): Define.
1120 2006-05-05 Thiemo Seufer <ths@mips.com>
1121 David Ung <davidu@mips.com>
1123 * mips.h (enum): Add macro M_CACHE_AB.
1125 2006-05-04 Thiemo Seufer <ths@mips.com>
1126 Nigel Stephens <nigel@mips.com>
1127 David Ung <davidu@mips.com>
1129 * mips.h: Add INSN_SMARTMIPS define.
1131 2006-04-30 Thiemo Seufer <ths@mips.com>
1132 David Ung <davidu@mips.com>
1134 * mips.h: Defines udi bits and masks. Add description of
1135 characters which may appear in the args field of udi
1138 2006-04-26 Thiemo Seufer <ths@networkno.de>
1140 * mips.h: Improve comments describing the bitfield instruction
1143 2006-04-26 Julian Brown <julian@codesourcery.com>
1145 * arm.h (FPU_VFP_EXT_V3): Define constant.
1146 (FPU_NEON_EXT_V1): Likewise.
1147 (FPU_VFP_HARD): Update.
1148 (FPU_VFP_V3): Define macro.
1149 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1151 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1153 * avr.h (AVR_ISA_PWMx): New.
1155 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1157 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1158 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1159 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1160 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1161 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1163 2006-03-10 Paul Brook <paul@codesourcery.com>
1165 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1167 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1169 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1170 first. Correct mask of bb "B" opcode.
1172 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1174 * i386.h (i386_optab): Support Intel Merom New Instructions.
1176 2006-02-24 Paul Brook <paul@codesourcery.com>
1178 * arm.h: Add V7 feature bits.
1180 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1182 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1184 2006-01-31 Paul Brook <paul@codesourcery.com>
1185 Richard Earnshaw <rearnsha@arm.com>
1187 * arm.h: Use ARM_CPU_FEATURE.
1188 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1189 (arm_feature_set): Change to a structure.
1190 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1191 ARM_FEATURE): New macros.
1193 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1195 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1196 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1197 (ADD_PC_INCR_OPCODE): Don't define.
1199 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1202 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1204 2005-11-14 David Ung <davidu@mips.com>
1206 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1207 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1208 save/restore encoding of the args field.
1210 2005-10-28 Dave Brolley <brolley@redhat.com>
1212 Contribute the following changes:
1213 2005-02-16 Dave Brolley <brolley@redhat.com>
1215 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1216 cgen_isa_mask_* to cgen_bitset_*.
1219 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1221 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1222 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1223 (CGEN_CPU_TABLE): Make isas a ponter.
1225 2003-09-29 Dave Brolley <brolley@redhat.com>
1227 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1228 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1229 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1231 2002-12-13 Dave Brolley <brolley@redhat.com>
1233 * cgen.h (symcat.h): #include it.
1234 (cgen-bitset.h): #include it.
1235 (CGEN_ATTR_VALUE_TYPE): Now a union.
1236 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1237 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1238 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1239 * cgen-bitset.h: New file.
1241 2005-09-30 Catherine Moore <clm@cm00re.com>
1245 2005-10-24 Jan Beulich <jbeulich@novell.com>
1247 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1250 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1252 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1253 Add FLAG_STRICT to pa10 ftest opcode.
1255 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1257 * hppa.h (pa_opcodes): Remove lha entries.
1259 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1261 * hppa.h (FLAG_STRICT): Revise comment.
1262 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1263 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1266 2005-09-30 Catherine Moore <clm@cm00re.com>
1270 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1272 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1274 2005-09-06 Chao-ying Fu <fu@mips.com>
1276 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1277 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1279 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1280 (INSN_ASE_MASK): Update to include INSN_MT.
1281 (INSN_MT): New define for MT ASE.
1283 2005-08-25 Chao-ying Fu <fu@mips.com>
1285 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1286 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1287 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1288 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1289 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1290 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1292 (INSN_DSP): New define for DSP ASE.
1294 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1298 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1300 * ppc.h (PPC_OPCODE_E300): Define.
1302 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1304 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1306 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1309 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1312 2005-07-27 Jan Beulich <jbeulich@novell.com>
1314 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1315 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1316 Add movq-s as 64-bit variants of movd-s.
1318 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1320 * hppa.h: Fix punctuation in comment.
1322 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1323 implicit space-register addressing. Set space-register bits on opcodes
1324 using implicit space-register addressing. Add various missing pa20
1325 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1326 space-register addressing. Use "fE" instead of "fe" in various
1329 2005-07-18 Jan Beulich <jbeulich@novell.com>
1331 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1333 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1335 * i386.h (i386_optab): Support Intel VMX Instructions.
1337 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1339 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1341 2005-07-05 Jan Beulich <jbeulich@novell.com>
1343 * i386.h (i386_optab): Add new insns.
1345 2005-07-01 Nick Clifton <nickc@redhat.com>
1347 * sparc.h: Add typedefs to structure declarations.
1349 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1352 * i386.h (i386_optab): Update comments for 64bit addressing on
1353 mov. Allow 64bit addressing for mov and movq.
1355 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1357 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1358 respectively, in various floating-point load and store patterns.
1360 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1362 * hppa.h (FLAG_STRICT): Correct comment.
1363 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1364 PA 2.0 mneumonics when equivalent. Entries with cache control
1365 completers now require PA 1.1. Adjust whitespace.
1367 2005-05-19 Anton Blanchard <anton@samba.org>
1369 * ppc.h (PPC_OPCODE_POWER5): Define.
1371 2005-05-10 Nick Clifton <nickc@redhat.com>
1373 * Update the address and phone number of the FSF organization in
1374 the GPL notices in the following files:
1375 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1376 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1377 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1378 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1379 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1380 tic54x.h, tic80.h, v850.h, vax.h
1382 2005-05-09 Jan Beulich <jbeulich@novell.com>
1384 * i386.h (i386_optab): Add ht and hnt.
1386 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1388 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1389 Add xcrypt-ctr. Provide aliases without hyphens.
1391 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1393 Moved from ../ChangeLog
1395 2005-04-12 Paul Brook <paul@codesourcery.com>
1396 * m88k.h: Rename psr macros to avoid conflicts.
1398 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1399 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1400 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1401 and ARM_ARCH_V6ZKT2.
1403 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1404 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1405 Remove redundant instruction types.
1406 (struct argument): X_op - new field.
1407 (struct cst4_entry): Remove.
1408 (no_op_insn): Declare.
1410 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1411 * crx.h (enum argtype): Rename types, remove unused types.
1413 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1414 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1415 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1416 (enum operand_type): Rearrange operands, edit comments.
1417 replace us<N> with ui<N> for unsigned immediate.
1418 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1419 displacements (respectively).
1420 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1421 (instruction type): Add NO_TYPE_INS.
1422 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1423 (operand_entry): New field - 'flags'.
1424 (operand flags): New.
1426 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1427 * crx.h (operand_type): Remove redundant types i3, i4,
1429 Add new unsigned immediate types us3, us4, us5, us16.
1431 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1433 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1434 adjust them accordingly.
1436 2005-04-01 Jan Beulich <jbeulich@novell.com>
1438 * i386.h (i386_optab): Add rdtscp.
1440 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1442 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1443 between memory and segment register. Allow movq for moving between
1444 general-purpose register and segment register.
1446 2005-02-09 Jan Beulich <jbeulich@novell.com>
1449 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1450 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1453 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1455 * m68k.h (m68008, m68ec030, m68882): Remove.
1457 (cpu_m68k, cpu_cf): New.
1458 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1459 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1461 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1463 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1464 * cgen.h (enum cgen_parse_operand_type): Add
1465 CGEN_PARSE_OPERAND_SYMBOLIC.
1467 2005-01-21 Fred Fish <fnf@specifixinc.com>
1469 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1470 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1471 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1473 2005-01-19 Fred Fish <fnf@specifixinc.com>
1475 * mips.h (struct mips_opcode): Add new pinfo2 member.
1476 (INSN_ALIAS): New define for opcode table entries that are
1477 specific instances of another entry, such as 'move' for an 'or'
1478 with a zero operand.
1479 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1480 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1482 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1484 * mips.h (CPU_RM9000): Define.
1485 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1487 2004-11-25 Jan Beulich <jbeulich@novell.com>
1489 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1490 to/from test registers are illegal in 64-bit mode. Add missing
1491 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1492 (previously one had to explicitly encode a rex64 prefix). Re-enable
1493 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1494 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1496 2004-11-23 Jan Beulich <jbeulich@novell.com>
1498 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1499 available only with SSE2. Change the MMX additions introduced by SSE
1500 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1501 instructions by their now designated identifier (since combining i686
1502 and 3DNow! does not really imply 3DNow!A).
1504 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1506 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1507 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1509 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1510 Vineet Sharma <vineets@noida.hcltech.com>
1512 * maxq.h: New file: Disassembly information for the maxq port.
1514 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1516 * i386.h (i386_optab): Put back "movzb".
1518 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1520 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1521 comments. Remove member cris_ver_sim. Add members
1522 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1523 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1524 (struct cris_support_reg, struct cris_cond15): New types.
1525 (cris_conds15): Declare.
1526 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1527 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1528 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1529 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1530 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1531 SIZE_FIELD_UNSIGNED.
1533 2004-11-04 Jan Beulich <jbeulich@novell.com>
1535 * i386.h (sldx_Suf): Remove.
1536 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1537 (q_FP): Define, implying no REX64.
1538 (x_FP, sl_FP): Imply FloatMF.
1539 (i386_optab): Split reg and mem forms of moving from segment registers
1540 so that the memory forms can ignore the 16-/32-bit operand size
1541 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1542 all non-floating-point instructions. Unite 32- and 64-bit forms of
1543 movsx, movzx, and movd. Adjust floating point operations for the above
1544 changes to the *FP macros. Add DefaultSize to floating point control
1545 insns operating on larger memory ranges. Remove left over comments
1546 hinting at certain insns being Intel-syntax ones where the ones
1547 actually meant are already gone.
1549 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1551 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1554 2004-09-30 Paul Brook <paul@codesourcery.com>
1556 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1557 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1559 2004-09-11 Theodore A. Roth <troth@openavr.org>
1561 * avr.h: Add support for
1562 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1564 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1566 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1568 2004-08-24 Dmitry Diky <diwil@spec.ru>
1570 * msp430.h (msp430_opc): Add new instructions.
1571 (msp430_rcodes): Declare new instructions.
1572 (msp430_hcodes): Likewise..
1574 2004-08-13 Nick Clifton <nickc@redhat.com>
1577 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1580 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1582 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1584 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1586 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1588 2004-07-21 Jan Beulich <jbeulich@novell.com>
1590 * i386.h: Adjust instruction descriptions to better match the
1593 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1595 * arm.h: Remove all old content. Replace with architecture defines
1596 from gas/config/tc-arm.c.
1598 2004-07-09 Andreas Schwab <schwab@suse.de>
1600 * m68k.h: Fix comment.
1602 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1606 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1608 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1610 2004-05-24 Peter Barada <peter@the-baradas.com>
1612 * m68k.h: Add 'size' to m68k_opcode.
1614 2004-05-05 Peter Barada <peter@the-baradas.com>
1616 * m68k.h: Switch from ColdFire chip name to core variant.
1618 2004-04-22 Peter Barada <peter@the-baradas.com>
1620 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1621 descriptions for new EMAC cases.
1622 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1623 handle Motorola MAC syntax.
1624 Allow disassembly of ColdFire V4e object files.
1626 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1628 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1630 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1632 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1634 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1636 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1638 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1640 * i386.h (i386_optab): Added xstore/xcrypt insns.
1642 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1644 * h8300.h (32bit ldc/stc): Add relaxing support.
1646 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1648 * h8300.h (BITOP): Pass MEMRELAX flag.
1650 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1652 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1655 For older changes see ChangeLog-9103
1657 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1659 Copying and distribution of this file, with or without modification,
1660 are permitted in any medium without royalty provided the copyright
1661 notice and this notice are preserved.
1667 version-control: never