1 2014-05-19 Nick Clifton <nickc@redhat.com>
3 * msp430.h (struct msp430_operand_s): Add vshift field.
5 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
7 * mips.h (INSN_ISA_MASK): Updated.
8 (INSN_ISA32R3): New define.
9 (INSN_ISA32R5): New define.
10 (INSN_ISA64R3): New define.
11 (INSN_ISA64R5): New define.
12 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
13 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
14 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
16 (INSN_UPTO32R3): New define.
17 (INSN_UPTO32R5): New define.
18 (INSN_UPTO64R3): New define.
19 (INSN_UPTO64R5): New define.
20 (ISA_MIPS32R3): New define.
21 (ISA_MIPS32R5): New define.
22 (ISA_MIPS64R3): New define.
23 (ISA_MIPS64R5): New define.
24 (CPU_MIPS32R3): New define.
25 (CPU_MIPS32R5): New define.
26 (CPU_MIPS64R3): New define.
27 (CPU_MIPS64R5): New define.
29 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
31 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
33 2014-04-22 Christian Svensson <blue@cmd.nu>
37 2014-03-05 Alan Modra <amodra@gmail.com>
39 Update copyright years.
41 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
43 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
46 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
47 Wei-Cheng Wang <cole945@gmail.com>
49 * nds32.h: New file for Andes NDS32.
51 2013-12-07 Mike Frysinger <vapier@gentoo.org>
53 * bfin.h: Remove +x file mode.
55 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
57 * aarch64.h (aarch64_pstatefields): Change element type to
60 2013-11-18 Renlin Li <Renlin.Li@arm.com>
62 * arm.h (ARM_AEXT_V7VE): New define.
63 (ARM_ARCH_V7VE): New define.
64 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
66 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
70 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
72 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
73 (aarch64_sys_reg_writeonly_p): Ditto.
75 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
77 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
78 (aarch64_sys_reg_writeonly_p): Ditto.
80 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
82 * aarch64.h (aarch64_sys_reg): New typedef.
83 (aarch64_sys_regs): Change to define with the new type.
84 (aarch64_sys_reg_deprecated_p): Declare.
86 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
88 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
89 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
91 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
93 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
94 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
95 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
96 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
97 For MIPS, update extension character sequences after +.
98 (ASE_MSA): New define.
99 (ASE_MSA64): New define.
100 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
101 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
102 For microMIPS, update extension character sequences after +.
104 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
109 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
111 * mips.h: Remove references to "+I" and imm2_expr.
113 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
115 * mips.h (M_DEXT, M_DINS): Delete.
117 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
119 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
120 (mips_optional_operand_p): New function.
122 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
123 Richard Sandiford <rdsandiford@googlemail.com>
125 * mips.h: Document new VU0 operand characters.
126 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
127 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
128 (OP_REG_R5900_ACC): New mips_reg_operand_types.
129 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
130 (mips_vu0_channel_mask): Declare.
132 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
134 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
135 (mips_int_operand_min, mips_int_operand_max): New functions.
136 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
138 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
140 * mips.h (mips_decode_reg_operand): New function.
141 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
142 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
143 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
145 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
146 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
147 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
148 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
149 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
150 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
151 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
152 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
153 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
154 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
155 macros to cover the gaps.
156 (INSN2_MOD_SP): Replace with...
157 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
158 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
159 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
160 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
161 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
164 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
166 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
167 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
168 (MIPS16_INSN_COND_BRANCH): Delete.
170 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
171 Kirill Yukhin <kirill.yukhin@intel.com>
172 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
174 * i386.h (BND_PREFIX_OPCODE): New.
176 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
178 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
179 OP_SAVE_RESTORE_LIST.
180 (decode_mips16_operand): Declare.
182 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
184 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
185 (mips_operand, mips_int_operand, mips_mapped_int_operand)
186 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
187 (mips_pcrel_operand): New structures.
188 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
189 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
190 (decode_mips_operand, decode_micromips_operand): Declare.
192 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
194 * mips.h: Document MIPS16 "I" opcode.
196 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
198 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
199 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
200 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
201 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
202 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
203 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
204 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
205 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
206 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
207 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
208 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
209 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
210 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
212 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
213 (M_USD_AB): ...these.
215 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
217 * mips.h: Remove documentation of "[" and "]". Update documentation
218 of "k" and the MDMX formats.
220 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
222 * mips.h: Update documentation of "+s" and "+S".
224 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
226 * mips.h: Document "+i".
228 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
230 * mips.h: Remove "mi" documentation. Update "mh" documentation.
231 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
233 (INSN2_WRITE_GPR_MHI): Rename to...
234 (INSN2_WRITE_GPR_MH): ...this.
236 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
238 * mips.h: Remove documentation of "+D" and "+T".
240 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
242 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
243 Use "source" rather than "destination" for microMIPS "G".
245 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
247 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
250 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
252 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
254 2013-06-17 Catherine Moore <clm@codesourcery.com>
255 Maciej W. Rozycki <macro@codesourcery.com>
256 Chao-Ying Fu <fu@mips.com>
258 * mips.h (OP_SH_EVAOFFSET): Define.
259 (OP_MASK_EVAOFFSET): Define.
260 (INSN_ASE_MASK): Delete.
262 (M_CACHEE_AB, M_CACHEE_OB): New.
263 (M_LBE_OB, M_LBE_AB): New.
264 (M_LBUE_OB, M_LBUE_AB): New.
265 (M_LHE_OB, M_LHE_AB): New.
266 (M_LHUE_OB, M_LHUE_AB): New.
267 (M_LLE_AB, M_LLE_OB): New.
268 (M_LWE_OB, M_LWE_AB): New.
269 (M_LWLE_AB, M_LWLE_OB): New.
270 (M_LWRE_AB, M_LWRE_OB): New.
271 (M_PREFE_AB, M_PREFE_OB): New.
272 (M_SCE_AB, M_SCE_OB): New.
273 (M_SBE_OB, M_SBE_AB): New.
274 (M_SHE_OB, M_SHE_AB): New.
275 (M_SWE_OB, M_SWE_AB): New.
276 (M_SWLE_AB, M_SWLE_OB): New.
277 (M_SWRE_AB, M_SWRE_OB): New.
278 (MICROMIPSOP_SH_EVAOFFSET): Define.
279 (MICROMIPSOP_MASK_EVAOFFSET): Define.
281 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
283 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
285 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
287 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
289 2013-05-09 Andrew Pinski <apinski@cavium.com>
291 * mips.h (OP_MASK_CODE10): Correct definition.
292 (OP_SH_CODE10): Likewise.
293 Add a comment that "+J" is used now for OP_*CODE10.
294 (INSN_ASE_MASK): Update.
295 (INSN_VIRT): New macro.
296 (INSN_VIRT64): New macro
298 2013-05-02 Nick Clifton <nickc@redhat.com>
300 * msp430.h: Add patterns for MSP430X instructions.
302 2013-04-06 David S. Miller <davem@davemloft.net>
304 * sparc.h (F_PREFERRED): Define.
305 (F_PREF_ALIAS): Define.
307 2013-04-03 Nick Clifton <nickc@redhat.com>
309 * v850.h (V850_INVERSE_PCREL): Define.
311 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
314 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
316 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
319 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
321 * tic6xc-opcode-table.h: Add 16-bit insns.
322 * tic6x.h: Add support for 16-bit insns.
324 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
326 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
327 and mov.b/w/l Rs,@(d:32,ERd).
329 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
332 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
333 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
334 tic6x_operand_xregpair operand coding type.
335 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
336 opcode field, usu ORXREGD1324 for the src2 operand and remove the
339 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
342 * tic6x.h (enum tic6x_coding_method): Add
343 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
344 separately the msb and lsb of a register pair. This is needed to
345 encode the opcodes in the same way as TI assembler does.
346 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
347 and rsqrdp opcodes to use the new field coding types.
349 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
351 * arm.h (CRC_EXT_ARMV8): New constant.
352 (ARCH_CRC_ARMV8): New macro.
354 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
356 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
358 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
359 Andrew Jenner <andrew@codesourcery.com>
361 Based on patches from Altera Corporation.
365 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
367 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
369 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
372 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
374 2013-01-24 Nick Clifton <nickc@redhat.com>
376 * v850.h: Add e3v5 support.
378 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
380 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
382 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
384 * ppc.h (PPC_OPCODE_POWER8): New define.
385 (PPC_OPCODE_HTM): Likewise.
387 2013-01-10 Will Newton <will.newton@imgtec.com>
391 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
393 * cr16.h (make_instruction): Rename to cr16_make_instruction.
394 (match_opcode): Rename to cr16_match_opcode.
396 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
398 * mips.h: Add support for r5900 instructions including lq and sq.
400 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
402 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
403 (make_instruction,match_opcode): Added function prototypes.
404 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
406 2012-11-23 Alan Modra <amodra@gmail.com>
408 * ppc.h (ppc_parse_cpu): Update prototype.
410 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
412 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
413 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
415 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
417 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
419 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
421 * ia64.h (ia64_opnd): Add new operand types.
423 2012-08-21 David S. Miller <davem@davemloft.net>
425 * sparc.h (F3F4): New macro.
427 2012-08-13 Ian Bolton <ian.bolton@arm.com>
428 Laurent Desnogues <laurent.desnogues@arm.com>
429 Jim MacArthur <jim.macarthur@arm.com>
430 Marcus Shawcroft <marcus.shawcroft@arm.com>
431 Nigel Stephens <nigel.stephens@arm.com>
432 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
433 Richard Earnshaw <rearnsha@arm.com>
434 Sofiane Naci <sofiane.naci@arm.com>
435 Tejas Belagod <tejas.belagod@arm.com>
436 Yufeng Zhang <yufeng.zhang@arm.com>
438 * aarch64.h: New file.
440 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
441 Maciej W. Rozycki <macro@codesourcery.com>
443 * mips.h (mips_opcode): Add the exclusions field.
444 (OPCODE_IS_MEMBER): Remove macro.
445 (cpu_is_member): New inline function.
446 (opcode_is_member): Likewise.
448 2012-07-31 Chao-Ying Fu <fu@mips.com>
449 Catherine Moore <clm@codesourcery.com>
450 Maciej W. Rozycki <macro@codesourcery.com>
452 * mips.h: Document microMIPS DSP ASE usage.
453 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
454 microMIPS DSP ASE support.
455 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
456 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
457 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
458 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
459 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
460 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
461 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
463 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
465 * mips.h: Fix a typo in description.
467 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
469 * avr.h: (AVR_ISA_XCH): New define.
470 (AVR_ISA_XMEGA): Use it.
471 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
473 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
475 * m68hc11.h: Add XGate definitions.
476 (struct m68hc11_opcode): Add xg_mask field.
478 2012-05-14 Catherine Moore <clm@codesourcery.com>
479 Maciej W. Rozycki <macro@codesourcery.com>
480 Rhonda Wittels <rhonda@codesourcery.com>
482 * ppc.h (PPC_OPCODE_VLE): New definition.
483 (PPC_OP_SA): New macro.
484 (PPC_OP_SE_VLE): New macro.
485 (PPC_OP): Use a variable shift amount.
486 (powerpc_operand): Update comments.
487 (PPC_OPSHIFT_INV): New macro.
488 (PPC_OPERAND_CR): Replace with...
489 (PPC_OPERAND_CR_BIT): ...this and
490 (PPC_OPERAND_CR_REG): ...this.
493 2012-05-03 Sean Keys <skeys@ipdatasys.com>
495 * xgate.h: Header file for XGATE assembler.
497 2012-04-27 David S. Miller <davem@davemloft.net>
499 * sparc.h: Document new arg code' )' for crypto RS3
502 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
503 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
504 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
505 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
506 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
507 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
508 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
509 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
510 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
511 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
512 HWCAP_CBCOND, HWCAP_CRC32): New defines.
514 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
516 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
518 2012-02-27 Alan Modra <amodra@gmail.com>
520 * crx.h (cst4_map): Update declaration.
522 2012-02-25 Walter Lee <walt@tilera.com>
524 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
526 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
527 TILEPRO_OPC_LW_TLS_SN.
529 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
531 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
532 (XRELEASE_PREFIX_OPCODE): Likewise.
534 2011-12-08 Andrew Pinski <apinski@cavium.com>
535 Adam Nemet <anemet@caviumnetworks.com>
537 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
538 (INSN_OCTEON2): New macro.
539 (CPU_OCTEON2): New macro.
540 (OPCODE_IS_MEMBER): Add Octeon2.
542 2011-11-29 Andrew Pinski <apinski@cavium.com>
544 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
545 (INSN_OCTEONP): New macro.
546 (CPU_OCTEONP): New macro.
547 (OPCODE_IS_MEMBER): Add Octeon+.
548 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
550 2011-11-01 DJ Delorie <dj@redhat.com>
554 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
556 * mips.h: Fix a typo in description.
558 2011-09-21 David S. Miller <davem@davemloft.net>
560 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
561 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
562 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
563 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
565 2011-08-09 Chao-ying Fu <fu@mips.com>
566 Maciej W. Rozycki <macro@codesourcery.com>
568 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
569 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
570 (INSN_ASE_MASK): Add the MCU bit.
571 (INSN_MCU): New macro.
572 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
573 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
575 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
577 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
578 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
579 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
580 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
581 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
582 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
583 (INSN2_READ_GPR_MMN): Likewise.
584 (INSN2_READ_FPR_D): Change the bit used.
585 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
586 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
587 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
588 (INSN2_COND_BRANCH): Likewise.
589 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
590 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
591 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
592 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
593 (INSN2_MOD_GPR_MN): Likewise.
595 2011-08-05 David S. Miller <davem@davemloft.net>
597 * sparc.h: Document new format codes '4', '5', and '('.
598 (OPF_LOW4, RS3): New macros.
600 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
602 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
603 order of flags documented.
605 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
607 * mips.h: Clarify the description of microMIPS instruction
609 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
611 2011-07-24 Chao-ying Fu <fu@mips.com>
612 Maciej W. Rozycki <macro@codesourcery.com>
614 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
615 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
616 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
617 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
618 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
619 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
620 (OP_MASK_RS3, OP_SH_RS3): Likewise.
621 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
622 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
623 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
624 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
625 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
626 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
627 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
628 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
629 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
630 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
631 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
632 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
633 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
634 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
635 (INSN_WRITE_GPR_S): New macro.
636 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
637 (INSN2_READ_FPR_D): Likewise.
638 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
639 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
640 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
641 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
642 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
643 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
644 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
645 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
646 (CPU_MICROMIPS): New macro.
647 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
648 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
649 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
650 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
651 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
652 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
653 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
654 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
655 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
656 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
657 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
658 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
659 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
660 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
661 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
662 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
663 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
664 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
665 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
666 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
667 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
668 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
669 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
670 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
671 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
672 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
673 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
674 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
675 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
676 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
677 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
678 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
679 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
680 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
681 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
682 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
683 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
684 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
685 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
686 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
687 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
688 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
689 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
690 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
691 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
692 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
693 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
694 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
695 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
696 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
697 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
698 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
699 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
700 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
701 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
702 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
703 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
704 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
705 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
706 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
707 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
708 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
709 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
710 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
711 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
712 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
713 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
714 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
715 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
716 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
717 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
718 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
719 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
720 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
721 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
722 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
723 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
724 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
725 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
726 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
727 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
728 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
729 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
730 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
731 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
732 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
733 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
734 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
735 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
736 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
737 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
738 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
739 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
740 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
741 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
742 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
743 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
744 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
745 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
746 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
747 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
748 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
749 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
750 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
751 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
752 (micromips_opcodes): New declaration.
753 (bfd_micromips_num_opcodes): Likewise.
755 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
757 * mips.h (INSN_TRAP): Rename to...
758 (INSN_NO_DELAY_SLOT): ... this.
759 (INSN_SYNC): Remove macro.
761 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
763 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
764 a duplicate of AVR_ISA_SPM.
766 2011-07-01 Nick Clifton <nickc@redhat.com>
768 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
770 2011-06-18 Robin Getz <robin.getz@analog.com>
772 * bfin.h (is_macmod_signed): New func
774 2011-06-18 Mike Frysinger <vapier@gentoo.org>
776 * bfin.h (is_macmod_pmove): Add missing space before func args.
777 (is_macmod_hmove): Likewise.
779 2011-06-13 Walter Lee <walt@tilera.com>
781 * tilegx.h: New file.
782 * tilepro.h: New file.
784 2011-05-31 Paul Brook <paul@codesourcery.com>
786 * arm.h (ARM_ARCH_V7R_IDIV): Define.
788 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
790 * s390.h: Replace S390_OPERAND_REG_EVEN with
791 S390_OPERAND_REG_PAIR.
793 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
795 * s390.h: Add S390_OPCODE_REG_EVEN flag.
797 2011-04-18 Julian Brown <julian@codesourcery.com>
799 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
801 2011-04-11 Dan McDonald <dan@wellkeeper.com>
804 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
806 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
808 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
809 New instruction set flags.
810 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
812 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
814 * mips.h (M_PREF_AB): New enum value.
816 2011-02-12 Mike Frysinger <vapier@gentoo.org>
818 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
820 (is_macmod_pmove, is_macmod_hmove): New functions.
822 2011-02-11 Mike Frysinger <vapier@gentoo.org>
824 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
826 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
828 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
829 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
831 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
834 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
837 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
840 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
842 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
844 * mips.h: Update commentary after last commit.
846 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
848 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
849 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
850 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
852 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
854 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
856 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
858 * mips.h: Fix previous commit.
860 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
862 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
863 (INSN_LOONGSON_3A): Clear bit 31.
865 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
868 * arm.h (ARM_AEXT_V6M_ONLY): New define.
869 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
870 (ARM_ARCH_V6M_ONLY): New define.
872 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
874 * mips.h (INSN_LOONGSON_3A): Defined.
875 (CPU_LOONGSON_3A): Defined.
876 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
878 2010-10-09 Matt Rice <ratmice@gmail.com>
880 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
881 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
883 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
885 * arm.h (ARM_EXT_VIRT): New define.
886 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
887 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
890 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
892 * arm.h (ARM_AEXT_ADIV): New define.
893 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
895 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
897 * arm.h (ARM_EXT_OS): New define.
898 (ARM_AEXT_V6SM): Likewise.
899 (ARM_ARCH_V6SM): Likewise.
901 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
903 * arm.h (ARM_EXT_MP): Add.
904 (ARM_ARCH_V7A_MP): Likewise.
906 2010-09-22 Mike Frysinger <vapier@gentoo.org>
908 * bfin.h: Declare pseudoChr structs/defines.
910 2010-09-21 Mike Frysinger <vapier@gentoo.org>
912 * bfin.h: Strip trailing whitespace.
914 2010-07-29 DJ Delorie <dj@redhat.com>
916 * rx.h (RX_Operand_Type): Add TwoReg.
917 (RX_Opcode_ID): Remove ediv and ediv2.
919 2010-07-27 DJ Delorie <dj@redhat.com>
921 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
923 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
924 Ina Pandit <ina.pandit@kpitcummins.com>
926 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
927 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
928 PROCESSOR_V850E2_ALL.
929 Remove PROCESSOR_V850EA support.
930 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
931 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
932 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
933 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
934 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
935 V850_OPERAND_PERCENT.
936 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
938 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
941 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
943 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
944 (MIPS16_INSN_BRANCH): Rename to...
945 (MIPS16_INSN_COND_BRANCH): ... this.
947 2010-07-03 Alan Modra <amodra@gmail.com>
949 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
950 Renumber other PPC_OPCODE defines.
952 2010-07-03 Alan Modra <amodra@gmail.com>
954 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
956 2010-06-29 Alan Modra <amodra@gmail.com>
958 * maxq.h: Delete file.
960 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
962 * ppc.h (PPC_OPCODE_E500): Define.
964 2010-05-26 Catherine Moore <clm@codesourcery.com>
966 * opcode/mips.h (INSN_MIPS16): Remove.
968 2010-04-21 Joseph Myers <joseph@codesourcery.com>
970 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
972 2010-04-15 Nick Clifton <nickc@redhat.com>
974 * alpha.h: Update copyright notice to use GPLv3.
980 * convex.h: Likewise.
994 * m68hc11.h: Likewise.
1000 * mn10200.h: Likewise.
1001 * mn10300.h: Likewise.
1002 * msp430.h: Likewise.
1004 * ns32k.h: Likewise.
1006 * pdp11.h: Likewise.
1013 * score-datadep.h: Likewise.
1014 * score-inst.h: Likewise.
1015 * sparc.h: Likewise.
1016 * spu-insns.h: Likewise.
1018 * tic30.h: Likewise.
1019 * tic4x.h: Likewise.
1020 * tic54x.h: Likewise.
1021 * tic80.h: Likewise.
1025 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1027 * tic6x-control-registers.h, tic6x-insn-formats.h,
1028 tic6x-opcode-table.h, tic6x.h: New.
1030 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1032 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1034 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1036 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1038 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1040 * ia64.h (ia64_find_opcode): Remove argument name.
1041 (ia64_find_next_opcode): Likewise.
1042 (ia64_dis_opcode): Likewise.
1043 (ia64_free_opcode): Likewise.
1044 (ia64_find_dependency): Likewise.
1046 2009-11-22 Doug Evans <dje@sebabeach.org>
1048 * cgen.h: Include bfd_stdint.h.
1049 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1051 2009-11-18 Paul Brook <paul@codesourcery.com>
1053 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1055 2009-11-17 Paul Brook <paul@codesourcery.com>
1056 Daniel Jacobowitz <dan@codesourcery.com>
1058 * arm.h (ARM_EXT_V6_DSP): Define.
1059 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1060 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1062 2009-11-04 DJ Delorie <dj@redhat.com>
1064 * rx.h (rx_decode_opcode) (mvtipl): Add.
1065 (mvtcp, mvfcp, opecp): Remove.
1067 2009-11-02 Paul Brook <paul@codesourcery.com>
1069 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1070 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1071 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1072 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1073 FPU_ARCH_NEON_VFP_V4): Define.
1075 2009-10-23 Doug Evans <dje@sebabeach.org>
1077 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1078 * cgen.h: Update. Improve multi-inclusion macro name.
1080 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1082 * ppc.h (PPC_OPCODE_476): Define.
1084 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1086 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1088 2009-09-29 DJ Delorie <dj@redhat.com>
1092 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1094 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1096 2009-09-21 Ben Elliston <bje@au.ibm.com>
1098 * ppc.h (PPC_OPCODE_PPCA2): New.
1100 2009-09-05 Martin Thuresson <martin@mtme.org>
1102 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1104 2009-08-29 Martin Thuresson <martin@mtme.org>
1106 * tic30.h (template): Rename type template to
1107 insn_template. Updated code to use new name.
1108 * tic54x.h (template): Rename type template to
1111 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1113 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1115 2009-06-11 Anthony Green <green@moxielogic.com>
1117 * moxie.h (MOXIE_F3_PCREL): Define.
1118 (moxie_form3_opc_info): Grow.
1120 2009-06-06 Anthony Green <green@moxielogic.com>
1122 * moxie.h (MOXIE_F1_M): Define.
1124 2009-04-15 Anthony Green <green@moxielogic.com>
1128 2009-04-06 DJ Delorie <dj@redhat.com>
1130 * h8300.h: Add relaxation attributes to MOVA opcodes.
1132 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1134 * ppc.h (ppc_parse_cpu): Declare.
1136 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1138 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1139 and _IMM11 for mbitclr and mbitset.
1140 * score-datadep.h: Update dependency information.
1142 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1144 * ppc.h (PPC_OPCODE_POWER7): New.
1146 2009-02-06 Doug Evans <dje@google.com>
1148 * i386.h: Add comment regarding sse* insns and prefixes.
1150 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1152 * mips.h (INSN_XLR): Define.
1153 (INSN_CHIP_MASK): Update.
1155 (OPCODE_IS_MEMBER): Update.
1156 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1158 2009-01-28 Doug Evans <dje@google.com>
1160 * opcode/i386.h: Add multiple inclusion protection.
1161 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1162 (EDI_REG_NUM): New macros.
1163 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1164 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1165 (REX_PREFIX_P): New macro.
1167 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1169 * ppc.h (struct powerpc_opcode): New field "deprecated".
1170 (PPC_OPCODE_NOPOWER4): Delete.
1172 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1174 * mips.h: Define CPU_R14000, CPU_R16000.
1175 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1177 2008-11-18 Catherine Moore <clm@codesourcery.com>
1179 * arm.h (FPU_NEON_FP16): New.
1180 (FPU_ARCH_NEON_FP16): New.
1182 2008-11-06 Chao-ying Fu <fu@mips.com>
1184 * mips.h: Doucument '1' for 5-bit sync type.
1186 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1188 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1191 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1193 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1195 2008-07-30 Michael J. Eager <eager@eagercon.com>
1197 * ppc.h (PPC_OPCODE_405): Define.
1198 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1200 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1202 * ppc.h (ppc_cpu_t): New typedef.
1203 (struct powerpc_opcode <flags>): Use it.
1204 (struct powerpc_operand <insert, extract>): Likewise.
1205 (struct powerpc_macro <flags>): Likewise.
1207 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1209 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1210 Update comment before MIPS16 field descriptors to mention MIPS16.
1211 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1213 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1214 New bit masks and shift counts for cins and exts.
1216 * mips.h: Document new field descriptors +Q.
1217 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1219 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1221 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1222 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1224 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1226 * ppc.h: (PPC_OPCODE_E500MC): New.
1228 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1230 * i386.h (MAX_OPERANDS): Set to 5.
1231 (MAX_MNEM_SIZE): Changed to 20.
1233 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1235 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1237 2008-03-09 Paul Brook <paul@codesourcery.com>
1239 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1241 2008-03-04 Paul Brook <paul@codesourcery.com>
1243 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1244 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1245 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1247 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1248 Nick Clifton <nickc@redhat.com>
1251 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1252 with a 32-bit displacement but without the top bit of the 4th byte
1255 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1257 * cr16.h (cr16_num_optab): Declared.
1259 2008-02-14 Hakan Ardo <hakan@debian.org>
1262 * avr.h (AVR_ISA_2xxe): Define.
1264 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1266 * mips.h: Update copyright.
1267 (INSN_CHIP_MASK): New macro.
1268 (INSN_OCTEON): New macro.
1269 (CPU_OCTEON): New macro.
1270 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1272 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1274 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1276 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1278 * avr.h (AVR_ISA_USB162): Add new opcode set.
1279 (AVR_ISA_AVR3): Likewise.
1281 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1283 * mips.h (INSN_LOONGSON_2E): New.
1284 (INSN_LOONGSON_2F): New.
1285 (CPU_LOONGSON_2E): New.
1286 (CPU_LOONGSON_2F): New.
1287 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1289 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1291 * mips.h (INSN_ISA*): Redefine certain values as an
1292 enumeration. Update comments.
1293 (mips_isa_table): New.
1294 (ISA_MIPS*): Redefine to match enumeration.
1295 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1298 2007-08-08 Ben Elliston <bje@au.ibm.com>
1300 * ppc.h (PPC_OPCODE_PPCPS): New.
1302 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1304 * m68k.h: Document j K & E.
1306 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1308 * cr16.h: New file for CR16 target.
1310 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1312 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1314 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1316 * m68k.h (mcfisa_c): New.
1317 (mcfusp, mcf_mask): Adjust.
1319 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1321 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1322 (num_powerpc_operands): Declare.
1323 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1324 (PPC_OPERAND_PLUS1): Define.
1326 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1328 * i386.h (REX_MODE64): Renamed to ...
1330 (REX_EXTX): Renamed to ...
1332 (REX_EXTY): Renamed to ...
1334 (REX_EXTZ): Renamed to ...
1337 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1339 * i386.h: Add entries from config/tc-i386.h and move tables
1340 to opcodes/i386-opc.h.
1342 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1344 * i386.h (FloatDR): Removed.
1345 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1347 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1349 * spu-insns.h: Add soma double-float insns.
1351 2007-02-20 Thiemo Seufer <ths@mips.com>
1352 Chao-Ying Fu <fu@mips.com>
1354 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1355 (INSN_DSPR2): Add flag for DSP R2 instructions.
1356 (M_BALIGN): New macro.
1358 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1360 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1361 and Seg3ShortFrom with Shortform.
1363 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1366 * i386.h (i386_optab): Put the real "test" before the pseudo
1369 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1371 * m68k.h (m68010up): OR fido_a.
1373 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1375 * m68k.h (fido_a): New.
1377 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1379 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1380 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1383 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1385 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1387 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1389 * score-inst.h (enum score_insn_type): Add Insn_internal.
1391 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1392 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1393 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1394 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1395 Alan Modra <amodra@bigpond.net.au>
1397 * spu-insns.h: New file.
1400 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1402 * ppc.h (PPC_OPCODE_CELL): Define.
1404 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1406 * i386.h : Modify opcode to support for the change in POPCNT opcode
1407 in amdfam10 architecture.
1409 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1411 * i386.h: Replace CpuMNI with CpuSSSE3.
1413 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1414 Joseph Myers <joseph@codesourcery.com>
1415 Ian Lance Taylor <ian@wasabisystems.com>
1416 Ben Elliston <bje@wasabisystems.com>
1418 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1420 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1422 * score-datadep.h: New file.
1423 * score-inst.h: New file.
1425 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1427 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1428 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1429 movdq2q and movq2dq.
1431 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1432 Michael Meissner <michael.meissner@amd.com>
1434 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1436 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1438 * i386.h (i386_optab): Add "nop" with memory reference.
1440 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1442 * i386.h (i386_optab): Update comment for 64bit NOP.
1444 2006-06-06 Ben Elliston <bje@au.ibm.com>
1445 Anton Blanchard <anton@samba.org>
1447 * ppc.h (PPC_OPCODE_POWER6): Define.
1450 2006-06-05 Thiemo Seufer <ths@mips.com>
1452 * mips.h: Improve description of MT flags.
1454 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1456 * m68k.h (mcf_mask): Define.
1458 2006-05-05 Thiemo Seufer <ths@mips.com>
1459 David Ung <davidu@mips.com>
1461 * mips.h (enum): Add macro M_CACHE_AB.
1463 2006-05-04 Thiemo Seufer <ths@mips.com>
1464 Nigel Stephens <nigel@mips.com>
1465 David Ung <davidu@mips.com>
1467 * mips.h: Add INSN_SMARTMIPS define.
1469 2006-04-30 Thiemo Seufer <ths@mips.com>
1470 David Ung <davidu@mips.com>
1472 * mips.h: Defines udi bits and masks. Add description of
1473 characters which may appear in the args field of udi
1476 2006-04-26 Thiemo Seufer <ths@networkno.de>
1478 * mips.h: Improve comments describing the bitfield instruction
1481 2006-04-26 Julian Brown <julian@codesourcery.com>
1483 * arm.h (FPU_VFP_EXT_V3): Define constant.
1484 (FPU_NEON_EXT_V1): Likewise.
1485 (FPU_VFP_HARD): Update.
1486 (FPU_VFP_V3): Define macro.
1487 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1489 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1491 * avr.h (AVR_ISA_PWMx): New.
1493 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1495 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1496 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1497 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1498 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1499 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1501 2006-03-10 Paul Brook <paul@codesourcery.com>
1503 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1505 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1507 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1508 first. Correct mask of bb "B" opcode.
1510 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1512 * i386.h (i386_optab): Support Intel Merom New Instructions.
1514 2006-02-24 Paul Brook <paul@codesourcery.com>
1516 * arm.h: Add V7 feature bits.
1518 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1520 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1522 2006-01-31 Paul Brook <paul@codesourcery.com>
1523 Richard Earnshaw <rearnsha@arm.com>
1525 * arm.h: Use ARM_CPU_FEATURE.
1526 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1527 (arm_feature_set): Change to a structure.
1528 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1529 ARM_FEATURE): New macros.
1531 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1533 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1534 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1535 (ADD_PC_INCR_OPCODE): Don't define.
1537 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1540 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1542 2005-11-14 David Ung <davidu@mips.com>
1544 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1545 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1546 save/restore encoding of the args field.
1548 2005-10-28 Dave Brolley <brolley@redhat.com>
1550 Contribute the following changes:
1551 2005-02-16 Dave Brolley <brolley@redhat.com>
1553 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1554 cgen_isa_mask_* to cgen_bitset_*.
1557 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1559 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1560 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1561 (CGEN_CPU_TABLE): Make isas a ponter.
1563 2003-09-29 Dave Brolley <brolley@redhat.com>
1565 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1566 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1567 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1569 2002-12-13 Dave Brolley <brolley@redhat.com>
1571 * cgen.h (symcat.h): #include it.
1572 (cgen-bitset.h): #include it.
1573 (CGEN_ATTR_VALUE_TYPE): Now a union.
1574 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1575 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1576 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1577 * cgen-bitset.h: New file.
1579 2005-09-30 Catherine Moore <clm@cm00re.com>
1583 2005-10-24 Jan Beulich <jbeulich@novell.com>
1585 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1588 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1590 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1591 Add FLAG_STRICT to pa10 ftest opcode.
1593 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1595 * hppa.h (pa_opcodes): Remove lha entries.
1597 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1599 * hppa.h (FLAG_STRICT): Revise comment.
1600 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1601 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1604 2005-09-30 Catherine Moore <clm@cm00re.com>
1608 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1610 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1612 2005-09-06 Chao-ying Fu <fu@mips.com>
1614 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1615 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1617 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1618 (INSN_ASE_MASK): Update to include INSN_MT.
1619 (INSN_MT): New define for MT ASE.
1621 2005-08-25 Chao-ying Fu <fu@mips.com>
1623 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1624 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1625 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1626 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1627 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1628 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1630 (INSN_DSP): New define for DSP ASE.
1632 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1636 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1638 * ppc.h (PPC_OPCODE_E300): Define.
1640 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1642 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1644 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1647 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1650 2005-07-27 Jan Beulich <jbeulich@novell.com>
1652 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1653 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1654 Add movq-s as 64-bit variants of movd-s.
1656 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1658 * hppa.h: Fix punctuation in comment.
1660 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1661 implicit space-register addressing. Set space-register bits on opcodes
1662 using implicit space-register addressing. Add various missing pa20
1663 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1664 space-register addressing. Use "fE" instead of "fe" in various
1667 2005-07-18 Jan Beulich <jbeulich@novell.com>
1669 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1671 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1673 * i386.h (i386_optab): Support Intel VMX Instructions.
1675 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1677 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1679 2005-07-05 Jan Beulich <jbeulich@novell.com>
1681 * i386.h (i386_optab): Add new insns.
1683 2005-07-01 Nick Clifton <nickc@redhat.com>
1685 * sparc.h: Add typedefs to structure declarations.
1687 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386.h (i386_optab): Update comments for 64bit addressing on
1691 mov. Allow 64bit addressing for mov and movq.
1693 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1695 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1696 respectively, in various floating-point load and store patterns.
1698 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1700 * hppa.h (FLAG_STRICT): Correct comment.
1701 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1702 PA 2.0 mneumonics when equivalent. Entries with cache control
1703 completers now require PA 1.1. Adjust whitespace.
1705 2005-05-19 Anton Blanchard <anton@samba.org>
1707 * ppc.h (PPC_OPCODE_POWER5): Define.
1709 2005-05-10 Nick Clifton <nickc@redhat.com>
1711 * Update the address and phone number of the FSF organization in
1712 the GPL notices in the following files:
1713 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1714 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1715 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1716 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1717 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1718 tic54x.h, tic80.h, v850.h, vax.h
1720 2005-05-09 Jan Beulich <jbeulich@novell.com>
1722 * i386.h (i386_optab): Add ht and hnt.
1724 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1726 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1727 Add xcrypt-ctr. Provide aliases without hyphens.
1729 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1731 Moved from ../ChangeLog
1733 2005-04-12 Paul Brook <paul@codesourcery.com>
1734 * m88k.h: Rename psr macros to avoid conflicts.
1736 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1737 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1738 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1739 and ARM_ARCH_V6ZKT2.
1741 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1742 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1743 Remove redundant instruction types.
1744 (struct argument): X_op - new field.
1745 (struct cst4_entry): Remove.
1746 (no_op_insn): Declare.
1748 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1749 * crx.h (enum argtype): Rename types, remove unused types.
1751 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1752 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1753 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1754 (enum operand_type): Rearrange operands, edit comments.
1755 replace us<N> with ui<N> for unsigned immediate.
1756 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1757 displacements (respectively).
1758 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1759 (instruction type): Add NO_TYPE_INS.
1760 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1761 (operand_entry): New field - 'flags'.
1762 (operand flags): New.
1764 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1765 * crx.h (operand_type): Remove redundant types i3, i4,
1767 Add new unsigned immediate types us3, us4, us5, us16.
1769 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1771 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1772 adjust them accordingly.
1774 2005-04-01 Jan Beulich <jbeulich@novell.com>
1776 * i386.h (i386_optab): Add rdtscp.
1778 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1780 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1781 between memory and segment register. Allow movq for moving between
1782 general-purpose register and segment register.
1784 2005-02-09 Jan Beulich <jbeulich@novell.com>
1787 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1788 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1791 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1793 * m68k.h (m68008, m68ec030, m68882): Remove.
1795 (cpu_m68k, cpu_cf): New.
1796 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1797 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1799 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1801 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1802 * cgen.h (enum cgen_parse_operand_type): Add
1803 CGEN_PARSE_OPERAND_SYMBOLIC.
1805 2005-01-21 Fred Fish <fnf@specifixinc.com>
1807 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1808 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1809 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1811 2005-01-19 Fred Fish <fnf@specifixinc.com>
1813 * mips.h (struct mips_opcode): Add new pinfo2 member.
1814 (INSN_ALIAS): New define for opcode table entries that are
1815 specific instances of another entry, such as 'move' for an 'or'
1816 with a zero operand.
1817 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1818 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1820 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1822 * mips.h (CPU_RM9000): Define.
1823 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1825 2004-11-25 Jan Beulich <jbeulich@novell.com>
1827 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1828 to/from test registers are illegal in 64-bit mode. Add missing
1829 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1830 (previously one had to explicitly encode a rex64 prefix). Re-enable
1831 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1832 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1834 2004-11-23 Jan Beulich <jbeulich@novell.com>
1836 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1837 available only with SSE2. Change the MMX additions introduced by SSE
1838 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1839 instructions by their now designated identifier (since combining i686
1840 and 3DNow! does not really imply 3DNow!A).
1842 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1844 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1845 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1847 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1848 Vineet Sharma <vineets@noida.hcltech.com>
1850 * maxq.h: New file: Disassembly information for the maxq port.
1852 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1854 * i386.h (i386_optab): Put back "movzb".
1856 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1858 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1859 comments. Remove member cris_ver_sim. Add members
1860 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1861 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1862 (struct cris_support_reg, struct cris_cond15): New types.
1863 (cris_conds15): Declare.
1864 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1865 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1866 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1867 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1868 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1869 SIZE_FIELD_UNSIGNED.
1871 2004-11-04 Jan Beulich <jbeulich@novell.com>
1873 * i386.h (sldx_Suf): Remove.
1874 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1875 (q_FP): Define, implying no REX64.
1876 (x_FP, sl_FP): Imply FloatMF.
1877 (i386_optab): Split reg and mem forms of moving from segment registers
1878 so that the memory forms can ignore the 16-/32-bit operand size
1879 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1880 all non-floating-point instructions. Unite 32- and 64-bit forms of
1881 movsx, movzx, and movd. Adjust floating point operations for the above
1882 changes to the *FP macros. Add DefaultSize to floating point control
1883 insns operating on larger memory ranges. Remove left over comments
1884 hinting at certain insns being Intel-syntax ones where the ones
1885 actually meant are already gone.
1887 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1889 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1892 2004-09-30 Paul Brook <paul@codesourcery.com>
1894 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1895 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1897 2004-09-11 Theodore A. Roth <troth@openavr.org>
1899 * avr.h: Add support for
1900 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1902 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1904 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1906 2004-08-24 Dmitry Diky <diwil@spec.ru>
1908 * msp430.h (msp430_opc): Add new instructions.
1909 (msp430_rcodes): Declare new instructions.
1910 (msp430_hcodes): Likewise..
1912 2004-08-13 Nick Clifton <nickc@redhat.com>
1915 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1918 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1920 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1922 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1924 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1926 2004-07-21 Jan Beulich <jbeulich@novell.com>
1928 * i386.h: Adjust instruction descriptions to better match the
1931 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1933 * arm.h: Remove all old content. Replace with architecture defines
1934 from gas/config/tc-arm.c.
1936 2004-07-09 Andreas Schwab <schwab@suse.de>
1938 * m68k.h: Fix comment.
1940 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1944 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1946 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1948 2004-05-24 Peter Barada <peter@the-baradas.com>
1950 * m68k.h: Add 'size' to m68k_opcode.
1952 2004-05-05 Peter Barada <peter@the-baradas.com>
1954 * m68k.h: Switch from ColdFire chip name to core variant.
1956 2004-04-22 Peter Barada <peter@the-baradas.com>
1958 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1959 descriptions for new EMAC cases.
1960 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1961 handle Motorola MAC syntax.
1962 Allow disassembly of ColdFire V4e object files.
1964 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1966 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1968 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1970 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1972 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1974 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1976 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1978 * i386.h (i386_optab): Added xstore/xcrypt insns.
1980 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1982 * h8300.h (32bit ldc/stc): Add relaxing support.
1984 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1986 * h8300.h (BITOP): Pass MEMRELAX flag.
1988 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1990 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1993 For older changes see ChangeLog-9103
1995 Copyright (C) 2004-2014 Free Software Foundation, Inc.
1997 Copying and distribution of this file, with or without modification,
1998 are permitted in any medium without royalty provided the copyright
1999 notice and this notice are preserved.
2005 version-control: never