include/opcode/ChangeLog

   1 2009-11-22  Doug Evans  <dje@sebabeach.org>
   2
   3         * cgen.h: Include bfd_stdint.h.
   4         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
   5
   6 2009-11-18  Paul Brook  <paul@codesourcery.com>
   7
   8         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
   9
  10 2009-11-17  Paul Brook  <paul@codesourcery.com>
  11         Daniel Jacobowitz  <dan@codesourcery.com>
  12
  13         * arm.h (ARM_EXT_V6_DSP): Define.
  14         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
  15         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
  16
  17 2009-11-04  DJ Delorie  <dj@redhat.com>
  18
  19         * rx.h (rx_decode_opcode) (mvtipl): Add.
  20         (mvtcp, mvfcp, opecp): Remove.
  21
  22 2009-11-02  Paul Brook  <paul@codesourcery.com>
  23
  24         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
  25         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
  26         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
  27         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
  28         FPU_ARCH_NEON_VFP_V4): Define.
  29
  30 2009-10-23  Doug Evans  <dje@sebabeach.org>
  31
  32         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
  33         * cgen.h: Update.  Improve multi-inclusion macro name.
  34
  35 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
  36
  37         * ppc.h (PPC_OPCODE_476): Define.
  38
  39 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
  40
  41         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
  42
  43 2009-09-29  DJ Delorie  <dj@redhat.com>
  44
  45         * rx.h: New file.
  46
  47 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  48
  49         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  50
  51 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  52
  53         * ppc.h (PPC_OPCODE_PPCA2): New.
  54
  55 2009-09-05  Martin Thuresson  <martin@mtme.org>
  56
  57         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  58
  59 2009-08-29  Martin Thuresson  <martin@mtme.org>
  60
  61         * tic30.h (template): Rename type template to
  62         insn_template. Updated code to use new name.
  63         * tic54x.h (template): Rename type template to
  64         insn_template.
  65
  66 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  67
  68         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  69
  70 2009-06-11  Anthony Green  <green@moxielogic.com>
  71
  72         * moxie.h (MOXIE_F3_PCREL): Define.
  73         (moxie_form3_opc_info): Grow.
  74
  75 2009-06-06  Anthony Green  <green@moxielogic.com>
  76
  77         * moxie.h (MOXIE_F1_M): Define.
  78
  79 2009-04-15  Anthony Green  <green@moxielogic.com>
  80
  81         * moxie.h: Created.
  82
  83 2009-04-06  DJ Delorie  <dj@redhat.com>
  84
  85         * h8300.h: Add relaxation attributes to MOVA opcodes.
  86
  87 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  88
  89         * ppc.h (ppc_parse_cpu): Declare.
  90
  91 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  92
  93         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  94         and _IMM11 for mbitclr and mbitset.
  95         * score-datadep.h: Update dependency information.
  96
  97 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  98
  99         * ppc.h (PPC_OPCODE_POWER7): New.
 100
 101 2009-02-06  Doug Evans  <dje@google.com>
 102
 103         * i386.h: Add comment regarding sse* insns and prefixes.
 104
 105 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 106
 107         * mips.h (INSN_XLR): Define.
 108         (INSN_CHIP_MASK): Update.
 109         (CPU_XLR): Define.
 110         (OPCODE_IS_MEMBER): Update.
 111         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 112
 113 2009-01-28  Doug Evans  <dje@google.com>
 114
 115         * opcode/i386.h: Add multiple inclusion protection.
 116         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 117         (EDI_REG_NUM): New macros.
 118         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 119         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 120         (REX_PREFIX_P): New macro.
 121
 122 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 123
 124         * ppc.h (struct powerpc_opcode): New field "deprecated".
 125         (PPC_OPCODE_NOPOWER4): Delete.
 126
 127 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 128
 129         * mips.h: Define CPU_R14000, CPU_R16000.
 130         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 131
 132 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 133
 134         * arm.h (FPU_NEON_FP16): New.
 135         (FPU_ARCH_NEON_FP16): New.
 136
 137 2008-11-06  Chao-ying Fu  <fu@mips.com>
 138
 139         * mips.h: Doucument '1' for 5-bit sync type.
 140
 141 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 144         IA64_RS_CR.
 145
 146 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 147
 148         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 149
 150 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 151
 152         * ppc.h (PPC_OPCODE_405): Define.
 153         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 154
 155 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 156
 157         * ppc.h (ppc_cpu_t): New typedef.
 158         (struct powerpc_opcode <flags>): Use it.
 159         (struct powerpc_operand <insert, extract>): Likewise.
 160         (struct powerpc_macro <flags>): Likewise.
 161
 162 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 163
 164         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 165         Update comment before MIPS16 field descriptors to mention MIPS16.
 166         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 167         BBIT.
 168         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 169         New bit masks and shift counts for cins and exts.
 170
 171         * mips.h: Document new field descriptors +Q.
 172         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 173
 174 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 175
 176         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 177         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 178
 179 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 180
 181         * ppc.h: (PPC_OPCODE_E500MC): New.
 182
 183 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         * i386.h (MAX_OPERANDS): Set to 5.
 186         (MAX_MNEM_SIZE): Changed to 20.
 187
 188 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 189
 190         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 191
 192 2008-03-09  Paul Brook  <paul@codesourcery.com>
 193
 194         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 195
 196 2008-03-04  Paul Brook  <paul@codesourcery.com>
 197
 198         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 199         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 200         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 201
 202 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 203             Nick Clifton  <nickc@redhat.com>
 204
 205         PR 3134
 206         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 207         with a 32-bit displacement but without the top bit of the 4th byte
 208         set.
 209
 210 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 211
 212         * cr16.h (cr16_num_optab): Declared.
 213
 214 2008-02-14  Hakan Ardo  <hakan@debian.org>
 215
 216         PR gas/2626
 217         * avr.h (AVR_ISA_2xxe): Define.
 218
 219 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 220
 221         * mips.h: Update copyright.
 222         (INSN_CHIP_MASK): New macro.
 223         (INSN_OCTEON): New macro.
 224         (CPU_OCTEON): New macro.
 225         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 226
 227 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 228
 229         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 230
 231 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 232
 233         * avr.h (AVR_ISA_USB162): Add new opcode set.
 234         (AVR_ISA_AVR3): Likewise.
 235
 236 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 237
 238         * mips.h (INSN_LOONGSON_2E): New.
 239         (INSN_LOONGSON_2F): New.
 240         (CPU_LOONGSON_2E): New.
 241         (CPU_LOONGSON_2F): New.
 242         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 243
 244 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 245
 246         * mips.h (INSN_ISA*): Redefine certain values as an
 247         enumeration.  Update comments.
 248         (mips_isa_table): New.
 249         (ISA_MIPS*): Redefine to match enumeration.
 250         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 251         values.
 252
 253 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 254
 255         * ppc.h (PPC_OPCODE_PPCPS): New.
 256
 257 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 258
 259         * m68k.h: Document j K & E.
 260
 261 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 262
 263         * cr16.h: New file for CR16 target.
 264
 265 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 266
 267         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 268
 269 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 270
 271         * m68k.h (mcfisa_c): New.
 272         (mcfusp, mcf_mask): Adjust.
 273
 274 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 275
 276         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 277         (num_powerpc_operands): Declare.
 278         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 279         (PPC_OPERAND_PLUS1): Define.
 280
 281 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         * i386.h (REX_MODE64): Renamed to ...
 284         (REX_W): This.
 285         (REX_EXTX): Renamed to ...
 286         (REX_R): This.
 287         (REX_EXTY): Renamed to ...
 288         (REX_X): This.
 289         (REX_EXTZ): Renamed to ...
 290         (REX_B): This.
 291
 292 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386.h: Add entries from config/tc-i386.h and move tables
 295         to opcodes/i386-opc.h.
 296
 297 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         * i386.h (FloatDR): Removed.
 300         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 301
 302 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 303
 304         * spu-insns.h: Add soma double-float insns.
 305
 306 2007-02-20  Thiemo Seufer  <ths@mips.com>
 307             Chao-Ying Fu  <fu@mips.com>
 308
 309         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 310         (INSN_DSPR2): Add flag for DSP R2 instructions.
 311         (M_BALIGN): New macro.
 312
 313 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 314
 315         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 316         and Seg3ShortFrom with Shortform.
 317
 318 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         PR gas/4027
 321         * i386.h (i386_optab): Put the real "test" before the pseudo
 322         one.
 323
 324 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 325
 326         * m68k.h (m68010up): OR fido_a.
 327
 328 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 329
 330         * m68k.h (fido_a): New.
 331
 332 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 333
 334         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 335         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 336         values.
 337
 338 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 341
 342 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 343
 344         * score-inst.h (enum score_insn_type): Add Insn_internal.
 345
 346 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 347             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 348             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 349             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 350             Alan Modra  <amodra@bigpond.net.au>
 351
 352         * spu-insns.h: New file.
 353         * spu.h: New file.
 354
 355 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 356
 357         * ppc.h (PPC_OPCODE_CELL): Define.
 358
 359 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 360
 361         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 362         in amdfam10 architecture.
 363
 364 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         * i386.h: Replace CpuMNI with CpuSSSE3.
 367
 368 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 369             Joseph Myers  <joseph@codesourcery.com>
 370             Ian Lance Taylor  <ian@wasabisystems.com>
 371             Ben Elliston  <bje@wasabisystems.com>
 372
 373         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 374
 375 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 376
 377         * score-datadep.h: New file.
 378         * score-inst.h: New file.
 379
 380 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 383         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 384         movdq2q and movq2dq.
 385
 386 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 387            Michael Meissner             <michael.meissner@amd.com>
 388
 389         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 390
 391 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         * i386.h (i386_optab): Add "nop" with memory reference.
 394
 395 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * i386.h (i386_optab): Update comment for 64bit NOP.
 398
 399 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 400             Anton Blanchard  <anton@samba.org>
 401
 402         * ppc.h (PPC_OPCODE_POWER6): Define.
 403         Adjust whitespace.
 404
 405 2006-06-05  Thiemo Seufer  <ths@mips.com>
 406
 407         * mips.h: Improve description of MT flags.
 408
 409 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 410
 411         * m68k.h (mcf_mask): Define.
 412
 413 2006-05-05  Thiemo Seufer  <ths@mips.com>
 414             David Ung  <davidu@mips.com>
 415
 416         * mips.h (enum): Add macro M_CACHE_AB.
 417
 418 2006-05-04  Thiemo Seufer  <ths@mips.com>
 419             Nigel Stephens  <nigel@mips.com>
 420             David Ung  <davidu@mips.com>
 421
 422         * mips.h: Add INSN_SMARTMIPS define.
 423
 424 2006-04-30  Thiemo Seufer  <ths@mips.com>
 425             David Ung  <davidu@mips.com>
 426
 427         * mips.h: Defines udi bits and masks.  Add description of
 428         characters which may appear in the args field of udi
 429         instructions.
 430
 431 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 432
 433         * mips.h: Improve comments describing the bitfield instruction
 434         fields.
 435
 436 2006-04-26  Julian Brown  <julian@codesourcery.com>
 437
 438         * arm.h (FPU_VFP_EXT_V3): Define constant.
 439         (FPU_NEON_EXT_V1): Likewise.
 440         (FPU_VFP_HARD): Update.
 441         (FPU_VFP_V3): Define macro.
 442         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 443
 444 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 445
 446         * avr.h (AVR_ISA_PWMx): New.
 447
 448 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 449
 450         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 451         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 452         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 453         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 454         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 455
 456 2006-03-10  Paul Brook  <paul@codesourcery.com>
 457
 458         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 459
 460 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 461
 462         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 463         first.  Correct mask of bb "B" opcode.
 464
 465 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 466
 467         * i386.h (i386_optab): Support Intel Merom New Instructions.
 468
 469 2006-02-24  Paul Brook  <paul@codesourcery.com>
 470
 471         * arm.h: Add V7 feature bits.
 472
 473 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 476
 477 2006-01-31  Paul Brook  <paul@codesourcery.com>
 478         Richard Earnshaw <rearnsha@arm.com>
 479
 480         * arm.h: Use ARM_CPU_FEATURE.
 481         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 482         (arm_feature_set): Change to a structure.
 483         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 484         ARM_FEATURE): New macros.
 485
 486 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 487
 488         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 489         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 490         (ADD_PC_INCR_OPCODE): Don't define.
 491
 492 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         PR gas/1874
 495         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 496
 497 2005-11-14  David Ung  <davidu@mips.com>
 498
 499         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 500         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 501         save/restore encoding of the args field.
 502
 503 2005-10-28  Dave Brolley  <brolley@redhat.com>
 504
 505         Contribute the following changes:
 506         2005-02-16  Dave Brolley  <brolley@redhat.com>
 507
 508         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 509         cgen_isa_mask_* to cgen_bitset_*.
 510         * cgen.h: Likewise.
 511
 512         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 513
 514         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 515         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 516         (CGEN_CPU_TABLE): Make isas a ponter.
 517
 518         2003-09-29  Dave Brolley  <brolley@redhat.com>
 519
 520         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 521         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 522         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 523
 524         2002-12-13  Dave Brolley  <brolley@redhat.com>
 525
 526         * cgen.h (symcat.h): #include it.
 527         (cgen-bitset.h): #include it.
 528         (CGEN_ATTR_VALUE_TYPE): Now a union.
 529         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 530         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 531         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 532         * cgen-bitset.h: New file.
 533
 534 2005-09-30  Catherine Moore  <clm@cm00re.com>
 535
 536         * bfin.h: New file.
 537
 538 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 539
 540         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 541         indirect operands.
 542
 543 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 544
 545         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 546         Add FLAG_STRICT to pa10 ftest opcode.
 547
 548 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 549
 550         * hppa.h (pa_opcodes): Remove lha entries.
 551
 552 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 553
 554         * hppa.h (FLAG_STRICT): Revise comment.
 555         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 556         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 557         entries for "fdc".
 558
 559 2005-09-30  Catherine Moore  <clm@cm00re.com>
 560
 561         * bfin.h: New file.
 562
 563 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 564
 565         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 566
 567 2005-09-06  Chao-ying Fu  <fu@mips.com>
 568
 569         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 570         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 571         define.
 572         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 573         (INSN_ASE_MASK): Update to include INSN_MT.
 574         (INSN_MT): New define for MT ASE.
 575
 576 2005-08-25  Chao-ying Fu  <fu@mips.com>
 577
 578         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 579         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 580         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 581         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 582         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 583         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 584         instructions.
 585         (INSN_DSP): New define for DSP ASE.
 586
 587 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 588
 589         * a29k.h: Delete.
 590
 591 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 592
 593         * ppc.h (PPC_OPCODE_E300): Define.
 594
 595 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 596
 597         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 598
 599 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 600
 601         PR gas/336
 602         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 603         and pitlb.
 604
 605 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 606
 607         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 608         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 609         Add movq-s as 64-bit variants of movd-s.
 610
 611 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 612
 613         * hppa.h: Fix punctuation in comment.
 614
 615         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 616         implicit space-register addressing.  Set space-register bits on opcodes
 617         using implicit space-register addressing.  Add various missing pa20
 618         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 619         space-register addressing.  Use "fE" instead of "fe" in various
 620         fstw opcodes.
 621
 622 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 623
 624         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 625
 626 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 627
 628         * i386.h (i386_optab): Support Intel VMX Instructions.
 629
 630 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 631
 632         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 633
 634 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 635
 636         * i386.h (i386_optab): Add new insns.
 637
 638 2005-07-01  Nick Clifton  <nickc@redhat.com>
 639
 640         * sparc.h: Add typedefs to structure declarations.
 641
 642 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         PR 1013
 645         * i386.h (i386_optab): Update comments for 64bit addressing on
 646         mov. Allow 64bit addressing for mov and movq.
 647
 648 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 649
 650         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 651         respectively, in various floating-point load and store patterns.
 652
 653 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 654
 655         * hppa.h (FLAG_STRICT): Correct comment.
 656         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 657         PA 2.0 mneumonics when equivalent.  Entries with cache control
 658         completers now require PA 1.1.  Adjust whitespace.
 659
 660 2005-05-19  Anton Blanchard  <anton@samba.org>
 661
 662         * ppc.h (PPC_OPCODE_POWER5): Define.
 663
 664 2005-05-10  Nick Clifton  <nickc@redhat.com>
 665
 666         * Update the address and phone number of the FSF organization in
 667         the GPL notices in the following files:
 668         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 669         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 670         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 671         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 672         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 673         tic54x.h, tic80.h, v850.h, vax.h
 674
 675 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 676
 677         * i386.h (i386_optab): Add ht and hnt.
 678
 679 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 680
 681         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 682         Add xcrypt-ctr.  Provide aliases without hyphens.
 683
 684 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 685
 686         Moved from ../ChangeLog
 687
 688         2005-04-12  Paul Brook  <paul@codesourcery.com>
 689         * m88k.h: Rename psr macros to avoid conflicts.
 690
 691         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 692         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 693         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 694         and ARM_ARCH_V6ZKT2.
 695
 696         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 697         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 698         Remove redundant instruction types.
 699         (struct argument): X_op - new field.
 700         (struct cst4_entry): Remove.
 701         (no_op_insn): Declare.
 702
 703         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 704         * crx.h (enum argtype): Rename types, remove unused types.
 705
 706         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 707         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 708         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 709         (enum operand_type): Rearrange operands, edit comments.
 710         replace us<N> with ui<N> for unsigned immediate.
 711         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 712         displacements (respectively).
 713         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 714         (instruction type): Add NO_TYPE_INS.
 715         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 716         (operand_entry): New field - 'flags'.
 717         (operand flags): New.
 718
 719         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 720         * crx.h (operand_type): Remove redundant types i3, i4,
 721         i5, i8, i12.
 722         Add new unsigned immediate types us3, us4, us5, us16.
 723
 724 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 725
 726         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 727         adjust them accordingly.
 728
 729 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 730
 731         * i386.h (i386_optab): Add rdtscp.
 732
 733 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 734
 735         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 736         between memory and segment register. Allow movq for moving between
 737         general-purpose register and segment register.
 738
 739 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 740
 741         PR gas/707
 742         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 743         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 744         fnstsw.
 745
 746 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 747
 748         * m68k.h (m68008, m68ec030, m68882): Remove.
 749         (m68k_mask): New.
 750         (cpu_m68k, cpu_cf): New.
 751         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 752         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 753
 754 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 755
 756         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 757         * cgen.h (enum cgen_parse_operand_type): Add
 758         CGEN_PARSE_OPERAND_SYMBOLIC.
 759
 760 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 761
 762         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 763         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 764         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 765
 766 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 767
 768         * mips.h (struct mips_opcode): Add new pinfo2 member.
 769         (INSN_ALIAS): New define for opcode table entries that are
 770         specific instances of another entry, such as 'move' for an 'or'
 771         with a zero operand.
 772         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 773         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 774
 775 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 776
 777         * mips.h (CPU_RM9000): Define.
 778         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 779
 780 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 781
 782         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 783         to/from test registers are illegal in 64-bit mode. Add missing
 784         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 785         (previously one had to explicitly encode a rex64 prefix). Re-enable
 786         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 787         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 788
 789 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 790
 791         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 792         available only with SSE2. Change the MMX additions introduced by SSE
 793         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 794         instructions by their now designated identifier (since combining i686
 795         and 3DNow! does not really imply 3DNow!A).
 796
 797 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 798
 799         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 800         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 801
 802 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 803             Vineet Sharma      <vineets@noida.hcltech.com>
 804
 805         * maxq.h: New file: Disassembly information for the maxq port.
 806
 807 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * i386.h (i386_optab): Put back "movzb".
 810
 811 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 812
 813         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 814         comments.  Remove member cris_ver_sim.  Add members
 815         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 816         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 817         (struct cris_support_reg, struct cris_cond15): New types.
 818         (cris_conds15): Declare.
 819         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 820         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 821         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 822         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 823         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 824         SIZE_FIELD_UNSIGNED.
 825
 826 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 827
 828         * i386.h (sldx_Suf): Remove.
 829         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 830         (q_FP): Define, implying no REX64.
 831         (x_FP, sl_FP): Imply FloatMF.
 832         (i386_optab): Split reg and mem forms of moving from segment registers
 833         so that the memory forms can ignore the 16-/32-bit operand size
 834         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 835         all non-floating-point instructions. Unite 32- and 64-bit forms of
 836         movsx, movzx, and movd. Adjust floating point operations for the above
 837         changes to the *FP macros. Add DefaultSize to floating point control
 838         insns operating on larger memory ranges. Remove left over comments
 839         hinting at certain insns being Intel-syntax ones where the ones
 840         actually meant are already gone.
 841
 842 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 843
 844         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 845         instruction type.
 846
 847 2004-09-30  Paul Brook  <paul@codesourcery.com>
 848
 849         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 850         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 851
 852 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 853
 854         * avr.h: Add support for
 855         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 856
 857 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 858
 859         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 860
 861 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 862
 863         * msp430.h (msp430_opc): Add new instructions.
 864         (msp430_rcodes): Declare new instructions.
 865         (msp430_hcodes): Likewise..
 866
 867 2004-08-13  Nick Clifton  <nickc@redhat.com>
 868
 869         PR/301
 870         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 871         processors.
 872
 873 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 874
 875         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 876
 877 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 880
 881 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 882
 883         * i386.h: Adjust instruction descriptions to better match the
 884         specification.
 885
 886 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 887
 888         * arm.h: Remove all old content.  Replace with architecture defines
 889         from gas/config/tc-arm.c.
 890
 891 2004-07-09  Andreas Schwab  <schwab@suse.de>
 892
 893         * m68k.h: Fix comment.
 894
 895 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 896
 897         * crx.h: New file.
 898
 899 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 900
 901         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 902
 903 2004-05-24  Peter Barada  <peter@the-baradas.com>
 904
 905         * m68k.h: Add 'size' to m68k_opcode.
 906
 907 2004-05-05  Peter Barada  <peter@the-baradas.com>
 908
 909         * m68k.h: Switch from ColdFire chip name to core variant.
 910
 911 2004-04-22  Peter Barada  <peter@the-baradas.com>
 912
 913         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 914         descriptions for new EMAC cases.
 915         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 916         handle Motorola MAC syntax.
 917         Allow disassembly of ColdFire V4e object files.
 918
 919 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 920
 921         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 922
 923 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 924
 925         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 926
 927 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 928
 929         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 930
 931 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 932
 933         * i386.h (i386_optab): Added xstore/xcrypt insns.
 934
 935 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 936
 937         * h8300.h (32bit ldc/stc): Add relaxing support.
 938
 939 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 940
 941         * h8300.h (BITOP): Pass MEMRELAX flag.
 942
 943 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 944
 945         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 946         except for the H8S.
 947
 948 For older changes see ChangeLog-9103
 949 \f
 950 Local Variables:
 951 mode: change-log
 952 left-margin: 8
 953 fill-column: 74
 954 version-control: never
 955 End: