1 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
5 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
7 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
8 (aarch64_sys_reg_writeonly_p): Ditto.
10 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
12 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
13 (aarch64_sys_reg_writeonly_p): Ditto.
15 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
17 * aarch64.h (aarch64_sys_reg): New typedef.
18 (aarch64_sys_regs): Change to define with the new type.
19 (aarch64_sys_reg_deprecated_p): Declare.
21 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
23 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
24 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
26 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
28 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
29 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
30 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
31 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
32 For MIPS, update extension character sequences after +.
33 (ASE_MSA): New define.
34 (ASE_MSA64): New define.
35 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
36 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
37 For microMIPS, update extension character sequences after +.
39 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
44 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
46 * mips.h: Remove references to "+I" and imm2_expr.
48 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
50 * mips.h (M_DEXT, M_DINS): Delete.
52 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
54 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
55 (mips_optional_operand_p): New function.
57 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
58 Richard Sandiford <rdsandiford@googlemail.com>
60 * mips.h: Document new VU0 operand characters.
61 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
62 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
63 (OP_REG_R5900_ACC): New mips_reg_operand_types.
64 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
65 (mips_vu0_channel_mask): Declare.
67 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
69 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
70 (mips_int_operand_min, mips_int_operand_max): New functions.
71 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
73 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
75 * mips.h (mips_decode_reg_operand): New function.
76 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
77 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
78 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
80 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
81 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
82 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
83 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
84 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
85 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
86 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
87 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
88 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
89 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
90 macros to cover the gaps.
91 (INSN2_MOD_SP): Replace with...
92 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
93 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
94 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
95 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
96 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
99 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
101 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
102 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
103 (MIPS16_INSN_COND_BRANCH): Delete.
105 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
106 Kirill Yukhin <kirill.yukhin@intel.com>
107 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
109 * i386.h (BND_PREFIX_OPCODE): New.
111 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
113 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
114 OP_SAVE_RESTORE_LIST.
115 (decode_mips16_operand): Declare.
117 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
119 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
120 (mips_operand, mips_int_operand, mips_mapped_int_operand)
121 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
122 (mips_pcrel_operand): New structures.
123 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
124 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
125 (decode_mips_operand, decode_micromips_operand): Declare.
127 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
129 * mips.h: Document MIPS16 "I" opcode.
131 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
133 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
134 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
135 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
136 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
137 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
138 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
139 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
140 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
141 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
142 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
143 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
144 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
145 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
147 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
148 (M_USD_AB): ...these.
150 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
152 * mips.h: Remove documentation of "[" and "]". Update documentation
153 of "k" and the MDMX formats.
155 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
157 * mips.h: Update documentation of "+s" and "+S".
159 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
161 * mips.h: Document "+i".
163 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
165 * mips.h: Remove "mi" documentation. Update "mh" documentation.
166 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
168 (INSN2_WRITE_GPR_MHI): Rename to...
169 (INSN2_WRITE_GPR_MH): ...this.
171 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
173 * mips.h: Remove documentation of "+D" and "+T".
175 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
177 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
178 Use "source" rather than "destination" for microMIPS "G".
180 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
182 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
185 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
187 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
189 2013-06-17 Catherine Moore <clm@codesourcery.com>
190 Maciej W. Rozycki <macro@codesourcery.com>
191 Chao-Ying Fu <fu@mips.com>
193 * mips.h (OP_SH_EVAOFFSET): Define.
194 (OP_MASK_EVAOFFSET): Define.
195 (INSN_ASE_MASK): Delete.
197 (M_CACHEE_AB, M_CACHEE_OB): New.
198 (M_LBE_OB, M_LBE_AB): New.
199 (M_LBUE_OB, M_LBUE_AB): New.
200 (M_LHE_OB, M_LHE_AB): New.
201 (M_LHUE_OB, M_LHUE_AB): New.
202 (M_LLE_AB, M_LLE_OB): New.
203 (M_LWE_OB, M_LWE_AB): New.
204 (M_LWLE_AB, M_LWLE_OB): New.
205 (M_LWRE_AB, M_LWRE_OB): New.
206 (M_PREFE_AB, M_PREFE_OB): New.
207 (M_SCE_AB, M_SCE_OB): New.
208 (M_SBE_OB, M_SBE_AB): New.
209 (M_SHE_OB, M_SHE_AB): New.
210 (M_SWE_OB, M_SWE_AB): New.
211 (M_SWLE_AB, M_SWLE_OB): New.
212 (M_SWRE_AB, M_SWRE_OB): New.
213 (MICROMIPSOP_SH_EVAOFFSET): Define.
214 (MICROMIPSOP_MASK_EVAOFFSET): Define.
216 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
218 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
220 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
222 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
224 2013-05-09 Andrew Pinski <apinski@cavium.com>
226 * mips.h (OP_MASK_CODE10): Correct definition.
227 (OP_SH_CODE10): Likewise.
228 Add a comment that "+J" is used now for OP_*CODE10.
229 (INSN_ASE_MASK): Update.
230 (INSN_VIRT): New macro.
231 (INSN_VIRT64): New macro
233 2013-05-02 Nick Clifton <nickc@redhat.com>
235 * msp430.h: Add patterns for MSP430X instructions.
237 2013-04-06 David S. Miller <davem@davemloft.net>
239 * sparc.h (F_PREFERRED): Define.
240 (F_PREF_ALIAS): Define.
242 2013-04-03 Nick Clifton <nickc@redhat.com>
244 * v850.h (V850_INVERSE_PCREL): Define.
246 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
249 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
251 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
254 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
256 * tic6xc-opcode-table.h: Add 16-bit insns.
257 * tic6x.h: Add support for 16-bit insns.
259 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
261 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
262 and mov.b/w/l Rs,@(d:32,ERd).
264 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
267 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
268 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
269 tic6x_operand_xregpair operand coding type.
270 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
271 opcode field, usu ORXREGD1324 for the src2 operand and remove the
274 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
277 * tic6x.h (enum tic6x_coding_method): Add
278 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
279 separately the msb and lsb of a register pair. This is needed to
280 encode the opcodes in the same way as TI assembler does.
281 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
282 and rsqrdp opcodes to use the new field coding types.
284 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
286 * arm.h (CRC_EXT_ARMV8): New constant.
287 (ARCH_CRC_ARMV8): New macro.
289 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
291 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
293 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
294 Andrew Jenner <andrew@codesourcery.com>
296 Based on patches from Altera Corporation.
300 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
302 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
304 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
307 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
309 2013-01-24 Nick Clifton <nickc@redhat.com>
311 * v850.h: Add e3v5 support.
313 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
315 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
317 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
319 * ppc.h (PPC_OPCODE_POWER8): New define.
320 (PPC_OPCODE_HTM): Likewise.
322 2013-01-10 Will Newton <will.newton@imgtec.com>
326 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
328 * cr16.h (make_instruction): Rename to cr16_make_instruction.
329 (match_opcode): Rename to cr16_match_opcode.
331 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
333 * mips.h: Add support for r5900 instructions including lq and sq.
335 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
337 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
338 (make_instruction,match_opcode): Added function prototypes.
339 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
341 2012-11-23 Alan Modra <amodra@gmail.com>
343 * ppc.h (ppc_parse_cpu): Update prototype.
345 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
347 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
348 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
350 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
352 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
354 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
356 * ia64.h (ia64_opnd): Add new operand types.
358 2012-08-21 David S. Miller <davem@davemloft.net>
360 * sparc.h (F3F4): New macro.
362 2012-08-13 Ian Bolton <ian.bolton@arm.com>
363 Laurent Desnogues <laurent.desnogues@arm.com>
364 Jim MacArthur <jim.macarthur@arm.com>
365 Marcus Shawcroft <marcus.shawcroft@arm.com>
366 Nigel Stephens <nigel.stephens@arm.com>
367 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
368 Richard Earnshaw <rearnsha@arm.com>
369 Sofiane Naci <sofiane.naci@arm.com>
370 Tejas Belagod <tejas.belagod@arm.com>
371 Yufeng Zhang <yufeng.zhang@arm.com>
373 * aarch64.h: New file.
375 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
376 Maciej W. Rozycki <macro@codesourcery.com>
378 * mips.h (mips_opcode): Add the exclusions field.
379 (OPCODE_IS_MEMBER): Remove macro.
380 (cpu_is_member): New inline function.
381 (opcode_is_member): Likewise.
383 2012-07-31 Chao-Ying Fu <fu@mips.com>
384 Catherine Moore <clm@codesourcery.com>
385 Maciej W. Rozycki <macro@codesourcery.com>
387 * mips.h: Document microMIPS DSP ASE usage.
388 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
389 microMIPS DSP ASE support.
390 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
391 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
392 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
393 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
394 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
395 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
396 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
398 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
400 * mips.h: Fix a typo in description.
402 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
404 * avr.h: (AVR_ISA_XCH): New define.
405 (AVR_ISA_XMEGA): Use it.
406 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
408 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
410 * m68hc11.h: Add XGate definitions.
411 (struct m68hc11_opcode): Add xg_mask field.
413 2012-05-14 Catherine Moore <clm@codesourcery.com>
414 Maciej W. Rozycki <macro@codesourcery.com>
415 Rhonda Wittels <rhonda@codesourcery.com>
417 * ppc.h (PPC_OPCODE_VLE): New definition.
418 (PPC_OP_SA): New macro.
419 (PPC_OP_SE_VLE): New macro.
420 (PPC_OP): Use a variable shift amount.
421 (powerpc_operand): Update comments.
422 (PPC_OPSHIFT_INV): New macro.
423 (PPC_OPERAND_CR): Replace with...
424 (PPC_OPERAND_CR_BIT): ...this and
425 (PPC_OPERAND_CR_REG): ...this.
428 2012-05-03 Sean Keys <skeys@ipdatasys.com>
430 * xgate.h: Header file for XGATE assembler.
432 2012-04-27 David S. Miller <davem@davemloft.net>
434 * sparc.h: Document new arg code' )' for crypto RS3
437 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
438 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
439 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
440 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
441 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
442 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
443 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
444 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
445 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
446 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
447 HWCAP_CBCOND, HWCAP_CRC32): New defines.
449 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
451 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
453 2012-02-27 Alan Modra <amodra@gmail.com>
455 * crx.h (cst4_map): Update declaration.
457 2012-02-25 Walter Lee <walt@tilera.com>
459 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
461 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
462 TILEPRO_OPC_LW_TLS_SN.
464 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
466 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
467 (XRELEASE_PREFIX_OPCODE): Likewise.
469 2011-12-08 Andrew Pinski <apinski@cavium.com>
470 Adam Nemet <anemet@caviumnetworks.com>
472 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
473 (INSN_OCTEON2): New macro.
474 (CPU_OCTEON2): New macro.
475 (OPCODE_IS_MEMBER): Add Octeon2.
477 2011-11-29 Andrew Pinski <apinski@cavium.com>
479 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
480 (INSN_OCTEONP): New macro.
481 (CPU_OCTEONP): New macro.
482 (OPCODE_IS_MEMBER): Add Octeon+.
483 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
485 2011-11-01 DJ Delorie <dj@redhat.com>
489 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
491 * mips.h: Fix a typo in description.
493 2011-09-21 David S. Miller <davem@davemloft.net>
495 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
496 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
497 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
498 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
500 2011-08-09 Chao-ying Fu <fu@mips.com>
501 Maciej W. Rozycki <macro@codesourcery.com>
503 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
504 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
505 (INSN_ASE_MASK): Add the MCU bit.
506 (INSN_MCU): New macro.
507 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
508 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
510 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
512 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
513 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
514 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
515 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
516 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
517 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
518 (INSN2_READ_GPR_MMN): Likewise.
519 (INSN2_READ_FPR_D): Change the bit used.
520 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
521 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
522 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
523 (INSN2_COND_BRANCH): Likewise.
524 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
525 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
526 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
527 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
528 (INSN2_MOD_GPR_MN): Likewise.
530 2011-08-05 David S. Miller <davem@davemloft.net>
532 * sparc.h: Document new format codes '4', '5', and '('.
533 (OPF_LOW4, RS3): New macros.
535 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
537 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
538 order of flags documented.
540 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
542 * mips.h: Clarify the description of microMIPS instruction
544 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
546 2011-07-24 Chao-ying Fu <fu@mips.com>
547 Maciej W. Rozycki <macro@codesourcery.com>
549 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
550 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
551 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
552 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
553 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
554 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
555 (OP_MASK_RS3, OP_SH_RS3): Likewise.
556 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
557 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
558 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
559 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
560 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
561 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
562 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
563 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
564 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
565 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
566 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
567 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
568 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
569 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
570 (INSN_WRITE_GPR_S): New macro.
571 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
572 (INSN2_READ_FPR_D): Likewise.
573 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
574 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
575 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
576 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
577 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
578 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
579 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
580 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
581 (CPU_MICROMIPS): New macro.
582 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
583 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
584 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
585 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
586 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
587 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
588 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
589 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
590 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
591 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
592 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
593 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
594 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
595 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
596 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
597 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
598 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
599 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
600 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
601 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
602 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
603 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
604 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
605 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
606 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
607 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
608 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
609 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
610 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
611 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
612 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
613 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
614 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
615 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
616 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
617 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
618 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
619 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
620 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
621 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
622 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
623 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
624 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
625 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
626 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
627 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
628 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
629 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
630 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
631 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
632 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
633 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
634 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
635 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
636 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
637 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
638 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
639 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
640 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
641 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
642 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
643 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
644 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
645 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
646 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
647 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
648 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
649 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
650 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
651 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
652 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
653 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
654 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
655 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
656 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
657 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
658 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
659 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
660 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
661 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
662 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
663 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
664 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
665 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
666 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
667 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
668 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
669 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
670 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
671 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
672 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
673 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
674 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
675 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
676 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
677 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
678 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
679 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
680 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
681 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
682 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
683 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
684 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
685 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
686 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
687 (micromips_opcodes): New declaration.
688 (bfd_micromips_num_opcodes): Likewise.
690 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
692 * mips.h (INSN_TRAP): Rename to...
693 (INSN_NO_DELAY_SLOT): ... this.
694 (INSN_SYNC): Remove macro.
696 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
698 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
699 a duplicate of AVR_ISA_SPM.
701 2011-07-01 Nick Clifton <nickc@redhat.com>
703 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
705 2011-06-18 Robin Getz <robin.getz@analog.com>
707 * bfin.h (is_macmod_signed): New func
709 2011-06-18 Mike Frysinger <vapier@gentoo.org>
711 * bfin.h (is_macmod_pmove): Add missing space before func args.
712 (is_macmod_hmove): Likewise.
714 2011-06-13 Walter Lee <walt@tilera.com>
716 * tilegx.h: New file.
717 * tilepro.h: New file.
719 2011-05-31 Paul Brook <paul@codesourcery.com>
721 * arm.h (ARM_ARCH_V7R_IDIV): Define.
723 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
725 * s390.h: Replace S390_OPERAND_REG_EVEN with
726 S390_OPERAND_REG_PAIR.
728 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
730 * s390.h: Add S390_OPCODE_REG_EVEN flag.
732 2011-04-18 Julian Brown <julian@codesourcery.com>
734 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
736 2011-04-11 Dan McDonald <dan@wellkeeper.com>
739 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
741 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
743 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
744 New instruction set flags.
745 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
747 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
749 * mips.h (M_PREF_AB): New enum value.
751 2011-02-12 Mike Frysinger <vapier@gentoo.org>
753 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
755 (is_macmod_pmove, is_macmod_hmove): New functions.
757 2011-02-11 Mike Frysinger <vapier@gentoo.org>
759 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
761 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
763 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
764 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
766 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
769 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
772 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
775 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
777 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
779 * mips.h: Update commentary after last commit.
781 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
783 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
784 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
785 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
787 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
789 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
791 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
793 * mips.h: Fix previous commit.
795 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
797 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
798 (INSN_LOONGSON_3A): Clear bit 31.
800 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
803 * arm.h (ARM_AEXT_V6M_ONLY): New define.
804 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
805 (ARM_ARCH_V6M_ONLY): New define.
807 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
809 * mips.h (INSN_LOONGSON_3A): Defined.
810 (CPU_LOONGSON_3A): Defined.
811 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
813 2010-10-09 Matt Rice <ratmice@gmail.com>
815 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
816 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
818 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
820 * arm.h (ARM_EXT_VIRT): New define.
821 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
822 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
825 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
827 * arm.h (ARM_AEXT_ADIV): New define.
828 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
830 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
832 * arm.h (ARM_EXT_OS): New define.
833 (ARM_AEXT_V6SM): Likewise.
834 (ARM_ARCH_V6SM): Likewise.
836 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
838 * arm.h (ARM_EXT_MP): Add.
839 (ARM_ARCH_V7A_MP): Likewise.
841 2010-09-22 Mike Frysinger <vapier@gentoo.org>
843 * bfin.h: Declare pseudoChr structs/defines.
845 2010-09-21 Mike Frysinger <vapier@gentoo.org>
847 * bfin.h: Strip trailing whitespace.
849 2010-07-29 DJ Delorie <dj@redhat.com>
851 * rx.h (RX_Operand_Type): Add TwoReg.
852 (RX_Opcode_ID): Remove ediv and ediv2.
854 2010-07-27 DJ Delorie <dj@redhat.com>
856 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
858 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
859 Ina Pandit <ina.pandit@kpitcummins.com>
861 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
862 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
863 PROCESSOR_V850E2_ALL.
864 Remove PROCESSOR_V850EA support.
865 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
866 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
867 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
868 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
869 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
870 V850_OPERAND_PERCENT.
871 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
873 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
876 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
878 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
879 (MIPS16_INSN_BRANCH): Rename to...
880 (MIPS16_INSN_COND_BRANCH): ... this.
882 2010-07-03 Alan Modra <amodra@gmail.com>
884 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
885 Renumber other PPC_OPCODE defines.
887 2010-07-03 Alan Modra <amodra@gmail.com>
889 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
891 2010-06-29 Alan Modra <amodra@gmail.com>
893 * maxq.h: Delete file.
895 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
897 * ppc.h (PPC_OPCODE_E500): Define.
899 2010-05-26 Catherine Moore <clm@codesourcery.com>
901 * opcode/mips.h (INSN_MIPS16): Remove.
903 2010-04-21 Joseph Myers <joseph@codesourcery.com>
905 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
907 2010-04-15 Nick Clifton <nickc@redhat.com>
909 * alpha.h: Update copyright notice to use GPLv3.
915 * convex.h: Likewise.
929 * m68hc11.h: Likewise.
935 * mn10200.h: Likewise.
936 * mn10300.h: Likewise.
937 * msp430.h: Likewise.
948 * score-datadep.h: Likewise.
949 * score-inst.h: Likewise.
951 * spu-insns.h: Likewise.
955 * tic54x.h: Likewise.
960 2010-03-25 Joseph Myers <joseph@codesourcery.com>
962 * tic6x-control-registers.h, tic6x-insn-formats.h,
963 tic6x-opcode-table.h, tic6x.h: New.
965 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
967 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
969 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
971 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
973 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
975 * ia64.h (ia64_find_opcode): Remove argument name.
976 (ia64_find_next_opcode): Likewise.
977 (ia64_dis_opcode): Likewise.
978 (ia64_free_opcode): Likewise.
979 (ia64_find_dependency): Likewise.
981 2009-11-22 Doug Evans <dje@sebabeach.org>
983 * cgen.h: Include bfd_stdint.h.
984 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
986 2009-11-18 Paul Brook <paul@codesourcery.com>
988 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
990 2009-11-17 Paul Brook <paul@codesourcery.com>
991 Daniel Jacobowitz <dan@codesourcery.com>
993 * arm.h (ARM_EXT_V6_DSP): Define.
994 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
995 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
997 2009-11-04 DJ Delorie <dj@redhat.com>
999 * rx.h (rx_decode_opcode) (mvtipl): Add.
1000 (mvtcp, mvfcp, opecp): Remove.
1002 2009-11-02 Paul Brook <paul@codesourcery.com>
1004 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1005 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1006 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1007 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1008 FPU_ARCH_NEON_VFP_V4): Define.
1010 2009-10-23 Doug Evans <dje@sebabeach.org>
1012 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1013 * cgen.h: Update. Improve multi-inclusion macro name.
1015 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1017 * ppc.h (PPC_OPCODE_476): Define.
1019 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1021 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1023 2009-09-29 DJ Delorie <dj@redhat.com>
1027 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1029 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1031 2009-09-21 Ben Elliston <bje@au.ibm.com>
1033 * ppc.h (PPC_OPCODE_PPCA2): New.
1035 2009-09-05 Martin Thuresson <martin@mtme.org>
1037 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1039 2009-08-29 Martin Thuresson <martin@mtme.org>
1041 * tic30.h (template): Rename type template to
1042 insn_template. Updated code to use new name.
1043 * tic54x.h (template): Rename type template to
1046 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1048 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1050 2009-06-11 Anthony Green <green@moxielogic.com>
1052 * moxie.h (MOXIE_F3_PCREL): Define.
1053 (moxie_form3_opc_info): Grow.
1055 2009-06-06 Anthony Green <green@moxielogic.com>
1057 * moxie.h (MOXIE_F1_M): Define.
1059 2009-04-15 Anthony Green <green@moxielogic.com>
1063 2009-04-06 DJ Delorie <dj@redhat.com>
1065 * h8300.h: Add relaxation attributes to MOVA opcodes.
1067 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1069 * ppc.h (ppc_parse_cpu): Declare.
1071 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1073 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1074 and _IMM11 for mbitclr and mbitset.
1075 * score-datadep.h: Update dependency information.
1077 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1079 * ppc.h (PPC_OPCODE_POWER7): New.
1081 2009-02-06 Doug Evans <dje@google.com>
1083 * i386.h: Add comment regarding sse* insns and prefixes.
1085 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1087 * mips.h (INSN_XLR): Define.
1088 (INSN_CHIP_MASK): Update.
1090 (OPCODE_IS_MEMBER): Update.
1091 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1093 2009-01-28 Doug Evans <dje@google.com>
1095 * opcode/i386.h: Add multiple inclusion protection.
1096 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1097 (EDI_REG_NUM): New macros.
1098 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1099 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1100 (REX_PREFIX_P): New macro.
1102 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1104 * ppc.h (struct powerpc_opcode): New field "deprecated".
1105 (PPC_OPCODE_NOPOWER4): Delete.
1107 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1109 * mips.h: Define CPU_R14000, CPU_R16000.
1110 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1112 2008-11-18 Catherine Moore <clm@codesourcery.com>
1114 * arm.h (FPU_NEON_FP16): New.
1115 (FPU_ARCH_NEON_FP16): New.
1117 2008-11-06 Chao-ying Fu <fu@mips.com>
1119 * mips.h: Doucument '1' for 5-bit sync type.
1121 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1123 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1126 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1128 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1130 2008-07-30 Michael J. Eager <eager@eagercon.com>
1132 * ppc.h (PPC_OPCODE_405): Define.
1133 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1135 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1137 * ppc.h (ppc_cpu_t): New typedef.
1138 (struct powerpc_opcode <flags>): Use it.
1139 (struct powerpc_operand <insert, extract>): Likewise.
1140 (struct powerpc_macro <flags>): Likewise.
1142 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1144 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1145 Update comment before MIPS16 field descriptors to mention MIPS16.
1146 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1148 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1149 New bit masks and shift counts for cins and exts.
1151 * mips.h: Document new field descriptors +Q.
1152 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1154 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1156 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1157 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1159 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1161 * ppc.h: (PPC_OPCODE_E500MC): New.
1163 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1165 * i386.h (MAX_OPERANDS): Set to 5.
1166 (MAX_MNEM_SIZE): Changed to 20.
1168 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1170 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1172 2008-03-09 Paul Brook <paul@codesourcery.com>
1174 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1176 2008-03-04 Paul Brook <paul@codesourcery.com>
1178 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1179 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1180 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1182 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1183 Nick Clifton <nickc@redhat.com>
1186 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1187 with a 32-bit displacement but without the top bit of the 4th byte
1190 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1192 * cr16.h (cr16_num_optab): Declared.
1194 2008-02-14 Hakan Ardo <hakan@debian.org>
1197 * avr.h (AVR_ISA_2xxe): Define.
1199 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1201 * mips.h: Update copyright.
1202 (INSN_CHIP_MASK): New macro.
1203 (INSN_OCTEON): New macro.
1204 (CPU_OCTEON): New macro.
1205 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1207 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1209 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1211 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1213 * avr.h (AVR_ISA_USB162): Add new opcode set.
1214 (AVR_ISA_AVR3): Likewise.
1216 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1218 * mips.h (INSN_LOONGSON_2E): New.
1219 (INSN_LOONGSON_2F): New.
1220 (CPU_LOONGSON_2E): New.
1221 (CPU_LOONGSON_2F): New.
1222 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1224 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1226 * mips.h (INSN_ISA*): Redefine certain values as an
1227 enumeration. Update comments.
1228 (mips_isa_table): New.
1229 (ISA_MIPS*): Redefine to match enumeration.
1230 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1233 2007-08-08 Ben Elliston <bje@au.ibm.com>
1235 * ppc.h (PPC_OPCODE_PPCPS): New.
1237 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1239 * m68k.h: Document j K & E.
1241 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1243 * cr16.h: New file for CR16 target.
1245 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1247 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1249 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1251 * m68k.h (mcfisa_c): New.
1252 (mcfusp, mcf_mask): Adjust.
1254 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1256 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1257 (num_powerpc_operands): Declare.
1258 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1259 (PPC_OPERAND_PLUS1): Define.
1261 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1263 * i386.h (REX_MODE64): Renamed to ...
1265 (REX_EXTX): Renamed to ...
1267 (REX_EXTY): Renamed to ...
1269 (REX_EXTZ): Renamed to ...
1272 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1274 * i386.h: Add entries from config/tc-i386.h and move tables
1275 to opcodes/i386-opc.h.
1277 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1279 * i386.h (FloatDR): Removed.
1280 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1282 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1284 * spu-insns.h: Add soma double-float insns.
1286 2007-02-20 Thiemo Seufer <ths@mips.com>
1287 Chao-Ying Fu <fu@mips.com>
1289 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1290 (INSN_DSPR2): Add flag for DSP R2 instructions.
1291 (M_BALIGN): New macro.
1293 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1295 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1296 and Seg3ShortFrom with Shortform.
1298 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1301 * i386.h (i386_optab): Put the real "test" before the pseudo
1304 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1306 * m68k.h (m68010up): OR fido_a.
1308 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1310 * m68k.h (fido_a): New.
1312 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1314 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1315 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1318 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1320 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1322 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1324 * score-inst.h (enum score_insn_type): Add Insn_internal.
1326 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1327 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1328 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1329 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1330 Alan Modra <amodra@bigpond.net.au>
1332 * spu-insns.h: New file.
1335 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1337 * ppc.h (PPC_OPCODE_CELL): Define.
1339 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1341 * i386.h : Modify opcode to support for the change in POPCNT opcode
1342 in amdfam10 architecture.
1344 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1346 * i386.h: Replace CpuMNI with CpuSSSE3.
1348 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1349 Joseph Myers <joseph@codesourcery.com>
1350 Ian Lance Taylor <ian@wasabisystems.com>
1351 Ben Elliston <bje@wasabisystems.com>
1353 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1355 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1357 * score-datadep.h: New file.
1358 * score-inst.h: New file.
1360 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1362 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1363 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1364 movdq2q and movq2dq.
1366 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1367 Michael Meissner <michael.meissner@amd.com>
1369 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1371 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1373 * i386.h (i386_optab): Add "nop" with memory reference.
1375 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1377 * i386.h (i386_optab): Update comment for 64bit NOP.
1379 2006-06-06 Ben Elliston <bje@au.ibm.com>
1380 Anton Blanchard <anton@samba.org>
1382 * ppc.h (PPC_OPCODE_POWER6): Define.
1385 2006-06-05 Thiemo Seufer <ths@mips.com>
1387 * mips.h: Improve description of MT flags.
1389 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1391 * m68k.h (mcf_mask): Define.
1393 2006-05-05 Thiemo Seufer <ths@mips.com>
1394 David Ung <davidu@mips.com>
1396 * mips.h (enum): Add macro M_CACHE_AB.
1398 2006-05-04 Thiemo Seufer <ths@mips.com>
1399 Nigel Stephens <nigel@mips.com>
1400 David Ung <davidu@mips.com>
1402 * mips.h: Add INSN_SMARTMIPS define.
1404 2006-04-30 Thiemo Seufer <ths@mips.com>
1405 David Ung <davidu@mips.com>
1407 * mips.h: Defines udi bits and masks. Add description of
1408 characters which may appear in the args field of udi
1411 2006-04-26 Thiemo Seufer <ths@networkno.de>
1413 * mips.h: Improve comments describing the bitfield instruction
1416 2006-04-26 Julian Brown <julian@codesourcery.com>
1418 * arm.h (FPU_VFP_EXT_V3): Define constant.
1419 (FPU_NEON_EXT_V1): Likewise.
1420 (FPU_VFP_HARD): Update.
1421 (FPU_VFP_V3): Define macro.
1422 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1424 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1426 * avr.h (AVR_ISA_PWMx): New.
1428 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1430 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1431 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1432 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1433 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1434 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1436 2006-03-10 Paul Brook <paul@codesourcery.com>
1438 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1440 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1442 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1443 first. Correct mask of bb "B" opcode.
1445 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1447 * i386.h (i386_optab): Support Intel Merom New Instructions.
1449 2006-02-24 Paul Brook <paul@codesourcery.com>
1451 * arm.h: Add V7 feature bits.
1453 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1455 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1457 2006-01-31 Paul Brook <paul@codesourcery.com>
1458 Richard Earnshaw <rearnsha@arm.com>
1460 * arm.h: Use ARM_CPU_FEATURE.
1461 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1462 (arm_feature_set): Change to a structure.
1463 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1464 ARM_FEATURE): New macros.
1466 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1468 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1469 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1470 (ADD_PC_INCR_OPCODE): Don't define.
1472 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1475 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1477 2005-11-14 David Ung <davidu@mips.com>
1479 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1480 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1481 save/restore encoding of the args field.
1483 2005-10-28 Dave Brolley <brolley@redhat.com>
1485 Contribute the following changes:
1486 2005-02-16 Dave Brolley <brolley@redhat.com>
1488 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1489 cgen_isa_mask_* to cgen_bitset_*.
1492 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1494 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1495 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1496 (CGEN_CPU_TABLE): Make isas a ponter.
1498 2003-09-29 Dave Brolley <brolley@redhat.com>
1500 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1501 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1502 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1504 2002-12-13 Dave Brolley <brolley@redhat.com>
1506 * cgen.h (symcat.h): #include it.
1507 (cgen-bitset.h): #include it.
1508 (CGEN_ATTR_VALUE_TYPE): Now a union.
1509 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1510 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1511 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1512 * cgen-bitset.h: New file.
1514 2005-09-30 Catherine Moore <clm@cm00re.com>
1518 2005-10-24 Jan Beulich <jbeulich@novell.com>
1520 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1523 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1525 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1526 Add FLAG_STRICT to pa10 ftest opcode.
1528 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1530 * hppa.h (pa_opcodes): Remove lha entries.
1532 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1534 * hppa.h (FLAG_STRICT): Revise comment.
1535 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1536 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1539 2005-09-30 Catherine Moore <clm@cm00re.com>
1543 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1545 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1547 2005-09-06 Chao-ying Fu <fu@mips.com>
1549 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1550 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1552 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1553 (INSN_ASE_MASK): Update to include INSN_MT.
1554 (INSN_MT): New define for MT ASE.
1556 2005-08-25 Chao-ying Fu <fu@mips.com>
1558 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1559 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1560 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1561 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1562 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1563 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1565 (INSN_DSP): New define for DSP ASE.
1567 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1571 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1573 * ppc.h (PPC_OPCODE_E300): Define.
1575 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1577 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1579 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1582 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1585 2005-07-27 Jan Beulich <jbeulich@novell.com>
1587 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1588 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1589 Add movq-s as 64-bit variants of movd-s.
1591 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1593 * hppa.h: Fix punctuation in comment.
1595 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1596 implicit space-register addressing. Set space-register bits on opcodes
1597 using implicit space-register addressing. Add various missing pa20
1598 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1599 space-register addressing. Use "fE" instead of "fe" in various
1602 2005-07-18 Jan Beulich <jbeulich@novell.com>
1604 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1606 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1608 * i386.h (i386_optab): Support Intel VMX Instructions.
1610 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1612 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1614 2005-07-05 Jan Beulich <jbeulich@novell.com>
1616 * i386.h (i386_optab): Add new insns.
1618 2005-07-01 Nick Clifton <nickc@redhat.com>
1620 * sparc.h: Add typedefs to structure declarations.
1622 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1625 * i386.h (i386_optab): Update comments for 64bit addressing on
1626 mov. Allow 64bit addressing for mov and movq.
1628 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1630 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1631 respectively, in various floating-point load and store patterns.
1633 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1635 * hppa.h (FLAG_STRICT): Correct comment.
1636 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1637 PA 2.0 mneumonics when equivalent. Entries with cache control
1638 completers now require PA 1.1. Adjust whitespace.
1640 2005-05-19 Anton Blanchard <anton@samba.org>
1642 * ppc.h (PPC_OPCODE_POWER5): Define.
1644 2005-05-10 Nick Clifton <nickc@redhat.com>
1646 * Update the address and phone number of the FSF organization in
1647 the GPL notices in the following files:
1648 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1649 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1650 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1651 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1652 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1653 tic54x.h, tic80.h, v850.h, vax.h
1655 2005-05-09 Jan Beulich <jbeulich@novell.com>
1657 * i386.h (i386_optab): Add ht and hnt.
1659 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1661 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1662 Add xcrypt-ctr. Provide aliases without hyphens.
1664 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1666 Moved from ../ChangeLog
1668 2005-04-12 Paul Brook <paul@codesourcery.com>
1669 * m88k.h: Rename psr macros to avoid conflicts.
1671 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1672 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1673 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1674 and ARM_ARCH_V6ZKT2.
1676 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1677 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1678 Remove redundant instruction types.
1679 (struct argument): X_op - new field.
1680 (struct cst4_entry): Remove.
1681 (no_op_insn): Declare.
1683 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1684 * crx.h (enum argtype): Rename types, remove unused types.
1686 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1687 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1688 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1689 (enum operand_type): Rearrange operands, edit comments.
1690 replace us<N> with ui<N> for unsigned immediate.
1691 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1692 displacements (respectively).
1693 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1694 (instruction type): Add NO_TYPE_INS.
1695 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1696 (operand_entry): New field - 'flags'.
1697 (operand flags): New.
1699 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1700 * crx.h (operand_type): Remove redundant types i3, i4,
1702 Add new unsigned immediate types us3, us4, us5, us16.
1704 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1706 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1707 adjust them accordingly.
1709 2005-04-01 Jan Beulich <jbeulich@novell.com>
1711 * i386.h (i386_optab): Add rdtscp.
1713 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1715 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1716 between memory and segment register. Allow movq for moving between
1717 general-purpose register and segment register.
1719 2005-02-09 Jan Beulich <jbeulich@novell.com>
1722 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1723 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1726 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1728 * m68k.h (m68008, m68ec030, m68882): Remove.
1730 (cpu_m68k, cpu_cf): New.
1731 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1732 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1734 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1736 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1737 * cgen.h (enum cgen_parse_operand_type): Add
1738 CGEN_PARSE_OPERAND_SYMBOLIC.
1740 2005-01-21 Fred Fish <fnf@specifixinc.com>
1742 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1743 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1744 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1746 2005-01-19 Fred Fish <fnf@specifixinc.com>
1748 * mips.h (struct mips_opcode): Add new pinfo2 member.
1749 (INSN_ALIAS): New define for opcode table entries that are
1750 specific instances of another entry, such as 'move' for an 'or'
1751 with a zero operand.
1752 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1753 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1755 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1757 * mips.h (CPU_RM9000): Define.
1758 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1760 2004-11-25 Jan Beulich <jbeulich@novell.com>
1762 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1763 to/from test registers are illegal in 64-bit mode. Add missing
1764 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1765 (previously one had to explicitly encode a rex64 prefix). Re-enable
1766 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1767 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1769 2004-11-23 Jan Beulich <jbeulich@novell.com>
1771 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1772 available only with SSE2. Change the MMX additions introduced by SSE
1773 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1774 instructions by their now designated identifier (since combining i686
1775 and 3DNow! does not really imply 3DNow!A).
1777 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1779 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1780 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1782 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1783 Vineet Sharma <vineets@noida.hcltech.com>
1785 * maxq.h: New file: Disassembly information for the maxq port.
1787 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1789 * i386.h (i386_optab): Put back "movzb".
1791 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1793 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1794 comments. Remove member cris_ver_sim. Add members
1795 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1796 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1797 (struct cris_support_reg, struct cris_cond15): New types.
1798 (cris_conds15): Declare.
1799 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1800 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1801 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1802 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1803 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1804 SIZE_FIELD_UNSIGNED.
1806 2004-11-04 Jan Beulich <jbeulich@novell.com>
1808 * i386.h (sldx_Suf): Remove.
1809 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1810 (q_FP): Define, implying no REX64.
1811 (x_FP, sl_FP): Imply FloatMF.
1812 (i386_optab): Split reg and mem forms of moving from segment registers
1813 so that the memory forms can ignore the 16-/32-bit operand size
1814 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1815 all non-floating-point instructions. Unite 32- and 64-bit forms of
1816 movsx, movzx, and movd. Adjust floating point operations for the above
1817 changes to the *FP macros. Add DefaultSize to floating point control
1818 insns operating on larger memory ranges. Remove left over comments
1819 hinting at certain insns being Intel-syntax ones where the ones
1820 actually meant are already gone.
1822 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1824 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1827 2004-09-30 Paul Brook <paul@codesourcery.com>
1829 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1830 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1832 2004-09-11 Theodore A. Roth <troth@openavr.org>
1834 * avr.h: Add support for
1835 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1837 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1839 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1841 2004-08-24 Dmitry Diky <diwil@spec.ru>
1843 * msp430.h (msp430_opc): Add new instructions.
1844 (msp430_rcodes): Declare new instructions.
1845 (msp430_hcodes): Likewise..
1847 2004-08-13 Nick Clifton <nickc@redhat.com>
1850 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1853 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1855 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1857 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1859 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1861 2004-07-21 Jan Beulich <jbeulich@novell.com>
1863 * i386.h: Adjust instruction descriptions to better match the
1866 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1868 * arm.h: Remove all old content. Replace with architecture defines
1869 from gas/config/tc-arm.c.
1871 2004-07-09 Andreas Schwab <schwab@suse.de>
1873 * m68k.h: Fix comment.
1875 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1879 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1881 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1883 2004-05-24 Peter Barada <peter@the-baradas.com>
1885 * m68k.h: Add 'size' to m68k_opcode.
1887 2004-05-05 Peter Barada <peter@the-baradas.com>
1889 * m68k.h: Switch from ColdFire chip name to core variant.
1891 2004-04-22 Peter Barada <peter@the-baradas.com>
1893 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1894 descriptions for new EMAC cases.
1895 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1896 handle Motorola MAC syntax.
1897 Allow disassembly of ColdFire V4e object files.
1899 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1901 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1903 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1905 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1907 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1909 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1911 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1913 * i386.h (i386_optab): Added xstore/xcrypt insns.
1915 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1917 * h8300.h (32bit ldc/stc): Add relaxing support.
1919 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1921 * h8300.h (BITOP): Pass MEMRELAX flag.
1923 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1925 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1928 For older changes see ChangeLog-9103
1930 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1932 Copying and distribution of this file, with or without modification,
1933 are permitted in any medium without royalty provided the copyright
1934 notice and this notice are preserved.
1940 version-control: never