include/opcode/ChangeLog

   1 2010-07-03  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
   4
   5 2010-06-29  Alan Modra  <amodra@gmail.com>
   6
   7         * maxq.h: Delete file.
   8
   9 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
  10
  11         * ppc.h (PPC_OPCODE_E500): Define.
  12
  13 2010-05-26  Catherine Moore  <clm@codesourcery.com>
  14
  15         * opcode/mips.h (INSN_MIPS16): Remove.
  16
  17 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
  18
  19         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
  20
  21 2010-04-15  Nick Clifton  <nickc@redhat.com>
  22
  23         * alpha.h: Update copyright notice to use GPLv3.
  24         * arc.h: Likewise.
  25         * arm.h: Likewise.
  26         * avr.h: Likewise.
  27         * bfin.h: Likewise.
  28         * cgen.h: Likewise.
  29         * convex.h: Likewise.
  30         * cr16.h: Likewise.
  31         * cris.h: Likewise.
  32         * crx.h: Likewise.
  33         * d10v.h: Likewise.
  34         * d30v.h: Likewise.
  35         * dlx.h: Likewise.
  36         * h8300.h: Likewise.
  37         * hppa.h: Likewise.
  38         * i370.h: Likewise.
  39         * i386.h: Likewise.
  40         * i860.h: Likewise.
  41         * i960.h: Likewise.
  42         * ia64.h: Likewise.
  43         * m68hc11.h: Likewise.
  44         * m68k.h: Likewise.
  45         * m88k.h: Likewise.
  46         * maxq.h: Likewise.
  47         * mips.h: Likewise.
  48         * mmix.h: Likewise.
  49         * mn10200.h: Likewise.
  50         * mn10300.h: Likewise.
  51         * msp430.h: Likewise.
  52         * np1.h: Likewise.
  53         * ns32k.h: Likewise.
  54         * or32.h: Likewise.
  55         * pdp11.h: Likewise.
  56         * pj.h: Likewise.
  57         * pn.h: Likewise.
  58         * ppc.h: Likewise.
  59         * pyr.h: Likewise.
  60         * rx.h: Likewise.
  61         * s390.h: Likewise.
  62         * score-datadep.h: Likewise.
  63         * score-inst.h: Likewise.
  64         * sparc.h: Likewise.
  65         * spu-insns.h: Likewise.
  66         * spu.h: Likewise.
  67         * tic30.h: Likewise.
  68         * tic4x.h: Likewise.
  69         * tic54x.h: Likewise.
  70         * tic80.h: Likewise.
  71         * v850.h: Likewise.
  72         * vax.h: Likewise.
  73
  74 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
  75
  76         * tic6x-control-registers.h, tic6x-insn-formats.h,
  77         tic6x-opcode-table.h, tic6x.h: New.
  78
  79 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
  80
  81         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
  82
  83 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
  84
  85         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
  86
  87 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
  88
  89         * ia64.h (ia64_find_opcode): Remove argument name.
  90         (ia64_find_next_opcode): Likewise.
  91         (ia64_dis_opcode): Likewise.
  92         (ia64_free_opcode): Likewise.
  93         (ia64_find_dependency): Likewise.
  94
  95 2009-11-22  Doug Evans  <dje@sebabeach.org>
  96
  97         * cgen.h: Include bfd_stdint.h.
  98         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
  99
 100 2009-11-18  Paul Brook  <paul@codesourcery.com>
 101
 102         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 103
 104 2009-11-17  Paul Brook  <paul@codesourcery.com>
 105         Daniel Jacobowitz  <dan@codesourcery.com>
 106
 107         * arm.h (ARM_EXT_V6_DSP): Define.
 108         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 109         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 110
 111 2009-11-04  DJ Delorie  <dj@redhat.com>
 112
 113         * rx.h (rx_decode_opcode) (mvtipl): Add.
 114         (mvtcp, mvfcp, opecp): Remove.
 115
 116 2009-11-02  Paul Brook  <paul@codesourcery.com>
 117
 118         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 119         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 120         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 121         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 122         FPU_ARCH_NEON_VFP_V4): Define.
 123
 124 2009-10-23  Doug Evans  <dje@sebabeach.org>
 125
 126         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 127         * cgen.h: Update.  Improve multi-inclusion macro name.
 128
 129 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 130
 131         * ppc.h (PPC_OPCODE_476): Define.
 132
 133 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 134
 135         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 136
 137 2009-09-29  DJ Delorie  <dj@redhat.com>
 138
 139         * rx.h: New file.
 140
 141 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 142
 143         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 144
 145 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 146
 147         * ppc.h (PPC_OPCODE_PPCA2): New.
 148
 149 2009-09-05  Martin Thuresson  <martin@mtme.org>
 150
 151         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 152
 153 2009-08-29  Martin Thuresson  <martin@mtme.org>
 154
 155         * tic30.h (template): Rename type template to
 156         insn_template. Updated code to use new name.
 157         * tic54x.h (template): Rename type template to
 158         insn_template.
 159
 160 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 161
 162         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 163
 164 2009-06-11  Anthony Green  <green@moxielogic.com>
 165
 166         * moxie.h (MOXIE_F3_PCREL): Define.
 167         (moxie_form3_opc_info): Grow.
 168
 169 2009-06-06  Anthony Green  <green@moxielogic.com>
 170
 171         * moxie.h (MOXIE_F1_M): Define.
 172
 173 2009-04-15  Anthony Green  <green@moxielogic.com>
 174
 175         * moxie.h: Created.
 176
 177 2009-04-06  DJ Delorie  <dj@redhat.com>
 178
 179         * h8300.h: Add relaxation attributes to MOVA opcodes.
 180
 181 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 182
 183         * ppc.h (ppc_parse_cpu): Declare.
 184
 185 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 186
 187         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 188         and _IMM11 for mbitclr and mbitset.
 189         * score-datadep.h: Update dependency information.
 190
 191 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 192
 193         * ppc.h (PPC_OPCODE_POWER7): New.
 194
 195 2009-02-06  Doug Evans  <dje@google.com>
 196
 197         * i386.h: Add comment regarding sse* insns and prefixes.
 198
 199 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 200
 201         * mips.h (INSN_XLR): Define.
 202         (INSN_CHIP_MASK): Update.
 203         (CPU_XLR): Define.
 204         (OPCODE_IS_MEMBER): Update.
 205         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 206
 207 2009-01-28  Doug Evans  <dje@google.com>
 208
 209         * opcode/i386.h: Add multiple inclusion protection.
 210         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 211         (EDI_REG_NUM): New macros.
 212         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 213         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 214         (REX_PREFIX_P): New macro.
 215
 216 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 217
 218         * ppc.h (struct powerpc_opcode): New field "deprecated".
 219         (PPC_OPCODE_NOPOWER4): Delete.
 220
 221 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 222
 223         * mips.h: Define CPU_R14000, CPU_R16000.
 224         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 225
 226 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 227
 228         * arm.h (FPU_NEON_FP16): New.
 229         (FPU_ARCH_NEON_FP16): New.
 230
 231 2008-11-06  Chao-ying Fu  <fu@mips.com>
 232
 233         * mips.h: Doucument '1' for 5-bit sync type.
 234
 235 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 238         IA64_RS_CR.
 239
 240 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 241
 242         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 243
 244 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 245
 246         * ppc.h (PPC_OPCODE_405): Define.
 247         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 248
 249 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 250
 251         * ppc.h (ppc_cpu_t): New typedef.
 252         (struct powerpc_opcode <flags>): Use it.
 253         (struct powerpc_operand <insert, extract>): Likewise.
 254         (struct powerpc_macro <flags>): Likewise.
 255
 256 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 257
 258         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 259         Update comment before MIPS16 field descriptors to mention MIPS16.
 260         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 261         BBIT.
 262         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 263         New bit masks and shift counts for cins and exts.
 264
 265         * mips.h: Document new field descriptors +Q.
 266         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 267
 268 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 269
 270         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 271         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 272
 273 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 274
 275         * ppc.h: (PPC_OPCODE_E500MC): New.
 276
 277 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * i386.h (MAX_OPERANDS): Set to 5.
 280         (MAX_MNEM_SIZE): Changed to 20.
 281
 282 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 283
 284         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 285
 286 2008-03-09  Paul Brook  <paul@codesourcery.com>
 287
 288         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 289
 290 2008-03-04  Paul Brook  <paul@codesourcery.com>
 291
 292         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 293         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 294         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 295
 296 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 297             Nick Clifton  <nickc@redhat.com>
 298
 299         PR 3134
 300         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 301         with a 32-bit displacement but without the top bit of the 4th byte
 302         set.
 303
 304 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 305
 306         * cr16.h (cr16_num_optab): Declared.
 307
 308 2008-02-14  Hakan Ardo  <hakan@debian.org>
 309
 310         PR gas/2626
 311         * avr.h (AVR_ISA_2xxe): Define.
 312
 313 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 314
 315         * mips.h: Update copyright.
 316         (INSN_CHIP_MASK): New macro.
 317         (INSN_OCTEON): New macro.
 318         (CPU_OCTEON): New macro.
 319         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 320
 321 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 322
 323         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 324
 325 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 326
 327         * avr.h (AVR_ISA_USB162): Add new opcode set.
 328         (AVR_ISA_AVR3): Likewise.
 329
 330 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 331
 332         * mips.h (INSN_LOONGSON_2E): New.
 333         (INSN_LOONGSON_2F): New.
 334         (CPU_LOONGSON_2E): New.
 335         (CPU_LOONGSON_2F): New.
 336         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 337
 338 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 339
 340         * mips.h (INSN_ISA*): Redefine certain values as an
 341         enumeration.  Update comments.
 342         (mips_isa_table): New.
 343         (ISA_MIPS*): Redefine to match enumeration.
 344         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 345         values.
 346
 347 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 348
 349         * ppc.h (PPC_OPCODE_PPCPS): New.
 350
 351 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 352
 353         * m68k.h: Document j K & E.
 354
 355 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 356
 357         * cr16.h: New file for CR16 target.
 358
 359 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 360
 361         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 362
 363 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 364
 365         * m68k.h (mcfisa_c): New.
 366         (mcfusp, mcf_mask): Adjust.
 367
 368 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 369
 370         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 371         (num_powerpc_operands): Declare.
 372         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 373         (PPC_OPERAND_PLUS1): Define.
 374
 375 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 376
 377         * i386.h (REX_MODE64): Renamed to ...
 378         (REX_W): This.
 379         (REX_EXTX): Renamed to ...
 380         (REX_R): This.
 381         (REX_EXTY): Renamed to ...
 382         (REX_X): This.
 383         (REX_EXTZ): Renamed to ...
 384         (REX_B): This.
 385
 386 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         * i386.h: Add entries from config/tc-i386.h and move tables
 389         to opcodes/i386-opc.h.
 390
 391 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         * i386.h (FloatDR): Removed.
 394         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 395
 396 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 397
 398         * spu-insns.h: Add soma double-float insns.
 399
 400 2007-02-20  Thiemo Seufer  <ths@mips.com>
 401             Chao-Ying Fu  <fu@mips.com>
 402
 403         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 404         (INSN_DSPR2): Add flag for DSP R2 instructions.
 405         (M_BALIGN): New macro.
 406
 407 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 408
 409         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 410         and Seg3ShortFrom with Shortform.
 411
 412 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         PR gas/4027
 415         * i386.h (i386_optab): Put the real "test" before the pseudo
 416         one.
 417
 418 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 419
 420         * m68k.h (m68010up): OR fido_a.
 421
 422 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 423
 424         * m68k.h (fido_a): New.
 425
 426 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 427
 428         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 429         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 430         values.
 431
 432 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 433
 434         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 435
 436 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 437
 438         * score-inst.h (enum score_insn_type): Add Insn_internal.
 439
 440 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 441             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 442             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 443             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 444             Alan Modra  <amodra@bigpond.net.au>
 445
 446         * spu-insns.h: New file.
 447         * spu.h: New file.
 448
 449 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 450
 451         * ppc.h (PPC_OPCODE_CELL): Define.
 452
 453 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 454
 455         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 456         in amdfam10 architecture.
 457
 458 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         * i386.h: Replace CpuMNI with CpuSSSE3.
 461
 462 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 463             Joseph Myers  <joseph@codesourcery.com>
 464             Ian Lance Taylor  <ian@wasabisystems.com>
 465             Ben Elliston  <bje@wasabisystems.com>
 466
 467         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 468
 469 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 470
 471         * score-datadep.h: New file.
 472         * score-inst.h: New file.
 473
 474 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 477         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 478         movdq2q and movq2dq.
 479
 480 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 481            Michael Meissner             <michael.meissner@amd.com>
 482
 483         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 484
 485 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         * i386.h (i386_optab): Add "nop" with memory reference.
 488
 489 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         * i386.h (i386_optab): Update comment for 64bit NOP.
 492
 493 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 494             Anton Blanchard  <anton@samba.org>
 495
 496         * ppc.h (PPC_OPCODE_POWER6): Define.
 497         Adjust whitespace.
 498
 499 2006-06-05  Thiemo Seufer  <ths@mips.com>
 500
 501         * mips.h: Improve description of MT flags.
 502
 503 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 504
 505         * m68k.h (mcf_mask): Define.
 506
 507 2006-05-05  Thiemo Seufer  <ths@mips.com>
 508             David Ung  <davidu@mips.com>
 509
 510         * mips.h (enum): Add macro M_CACHE_AB.
 511
 512 2006-05-04  Thiemo Seufer  <ths@mips.com>
 513             Nigel Stephens  <nigel@mips.com>
 514             David Ung  <davidu@mips.com>
 515
 516         * mips.h: Add INSN_SMARTMIPS define.
 517
 518 2006-04-30  Thiemo Seufer  <ths@mips.com>
 519             David Ung  <davidu@mips.com>
 520
 521         * mips.h: Defines udi bits and masks.  Add description of
 522         characters which may appear in the args field of udi
 523         instructions.
 524
 525 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 526
 527         * mips.h: Improve comments describing the bitfield instruction
 528         fields.
 529
 530 2006-04-26  Julian Brown  <julian@codesourcery.com>
 531
 532         * arm.h (FPU_VFP_EXT_V3): Define constant.
 533         (FPU_NEON_EXT_V1): Likewise.
 534         (FPU_VFP_HARD): Update.
 535         (FPU_VFP_V3): Define macro.
 536         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 537
 538 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 539
 540         * avr.h (AVR_ISA_PWMx): New.
 541
 542 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 543
 544         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 545         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 546         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 547         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 548         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 549
 550 2006-03-10  Paul Brook  <paul@codesourcery.com>
 551
 552         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 553
 554 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 555
 556         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 557         first.  Correct mask of bb "B" opcode.
 558
 559 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 560
 561         * i386.h (i386_optab): Support Intel Merom New Instructions.
 562
 563 2006-02-24  Paul Brook  <paul@codesourcery.com>
 564
 565         * arm.h: Add V7 feature bits.
 566
 567 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 568
 569         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 570
 571 2006-01-31  Paul Brook  <paul@codesourcery.com>
 572         Richard Earnshaw <rearnsha@arm.com>
 573
 574         * arm.h: Use ARM_CPU_FEATURE.
 575         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 576         (arm_feature_set): Change to a structure.
 577         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 578         ARM_FEATURE): New macros.
 579
 580 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 581
 582         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 583         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 584         (ADD_PC_INCR_OPCODE): Don't define.
 585
 586 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         PR gas/1874
 589         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 590
 591 2005-11-14  David Ung  <davidu@mips.com>
 592
 593         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 594         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 595         save/restore encoding of the args field.
 596
 597 2005-10-28  Dave Brolley  <brolley@redhat.com>
 598
 599         Contribute the following changes:
 600         2005-02-16  Dave Brolley  <brolley@redhat.com>
 601
 602         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 603         cgen_isa_mask_* to cgen_bitset_*.
 604         * cgen.h: Likewise.
 605
 606         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 607
 608         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 609         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 610         (CGEN_CPU_TABLE): Make isas a ponter.
 611
 612         2003-09-29  Dave Brolley  <brolley@redhat.com>
 613
 614         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 615         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 616         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 617
 618         2002-12-13  Dave Brolley  <brolley@redhat.com>
 619
 620         * cgen.h (symcat.h): #include it.
 621         (cgen-bitset.h): #include it.
 622         (CGEN_ATTR_VALUE_TYPE): Now a union.
 623         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 624         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 625         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 626         * cgen-bitset.h: New file.
 627
 628 2005-09-30  Catherine Moore  <clm@cm00re.com>
 629
 630         * bfin.h: New file.
 631
 632 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 633
 634         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 635         indirect operands.
 636
 637 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 638
 639         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 640         Add FLAG_STRICT to pa10 ftest opcode.
 641
 642 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 643
 644         * hppa.h (pa_opcodes): Remove lha entries.
 645
 646 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 647
 648         * hppa.h (FLAG_STRICT): Revise comment.
 649         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 650         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 651         entries for "fdc".
 652
 653 2005-09-30  Catherine Moore  <clm@cm00re.com>
 654
 655         * bfin.h: New file.
 656
 657 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 658
 659         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 660
 661 2005-09-06  Chao-ying Fu  <fu@mips.com>
 662
 663         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 664         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 665         define.
 666         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 667         (INSN_ASE_MASK): Update to include INSN_MT.
 668         (INSN_MT): New define for MT ASE.
 669
 670 2005-08-25  Chao-ying Fu  <fu@mips.com>
 671
 672         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 673         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 674         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 675         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 676         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 677         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 678         instructions.
 679         (INSN_DSP): New define for DSP ASE.
 680
 681 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 682
 683         * a29k.h: Delete.
 684
 685 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 686
 687         * ppc.h (PPC_OPCODE_E300): Define.
 688
 689 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 690
 691         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 692
 693 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 694
 695         PR gas/336
 696         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 697         and pitlb.
 698
 699 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 700
 701         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 702         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 703         Add movq-s as 64-bit variants of movd-s.
 704
 705 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 706
 707         * hppa.h: Fix punctuation in comment.
 708
 709         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 710         implicit space-register addressing.  Set space-register bits on opcodes
 711         using implicit space-register addressing.  Add various missing pa20
 712         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 713         space-register addressing.  Use "fE" instead of "fe" in various
 714         fstw opcodes.
 715
 716 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 717
 718         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 719
 720 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 721
 722         * i386.h (i386_optab): Support Intel VMX Instructions.
 723
 724 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 725
 726         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 727
 728 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 729
 730         * i386.h (i386_optab): Add new insns.
 731
 732 2005-07-01  Nick Clifton  <nickc@redhat.com>
 733
 734         * sparc.h: Add typedefs to structure declarations.
 735
 736 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         PR 1013
 739         * i386.h (i386_optab): Update comments for 64bit addressing on
 740         mov. Allow 64bit addressing for mov and movq.
 741
 742 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 743
 744         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 745         respectively, in various floating-point load and store patterns.
 746
 747 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 748
 749         * hppa.h (FLAG_STRICT): Correct comment.
 750         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 751         PA 2.0 mneumonics when equivalent.  Entries with cache control
 752         completers now require PA 1.1.  Adjust whitespace.
 753
 754 2005-05-19  Anton Blanchard  <anton@samba.org>
 755
 756         * ppc.h (PPC_OPCODE_POWER5): Define.
 757
 758 2005-05-10  Nick Clifton  <nickc@redhat.com>
 759
 760         * Update the address and phone number of the FSF organization in
 761         the GPL notices in the following files:
 762         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 763         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 764         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 765         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 766         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 767         tic54x.h, tic80.h, v850.h, vax.h
 768
 769 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 770
 771         * i386.h (i386_optab): Add ht and hnt.
 772
 773 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 774
 775         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 776         Add xcrypt-ctr.  Provide aliases without hyphens.
 777
 778 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         Moved from ../ChangeLog
 781
 782         2005-04-12  Paul Brook  <paul@codesourcery.com>
 783         * m88k.h: Rename psr macros to avoid conflicts.
 784
 785         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 786         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 787         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 788         and ARM_ARCH_V6ZKT2.
 789
 790         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 791         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 792         Remove redundant instruction types.
 793         (struct argument): X_op - new field.
 794         (struct cst4_entry): Remove.
 795         (no_op_insn): Declare.
 796
 797         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 798         * crx.h (enum argtype): Rename types, remove unused types.
 799
 800         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 801         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 802         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 803         (enum operand_type): Rearrange operands, edit comments.
 804         replace us<N> with ui<N> for unsigned immediate.
 805         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 806         displacements (respectively).
 807         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 808         (instruction type): Add NO_TYPE_INS.
 809         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 810         (operand_entry): New field - 'flags'.
 811         (operand flags): New.
 812
 813         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 814         * crx.h (operand_type): Remove redundant types i3, i4,
 815         i5, i8, i12.
 816         Add new unsigned immediate types us3, us4, us5, us16.
 817
 818 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 819
 820         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 821         adjust them accordingly.
 822
 823 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 824
 825         * i386.h (i386_optab): Add rdtscp.
 826
 827 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 830         between memory and segment register. Allow movq for moving between
 831         general-purpose register and segment register.
 832
 833 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 834
 835         PR gas/707
 836         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 837         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 838         fnstsw.
 839
 840 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 841
 842         * m68k.h (m68008, m68ec030, m68882): Remove.
 843         (m68k_mask): New.
 844         (cpu_m68k, cpu_cf): New.
 845         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 846         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 847
 848 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 849
 850         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 851         * cgen.h (enum cgen_parse_operand_type): Add
 852         CGEN_PARSE_OPERAND_SYMBOLIC.
 853
 854 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 855
 856         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 857         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 858         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 859
 860 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 861
 862         * mips.h (struct mips_opcode): Add new pinfo2 member.
 863         (INSN_ALIAS): New define for opcode table entries that are
 864         specific instances of another entry, such as 'move' for an 'or'
 865         with a zero operand.
 866         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 867         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 868
 869 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 870
 871         * mips.h (CPU_RM9000): Define.
 872         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 873
 874 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 875
 876         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 877         to/from test registers are illegal in 64-bit mode. Add missing
 878         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 879         (previously one had to explicitly encode a rex64 prefix). Re-enable
 880         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 881         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 882
 883 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 884
 885         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 886         available only with SSE2. Change the MMX additions introduced by SSE
 887         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 888         instructions by their now designated identifier (since combining i686
 889         and 3DNow! does not really imply 3DNow!A).
 890
 891 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 892
 893         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 894         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 895
 896 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 897             Vineet Sharma      <vineets@noida.hcltech.com>
 898
 899         * maxq.h: New file: Disassembly information for the maxq port.
 900
 901 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * i386.h (i386_optab): Put back "movzb".
 904
 905 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 906
 907         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 908         comments.  Remove member cris_ver_sim.  Add members
 909         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 910         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 911         (struct cris_support_reg, struct cris_cond15): New types.
 912         (cris_conds15): Declare.
 913         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 914         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 915         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 916         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 917         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 918         SIZE_FIELD_UNSIGNED.
 919
 920 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 921
 922         * i386.h (sldx_Suf): Remove.
 923         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 924         (q_FP): Define, implying no REX64.
 925         (x_FP, sl_FP): Imply FloatMF.
 926         (i386_optab): Split reg and mem forms of moving from segment registers
 927         so that the memory forms can ignore the 16-/32-bit operand size
 928         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 929         all non-floating-point instructions. Unite 32- and 64-bit forms of
 930         movsx, movzx, and movd. Adjust floating point operations for the above
 931         changes to the *FP macros. Add DefaultSize to floating point control
 932         insns operating on larger memory ranges. Remove left over comments
 933         hinting at certain insns being Intel-syntax ones where the ones
 934         actually meant are already gone.
 935
 936 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 937
 938         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 939         instruction type.
 940
 941 2004-09-30  Paul Brook  <paul@codesourcery.com>
 942
 943         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 944         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 945
 946 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 947
 948         * avr.h: Add support for
 949         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 950
 951 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 952
 953         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 954
 955 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 956
 957         * msp430.h (msp430_opc): Add new instructions.
 958         (msp430_rcodes): Declare new instructions.
 959         (msp430_hcodes): Likewise..
 960
 961 2004-08-13  Nick Clifton  <nickc@redhat.com>
 962
 963         PR/301
 964         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 965         processors.
 966
 967 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 968
 969         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 970
 971 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 972
 973         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 974
 975 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 976
 977         * i386.h: Adjust instruction descriptions to better match the
 978         specification.
 979
 980 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 981
 982         * arm.h: Remove all old content.  Replace with architecture defines
 983         from gas/config/tc-arm.c.
 984
 985 2004-07-09  Andreas Schwab  <schwab@suse.de>
 986
 987         * m68k.h: Fix comment.
 988
 989 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 990
 991         * crx.h: New file.
 992
 993 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 994
 995         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 996
 997 2004-05-24  Peter Barada  <peter@the-baradas.com>
 998
 999         * m68k.h: Add 'size' to m68k_opcode.
1000
1001 2004-05-05  Peter Barada  <peter@the-baradas.com>
1002
1003         * m68k.h: Switch from ColdFire chip name to core variant.
1004
1005 2004-04-22  Peter Barada  <peter@the-baradas.com>
1006
1007         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1008         descriptions for new EMAC cases.
1009         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1010         handle Motorola MAC syntax.
1011         Allow disassembly of ColdFire V4e object files.
1012
1013 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1014
1015         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1016
1017 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1018
1019         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1020
1021 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1022
1023         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1024
1025 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1026
1027         * i386.h (i386_optab): Added xstore/xcrypt insns.
1028
1029 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1030
1031         * h8300.h (32bit ldc/stc): Add relaxing support.
1032
1033 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1034
1035         * h8300.h (BITOP): Pass MEMRELAX flag.
1036
1037 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1038
1039         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1040         except for the H8S.
1041
1042 For older changes see ChangeLog-9103
1043 \f
1044 Local Variables:
1045 mode: change-log
1046 left-margin: 8
1047 fill-column: 74
1048 version-control: never
1049 End: