include/opcode/ChangeLog

   1 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * bfin.h: Remove +x file mode.
   4
   5 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
   6
   7         * aarch64.h (aarch64_pstatefields): Change element type to
   8         aarch64_sys_reg.
   9
  10 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  11
  12         * arm.h (ARM_AEXT_V7VE): New define.
  13         (ARM_ARCH_V7VE): New define.
  14         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  15
  16 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  17
  18         Revert
  19
  20         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  21
  22         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  23         (aarch64_sys_reg_writeonly_p): Ditto.
  24
  25 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  26
  27         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  28         (aarch64_sys_reg_writeonly_p): Ditto.
  29
  30 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  31
  32         * aarch64.h (aarch64_sys_reg): New typedef.
  33         (aarch64_sys_regs): Change to define with the new type.
  34         (aarch64_sys_reg_deprecated_p): Declare.
  35
  36 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  37
  38         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
  39         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
  40
  41 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  42
  43         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
  44         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
  45         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  46         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  47         For MIPS, update extension character sequences after +.
  48         (ASE_MSA): New define.
  49         (ASE_MSA64): New define.
  50         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  51         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  52         For microMIPS, update extension character sequences after +.
  53
  54 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  55
  56         PR binutils/15834
  57         * i960.h: Fix typos.
  58
  59 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  60
  61         * mips.h: Remove references to "+I" and imm2_expr.
  62
  63 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  64
  65         * mips.h (M_DEXT, M_DINS): Delete.
  66
  67 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  68
  69         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
  70         (mips_optional_operand_p): New function.
  71
  72 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  73             Richard Sandiford  <rdsandiford@googlemail.com>
  74
  75         * mips.h: Document new VU0 operand characters.
  76         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
  77         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
  78         (OP_REG_R5900_ACC): New mips_reg_operand_types.
  79         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
  80         (mips_vu0_channel_mask): Declare.
  81
  82 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  83
  84         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
  85         (mips_int_operand_min, mips_int_operand_max): New functions.
  86         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
  87
  88 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  89
  90         * mips.h (mips_decode_reg_operand): New function.
  91         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
  92         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
  93         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
  94         New macros.
  95         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
  96         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
  97         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
  98         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
  99         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 100         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 101         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 102         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 103         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 104         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 105         macros to cover the gaps.
 106         (INSN2_MOD_SP): Replace with...
 107         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 108         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 109         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 110         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 111         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 112         Delete.
 113
 114 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 115
 116         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 117         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 118         (MIPS16_INSN_COND_BRANCH): Delete.
 119
 120 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 121             Kirill Yukhin  <kirill.yukhin@intel.com>
 122             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 123
 124         * i386.h (BND_PREFIX_OPCODE): New.
 125
 126 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 127
 128         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 129         OP_SAVE_RESTORE_LIST.
 130         (decode_mips16_operand): Declare.
 131
 132 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 133
 134         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 135         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 136         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 137         (mips_pcrel_operand): New structures.
 138         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 139         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 140         (decode_mips_operand, decode_micromips_operand): Declare.
 141
 142 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * mips.h: Document MIPS16 "I" opcode.
 145
 146 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 147
 148         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 149         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 150         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 151         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 152         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 153         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 154         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 155         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 156         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 157         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 158         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 159         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 160         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 161         Rename to...
 162         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 163         (M_USD_AB): ...these.
 164
 165 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 166
 167         * mips.h: Remove documentation of "[" and "]".  Update documentation
 168         of "k" and the MDMX formats.
 169
 170 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 171
 172         * mips.h: Update documentation of "+s" and "+S".
 173
 174 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 175
 176         * mips.h: Document "+i".
 177
 178 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 179
 180         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 181         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 182         Delete.
 183         (INSN2_WRITE_GPR_MHI): Rename to...
 184         (INSN2_WRITE_GPR_MH): ...this.
 185
 186 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 187
 188         * mips.h: Remove documentation of "+D" and "+T".
 189
 190 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 191
 192         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 193         Use "source" rather than "destination" for microMIPS "G".
 194
 195 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 196
 197         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 198         values.
 199
 200 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 201
 202         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 203
 204 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 205             Maciej W. Rozycki  <macro@codesourcery.com>
 206             Chao-Ying Fu  <fu@mips.com>
 207
 208         * mips.h (OP_SH_EVAOFFSET): Define.
 209         (OP_MASK_EVAOFFSET): Define.
 210         (INSN_ASE_MASK): Delete.
 211         (ASE_EVA): Define.
 212         (M_CACHEE_AB, M_CACHEE_OB): New.
 213         (M_LBE_OB, M_LBE_AB): New.
 214         (M_LBUE_OB, M_LBUE_AB): New.
 215         (M_LHE_OB, M_LHE_AB): New.
 216         (M_LHUE_OB, M_LHUE_AB): New.
 217         (M_LLE_AB, M_LLE_OB): New.
 218         (M_LWE_OB, M_LWE_AB): New.
 219         (M_LWLE_AB, M_LWLE_OB): New.
 220         (M_LWRE_AB, M_LWRE_OB): New.
 221         (M_PREFE_AB, M_PREFE_OB): New.
 222         (M_SCE_AB, M_SCE_OB): New.
 223         (M_SBE_OB, M_SBE_AB): New.
 224         (M_SHE_OB, M_SHE_AB): New.
 225         (M_SWE_OB, M_SWE_AB): New.
 226         (M_SWLE_AB, M_SWLE_OB): New.
 227         (M_SWRE_AB, M_SWRE_OB): New.
 228         (MICROMIPSOP_SH_EVAOFFSET): Define.
 229         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 230
 231 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 232
 233         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 234
 235 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 236
 237         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 238
 239 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 240
 241         * mips.h (OP_MASK_CODE10): Correct definition.
 242         (OP_SH_CODE10): Likewise.
 243         Add a comment that "+J" is used now for OP_*CODE10.
 244         (INSN_ASE_MASK): Update.
 245         (INSN_VIRT): New macro.
 246         (INSN_VIRT64): New macro
 247
 248 2013-05-02  Nick Clifton  <nickc@redhat.com>
 249
 250         * msp430.h: Add patterns for MSP430X instructions.
 251
 252 2013-04-06  David S. Miller  <davem@davemloft.net>
 253
 254         * sparc.h (F_PREFERRED): Define.
 255         (F_PREF_ALIAS): Define.
 256
 257 2013-04-03  Nick Clifton  <nickc@redhat.com>
 258
 259         * v850.h (V850_INVERSE_PCREL): Define.
 260
 261 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 262
 263         PR binutils/15068
 264         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 265
 266 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 267
 268         PR binutils/15068
 269         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 270         Add 16-bit opcodes.
 271         * tic6xc-opcode-table.h: Add 16-bit insns.
 272         * tic6x.h: Add support for 16-bit insns.
 273
 274 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 275
 276         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 277         and mov.b/w/l Rs,@(d:32,ERd).
 278
 279 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 280
 281         PR gas/15082
 282         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 283         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 284         tic6x_operand_xregpair operand coding type.
 285         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 286         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 287         TIC6X_FLAG_NO_CROSS.
 288
 289 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 290
 291         PR gas/15095
 292         * tic6x.h (enum tic6x_coding_method): Add
 293         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 294         separately the msb and lsb of a register pair.  This is needed to
 295         encode the opcodes in the same way as TI assembler does.
 296         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 297         and rsqrdp opcodes to use the new field coding types.
 298
 299 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 300
 301         * arm.h (CRC_EXT_ARMV8): New constant.
 302         (ARCH_CRC_ARMV8): New macro.
 303
 304 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 305
 306         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 307
 308 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 309             Andrew Jenner <andrew@codesourcery.com>
 310
 311         Based on patches from Altera Corporation.
 312
 313         * nios2.h: New file.
 314
 315 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 316
 317         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 318
 319 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 320
 321         PR gas/15069
 322         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 323
 324 2013-01-24  Nick Clifton  <nickc@redhat.com>
 325
 326         * v850.h: Add e3v5 support.
 327
 328 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 329
 330         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 331
 332 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 333
 334         * ppc.h (PPC_OPCODE_POWER8): New define.
 335         (PPC_OPCODE_HTM): Likewise.
 336
 337 2013-01-10  Will Newton <will.newton@imgtec.com>
 338
 339         * metag.h: New file.
 340
 341 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 342
 343         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 344         (match_opcode): Rename to cr16_match_opcode.
 345
 346 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 347
 348         * mips.h: Add support for r5900 instructions including lq and sq.
 349
 350 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 351
 352         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 353         (make_instruction,match_opcode): Added function prototypes.
 354         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 355
 356 2012-11-23  Alan Modra  <amodra@gmail.com>
 357
 358         * ppc.h (ppc_parse_cpu): Update prototype.
 359
 360 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 361
 362         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 363         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 364
 365 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 366
 367         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 368
 369 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 370
 371         * ia64.h (ia64_opnd): Add new operand types.
 372
 373 2012-08-21  David S. Miller  <davem@davemloft.net>
 374
 375         * sparc.h (F3F4): New macro.
 376
 377 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 378             Laurent Desnogues  <laurent.desnogues@arm.com>
 379             Jim MacArthur  <jim.macarthur@arm.com>
 380             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 381             Nigel Stephens  <nigel.stephens@arm.com>
 382             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 383             Richard Earnshaw  <rearnsha@arm.com>
 384             Sofiane Naci  <sofiane.naci@arm.com>
 385             Tejas Belagod  <tejas.belagod@arm.com>
 386             Yufeng Zhang  <yufeng.zhang@arm.com>
 387
 388         * aarch64.h: New file.
 389
 390 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 391             Maciej W. Rozycki  <macro@codesourcery.com>
 392
 393         * mips.h (mips_opcode): Add the exclusions field.
 394         (OPCODE_IS_MEMBER): Remove macro.
 395         (cpu_is_member): New inline function.
 396         (opcode_is_member): Likewise.
 397
 398 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 399             Catherine Moore  <clm@codesourcery.com>
 400             Maciej W. Rozycki  <macro@codesourcery.com>
 401
 402         * mips.h: Document microMIPS DSP ASE usage.
 403         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 404         microMIPS DSP ASE support.
 405         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 406         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 407         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 408         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 409         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 410         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 411         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 412
 413 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 414
 415         * mips.h: Fix a typo in description.
 416
 417 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 418
 419         * avr.h: (AVR_ISA_XCH): New define.
 420         (AVR_ISA_XMEGA): Use it.
 421         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 422
 423 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 424
 425         * m68hc11.h: Add XGate definitions.
 426         (struct m68hc11_opcode): Add xg_mask field.
 427
 428 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 429             Maciej W. Rozycki  <macro@codesourcery.com>
 430             Rhonda Wittels  <rhonda@codesourcery.com>
 431
 432         * ppc.h (PPC_OPCODE_VLE): New definition.
 433         (PPC_OP_SA): New macro.
 434         (PPC_OP_SE_VLE): New macro.
 435         (PPC_OP): Use a variable shift amount.
 436         (powerpc_operand): Update comments.
 437         (PPC_OPSHIFT_INV): New macro.
 438         (PPC_OPERAND_CR): Replace with...
 439         (PPC_OPERAND_CR_BIT): ...this and
 440         (PPC_OPERAND_CR_REG): ...this.
 441
 442
 443 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 444
 445         * xgate.h: Header file for XGATE assembler.
 446
 447 2012-04-27  David S. Miller  <davem@davemloft.net>
 448
 449         * sparc.h: Document new arg code' )' for crypto RS3
 450         immediates.
 451
 452         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 453         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 454         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 455         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 456         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 457         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 458         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 459         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 460         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 461         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 462         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 463
 464 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 465
 466         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 467
 468 2012-02-27  Alan Modra  <amodra@gmail.com>
 469
 470         * crx.h (cst4_map): Update declaration.
 471
 472 2012-02-25  Walter Lee  <walt@tilera.com>
 473
 474         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 475         TILEGX_OPC_LD_TLS.
 476         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 477         TILEPRO_OPC_LW_TLS_SN.
 478
 479 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 482         (XRELEASE_PREFIX_OPCODE): Likewise.
 483
 484 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 485             Adam Nemet  <anemet@caviumnetworks.com>
 486
 487         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 488         (INSN_OCTEON2): New macro.
 489         (CPU_OCTEON2): New macro.
 490         (OPCODE_IS_MEMBER): Add Octeon2.
 491
 492 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 493
 494         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 495         (INSN_OCTEONP): New macro.
 496         (CPU_OCTEONP): New macro.
 497         (OPCODE_IS_MEMBER): Add Octeon+.
 498         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 499
 500 2011-11-01  DJ Delorie  <dj@redhat.com>
 501
 502         * rl78.h: New file.
 503
 504 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 505
 506         * mips.h: Fix a typo in description.
 507
 508 2011-09-21  David S. Miller  <davem@davemloft.net>
 509
 510         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 511         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 512         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 513         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 514
 515 2011-08-09  Chao-ying Fu  <fu@mips.com>
 516             Maciej W. Rozycki  <macro@codesourcery.com>
 517
 518         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 519         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 520         (INSN_ASE_MASK): Add the MCU bit.
 521         (INSN_MCU): New macro.
 522         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 523         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 524
 525 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 526
 527         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 528         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 529         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 530         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 531         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 532         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 533         (INSN2_READ_GPR_MMN): Likewise.
 534         (INSN2_READ_FPR_D): Change the bit used.
 535         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 536         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 537         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 538         (INSN2_COND_BRANCH): Likewise.
 539         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 540         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 541         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 542         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 543         (INSN2_MOD_GPR_MN): Likewise.
 544
 545 2011-08-05  David S. Miller  <davem@davemloft.net>
 546
 547         * sparc.h: Document new format codes '4', '5', and '('.
 548         (OPF_LOW4, RS3): New macros.
 549
 550 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 551
 552         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 553         order of flags documented.
 554
 555 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 556
 557         * mips.h: Clarify the description of microMIPS instruction
 558         manipulation macros.
 559         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 560
 561 2011-07-24  Chao-ying Fu  <fu@mips.com>
 562             Maciej W. Rozycki  <macro@codesourcery.com>
 563
 564         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 565         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 566         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 567         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 568         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 569         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 570         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 571         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 572         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 573         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 574         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 575         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 576         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 577         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 578         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 579         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 580         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 581         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 582         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 583         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 584         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 585         (INSN_WRITE_GPR_S): New macro.
 586         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 587         (INSN2_READ_FPR_D): Likewise.
 588         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 589         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 590         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 591         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 592         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 593         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 594         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 595         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 596         (CPU_MICROMIPS): New macro.
 597         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 598         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 599         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 600         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 601         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 602         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 603         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 604         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 605         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 606         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 607         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 608         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 609         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 610         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 611         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 612         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 613         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 614         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 615         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 616         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 617         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 618         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 619         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 620         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 621         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 622         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 623         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 624         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 625         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 626         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 627         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 628         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 629         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 630         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 631         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 632         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 633         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 634         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 635         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 636         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 637         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 638         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 639         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 640         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 641         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 642         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 643         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 644         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 645         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 646         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 647         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 648         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 649         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 650         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 651         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 652         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 653         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 654         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 655         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 656         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 657         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 658         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 659         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 660         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 661         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 662         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 663         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 664         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 665         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 666         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 667         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 668         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 669         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 670         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 671         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 672         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 673         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 674         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 675         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 676         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 677         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 678         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 679         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 680         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 681         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 682         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 683         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 684         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 685         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 686         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 687         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 688         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 689         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 690         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 691         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 692         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 693         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 694         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 695         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 696         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 697         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 698         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 699         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 700         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 701         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 702         (micromips_opcodes): New declaration.
 703         (bfd_micromips_num_opcodes): Likewise.
 704
 705 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 706
 707         * mips.h (INSN_TRAP): Rename to...
 708         (INSN_NO_DELAY_SLOT): ... this.
 709         (INSN_SYNC): Remove macro.
 710
 711 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 712
 713         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 714         a duplicate of AVR_ISA_SPM.
 715
 716 2011-07-01  Nick Clifton  <nickc@redhat.com>
 717
 718         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 719
 720 2011-06-18  Robin Getz  <robin.getz@analog.com>
 721
 722         * bfin.h (is_macmod_signed): New func
 723
 724 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 725
 726         * bfin.h (is_macmod_pmove): Add missing space before func args.
 727         (is_macmod_hmove): Likewise.
 728
 729 2011-06-13  Walter Lee  <walt@tilera.com>
 730
 731         * tilegx.h: New file.
 732         * tilepro.h: New file.
 733
 734 2011-05-31  Paul Brook  <paul@codesourcery.com>
 735
 736         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 737
 738 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 739
 740         * s390.h: Replace S390_OPERAND_REG_EVEN with
 741         S390_OPERAND_REG_PAIR.
 742
 743 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 744
 745         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 746
 747 2011-04-18  Julian Brown  <julian@codesourcery.com>
 748
 749         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 750
 751 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 752
 753         PR gas/12296
 754         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 755
 756 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 757
 758         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 759         New instruction set flags.
 760         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 761
 762 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 763
 764         * mips.h (M_PREF_AB): New enum value.
 765
 766 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 767
 768         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 769         M_IU): Define.
 770         (is_macmod_pmove, is_macmod_hmove): New functions.
 771
 772 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 773
 774         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 775
 776 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 777
 778         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 779         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 780
 781 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 782
 783         PR gas/11395
 784         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 785         "bb" entries.
 786
 787 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 788
 789         PR gas/11395
 790         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 791
 792 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 793
 794         * mips.h: Update commentary after last commit.
 795
 796 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 797
 798         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 799         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 800         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 801
 802 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 803
 804         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 805
 806 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 807
 808         * mips.h: Fix previous commit.
 809
 810 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 811
 812         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 813         (INSN_LOONGSON_3A): Clear bit 31.
 814
 815 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 816
 817         PR gas/12198
 818         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 819         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 820         (ARM_ARCH_V6M_ONLY): New define.
 821
 822 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 823
 824         * mips.h (INSN_LOONGSON_3A): Defined.
 825         (CPU_LOONGSON_3A): Defined.
 826         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 827
 828 2010-10-09  Matt Rice  <ratmice@gmail.com>
 829
 830         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 831         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 832
 833 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 834
 835         * arm.h (ARM_EXT_VIRT): New define.
 836         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 837         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 838         Extensions.
 839
 840 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 841
 842         * arm.h (ARM_AEXT_ADIV): New define.
 843         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 844
 845 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 846
 847         * arm.h (ARM_EXT_OS): New define.
 848         (ARM_AEXT_V6SM): Likewise.
 849         (ARM_ARCH_V6SM): Likewise.
 850
 851 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 852
 853         * arm.h (ARM_EXT_MP): Add.
 854         (ARM_ARCH_V7A_MP): Likewise.
 855
 856 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 857
 858         * bfin.h: Declare pseudoChr structs/defines.
 859
 860 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 861
 862         * bfin.h: Strip trailing whitespace.
 863
 864 2010-07-29  DJ Delorie  <dj@redhat.com>
 865
 866         * rx.h (RX_Operand_Type): Add TwoReg.
 867         (RX_Opcode_ID): Remove ediv and ediv2.
 868
 869 2010-07-27  DJ Delorie  <dj@redhat.com>
 870
 871         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 872
 873 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 874             Ina Pandit  <ina.pandit@kpitcummins.com>
 875
 876         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 877         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 878         PROCESSOR_V850E2_ALL.
 879         Remove PROCESSOR_V850EA support.
 880         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 881         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 882         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 883         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 884         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 885         V850_OPERAND_PERCENT.
 886         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 887         V850_NOT_R0.
 888         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 889         and V850E_PUSH_POP
 890
 891 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 892
 893         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 894         (MIPS16_INSN_BRANCH): Rename to...
 895         (MIPS16_INSN_COND_BRANCH): ... this.
 896
 897 2010-07-03  Alan Modra  <amodra@gmail.com>
 898
 899         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 900         Renumber other PPC_OPCODE defines.
 901
 902 2010-07-03  Alan Modra  <amodra@gmail.com>
 903
 904         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 905
 906 2010-06-29  Alan Modra  <amodra@gmail.com>
 907
 908         * maxq.h: Delete file.
 909
 910 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 911
 912         * ppc.h (PPC_OPCODE_E500): Define.
 913
 914 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 915
 916         * opcode/mips.h (INSN_MIPS16): Remove.
 917
 918 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 919
 920         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 921
 922 2010-04-15  Nick Clifton  <nickc@redhat.com>
 923
 924         * alpha.h: Update copyright notice to use GPLv3.
 925         * arc.h: Likewise.
 926         * arm.h: Likewise.
 927         * avr.h: Likewise.
 928         * bfin.h: Likewise.
 929         * cgen.h: Likewise.
 930         * convex.h: Likewise.
 931         * cr16.h: Likewise.
 932         * cris.h: Likewise.
 933         * crx.h: Likewise.
 934         * d10v.h: Likewise.
 935         * d30v.h: Likewise.
 936         * dlx.h: Likewise.
 937         * h8300.h: Likewise.
 938         * hppa.h: Likewise.
 939         * i370.h: Likewise.
 940         * i386.h: Likewise.
 941         * i860.h: Likewise.
 942         * i960.h: Likewise.
 943         * ia64.h: Likewise.
 944         * m68hc11.h: Likewise.
 945         * m68k.h: Likewise.
 946         * m88k.h: Likewise.
 947         * maxq.h: Likewise.
 948         * mips.h: Likewise.
 949         * mmix.h: Likewise.
 950         * mn10200.h: Likewise.
 951         * mn10300.h: Likewise.
 952         * msp430.h: Likewise.
 953         * np1.h: Likewise.
 954         * ns32k.h: Likewise.
 955         * or32.h: Likewise.
 956         * pdp11.h: Likewise.
 957         * pj.h: Likewise.
 958         * pn.h: Likewise.
 959         * ppc.h: Likewise.
 960         * pyr.h: Likewise.
 961         * rx.h: Likewise.
 962         * s390.h: Likewise.
 963         * score-datadep.h: Likewise.
 964         * score-inst.h: Likewise.
 965         * sparc.h: Likewise.
 966         * spu-insns.h: Likewise.
 967         * spu.h: Likewise.
 968         * tic30.h: Likewise.
 969         * tic4x.h: Likewise.
 970         * tic54x.h: Likewise.
 971         * tic80.h: Likewise.
 972         * v850.h: Likewise.
 973         * vax.h: Likewise.
 974
 975 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 976
 977         * tic6x-control-registers.h, tic6x-insn-formats.h,
 978         tic6x-opcode-table.h, tic6x.h: New.
 979
 980 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 981
 982         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 983
 984 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 985
 986         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 987
 988 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * ia64.h (ia64_find_opcode): Remove argument name.
 991         (ia64_find_next_opcode): Likewise.
 992         (ia64_dis_opcode): Likewise.
 993         (ia64_free_opcode): Likewise.
 994         (ia64_find_dependency): Likewise.
 995
 996 2009-11-22  Doug Evans  <dje@sebabeach.org>
 997
 998         * cgen.h: Include bfd_stdint.h.
 999         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1000
1001 2009-11-18  Paul Brook  <paul@codesourcery.com>
1002
1003         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1004
1005 2009-11-17  Paul Brook  <paul@codesourcery.com>
1006         Daniel Jacobowitz  <dan@codesourcery.com>
1007
1008         * arm.h (ARM_EXT_V6_DSP): Define.
1009         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1010         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1011
1012 2009-11-04  DJ Delorie  <dj@redhat.com>
1013
1014         * rx.h (rx_decode_opcode) (mvtipl): Add.
1015         (mvtcp, mvfcp, opecp): Remove.
1016
1017 2009-11-02  Paul Brook  <paul@codesourcery.com>
1018
1019         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1020         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1021         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1022         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1023         FPU_ARCH_NEON_VFP_V4): Define.
1024
1025 2009-10-23  Doug Evans  <dje@sebabeach.org>
1026
1027         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1028         * cgen.h: Update.  Improve multi-inclusion macro name.
1029
1030 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1031
1032         * ppc.h (PPC_OPCODE_476): Define.
1033
1034 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1035
1036         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1037
1038 2009-09-29  DJ Delorie  <dj@redhat.com>
1039
1040         * rx.h: New file.
1041
1042 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1043
1044         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1045
1046 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1047
1048         * ppc.h (PPC_OPCODE_PPCA2): New.
1049
1050 2009-09-05  Martin Thuresson  <martin@mtme.org>
1051
1052         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1053
1054 2009-08-29  Martin Thuresson  <martin@mtme.org>
1055
1056         * tic30.h (template): Rename type template to
1057         insn_template. Updated code to use new name.
1058         * tic54x.h (template): Rename type template to
1059         insn_template.
1060
1061 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1062
1063         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1064
1065 2009-06-11  Anthony Green  <green@moxielogic.com>
1066
1067         * moxie.h (MOXIE_F3_PCREL): Define.
1068         (moxie_form3_opc_info): Grow.
1069
1070 2009-06-06  Anthony Green  <green@moxielogic.com>
1071
1072         * moxie.h (MOXIE_F1_M): Define.
1073
1074 2009-04-15  Anthony Green  <green@moxielogic.com>
1075
1076         * moxie.h: Created.
1077
1078 2009-04-06  DJ Delorie  <dj@redhat.com>
1079
1080         * h8300.h: Add relaxation attributes to MOVA opcodes.
1081
1082 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1083
1084         * ppc.h (ppc_parse_cpu): Declare.
1085
1086 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1087
1088         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1089         and _IMM11 for mbitclr and mbitset.
1090         * score-datadep.h: Update dependency information.
1091
1092 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1093
1094         * ppc.h (PPC_OPCODE_POWER7): New.
1095
1096 2009-02-06  Doug Evans  <dje@google.com>
1097
1098         * i386.h: Add comment regarding sse* insns and prefixes.
1099
1100 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1101
1102         * mips.h (INSN_XLR): Define.
1103         (INSN_CHIP_MASK): Update.
1104         (CPU_XLR): Define.
1105         (OPCODE_IS_MEMBER): Update.
1106         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1107
1108 2009-01-28  Doug Evans  <dje@google.com>
1109
1110         * opcode/i386.h: Add multiple inclusion protection.
1111         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1112         (EDI_REG_NUM): New macros.
1113         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1114         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1115         (REX_PREFIX_P): New macro.
1116
1117 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1118
1119         * ppc.h (struct powerpc_opcode): New field "deprecated".
1120         (PPC_OPCODE_NOPOWER4): Delete.
1121
1122 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1123
1124         * mips.h: Define CPU_R14000, CPU_R16000.
1125         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1126
1127 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1128
1129         * arm.h (FPU_NEON_FP16): New.
1130         (FPU_ARCH_NEON_FP16): New.
1131
1132 2008-11-06  Chao-ying Fu  <fu@mips.com>
1133
1134         * mips.h: Doucument '1' for 5-bit sync type.
1135
1136 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1139         IA64_RS_CR.
1140
1141 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1142
1143         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1144
1145 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1146
1147         * ppc.h (PPC_OPCODE_405): Define.
1148         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1149
1150 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1151
1152         * ppc.h (ppc_cpu_t): New typedef.
1153         (struct powerpc_opcode <flags>): Use it.
1154         (struct powerpc_operand <insert, extract>): Likewise.
1155         (struct powerpc_macro <flags>): Likewise.
1156
1157 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1158
1159         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1160         Update comment before MIPS16 field descriptors to mention MIPS16.
1161         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1162         BBIT.
1163         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1164         New bit masks and shift counts for cins and exts.
1165
1166         * mips.h: Document new field descriptors +Q.
1167         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1168
1169 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1170
1171         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1172         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1173
1174 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1175
1176         * ppc.h: (PPC_OPCODE_E500MC): New.
1177
1178 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1179
1180         * i386.h (MAX_OPERANDS): Set to 5.
1181         (MAX_MNEM_SIZE): Changed to 20.
1182
1183 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1184
1185         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1186
1187 2008-03-09  Paul Brook  <paul@codesourcery.com>
1188
1189         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1190
1191 2008-03-04  Paul Brook  <paul@codesourcery.com>
1192
1193         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1194         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1195         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1196
1197 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1198             Nick Clifton  <nickc@redhat.com>
1199
1200         PR 3134
1201         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1202         with a 32-bit displacement but without the top bit of the 4th byte
1203         set.
1204
1205 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1206
1207         * cr16.h (cr16_num_optab): Declared.
1208
1209 2008-02-14  Hakan Ardo  <hakan@debian.org>
1210
1211         PR gas/2626
1212         * avr.h (AVR_ISA_2xxe): Define.
1213
1214 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1215
1216         * mips.h: Update copyright.
1217         (INSN_CHIP_MASK): New macro.
1218         (INSN_OCTEON): New macro.
1219         (CPU_OCTEON): New macro.
1220         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1221
1222 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1223
1224         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1225
1226 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1227
1228         * avr.h (AVR_ISA_USB162): Add new opcode set.
1229         (AVR_ISA_AVR3): Likewise.
1230
1231 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1232
1233         * mips.h (INSN_LOONGSON_2E): New.
1234         (INSN_LOONGSON_2F): New.
1235         (CPU_LOONGSON_2E): New.
1236         (CPU_LOONGSON_2F): New.
1237         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1238
1239 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1240
1241         * mips.h (INSN_ISA*): Redefine certain values as an
1242         enumeration.  Update comments.
1243         (mips_isa_table): New.
1244         (ISA_MIPS*): Redefine to match enumeration.
1245         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1246         values.
1247
1248 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1249
1250         * ppc.h (PPC_OPCODE_PPCPS): New.
1251
1252 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1253
1254         * m68k.h: Document j K & E.
1255
1256 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1257
1258         * cr16.h: New file for CR16 target.
1259
1260 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1261
1262         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1263
1264 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1265
1266         * m68k.h (mcfisa_c): New.
1267         (mcfusp, mcf_mask): Adjust.
1268
1269 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1270
1271         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1272         (num_powerpc_operands): Declare.
1273         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1274         (PPC_OPERAND_PLUS1): Define.
1275
1276 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1277
1278         * i386.h (REX_MODE64): Renamed to ...
1279         (REX_W): This.
1280         (REX_EXTX): Renamed to ...
1281         (REX_R): This.
1282         (REX_EXTY): Renamed to ...
1283         (REX_X): This.
1284         (REX_EXTZ): Renamed to ...
1285         (REX_B): This.
1286
1287 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1288
1289         * i386.h: Add entries from config/tc-i386.h and move tables
1290         to opcodes/i386-opc.h.
1291
1292 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1293
1294         * i386.h (FloatDR): Removed.
1295         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1296
1297 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1298
1299         * spu-insns.h: Add soma double-float insns.
1300
1301 2007-02-20  Thiemo Seufer  <ths@mips.com>
1302             Chao-Ying Fu  <fu@mips.com>
1303
1304         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1305         (INSN_DSPR2): Add flag for DSP R2 instructions.
1306         (M_BALIGN): New macro.
1307
1308 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1309
1310         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1311         and Seg3ShortFrom with Shortform.
1312
1313 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1314
1315         PR gas/4027
1316         * i386.h (i386_optab): Put the real "test" before the pseudo
1317         one.
1318
1319 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1320
1321         * m68k.h (m68010up): OR fido_a.
1322
1323 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1324
1325         * m68k.h (fido_a): New.
1326
1327 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1328
1329         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1330         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1331         values.
1332
1333 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1334
1335         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1336
1337 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1338
1339         * score-inst.h (enum score_insn_type): Add Insn_internal.
1340
1341 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1342             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1343             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1344             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1345             Alan Modra  <amodra@bigpond.net.au>
1346
1347         * spu-insns.h: New file.
1348         * spu.h: New file.
1349
1350 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1351
1352         * ppc.h (PPC_OPCODE_CELL): Define.
1353
1354 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1355
1356         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1357         in amdfam10 architecture.
1358
1359 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1360
1361         * i386.h: Replace CpuMNI with CpuSSSE3.
1362
1363 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1364             Joseph Myers  <joseph@codesourcery.com>
1365             Ian Lance Taylor  <ian@wasabisystems.com>
1366             Ben Elliston  <bje@wasabisystems.com>
1367
1368         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1369
1370 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1371
1372         * score-datadep.h: New file.
1373         * score-inst.h: New file.
1374
1375 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1376
1377         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1378         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1379         movdq2q and movq2dq.
1380
1381 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1382            Michael Meissner             <michael.meissner@amd.com>
1383
1384         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1385
1386 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         * i386.h (i386_optab): Add "nop" with memory reference.
1389
1390 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1391
1392         * i386.h (i386_optab): Update comment for 64bit NOP.
1393
1394 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1395             Anton Blanchard  <anton@samba.org>
1396
1397         * ppc.h (PPC_OPCODE_POWER6): Define.
1398         Adjust whitespace.
1399
1400 2006-06-05  Thiemo Seufer  <ths@mips.com>
1401
1402         * mips.h: Improve description of MT flags.
1403
1404 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1405
1406         * m68k.h (mcf_mask): Define.
1407
1408 2006-05-05  Thiemo Seufer  <ths@mips.com>
1409             David Ung  <davidu@mips.com>
1410
1411         * mips.h (enum): Add macro M_CACHE_AB.
1412
1413 2006-05-04  Thiemo Seufer  <ths@mips.com>
1414             Nigel Stephens  <nigel@mips.com>
1415             David Ung  <davidu@mips.com>
1416
1417         * mips.h: Add INSN_SMARTMIPS define.
1418
1419 2006-04-30  Thiemo Seufer  <ths@mips.com>
1420             David Ung  <davidu@mips.com>
1421
1422         * mips.h: Defines udi bits and masks.  Add description of
1423         characters which may appear in the args field of udi
1424         instructions.
1425
1426 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1427
1428         * mips.h: Improve comments describing the bitfield instruction
1429         fields.
1430
1431 2006-04-26  Julian Brown  <julian@codesourcery.com>
1432
1433         * arm.h (FPU_VFP_EXT_V3): Define constant.
1434         (FPU_NEON_EXT_V1): Likewise.
1435         (FPU_VFP_HARD): Update.
1436         (FPU_VFP_V3): Define macro.
1437         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1438
1439 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1440
1441         * avr.h (AVR_ISA_PWMx): New.
1442
1443 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1444
1445         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1446         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1447         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1448         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1449         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1450
1451 2006-03-10  Paul Brook  <paul@codesourcery.com>
1452
1453         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1454
1455 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1456
1457         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1458         first.  Correct mask of bb "B" opcode.
1459
1460 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1461
1462         * i386.h (i386_optab): Support Intel Merom New Instructions.
1463
1464 2006-02-24  Paul Brook  <paul@codesourcery.com>
1465
1466         * arm.h: Add V7 feature bits.
1467
1468 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1469
1470         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1471
1472 2006-01-31  Paul Brook  <paul@codesourcery.com>
1473         Richard Earnshaw <rearnsha@arm.com>
1474
1475         * arm.h: Use ARM_CPU_FEATURE.
1476         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1477         (arm_feature_set): Change to a structure.
1478         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1479         ARM_FEATURE): New macros.
1480
1481 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1482
1483         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1484         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1485         (ADD_PC_INCR_OPCODE): Don't define.
1486
1487 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1488
1489         PR gas/1874
1490         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1491
1492 2005-11-14  David Ung  <davidu@mips.com>
1493
1494         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1495         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1496         save/restore encoding of the args field.
1497
1498 2005-10-28  Dave Brolley  <brolley@redhat.com>
1499
1500         Contribute the following changes:
1501         2005-02-16  Dave Brolley  <brolley@redhat.com>
1502
1503         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1504         cgen_isa_mask_* to cgen_bitset_*.
1505         * cgen.h: Likewise.
1506
1507         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1508
1509         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1510         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1511         (CGEN_CPU_TABLE): Make isas a ponter.
1512
1513         2003-09-29  Dave Brolley  <brolley@redhat.com>
1514
1515         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1516         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1517         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1518
1519         2002-12-13  Dave Brolley  <brolley@redhat.com>
1520
1521         * cgen.h (symcat.h): #include it.
1522         (cgen-bitset.h): #include it.
1523         (CGEN_ATTR_VALUE_TYPE): Now a union.
1524         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1525         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1526         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1527         * cgen-bitset.h: New file.
1528
1529 2005-09-30  Catherine Moore  <clm@cm00re.com>
1530
1531         * bfin.h: New file.
1532
1533 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1534
1535         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1536         indirect operands.
1537
1538 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1539
1540         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1541         Add FLAG_STRICT to pa10 ftest opcode.
1542
1543 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1544
1545         * hppa.h (pa_opcodes): Remove lha entries.
1546
1547 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1548
1549         * hppa.h (FLAG_STRICT): Revise comment.
1550         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1551         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1552         entries for "fdc".
1553
1554 2005-09-30  Catherine Moore  <clm@cm00re.com>
1555
1556         * bfin.h: New file.
1557
1558 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1559
1560         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1561
1562 2005-09-06  Chao-ying Fu  <fu@mips.com>
1563
1564         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1565         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1566         define.
1567         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1568         (INSN_ASE_MASK): Update to include INSN_MT.
1569         (INSN_MT): New define for MT ASE.
1570
1571 2005-08-25  Chao-ying Fu  <fu@mips.com>
1572
1573         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1574         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1575         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1576         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1577         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1578         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1579         instructions.
1580         (INSN_DSP): New define for DSP ASE.
1581
1582 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1583
1584         * a29k.h: Delete.
1585
1586 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1587
1588         * ppc.h (PPC_OPCODE_E300): Define.
1589
1590 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1591
1592         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1593
1594 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1595
1596         PR gas/336
1597         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1598         and pitlb.
1599
1600 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1601
1602         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1603         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1604         Add movq-s as 64-bit variants of movd-s.
1605
1606 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1607
1608         * hppa.h: Fix punctuation in comment.
1609
1610         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1611         implicit space-register addressing.  Set space-register bits on opcodes
1612         using implicit space-register addressing.  Add various missing pa20
1613         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1614         space-register addressing.  Use "fE" instead of "fe" in various
1615         fstw opcodes.
1616
1617 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1618
1619         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1620
1621 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1622
1623         * i386.h (i386_optab): Support Intel VMX Instructions.
1624
1625 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1626
1627         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1628
1629 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1630
1631         * i386.h (i386_optab): Add new insns.
1632
1633 2005-07-01  Nick Clifton  <nickc@redhat.com>
1634
1635         * sparc.h: Add typedefs to structure declarations.
1636
1637 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1638
1639         PR 1013
1640         * i386.h (i386_optab): Update comments for 64bit addressing on
1641         mov. Allow 64bit addressing for mov and movq.
1642
1643 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1644
1645         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1646         respectively, in various floating-point load and store patterns.
1647
1648 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1649
1650         * hppa.h (FLAG_STRICT): Correct comment.
1651         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1652         PA 2.0 mneumonics when equivalent.  Entries with cache control
1653         completers now require PA 1.1.  Adjust whitespace.
1654
1655 2005-05-19  Anton Blanchard  <anton@samba.org>
1656
1657         * ppc.h (PPC_OPCODE_POWER5): Define.
1658
1659 2005-05-10  Nick Clifton  <nickc@redhat.com>
1660
1661         * Update the address and phone number of the FSF organization in
1662         the GPL notices in the following files:
1663         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1664         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1665         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1666         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1667         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1668         tic54x.h, tic80.h, v850.h, vax.h
1669
1670 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1671
1672         * i386.h (i386_optab): Add ht and hnt.
1673
1674 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1675
1676         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1677         Add xcrypt-ctr.  Provide aliases without hyphens.
1678
1679 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1680
1681         Moved from ../ChangeLog
1682
1683         2005-04-12  Paul Brook  <paul@codesourcery.com>
1684         * m88k.h: Rename psr macros to avoid conflicts.
1685
1686         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1687         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1688         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1689         and ARM_ARCH_V6ZKT2.
1690
1691         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1692         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1693         Remove redundant instruction types.
1694         (struct argument): X_op - new field.
1695         (struct cst4_entry): Remove.
1696         (no_op_insn): Declare.
1697
1698         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1699         * crx.h (enum argtype): Rename types, remove unused types.
1700
1701         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1702         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1703         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1704         (enum operand_type): Rearrange operands, edit comments.
1705         replace us<N> with ui<N> for unsigned immediate.
1706         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1707         displacements (respectively).
1708         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1709         (instruction type): Add NO_TYPE_INS.
1710         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1711         (operand_entry): New field - 'flags'.
1712         (operand flags): New.
1713
1714         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1715         * crx.h (operand_type): Remove redundant types i3, i4,
1716         i5, i8, i12.
1717         Add new unsigned immediate types us3, us4, us5, us16.
1718
1719 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1720
1721         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1722         adjust them accordingly.
1723
1724 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1725
1726         * i386.h (i386_optab): Add rdtscp.
1727
1728 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1729
1730         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1731         between memory and segment register. Allow movq for moving between
1732         general-purpose register and segment register.
1733
1734 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1735
1736         PR gas/707
1737         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1738         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1739         fnstsw.
1740
1741 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1742
1743         * m68k.h (m68008, m68ec030, m68882): Remove.
1744         (m68k_mask): New.
1745         (cpu_m68k, cpu_cf): New.
1746         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1747         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1748
1749 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1750
1751         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1752         * cgen.h (enum cgen_parse_operand_type): Add
1753         CGEN_PARSE_OPERAND_SYMBOLIC.
1754
1755 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1756
1757         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1758         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1759         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1760
1761 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1762
1763         * mips.h (struct mips_opcode): Add new pinfo2 member.
1764         (INSN_ALIAS): New define for opcode table entries that are
1765         specific instances of another entry, such as 'move' for an 'or'
1766         with a zero operand.
1767         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1768         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1769
1770 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1771
1772         * mips.h (CPU_RM9000): Define.
1773         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1774
1775 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1776
1777         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1778         to/from test registers are illegal in 64-bit mode. Add missing
1779         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1780         (previously one had to explicitly encode a rex64 prefix). Re-enable
1781         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1782         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1783
1784 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1785
1786         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1787         available only with SSE2. Change the MMX additions introduced by SSE
1788         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1789         instructions by their now designated identifier (since combining i686
1790         and 3DNow! does not really imply 3DNow!A).
1791
1792 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1793
1794         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1795         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1796
1797 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1798             Vineet Sharma      <vineets@noida.hcltech.com>
1799
1800         * maxq.h: New file: Disassembly information for the maxq port.
1801
1802 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1803
1804         * i386.h (i386_optab): Put back "movzb".
1805
1806 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1807
1808         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1809         comments.  Remove member cris_ver_sim.  Add members
1810         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1811         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1812         (struct cris_support_reg, struct cris_cond15): New types.
1813         (cris_conds15): Declare.
1814         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1815         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1816         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1817         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1818         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1819         SIZE_FIELD_UNSIGNED.
1820
1821 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1822
1823         * i386.h (sldx_Suf): Remove.
1824         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1825         (q_FP): Define, implying no REX64.
1826         (x_FP, sl_FP): Imply FloatMF.
1827         (i386_optab): Split reg and mem forms of moving from segment registers
1828         so that the memory forms can ignore the 16-/32-bit operand size
1829         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1830         all non-floating-point instructions. Unite 32- and 64-bit forms of
1831         movsx, movzx, and movd. Adjust floating point operations for the above
1832         changes to the *FP macros. Add DefaultSize to floating point control
1833         insns operating on larger memory ranges. Remove left over comments
1834         hinting at certain insns being Intel-syntax ones where the ones
1835         actually meant are already gone.
1836
1837 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1838
1839         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1840         instruction type.
1841
1842 2004-09-30  Paul Brook  <paul@codesourcery.com>
1843
1844         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1845         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1846
1847 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1848
1849         * avr.h: Add support for
1850         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1851
1852 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1853
1854         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1855
1856 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1857
1858         * msp430.h (msp430_opc): Add new instructions.
1859         (msp430_rcodes): Declare new instructions.
1860         (msp430_hcodes): Likewise..
1861
1862 2004-08-13  Nick Clifton  <nickc@redhat.com>
1863
1864         PR/301
1865         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1866         processors.
1867
1868 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1869
1870         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1871
1872 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1873
1874         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1875
1876 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1877
1878         * i386.h: Adjust instruction descriptions to better match the
1879         specification.
1880
1881 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1882
1883         * arm.h: Remove all old content.  Replace with architecture defines
1884         from gas/config/tc-arm.c.
1885
1886 2004-07-09  Andreas Schwab  <schwab@suse.de>
1887
1888         * m68k.h: Fix comment.
1889
1890 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1891
1892         * crx.h: New file.
1893
1894 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1895
1896         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1897
1898 2004-05-24  Peter Barada  <peter@the-baradas.com>
1899
1900         * m68k.h: Add 'size' to m68k_opcode.
1901
1902 2004-05-05  Peter Barada  <peter@the-baradas.com>
1903
1904         * m68k.h: Switch from ColdFire chip name to core variant.
1905
1906 2004-04-22  Peter Barada  <peter@the-baradas.com>
1907
1908         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1909         descriptions for new EMAC cases.
1910         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1911         handle Motorola MAC syntax.
1912         Allow disassembly of ColdFire V4e object files.
1913
1914 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1915
1916         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1917
1918 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1919
1920         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1921
1922 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1923
1924         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1925
1926 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1927
1928         * i386.h (i386_optab): Added xstore/xcrypt insns.
1929
1930 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1931
1932         * h8300.h (32bit ldc/stc): Add relaxing support.
1933
1934 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1935
1936         * h8300.h (BITOP): Pass MEMRELAX flag.
1937
1938 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1939
1940         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1941         except for the H8S.
1942
1943 For older changes see ChangeLog-9103
1944 \f
1945 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1946
1947 Copying and distribution of this file, with or without modification,
1948 are permitted in any medium without royalty provided the copyright
1949 notice and this notice are preserved.
1950
1951 Local Variables:
1952 mode: change-log
1953 left-margin: 8
1954 fill-column: 74
1955 version-control: never
1956 End: