1 2011-08-05 David S. Miller <davem@davemloft.net>
3 * sparc.h: Document new format codes '4', '5', and '('.
4 (OPF_LOW4, RS3): New macros.
6 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
8 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
9 order of flags documented.
11 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
13 * mips.h: Clarify the description of microMIPS instruction
15 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
17 2011-07-24 Chao-ying Fu <fu@mips.com>
18 Maciej W. Rozycki <macro@codesourcery.com>
20 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
21 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
22 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
23 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
24 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
25 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
26 (OP_MASK_RS3, OP_SH_RS3): Likewise.
27 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
28 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
29 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
30 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
31 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
32 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
33 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
34 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
35 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
36 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
37 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
38 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
39 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
40 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
41 (INSN_WRITE_GPR_S): New macro.
42 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
43 (INSN2_READ_FPR_D): Likewise.
44 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
45 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
46 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
47 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
48 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
49 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
50 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
51 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
52 (CPU_MICROMIPS): New macro.
53 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
54 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
55 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
56 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
57 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
58 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
59 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
60 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
61 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
62 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
63 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
64 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
65 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
66 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
67 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
68 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
69 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
70 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
71 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
72 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
73 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
74 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
75 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
76 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
77 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
78 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
79 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
80 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
81 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
82 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
83 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
84 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
85 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
86 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
87 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
88 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
89 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
90 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
91 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
92 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
93 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
94 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
95 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
96 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
97 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
98 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
99 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
100 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
101 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
102 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
103 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
104 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
105 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
106 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
107 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
108 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
109 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
110 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
111 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
112 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
113 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
114 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
115 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
116 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
117 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
118 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
119 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
120 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
121 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
122 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
123 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
124 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
125 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
126 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
127 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
128 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
129 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
130 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
131 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
132 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
133 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
134 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
135 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
136 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
137 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
138 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
139 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
140 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
141 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
142 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
143 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
144 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
145 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
146 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
147 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
148 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
149 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
150 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
151 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
152 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
153 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
154 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
155 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
156 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
157 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
158 (micromips_opcodes): New declaration.
159 (bfd_micromips_num_opcodes): Likewise.
161 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips.h (INSN_TRAP): Rename to...
164 (INSN_NO_DELAY_SLOT): ... this.
165 (INSN_SYNC): Remove macro.
167 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
169 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
170 a duplicate of AVR_ISA_SPM.
172 2011-07-01 Nick Clifton <nickc@redhat.com>
174 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
176 2011-06-18 Robin Getz <robin.getz@analog.com>
178 * bfin.h (is_macmod_signed): New func
180 2011-06-18 Mike Frysinger <vapier@gentoo.org>
182 * bfin.h (is_macmod_pmove): Add missing space before func args.
183 (is_macmod_hmove): Likewise.
185 2011-06-13 Walter Lee <walt@tilera.com>
187 * tilegx.h: New file.
188 * tilepro.h: New file.
190 2011-05-31 Paul Brook <paul@codesourcery.com>
192 * arm.h (ARM_ARCH_V7R_IDIV): Define.
194 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
196 * s390.h: Replace S390_OPERAND_REG_EVEN with
197 S390_OPERAND_REG_PAIR.
199 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
201 * s390.h: Add S390_OPCODE_REG_EVEN flag.
203 2011-04-18 Julian Brown <julian@codesourcery.com>
205 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
207 2011-04-11 Dan McDonald <dan@wellkeeper.com>
210 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
212 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
214 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
215 New instruction set flags.
216 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
218 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
220 * mips.h (M_PREF_AB): New enum value.
222 2011-02-12 Mike Frysinger <vapier@gentoo.org>
224 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
226 (is_macmod_pmove, is_macmod_hmove): New functions.
228 2011-02-11 Mike Frysinger <vapier@gentoo.org>
230 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
232 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
234 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
235 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
237 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
240 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
243 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
246 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
248 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
250 * mips.h: Update commentary after last commit.
252 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
254 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
255 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
256 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
258 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
260 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
262 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
264 * mips.h: Fix previous commit.
266 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
268 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
269 (INSN_LOONGSON_3A): Clear bit 31.
271 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
274 * arm.h (ARM_AEXT_V6M_ONLY): New define.
275 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
276 (ARM_ARCH_V6M_ONLY): New define.
278 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
280 * mips.h (INSN_LOONGSON_3A): Defined.
281 (CPU_LOONGSON_3A): Defined.
282 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
284 2010-10-09 Matt Rice <ratmice@gmail.com>
286 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
287 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
289 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
291 * arm.h (ARM_EXT_VIRT): New define.
292 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
293 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
296 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
298 * arm.h (ARM_AEXT_ADIV): New define.
299 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
301 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
303 * arm.h (ARM_EXT_OS): New define.
304 (ARM_AEXT_V6SM): Likewise.
305 (ARM_ARCH_V6SM): Likewise.
307 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
309 * arm.h (ARM_EXT_MP): Add.
310 (ARM_ARCH_V7A_MP): Likewise.
312 2010-09-22 Mike Frysinger <vapier@gentoo.org>
314 * bfin.h: Declare pseudoChr structs/defines.
316 2010-09-21 Mike Frysinger <vapier@gentoo.org>
318 * bfin.h: Strip trailing whitespace.
320 2010-07-29 DJ Delorie <dj@redhat.com>
322 * rx.h (RX_Operand_Type): Add TwoReg.
323 (RX_Opcode_ID): Remove ediv and ediv2.
325 2010-07-27 DJ Delorie <dj@redhat.com>
327 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
329 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
330 Ina Pandit <ina.pandit@kpitcummins.com>
332 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
333 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
334 PROCESSOR_V850E2_ALL.
335 Remove PROCESSOR_V850EA support.
336 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
337 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
338 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
339 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
340 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
341 V850_OPERAND_PERCENT.
342 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
344 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
347 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
349 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
350 (MIPS16_INSN_BRANCH): Rename to...
351 (MIPS16_INSN_COND_BRANCH): ... this.
353 2010-07-03 Alan Modra <amodra@gmail.com>
355 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
356 Renumber other PPC_OPCODE defines.
358 2010-07-03 Alan Modra <amodra@gmail.com>
360 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
362 2010-06-29 Alan Modra <amodra@gmail.com>
364 * maxq.h: Delete file.
366 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
368 * ppc.h (PPC_OPCODE_E500): Define.
370 2010-05-26 Catherine Moore <clm@codesourcery.com>
372 * opcode/mips.h (INSN_MIPS16): Remove.
374 2010-04-21 Joseph Myers <joseph@codesourcery.com>
376 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
378 2010-04-15 Nick Clifton <nickc@redhat.com>
380 * alpha.h: Update copyright notice to use GPLv3.
386 * convex.h: Likewise.
400 * m68hc11.h: Likewise.
406 * mn10200.h: Likewise.
407 * mn10300.h: Likewise.
408 * msp430.h: Likewise.
419 * score-datadep.h: Likewise.
420 * score-inst.h: Likewise.
422 * spu-insns.h: Likewise.
426 * tic54x.h: Likewise.
431 2010-03-25 Joseph Myers <joseph@codesourcery.com>
433 * tic6x-control-registers.h, tic6x-insn-formats.h,
434 tic6x-opcode-table.h, tic6x.h: New.
436 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
438 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
440 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
442 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
444 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
446 * ia64.h (ia64_find_opcode): Remove argument name.
447 (ia64_find_next_opcode): Likewise.
448 (ia64_dis_opcode): Likewise.
449 (ia64_free_opcode): Likewise.
450 (ia64_find_dependency): Likewise.
452 2009-11-22 Doug Evans <dje@sebabeach.org>
454 * cgen.h: Include bfd_stdint.h.
455 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
457 2009-11-18 Paul Brook <paul@codesourcery.com>
459 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
461 2009-11-17 Paul Brook <paul@codesourcery.com>
462 Daniel Jacobowitz <dan@codesourcery.com>
464 * arm.h (ARM_EXT_V6_DSP): Define.
465 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
466 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
468 2009-11-04 DJ Delorie <dj@redhat.com>
470 * rx.h (rx_decode_opcode) (mvtipl): Add.
471 (mvtcp, mvfcp, opecp): Remove.
473 2009-11-02 Paul Brook <paul@codesourcery.com>
475 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
476 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
477 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
478 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
479 FPU_ARCH_NEON_VFP_V4): Define.
481 2009-10-23 Doug Evans <dje@sebabeach.org>
483 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
484 * cgen.h: Update. Improve multi-inclusion macro name.
486 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
488 * ppc.h (PPC_OPCODE_476): Define.
490 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
492 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
494 2009-09-29 DJ Delorie <dj@redhat.com>
498 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
500 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
502 2009-09-21 Ben Elliston <bje@au.ibm.com>
504 * ppc.h (PPC_OPCODE_PPCA2): New.
506 2009-09-05 Martin Thuresson <martin@mtme.org>
508 * ia64.h (struct ia64_operand): Renamed member class to op_class.
510 2009-08-29 Martin Thuresson <martin@mtme.org>
512 * tic30.h (template): Rename type template to
513 insn_template. Updated code to use new name.
514 * tic54x.h (template): Rename type template to
517 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
519 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
521 2009-06-11 Anthony Green <green@moxielogic.com>
523 * moxie.h (MOXIE_F3_PCREL): Define.
524 (moxie_form3_opc_info): Grow.
526 2009-06-06 Anthony Green <green@moxielogic.com>
528 * moxie.h (MOXIE_F1_M): Define.
530 2009-04-15 Anthony Green <green@moxielogic.com>
534 2009-04-06 DJ Delorie <dj@redhat.com>
536 * h8300.h: Add relaxation attributes to MOVA opcodes.
538 2009-03-10 Alan Modra <amodra@bigpond.net.au>
540 * ppc.h (ppc_parse_cpu): Declare.
542 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
544 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
545 and _IMM11 for mbitclr and mbitset.
546 * score-datadep.h: Update dependency information.
548 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
550 * ppc.h (PPC_OPCODE_POWER7): New.
552 2009-02-06 Doug Evans <dje@google.com>
554 * i386.h: Add comment regarding sse* insns and prefixes.
556 2009-02-03 Sandip Matte <sandip@rmicorp.com>
558 * mips.h (INSN_XLR): Define.
559 (INSN_CHIP_MASK): Update.
561 (OPCODE_IS_MEMBER): Update.
562 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
564 2009-01-28 Doug Evans <dje@google.com>
566 * opcode/i386.h: Add multiple inclusion protection.
567 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
568 (EDI_REG_NUM): New macros.
569 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
570 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
571 (REX_PREFIX_P): New macro.
573 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
575 * ppc.h (struct powerpc_opcode): New field "deprecated".
576 (PPC_OPCODE_NOPOWER4): Delete.
578 2008-11-28 Joshua Kinard <kumba@gentoo.org>
580 * mips.h: Define CPU_R14000, CPU_R16000.
581 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
583 2008-11-18 Catherine Moore <clm@codesourcery.com>
585 * arm.h (FPU_NEON_FP16): New.
586 (FPU_ARCH_NEON_FP16): New.
588 2008-11-06 Chao-ying Fu <fu@mips.com>
590 * mips.h: Doucument '1' for 5-bit sync type.
592 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
594 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
597 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
599 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
601 2008-07-30 Michael J. Eager <eager@eagercon.com>
603 * ppc.h (PPC_OPCODE_405): Define.
604 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
606 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
608 * ppc.h (ppc_cpu_t): New typedef.
609 (struct powerpc_opcode <flags>): Use it.
610 (struct powerpc_operand <insert, extract>): Likewise.
611 (struct powerpc_macro <flags>): Likewise.
613 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
615 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
616 Update comment before MIPS16 field descriptors to mention MIPS16.
617 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
619 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
620 New bit masks and shift counts for cins and exts.
622 * mips.h: Document new field descriptors +Q.
623 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
625 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
627 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
628 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
630 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
632 * ppc.h: (PPC_OPCODE_E500MC): New.
634 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
636 * i386.h (MAX_OPERANDS): Set to 5.
637 (MAX_MNEM_SIZE): Changed to 20.
639 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
641 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
643 2008-03-09 Paul Brook <paul@codesourcery.com>
645 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
647 2008-03-04 Paul Brook <paul@codesourcery.com>
649 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
650 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
651 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
653 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
654 Nick Clifton <nickc@redhat.com>
657 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
658 with a 32-bit displacement but without the top bit of the 4th byte
661 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
663 * cr16.h (cr16_num_optab): Declared.
665 2008-02-14 Hakan Ardo <hakan@debian.org>
668 * avr.h (AVR_ISA_2xxe): Define.
670 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
672 * mips.h: Update copyright.
673 (INSN_CHIP_MASK): New macro.
674 (INSN_OCTEON): New macro.
675 (CPU_OCTEON): New macro.
676 (OPCODE_IS_MEMBER): Handle Octeon instructions.
678 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
680 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
682 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
684 * avr.h (AVR_ISA_USB162): Add new opcode set.
685 (AVR_ISA_AVR3): Likewise.
687 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
689 * mips.h (INSN_LOONGSON_2E): New.
690 (INSN_LOONGSON_2F): New.
691 (CPU_LOONGSON_2E): New.
692 (CPU_LOONGSON_2F): New.
693 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
695 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
697 * mips.h (INSN_ISA*): Redefine certain values as an
698 enumeration. Update comments.
699 (mips_isa_table): New.
700 (ISA_MIPS*): Redefine to match enumeration.
701 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
704 2007-08-08 Ben Elliston <bje@au.ibm.com>
706 * ppc.h (PPC_OPCODE_PPCPS): New.
708 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
710 * m68k.h: Document j K & E.
712 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
714 * cr16.h: New file for CR16 target.
716 2007-05-02 Alan Modra <amodra@bigpond.net.au>
718 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
720 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
722 * m68k.h (mcfisa_c): New.
723 (mcfusp, mcf_mask): Adjust.
725 2007-04-20 Alan Modra <amodra@bigpond.net.au>
727 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
728 (num_powerpc_operands): Declare.
729 (PPC_OPERAND_SIGNED et al): Redefine as hex.
730 (PPC_OPERAND_PLUS1): Define.
732 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
734 * i386.h (REX_MODE64): Renamed to ...
736 (REX_EXTX): Renamed to ...
738 (REX_EXTY): Renamed to ...
740 (REX_EXTZ): Renamed to ...
743 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
745 * i386.h: Add entries from config/tc-i386.h and move tables
746 to opcodes/i386-opc.h.
748 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
750 * i386.h (FloatDR): Removed.
751 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
753 2007-03-01 Alan Modra <amodra@bigpond.net.au>
755 * spu-insns.h: Add soma double-float insns.
757 2007-02-20 Thiemo Seufer <ths@mips.com>
758 Chao-Ying Fu <fu@mips.com>
760 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
761 (INSN_DSPR2): Add flag for DSP R2 instructions.
762 (M_BALIGN): New macro.
764 2007-02-14 Alan Modra <amodra@bigpond.net.au>
766 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
767 and Seg3ShortFrom with Shortform.
769 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
772 * i386.h (i386_optab): Put the real "test" before the pseudo
775 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
777 * m68k.h (m68010up): OR fido_a.
779 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
781 * m68k.h (fido_a): New.
783 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
785 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
786 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
789 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
791 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
793 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
795 * score-inst.h (enum score_insn_type): Add Insn_internal.
797 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
798 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
799 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
800 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
801 Alan Modra <amodra@bigpond.net.au>
803 * spu-insns.h: New file.
806 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
808 * ppc.h (PPC_OPCODE_CELL): Define.
810 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
812 * i386.h : Modify opcode to support for the change in POPCNT opcode
813 in amdfam10 architecture.
815 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
817 * i386.h: Replace CpuMNI with CpuSSSE3.
819 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
820 Joseph Myers <joseph@codesourcery.com>
821 Ian Lance Taylor <ian@wasabisystems.com>
822 Ben Elliston <bje@wasabisystems.com>
824 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
826 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
828 * score-datadep.h: New file.
829 * score-inst.h: New file.
831 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
833 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
834 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
837 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
838 Michael Meissner <michael.meissner@amd.com>
840 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
842 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
844 * i386.h (i386_optab): Add "nop" with memory reference.
846 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
848 * i386.h (i386_optab): Update comment for 64bit NOP.
850 2006-06-06 Ben Elliston <bje@au.ibm.com>
851 Anton Blanchard <anton@samba.org>
853 * ppc.h (PPC_OPCODE_POWER6): Define.
856 2006-06-05 Thiemo Seufer <ths@mips.com>
858 * mips.h: Improve description of MT flags.
860 2006-05-25 Richard Sandiford <richard@codesourcery.com>
862 * m68k.h (mcf_mask): Define.
864 2006-05-05 Thiemo Seufer <ths@mips.com>
865 David Ung <davidu@mips.com>
867 * mips.h (enum): Add macro M_CACHE_AB.
869 2006-05-04 Thiemo Seufer <ths@mips.com>
870 Nigel Stephens <nigel@mips.com>
871 David Ung <davidu@mips.com>
873 * mips.h: Add INSN_SMARTMIPS define.
875 2006-04-30 Thiemo Seufer <ths@mips.com>
876 David Ung <davidu@mips.com>
878 * mips.h: Defines udi bits and masks. Add description of
879 characters which may appear in the args field of udi
882 2006-04-26 Thiemo Seufer <ths@networkno.de>
884 * mips.h: Improve comments describing the bitfield instruction
887 2006-04-26 Julian Brown <julian@codesourcery.com>
889 * arm.h (FPU_VFP_EXT_V3): Define constant.
890 (FPU_NEON_EXT_V1): Likewise.
891 (FPU_VFP_HARD): Update.
892 (FPU_VFP_V3): Define macro.
893 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
895 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
897 * avr.h (AVR_ISA_PWMx): New.
899 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
901 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
902 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
903 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
904 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
905 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
907 2006-03-10 Paul Brook <paul@codesourcery.com>
909 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
911 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
913 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
914 first. Correct mask of bb "B" opcode.
916 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
918 * i386.h (i386_optab): Support Intel Merom New Instructions.
920 2006-02-24 Paul Brook <paul@codesourcery.com>
922 * arm.h: Add V7 feature bits.
924 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
926 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
928 2006-01-31 Paul Brook <paul@codesourcery.com>
929 Richard Earnshaw <rearnsha@arm.com>
931 * arm.h: Use ARM_CPU_FEATURE.
932 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
933 (arm_feature_set): Change to a structure.
934 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
935 ARM_FEATURE): New macros.
937 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
939 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
940 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
941 (ADD_PC_INCR_OPCODE): Don't define.
943 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
946 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
948 2005-11-14 David Ung <davidu@mips.com>
950 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
951 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
952 save/restore encoding of the args field.
954 2005-10-28 Dave Brolley <brolley@redhat.com>
956 Contribute the following changes:
957 2005-02-16 Dave Brolley <brolley@redhat.com>
959 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
960 cgen_isa_mask_* to cgen_bitset_*.
963 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
965 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
966 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
967 (CGEN_CPU_TABLE): Make isas a ponter.
969 2003-09-29 Dave Brolley <brolley@redhat.com>
971 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
972 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
973 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
975 2002-12-13 Dave Brolley <brolley@redhat.com>
977 * cgen.h (symcat.h): #include it.
978 (cgen-bitset.h): #include it.
979 (CGEN_ATTR_VALUE_TYPE): Now a union.
980 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
981 (CGEN_ATTR_ENTRY): 'value' now unsigned.
982 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
983 * cgen-bitset.h: New file.
985 2005-09-30 Catherine Moore <clm@cm00re.com>
989 2005-10-24 Jan Beulich <jbeulich@novell.com>
991 * ia64.h (enum ia64_opnd): Move memory operand out of set of
994 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
996 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
997 Add FLAG_STRICT to pa10 ftest opcode.
999 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1001 * hppa.h (pa_opcodes): Remove lha entries.
1003 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1005 * hppa.h (FLAG_STRICT): Revise comment.
1006 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1007 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1010 2005-09-30 Catherine Moore <clm@cm00re.com>
1014 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1016 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1018 2005-09-06 Chao-ying Fu <fu@mips.com>
1020 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1021 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1023 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1024 (INSN_ASE_MASK): Update to include INSN_MT.
1025 (INSN_MT): New define for MT ASE.
1027 2005-08-25 Chao-ying Fu <fu@mips.com>
1029 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1030 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1031 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1032 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1033 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1034 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1036 (INSN_DSP): New define for DSP ASE.
1038 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1042 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1044 * ppc.h (PPC_OPCODE_E300): Define.
1046 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1048 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1050 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1053 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1056 2005-07-27 Jan Beulich <jbeulich@novell.com>
1058 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1059 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1060 Add movq-s as 64-bit variants of movd-s.
1062 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1064 * hppa.h: Fix punctuation in comment.
1066 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1067 implicit space-register addressing. Set space-register bits on opcodes
1068 using implicit space-register addressing. Add various missing pa20
1069 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1070 space-register addressing. Use "fE" instead of "fe" in various
1073 2005-07-18 Jan Beulich <jbeulich@novell.com>
1075 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1077 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386.h (i386_optab): Support Intel VMX Instructions.
1081 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1083 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1085 2005-07-05 Jan Beulich <jbeulich@novell.com>
1087 * i386.h (i386_optab): Add new insns.
1089 2005-07-01 Nick Clifton <nickc@redhat.com>
1091 * sparc.h: Add typedefs to structure declarations.
1093 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1096 * i386.h (i386_optab): Update comments for 64bit addressing on
1097 mov. Allow 64bit addressing for mov and movq.
1099 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1101 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1102 respectively, in various floating-point load and store patterns.
1104 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1106 * hppa.h (FLAG_STRICT): Correct comment.
1107 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1108 PA 2.0 mneumonics when equivalent. Entries with cache control
1109 completers now require PA 1.1. Adjust whitespace.
1111 2005-05-19 Anton Blanchard <anton@samba.org>
1113 * ppc.h (PPC_OPCODE_POWER5): Define.
1115 2005-05-10 Nick Clifton <nickc@redhat.com>
1117 * Update the address and phone number of the FSF organization in
1118 the GPL notices in the following files:
1119 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1120 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1121 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1122 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1123 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1124 tic54x.h, tic80.h, v850.h, vax.h
1126 2005-05-09 Jan Beulich <jbeulich@novell.com>
1128 * i386.h (i386_optab): Add ht and hnt.
1130 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1132 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1133 Add xcrypt-ctr. Provide aliases without hyphens.
1135 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1137 Moved from ../ChangeLog
1139 2005-04-12 Paul Brook <paul@codesourcery.com>
1140 * m88k.h: Rename psr macros to avoid conflicts.
1142 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1143 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1144 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1145 and ARM_ARCH_V6ZKT2.
1147 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1148 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1149 Remove redundant instruction types.
1150 (struct argument): X_op - new field.
1151 (struct cst4_entry): Remove.
1152 (no_op_insn): Declare.
1154 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1155 * crx.h (enum argtype): Rename types, remove unused types.
1157 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1158 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1159 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1160 (enum operand_type): Rearrange operands, edit comments.
1161 replace us<N> with ui<N> for unsigned immediate.
1162 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1163 displacements (respectively).
1164 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1165 (instruction type): Add NO_TYPE_INS.
1166 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1167 (operand_entry): New field - 'flags'.
1168 (operand flags): New.
1170 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1171 * crx.h (operand_type): Remove redundant types i3, i4,
1173 Add new unsigned immediate types us3, us4, us5, us16.
1175 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1177 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1178 adjust them accordingly.
1180 2005-04-01 Jan Beulich <jbeulich@novell.com>
1182 * i386.h (i386_optab): Add rdtscp.
1184 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1186 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1187 between memory and segment register. Allow movq for moving between
1188 general-purpose register and segment register.
1190 2005-02-09 Jan Beulich <jbeulich@novell.com>
1193 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1194 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1197 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1199 * m68k.h (m68008, m68ec030, m68882): Remove.
1201 (cpu_m68k, cpu_cf): New.
1202 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1203 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1205 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1207 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1208 * cgen.h (enum cgen_parse_operand_type): Add
1209 CGEN_PARSE_OPERAND_SYMBOLIC.
1211 2005-01-21 Fred Fish <fnf@specifixinc.com>
1213 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1214 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1215 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1217 2005-01-19 Fred Fish <fnf@specifixinc.com>
1219 * mips.h (struct mips_opcode): Add new pinfo2 member.
1220 (INSN_ALIAS): New define for opcode table entries that are
1221 specific instances of another entry, such as 'move' for an 'or'
1222 with a zero operand.
1223 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1224 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1226 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1228 * mips.h (CPU_RM9000): Define.
1229 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1231 2004-11-25 Jan Beulich <jbeulich@novell.com>
1233 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1234 to/from test registers are illegal in 64-bit mode. Add missing
1235 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1236 (previously one had to explicitly encode a rex64 prefix). Re-enable
1237 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1238 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1240 2004-11-23 Jan Beulich <jbeulich@novell.com>
1242 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1243 available only with SSE2. Change the MMX additions introduced by SSE
1244 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1245 instructions by their now designated identifier (since combining i686
1246 and 3DNow! does not really imply 3DNow!A).
1248 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1250 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1251 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1253 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1254 Vineet Sharma <vineets@noida.hcltech.com>
1256 * maxq.h: New file: Disassembly information for the maxq port.
1258 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1260 * i386.h (i386_optab): Put back "movzb".
1262 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1264 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1265 comments. Remove member cris_ver_sim. Add members
1266 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1267 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1268 (struct cris_support_reg, struct cris_cond15): New types.
1269 (cris_conds15): Declare.
1270 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1271 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1272 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1273 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1274 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1275 SIZE_FIELD_UNSIGNED.
1277 2004-11-04 Jan Beulich <jbeulich@novell.com>
1279 * i386.h (sldx_Suf): Remove.
1280 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1281 (q_FP): Define, implying no REX64.
1282 (x_FP, sl_FP): Imply FloatMF.
1283 (i386_optab): Split reg and mem forms of moving from segment registers
1284 so that the memory forms can ignore the 16-/32-bit operand size
1285 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1286 all non-floating-point instructions. Unite 32- and 64-bit forms of
1287 movsx, movzx, and movd. Adjust floating point operations for the above
1288 changes to the *FP macros. Add DefaultSize to floating point control
1289 insns operating on larger memory ranges. Remove left over comments
1290 hinting at certain insns being Intel-syntax ones where the ones
1291 actually meant are already gone.
1293 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1295 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1298 2004-09-30 Paul Brook <paul@codesourcery.com>
1300 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1301 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1303 2004-09-11 Theodore A. Roth <troth@openavr.org>
1305 * avr.h: Add support for
1306 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1308 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1310 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1312 2004-08-24 Dmitry Diky <diwil@spec.ru>
1314 * msp430.h (msp430_opc): Add new instructions.
1315 (msp430_rcodes): Declare new instructions.
1316 (msp430_hcodes): Likewise..
1318 2004-08-13 Nick Clifton <nickc@redhat.com>
1321 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1324 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1326 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1328 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1330 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1332 2004-07-21 Jan Beulich <jbeulich@novell.com>
1334 * i386.h: Adjust instruction descriptions to better match the
1337 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1339 * arm.h: Remove all old content. Replace with architecture defines
1340 from gas/config/tc-arm.c.
1342 2004-07-09 Andreas Schwab <schwab@suse.de>
1344 * m68k.h: Fix comment.
1346 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1350 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1352 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1354 2004-05-24 Peter Barada <peter@the-baradas.com>
1356 * m68k.h: Add 'size' to m68k_opcode.
1358 2004-05-05 Peter Barada <peter@the-baradas.com>
1360 * m68k.h: Switch from ColdFire chip name to core variant.
1362 2004-04-22 Peter Barada <peter@the-baradas.com>
1364 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1365 descriptions for new EMAC cases.
1366 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1367 handle Motorola MAC syntax.
1368 Allow disassembly of ColdFire V4e object files.
1370 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1372 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1374 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1376 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1378 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1380 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1382 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1384 * i386.h (i386_optab): Added xstore/xcrypt insns.
1386 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1388 * h8300.h (32bit ldc/stc): Add relaxing support.
1390 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1392 * h8300.h (BITOP): Pass MEMRELAX flag.
1394 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1396 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1399 For older changes see ChangeLog-9103
1405 version-control: never